* [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace
@ 2018-09-24 12:38 Christian König
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
That is superflous here.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 2e87414422f9..e9bf70e2ac51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -103,7 +103,7 @@ TRACE_EVENT(amdgpu_iv,
__entry->src_data[2] = iv->src_data[2];
__entry->src_data[3] = iv->src_data[3];
),
- TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x\n",
+ TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
__entry->client_id, __entry->src_id,
__entry->ring_id, __entry->vmid,
__entry->timestamp, __entry->pasid,
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/9] drm/amdgpu: make function pointers mandatory
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c Christian König
` (7 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
We always want those to be setup correctly.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 20 ++++++++------------
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 20 ++++++++------------
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++++------------
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++++++++------------
drivers/gpu/drm/amd/amdgpu/si_dma.c | 20 ++++++++------------
drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 3 +--
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 3 +--
20 files changed, 55 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 44d10c2172f6..e75183e09820 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -468,8 +468,7 @@ static const struct amdgpu_ih_funcs cik_ih_funcs = {
static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &cik_ih_funcs;
+ adev->irq.ih_funcs = &cik_ih_funcs;
}
const struct amdgpu_ip_block_version cik_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 154b1499b07e..ee9d5c92edb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1370,10 +1370,8 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
{
- if (adev->mman.buffer_funcs == NULL) {
- adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
- }
+ adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
@@ -1389,15 +1387,13 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
struct drm_gpu_scheduler *sched;
unsigned i;
- if (adev->vm_manager.vm_pte_funcs == NULL) {
- adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- }
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_rqs[i] =
+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
}
const struct amdgpu_ip_block_version cik_sdma_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 960c29e17da6..9385da1e1e40 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -449,8 +449,7 @@ static const struct amdgpu_ih_funcs cz_ih_funcs = {
static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &cz_ih_funcs;
+ adev->irq.ih_funcs = &cz_ih_funcs;
}
const struct amdgpu_ip_block_version cz_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 3916aa6cc4ec..89c09c396fe6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3570,8 +3570,7 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
{
- if (adev->mode_info.funcs == NULL)
- adev->mode_info.funcs = &dce_v10_0_display_funcs;
+ adev->mode_info.funcs = &dce_v10_0_display_funcs;
}
static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 4ffb612a4e53..cf6faaa05dbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3702,8 +3702,7 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
{
- if (adev->mode_info.funcs == NULL)
- adev->mode_info.funcs = &dce_v11_0_display_funcs;
+ adev->mode_info.funcs = &dce_v11_0_display_funcs;
}
static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 480c5348a14f..371aa05bf537 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3376,8 +3376,7 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
{
- if (adev->mode_info.funcs == NULL)
- adev->mode_info.funcs = &dce_v6_0_display_funcs;
+ adev->mode_info.funcs = &dce_v6_0_display_funcs;
}
static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 797196476c94..30e76f2407c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3458,8 +3458,7 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
{
- if (adev->mode_info.funcs == NULL)
- adev->mode_info.funcs = &dce_v8_0_display_funcs;
+ adev->mode_info.funcs = &dce_v8_0_display_funcs;
}
static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 15257634a53a..2cc480d65394 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -649,8 +649,7 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
{
- if (adev->mode_info.funcs == NULL)
- adev->mode_info.funcs = &dce_virtual_display_funcs;
+ adev->mode_info.funcs = &dce_virtual_display_funcs;
}
static int dce_virtual_pageflip(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 4411463ca719..3b8ac4442f06 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1180,8 +1180,7 @@ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
{
- if (adev->gmc.gmc_funcs == NULL)
- adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
+ adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
}
static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ae776ce9a415..899634ce4238 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1388,8 +1388,7 @@ static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
{
- if (adev->gmc.gmc_funcs == NULL)
- adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
+ adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
}
static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 53ae49b8bde8..79143ca7cfac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1733,8 +1733,7 @@ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
{
- if (adev->gmc.gmc_funcs == NULL)
- adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
+ adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
}
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index aad3c7c5fb3a..f35d7a554ad5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -593,8 +593,7 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
{
- if (adev->gmc.gmc_funcs == NULL)
- adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
+ adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
}
static int gmc_v9_0_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 842c4b677b4d..45ef0a818e11 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -447,8 +447,7 @@ static const struct amdgpu_ih_funcs iceland_ih_funcs = {
static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &iceland_ih_funcs;
+ adev->irq.ih_funcs = &iceland_ih_funcs;
}
const struct amdgpu_ip_block_version iceland_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index c403bdf8ad70..0c5a576dee13 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1296,10 +1296,8 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
{
- if (adev->mman.buffer_funcs == NULL) {
- adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
- }
+ adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
@@ -1315,15 +1313,13 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
struct drm_gpu_scheduler *sched;
unsigned i;
- if (adev->vm_manager.vm_pte_funcs == NULL) {
- adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- }
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_rqs[i] =
+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
}
const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2677d6a1bf42..2587b8de918a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1736,10 +1736,8 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
{
- if (adev->mman.buffer_funcs == NULL) {
- adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
- }
+ adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
@@ -1755,15 +1753,13 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
struct drm_gpu_scheduler *sched;
unsigned i;
- if (adev->vm_manager.vm_pte_funcs == NULL) {
- adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- }
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_rqs[i] =
+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
}
const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 9da4a1bff5c5..a3e2ed15fff2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1807,10 +1807,8 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
{
- if (adev->mman.buffer_funcs == NULL) {
- adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
- }
+ adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
@@ -1826,15 +1824,13 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
struct drm_gpu_scheduler *sched;
unsigned i;
- if (adev->vm_manager.vm_pte_funcs == NULL) {
- adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- }
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_rqs[i] =
+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
}
const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index fafaf259b17b..c3510a703f9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -863,10 +863,8 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = {
static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
{
- if (adev->mman.buffer_funcs == NULL) {
- adev->mman.buffer_funcs = &si_dma_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
- }
+ adev->mman.buffer_funcs = &si_dma_buffer_funcs;
+ adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
}
static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
@@ -882,15 +880,13 @@ static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
struct drm_gpu_scheduler *sched;
unsigned i;
- if (adev->vm_manager.vm_pte_funcs == NULL) {
- adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_rqs[i] =
- &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
- }
- adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
+ adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_rqs[i] =
+ &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
}
+ adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
}
const struct amdgpu_ip_block_version si_dma_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 60dad63098a2..97711d327527 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -308,8 +308,7 @@ static const struct amdgpu_ih_funcs si_ih_funcs = {
static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &si_ih_funcs;
+ adev->irq.ih_funcs = &si_ih_funcs;
}
const struct amdgpu_ip_block_version si_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 52853d8a8fdd..a79a3776888a 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -513,8 +513,7 @@ static const struct amdgpu_ih_funcs tonga_ih_funcs = {
static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &tonga_ih_funcs;
+ adev->irq.ih_funcs = &tonga_ih_funcs;
}
const struct amdgpu_ip_block_version tonga_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index acbe5a770207..37487b4cbd6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -494,8 +494,7 @@ static const struct amdgpu_ih_funcs vega10_ih_funcs = {
static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- if (adev->irq.ih_funcs == NULL)
- adev->irq.ih_funcs = &vega10_ih_funcs;
+ adev->irq.ih_funcs = &vega10_ih_funcs;
}
const struct amdgpu_ip_block_version vega10_ih_ip_block =
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 2/9] drm/amdgpu: make function pointers mandatory Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c Christian König
` (6 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++++++++++++++------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
9 files changed, 84 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 4ed86218cef3..15fb0f9738ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -26,44 +26,20 @@
#include "amdgpu_ih.h"
#include "amdgpu_amdkfd.h"
-/**
- * amdgpu_ih_ring_alloc - allocate memory for the IH ring
- *
- * @adev: amdgpu_device pointer
- *
- * Allocate a ring buffer for the interrupt controller.
- * Returns 0 for success, errors for failure.
- */
-static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
-{
- int r;
-
- /* Allocate ring buffer */
- if (adev->irq.ih.ring_obj == NULL) {
- r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
- &adev->irq.ih.ring_obj,
- &adev->irq.ih.gpu_addr,
- (void **)&adev->irq.ih.ring);
- if (r) {
- DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
- return r;
- }
- }
- return 0;
-}
-
/**
* amdgpu_ih_ring_init - initialize the IH state
*
* @adev: amdgpu_device pointer
+ * @ih: ih ring to initialize
+ * @ring_size: ring size to allocate
+ * @use_bus_addr: true when we can use dma_alloc_coherent
*
* Initializes the IH state and allocates a buffer
* for the IH ring buffer.
* Returns 0 for success, errors for failure.
*/
-int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
- bool use_bus_addr)
+int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ unsigned ring_size, bool use_bus_addr)
{
u32 rb_bufsz;
int r;
@@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
/* Align ring size */
rb_bufsz = order_base_2(ring_size / 4);
ring_size = (1 << rb_bufsz) * 4;
- adev->irq.ih.ring_size = ring_size;
- adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
- adev->irq.ih.rptr = 0;
- adev->irq.ih.use_bus_addr = use_bus_addr;
-
- if (adev->irq.ih.use_bus_addr) {
- if (!adev->irq.ih.ring) {
- /* add 8 bytes for the rptr/wptr shadows and
- * add them to the end of the ring allocation.
- */
- adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
- adev->irq.ih.ring_size + 8,
- &adev->irq.ih.rb_dma_addr);
- if (adev->irq.ih.ring == NULL)
- return -ENOMEM;
- memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
- adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
- adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
- }
- return 0;
+ ih->ring_size = ring_size;
+ ih->ptr_mask = ih->ring_size - 1;
+ ih->rptr = 0;
+ ih->use_bus_addr = use_bus_addr;
+
+ if (use_bus_addr) {
+ if (ih->ring)
+ return 0;
+
+ /* add 8 bytes for the rptr/wptr shadows and
+ * add them to the end of the ring allocation.
+ */
+ ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
+ &ih->rb_dma_addr, GFP_KERNEL);
+ if (ih->ring == NULL)
+ return -ENOMEM;
+
+ memset((void *)ih->ring, 0, ih->ring_size + 8);
+ ih->wptr_offs = (ih->ring_size / 4) + 0;
+ ih->rptr_offs = (ih->ring_size / 4) + 1;
} else {
- r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
+ r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
+ if (r)
+ return r;
+
+ r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
if (r) {
- dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
+ amdgpu_device_wb_free(adev, ih->wptr_offs);
return r;
}
- r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
+ r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
+ &ih->ring_obj, &ih->gpu_addr,
+ (void **)&ih->ring);
if (r) {
- amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
- dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
+ amdgpu_device_wb_free(adev, ih->rptr_offs);
+ amdgpu_device_wb_free(adev, ih->wptr_offs);
return r;
}
-
- return amdgpu_ih_ring_alloc(adev);
}
+ return 0;
}
/**
* amdgpu_ih_ring_fini - tear down the IH state
*
* @adev: amdgpu_device pointer
+ * @ih: ih ring to tear down
*
* Tears down the IH state and frees buffer
* used for the IH ring buffer.
*/
-void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
+void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
{
- if (adev->irq.ih.use_bus_addr) {
- if (adev->irq.ih.ring) {
- /* add 8 bytes for the rptr/wptr shadows and
- * add them to the end of the ring allocation.
- */
- pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
- (void *)adev->irq.ih.ring,
- adev->irq.ih.rb_dma_addr);
- adev->irq.ih.ring = NULL;
- }
+ if (ih->use_bus_addr) {
+ if (!ih->ring)
+ return;
+
+ /* add 8 bytes for the rptr/wptr shadows and
+ * add them to the end of the ring allocation.
+ */
+ dma_free_coherent(adev->dev, ih->ring_size + 8,
+ (void *)ih->ring, ih->rb_dma_addr);
+ ih->ring = NULL;
} else {
- amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
- &adev->irq.ih.gpu_addr,
- (void **)&adev->irq.ih.ring);
- amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
- amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
+ amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
+ (void **)&ih->ring);
+ amdgpu_device_wb_free(adev, ih->wptr_offs);
+ amdgpu_device_wb_free(adev, ih->rptr_offs);
}
}
@@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
* amdgpu_ih_process - interrupt handler
*
* @adev: amdgpu_device pointer
+ * @ih: ih ring to process
*
* Interrupt hander (VI), walk the IH ring.
* Returns irq process return code.
*/
-int amdgpu_ih_process(struct amdgpu_device *adev)
+int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
{
struct amdgpu_iv_entry entry;
u32 wptr;
- if (!adev->irq.ih.enabled || adev->shutdown)
+ if (!ih->enabled || adev->shutdown)
return IRQ_NONE;
wptr = amdgpu_ih_get_wptr(adev);
restart_ih:
/* is somebody else already processing irqs? */
- if (atomic_xchg(&adev->irq.ih.lock, 1))
+ if (atomic_xchg(&ih->lock, 1))
return IRQ_NONE;
- DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
+ DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
/* Order reading of wptr vs. reading of IH ring data */
rmb();
- while (adev->irq.ih.rptr != wptr) {
- u32 ring_index = adev->irq.ih.rptr >> 2;
+ while (ih->rptr != wptr) {
+ u32 ring_index = ih->rptr >> 2;
/* Prescreening of high-frequency interrupts */
if (!amdgpu_ih_prescreen_iv(adev)) {
- adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
+ ih->rptr &= ih->ptr_mask;
continue;
}
/* Before dispatching irq to IP blocks, send it to amdkfd */
amdgpu_amdkfd_interrupt(adev,
- (const void *) &adev->irq.ih.ring[ring_index]);
+ (const void *) &ih->ring[ring_index]);
- entry.iv_entry = (const uint32_t *)
- &adev->irq.ih.ring[ring_index];
+ entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
amdgpu_ih_decode_iv(adev, &entry);
- adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
+ ih->rptr &= ih->ptr_mask;
amdgpu_irq_dispatch(adev, &entry);
}
amdgpu_ih_set_rptr(adev);
- atomic_set(&adev->irq.ih.lock, 0);
+ atomic_set(&ih->lock, 0);
/* make sure wptr hasn't changed while processing */
wptr = amdgpu_ih_get_wptr(adev);
- if (wptr != adev->irq.ih.rptr)
+ if (wptr != ih->rptr)
goto restart_ih;
return IRQ_HANDLED;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 0d5b3f5201d2..3e55f985005c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
-int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
- bool use_bus_addr);
-void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
-int amdgpu_ih_process(struct amdgpu_device *adev);
+int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ unsigned ring_size, bool use_bus_addr);
+void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index b927e8798534..aaa8545e458a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
struct amdgpu_device *adev = dev->dev_private;
irqreturn_t ret;
- ret = amdgpu_ih_process(adev);
+ ret = amdgpu_ih_process(adev, &adev->irq.ih);
if (ret == IRQ_HANDLED)
pm_runtime_mark_last_busy(dev->dev);
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index e75183e09820..c37c4b76e7e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
if (r)
return r;
@@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
amdgpu_irq_remove_domain(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 9385da1e1e40..306e0bd154fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
if (r)
return r;
@@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
amdgpu_irq_remove_domain(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 45ef0a818e11..9005deeec612 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
if (r)
return r;
@@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
amdgpu_irq_remove_domain(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 97711d327527..acdf6075957a 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
if (r)
return r;
@@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index a79a3776888a..83fdf810ffc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
if (r)
return r;
@@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
amdgpu_irq_remove_domain(adev);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 37487b4cbd6e..a99f71797aa3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
if (r)
return r;
@@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
- amdgpu_ih_ring_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih);
return 0;
}
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 2/9] drm/amdgpu: make function pointers mandatory Christian König
2018-09-24 12:38 ` [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h Christian König
` (5 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Add a callback to amdgpu_ih_process to remove most of the IV logic.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 24 +++++-------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 31 ++++++++++++++++++++++++++++++-
3 files changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 15fb0f9738ab..8af67f649660 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -24,7 +24,6 @@
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_ih.h"
-#include "amdgpu_amdkfd.h"
/**
* amdgpu_ih_ring_init - initialize the IH state
@@ -129,9 +128,10 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
* Interrupt hander (VI), walk the IH ring.
* Returns irq process return code.
*/
-int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
+int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ void (*callback)(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih))
{
- struct amdgpu_iv_entry entry;
u32 wptr;
if (!ih->enabled || adev->shutdown)
@@ -150,24 +150,10 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
rmb();
while (ih->rptr != wptr) {
- u32 ring_index = ih->rptr >> 2;
-
- /* Prescreening of high-frequency interrupts */
- if (!amdgpu_ih_prescreen_iv(adev)) {
- ih->rptr &= ih->ptr_mask;
- continue;
- }
-
- /* Before dispatching irq to IP blocks, send it to amdkfd */
- amdgpu_amdkfd_interrupt(adev,
- (const void *) &ih->ring[ring_index]);
-
- entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
- amdgpu_ih_decode_iv(adev, &entry);
+ callback(adev, ih);
ih->rptr &= ih->ptr_mask;
-
- amdgpu_irq_dispatch(adev, &entry);
}
+
amdgpu_ih_set_rptr(adev);
atomic_set(&ih->lock, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 3e55f985005c..fd2bbaa20ab4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -85,6 +85,8 @@ struct amdgpu_ih_funcs {
int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned ring_size, bool use_bus_addr);
void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
-int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+ void (*callback)(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih));
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index aaa8545e458a..2fca08e130b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -51,6 +51,7 @@
#include "atom.h"
#include "amdgpu_connectors.h"
#include "amdgpu_trace.h"
+#include "amdgpu_amdkfd.h"
#include <linux/pm_runtime.h>
@@ -146,6 +147,34 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
spin_unlock_irqrestore(&adev->irq.lock, irqflags);
}
+/**
+ * amdgpu_irq_callback - callback from the IH ring
+ *
+ * @adev: amdgpu device pointer
+ * @ih: amdgpu ih ring
+ *
+ * Callback from IH ring processing to handle the entry at the current position
+ * and advance the read pointer.
+ */
+static void amdgpu_irq_callback(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
+{
+ u32 ring_index = ih->rptr >> 2;
+ struct amdgpu_iv_entry entry;
+
+ /* Prescreening of high-frequency interrupts */
+ if (!amdgpu_ih_prescreen_iv(adev))
+ return;
+
+ /* Before dispatching irq to IP blocks, send it to amdkfd */
+ amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
+
+ entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
+ amdgpu_ih_decode_iv(adev, &entry);
+
+ amdgpu_irq_dispatch(adev, &entry);
+}
+
/**
* amdgpu_irq_handler - IRQ handler
*
@@ -163,7 +192,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
struct amdgpu_device *adev = dev->dev_private;
irqreturn_t ret;
- ret = amdgpu_ih_process(adev, &adev->irq.ih);
+ ret = amdgpu_ih_process(adev, &adev->irq.ih, amdgpu_irq_callback);
if (ret == IRQ_HANDLED)
pm_runtime_mark_last_busy(dev->dev);
return ret;
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-5-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs Christian König
` (4 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Everything that isn't related to the IH ring.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 22 +-------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 10 ++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 25 ++++++++++++++++++++---
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++++------
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 2 +-
35 files changed, 94 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index fd2bbaa20ab4..9ce8c93ec19b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -24,12 +24,8 @@
#ifndef __AMDGPU_IH_H__
#define __AMDGPU_IH_H__
-#include "soc15_ih_clientid.h"
-
struct amdgpu_device;
-
-#define AMDGPU_IH_CLIENTID_LEGACY 0
-#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
+struct amdgpu_iv_entry;
/*
* R6xx+ IH ring
@@ -51,22 +47,6 @@ struct amdgpu_ih_ring {
dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
};
-#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
-
-struct amdgpu_iv_entry {
- unsigned client_id;
- unsigned src_id;
- unsigned ring_id;
- unsigned vmid;
- unsigned vmid_src;
- uint64_t timestamp;
- unsigned timestamp_src;
- unsigned pasid;
- unsigned pasid_src;
- unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
- const uint32_t *iv_entry;
-};
-
/* provided by the ih block */
struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 2fca08e130b6..52c17f6219a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -124,7 +124,7 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
int r;
spin_lock_irqsave(&adev->irq.lock, irqflags);
- for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+ for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
@@ -302,7 +302,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
cancel_work_sync(&adev->reset_work);
}
- for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+ for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
@@ -342,7 +342,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev,
unsigned client_id, unsigned src_id,
struct amdgpu_irq_src *source)
{
- if (client_id >= AMDGPU_IH_CLIENTID_MAX)
+ if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
return -EINVAL;
if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
@@ -396,7 +396,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
trace_amdgpu_iv(entry);
- if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
+ if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
return;
}
@@ -469,7 +469,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
{
int i, j, k;
- for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+ for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
if (!adev->irq.client[i].sources)
continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index 3375ad778edc..f6ce171cb8aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -25,19 +25,38 @@
#define __AMDGPU_IRQ_H__
#include <linux/irqdomain.h>
+#include "soc15_ih_clientid.h"
#include "amdgpu_ih.h"
-#define AMDGPU_MAX_IRQ_SRC_ID 0x100
+#define AMDGPU_MAX_IRQ_SRC_ID 0x100
#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
+#define AMDGPU_IRQ_CLIENTID_LEGACY 0
+#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
+
+#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
+
struct amdgpu_device;
-struct amdgpu_iv_entry;
enum amdgpu_interrupt_state {
AMDGPU_IRQ_STATE_DISABLE,
AMDGPU_IRQ_STATE_ENABLE,
};
+struct amdgpu_iv_entry {
+ unsigned client_id;
+ unsigned src_id;
+ unsigned ring_id;
+ unsigned vmid;
+ unsigned vmid_src;
+ uint64_t timestamp;
+ unsigned timestamp_src;
+ unsigned pasid;
+ unsigned pasid_src;
+ unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
+ const uint32_t *iv_entry;
+};
+
struct amdgpu_irq_src {
unsigned num_types;
atomic_t *enabled_types;
@@ -63,7 +82,7 @@ struct amdgpu_irq {
bool installed;
spinlock_t lock;
/* interrupt sources */
- struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX];
+ struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
/* status, etc. */
bool msi_enabled; /* msi enabled */
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index d2469453dca2..79220a91abe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6277,12 +6277,12 @@ static int ci_dpm_sw_init(void *handle)
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
&adev->pm.dpm.thermal.irq);
if (ret)
return ret;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
&adev->pm.dpm.thermal.irq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index c37c4b76e7e9..b5775c6a857b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -276,7 +276,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index ee9d5c92edb1..b918c8886b75 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -970,19 +970,19 @@ static int cik_sdma_sw_init(void *handle)
}
/* SDMA trap event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
&adev->sdma.trap_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 306e0bd154fa..df5ac4d85a00 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -255,7 +255,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 89c09c396fe6..4cfecdce29a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2746,19 +2746,19 @@ static int dce_v10_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
if (r)
return r;
}
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
if (r)
return r;
}
/* HPD hotplug */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index cf6faaa05dbb..7c868916d90f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2867,19 +2867,19 @@ static int dce_v11_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
if (r)
return r;
}
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
if (r)
return r;
}
/* HPD hotplug */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 371aa05bf537..17eaaba36017 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2616,19 +2616,19 @@ static int dce_v6_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
if (r)
return r;
}
for (i = 8; i < 20; i += 2) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
if (r)
return r;
}
/* HPD hotplug */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 30e76f2407c2..8c0576978d36 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2643,19 +2643,19 @@ static int dce_v8_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
if (r)
return r;
}
for (i = 8; i < 20; i += 2) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
if (r)
return r;
}
/* HPD hotplug */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 2cc480d65394..fdace004544d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -372,7 +372,7 @@ static int dce_virtual_sw_init(void *handle)
int r, i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index de184a886057..7cda0031bd57 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3094,15 +3094,15 @@ static int gfx_v6_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i, r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index fc39ebbc9d9f..90f030acb685 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4516,18 +4516,18 @@ static int gfx_v7_0_sw_init(void *handle)
adev->gfx.mec.num_queue_per_pipe = 8;
/* EOP Event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
if (r)
return r;
/* Privileged reg */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
&adev->gfx.priv_reg_irq);
if (r)
return r;
/* Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
&adev->gfx.priv_inst_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 470dc80f4fe7..b6160de70d12 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2049,35 +2049,35 @@ static int gfx_v8_0_sw_init(void *handle)
adev->gfx.mec.num_queue_per_pipe = 8;
/* KIQ event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
if (r)
return r;
/* EOP Event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
if (r)
return r;
/* Privileged reg */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
&adev->gfx.priv_reg_irq);
if (r)
return r;
/* Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
&adev->gfx.priv_inst_irq);
if (r)
return r;
/* Add CP EDC/ECC irq */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
&adev->gfx.cp_ecc_error_irq);
if (r)
return r;
/* SQ interrupts. */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
&adev->gfx.sq_irq);
if (r) {
DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 3b8ac4442f06..e1c2b4e9c7b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -859,11 +859,11 @@ static int gmc_v6_0_sw_init(void *handle)
adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
}
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 899634ce4238..910c4ce19cb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -991,11 +991,11 @@ static int gmc_v7_0_sw_init(void *handle)
adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
}
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 79143ca7cfac..1d3265c97b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1095,11 +1095,11 @@ static int gmc_v8_0_sw_init(void *handle)
adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
}
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 9005deeec612..cf0fc61aebe6 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -255,7 +255,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index cb79a93c2eb7..d0e478f43443 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2995,12 +2995,12 @@ static int kv_dpm_sw_init(void *handle)
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
&adev->pm.dpm.thermal.irq);
if (ret)
return ret;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
&adev->pm.dpm.thermal.irq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 842567b53df5..64e875d528dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -580,11 +580,11 @@ int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
{
int r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
if (r)
return r;
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
if (r) {
amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0c5a576dee13..cd781abc4953 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -898,19 +898,19 @@ static int sdma_v2_4_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* SDMA trap event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
&adev->sdma.trap_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2587b8de918a..6d5c8ac64874 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1177,19 +1177,19 @@ static int sdma_v3_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* SDMA trap event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
&adev->sdma.trap_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
/* SDMA Privileged inst */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
&adev->sdma.illegal_inst_irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index c3510a703f9f..d4ceaf440f26 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -502,12 +502,12 @@ static int si_dma_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* DMA0 trap event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
if (r)
return r;
/* DMA1 trap event */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 1de96995e690..da58040fdbdc 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7687,11 +7687,11 @@ static int si_dpm_sw_init(void *handle)
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
if (ret)
return ret;
- ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
+ ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index acdf6075957a..b3d7d9f83202 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -142,7 +142,7 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 83fdf810ffc7..3abffd06b5c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -266,7 +266,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
- entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
entry->src_id = dw[0] & 0xff;
entry->src_data[0] = dw[1] & 0xfffffff;
entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 8a926d1df939..1fc17bf39fed 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -108,7 +108,7 @@ static int uvd_v4_2_sw_init(void *handle)
int r;
/* UVD TRAP */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 50248059412e..fde6ad5ac9ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -105,7 +105,7 @@ static int uvd_v5_0_sw_init(void *handle)
int r;
/* UVD TRAP */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 6ae82cc2e55e..8ef4a5392112 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -393,14 +393,14 @@ static int uvd_v6_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* UVD TRAP */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
if (r)
return r;
/* UVD ENC TRAP */
if (uvd_v6_0_enc_support(adev)) {
for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 7eaa54ba016b..ea28828360d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -417,7 +417,7 @@ static int vce_v2_0_sw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* VCE */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index c8390f9adfd6..6dbd39730070 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -423,7 +423,7 @@ static int vce_v3_0_sw_init(void *handle)
int r, i;
/* VCE */
- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
+ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0f10d920a785..8c821854a19a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1198,7 +1198,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
struct dc_interrupt_params int_params = {0};
int r;
int i;
- unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
+ unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 04b7da0e39a6..32a8c10d6666 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4106,17 +4106,17 @@ static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
source->funcs = &smu7_irq_funcs;
amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
- AMDGPU_IH_CLIENTID_LEGACY,
+ AMDGPU_IRQ_CLIENTID_LEGACY,
VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
source);
amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
- AMDGPU_IH_CLIENTID_LEGACY,
+ AMDGPU_IRQ_CLIENTID_LEGACY,
VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
source);
/* Register CTF(GPIO_19) interrupt */
amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
- AMDGPU_IH_CLIENTID_LEGACY,
+ AMDGPU_IRQ_CLIENTID_LEGACY,
VISLANDS30_IV_SRCID_GPIO_19,
source);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
index 2aab1b475945..8ad4e6960efd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
@@ -545,7 +545,7 @@ int phm_irq_process(struct amdgpu_device *adev,
uint32_t client_id = entry->client_id;
uint32_t src_id = entry->src_id;
- if (client_id == AMDGPU_IH_CLIENTID_LEGACY) {
+ if (client_id == AMDGPU_IRQ_CLIENTID_LEGACY) {
if (src_id == VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH)
pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
PCI_BUS_NUM(adev->pdev->devfn),
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-6-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr Christian König
` (3 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
One for the ring buffer and one for the IV handling.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++++++++++-
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 ++++++--
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 ++++++--
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 ++++++--
drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++++--
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 ++++++--
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 ++++++--
9 files changed, 52 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 9ce8c93ec19b..d88f82321ee4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -45,22 +45,19 @@ struct amdgpu_ih_ring {
bool use_doorbell;
bool use_bus_addr;
dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
+
+ const struct amdgpu_ih_funcs *funcs;
};
/* provided by the ih block */
struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
u32 (*get_wptr)(struct amdgpu_device *adev);
- bool (*prescreen_iv)(struct amdgpu_device *adev);
- void (*decode_iv)(struct amdgpu_device *adev,
- struct amdgpu_iv_entry *entry);
void (*set_rptr)(struct amdgpu_device *adev);
};
-#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
-#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
-#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
+#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
+#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned ring_size, bool use_bus_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 52c17f6219a7..8e5ce25f3fe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -163,14 +163,14 @@ static void amdgpu_irq_callback(struct amdgpu_device *adev,
struct amdgpu_iv_entry entry;
/* Prescreening of high-frequency interrupts */
- if (!amdgpu_ih_prescreen_iv(adev))
+ if (!amdgpu_irq_prescreen_iv(adev))
return;
/* Before dispatching irq to IP blocks, send it to amdkfd */
amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
- amdgpu_ih_decode_iv(adev, &entry);
+ amdgpu_irq_decode_iv(adev, &entry);
amdgpu_irq_dispatch(adev, &entry);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index f6ce171cb8aa..3cc0e7ce40a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -68,6 +68,12 @@ struct amdgpu_irq_client {
struct amdgpu_irq_src **sources;
};
+struct amdgpu_irq_funcs {
+ bool (*prescreen_iv)(struct amdgpu_device *adev);
+ void (*decode_iv)(struct amdgpu_device *adev,
+ struct amdgpu_iv_entry *entry);
+};
+
/* provided by interrupt generating IP blocks */
struct amdgpu_irq_src_funcs {
int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
@@ -89,12 +95,12 @@ struct amdgpu_irq {
/* interrupt ring */
struct amdgpu_ih_ring ih;
- const struct amdgpu_ih_funcs *ih_funcs;
/* gen irq stuff */
struct irq_domain *domain; /* GPU irq controller domain */
unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
uint32_t srbm_soft_reset;
+ const struct amdgpu_irq_funcs *funcs;
};
void amdgpu_irq_disable_all(struct amdgpu_device *adev);
@@ -121,4 +127,7 @@ int amdgpu_irq_add_domain(struct amdgpu_device *adev);
void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
+#define amdgpu_irq_prescreen_iv(adev) (adev)->irq.funcs->prescreen_iv((adev))
+#define amdgpu_irq_decode_iv(adev, iv) (adev)->irq.funcs->decode_iv((adev), (iv))
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index b5775c6a857b..161f0225749c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -461,14 +461,18 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cik_ih_funcs = {
.get_wptr = cik_ih_get_wptr,
+ .set_rptr = cik_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs cik_irq_funcs = {
.prescreen_iv = cik_ih_prescreen_iv,
.decode_iv = cik_ih_decode_iv,
- .set_rptr = cik_ih_set_rptr
};
static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &cik_ih_funcs;
+ adev->irq.ih.funcs = &cik_ih_funcs;
+ adev->irq.funcs = &cik_irq_funcs;
}
const struct amdgpu_ip_block_version cik_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index df5ac4d85a00..648ecd774611 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -442,14 +442,18 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
static const struct amdgpu_ih_funcs cz_ih_funcs = {
.get_wptr = cz_ih_get_wptr,
+ .set_rptr = cz_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs cz_irq_funcs = {
.prescreen_iv = cz_ih_prescreen_iv,
.decode_iv = cz_ih_decode_iv,
- .set_rptr = cz_ih_set_rptr
};
static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &cz_ih_funcs;
+ adev->irq.ih.funcs = &cz_ih_funcs;
+ adev->irq.funcs = &cz_irq_funcs;
}
const struct amdgpu_ip_block_version cz_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index cf0fc61aebe6..6139186ccd36 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -440,14 +440,18 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
static const struct amdgpu_ih_funcs iceland_ih_funcs = {
.get_wptr = iceland_ih_get_wptr,
+ .set_rptr = iceland_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs iceland_irq_funcs = {
.prescreen_iv = iceland_ih_prescreen_iv,
.decode_iv = iceland_ih_decode_iv,
- .set_rptr = iceland_ih_set_rptr
};
static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &iceland_ih_funcs;
+ adev->irq.ih.funcs = &iceland_ih_funcs;
+ adev->irq.funcs = &iceland_irq_funcs;
}
const struct amdgpu_ip_block_version iceland_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index b3d7d9f83202..16f212f3b534 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -301,14 +301,18 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
static const struct amdgpu_ih_funcs si_ih_funcs = {
.get_wptr = si_ih_get_wptr,
+ .set_rptr = si_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs si_irq_funcs = {
.prescreen_iv = si_ih_prescreen_iv,
.decode_iv = si_ih_decode_iv,
- .set_rptr = si_ih_set_rptr
};
static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &si_ih_funcs;
+ adev->irq.ih.funcs = &si_ih_funcs;
+ adev->irq.funcs = &si_irq_funcs;
}
const struct amdgpu_ip_block_version si_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 3abffd06b5c7..6120ac3c7667 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -506,14 +506,18 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
static const struct amdgpu_ih_funcs tonga_ih_funcs = {
.get_wptr = tonga_ih_get_wptr,
+ .set_rptr = tonga_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs tonga_irq_funcs = {
.prescreen_iv = tonga_ih_prescreen_iv,
.decode_iv = tonga_ih_decode_iv,
- .set_rptr = tonga_ih_set_rptr
};
static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &tonga_ih_funcs;
+ adev->irq.ih.funcs = &tonga_ih_funcs;
+ adev->irq.funcs = &tonga_irq_funcs;
}
const struct amdgpu_ip_block_version tonga_ih_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a99f71797aa3..a9737adf8392 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -487,14 +487,18 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
static const struct amdgpu_ih_funcs vega10_ih_funcs = {
.get_wptr = vega10_ih_get_wptr,
+ .set_rptr = vega10_ih_set_rptr
+};
+
+static const struct amdgpu_irq_funcs vega10_irq_funcs = {
.prescreen_iv = vega10_ih_prescreen_iv,
.decode_iv = vega10_ih_decode_iv,
- .set_rptr = vega10_ih_set_rptr
};
static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
- adev->irq.ih_funcs = &vega10_ih_funcs;
+ adev->irq.ih.funcs = &vega10_ih_funcs;
+ adev->irq.funcs = &vega10_irq_funcs;
}
const struct amdgpu_ip_block_version vega10_ih_ip_block =
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-7-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 8/9] drm/amdgpu: simplify IH programming Christian König
` (2 subsequent siblings)
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Let's start to support multiple rings.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 ++++----
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 16 +++++++++-------
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 16 +++++++++-------
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 16 +++++++++-------
drivers/gpu/drm/amd/amdgpu/si_ih.c | 16 +++++++++-------
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 28 +++++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 32 +++++++++++++++++---------------
8 files changed, 75 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 8af67f649660..fb8dd6179926 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -137,7 +137,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
if (!ih->enabled || adev->shutdown)
return IRQ_NONE;
- wptr = amdgpu_ih_get_wptr(adev);
+ wptr = amdgpu_ih_get_wptr(adev, ih);
restart_ih:
/* is somebody else already processing irqs? */
@@ -154,11 +154,11 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
ih->rptr &= ih->ptr_mask;
}
- amdgpu_ih_set_rptr(adev);
+ amdgpu_ih_set_rptr(adev, ih);
atomic_set(&ih->lock, 0);
/* make sure wptr hasn't changed while processing */
- wptr = amdgpu_ih_get_wptr(adev);
+ wptr = amdgpu_ih_get_wptr(adev, ih);
if (wptr != ih->rptr)
goto restart_ih;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index d88f82321ee4..61967e7b64a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -52,12 +52,12 @@ struct amdgpu_ih_ring {
/* provided by the ih block */
struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
- u32 (*get_wptr)(struct amdgpu_device *adev);
- void (*set_rptr)(struct amdgpu_device *adev);
+ u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+ void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
};
-#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
-#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
+#define amdgpu_ih_get_wptr(adev, ih) (ih)->funcs->get_wptr((adev), (ih))
+#define amdgpu_ih_set_rptr(adev, ih) (ih)->funcs->set_rptr((adev), (ih))
int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
unsigned ring_size, bool use_bus_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 161f0225749c..341092768809 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -183,11 +183,12 @@ static void cik_ih_irq_disable(struct amdgpu_device *adev)
* Used by cik_irq_process().
* Returns the value of the wptr.
*/
-static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
+static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
@@ -196,13 +197,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
* this should allow us to catchup.
*/
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
- adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+ ih->rptr = (wptr + 16) & ih->ptr_mask;
tmp = RREG32(mmIH_RB_CNTL);
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(mmIH_RB_CNTL, tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/* CIK IV Ring
@@ -294,9 +295,10 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
*
* Set the IH ring buffer rptr.
*/
-static void cik_ih_set_rptr(struct amdgpu_device *adev)
+static void cik_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32(mmIH_RB_RPTR, ih->rptr);
}
static int cik_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 648ecd774611..6ed750187ad7 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -185,11 +185,12 @@ static void cz_ih_irq_disable(struct amdgpu_device *adev)
* Used by cz_irq_process(VI).
* Returns the value of the wptr.
*/
-static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
+static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -198,13 +199,13 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
* this should allow us to catchup.
*/
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
- adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+ ih->rptr = (wptr + 16) & ih->ptr_mask;
tmp = RREG32(mmIH_RB_CNTL);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/**
@@ -273,9 +274,10 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
*
* Set the IH ring buffer rptr.
*/
-static void cz_ih_set_rptr(struct amdgpu_device *adev)
+static void cz_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32(mmIH_RB_RPTR, ih->rptr);
}
static int cz_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 6139186ccd36..c779d708c306 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -185,11 +185,12 @@ static void iceland_ih_irq_disable(struct amdgpu_device *adev)
* Used by cz_irq_process(VI).
* Returns the value of the wptr.
*/
-static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
+static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -198,13 +199,13 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
* this should allow us to catchup.
*/
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
- adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+ ih->rptr = (wptr + 16) & ih->ptr_mask;
tmp = RREG32(mmIH_RB_CNTL);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/**
@@ -273,9 +274,10 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
*
* Set the IH ring buffer rptr.
*/
-static void iceland_ih_set_rptr(struct amdgpu_device *adev)
+static void iceland_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32(mmIH_RB_RPTR, ih->rptr);
}
static int iceland_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 16f212f3b534..a005824d8b9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -100,22 +100,23 @@ static void si_ih_irq_disable(struct amdgpu_device *adev)
mdelay(1);
}
-static u32 si_ih_get_wptr(struct amdgpu_device *adev)
+static u32 si_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
- adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+ ih->rptr = (wptr + 16) & ih->ptr_mask;
tmp = RREG32(IH_RB_CNTL);
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(IH_RB_CNTL, tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/**
@@ -151,9 +152,10 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
adev->irq.ih.rptr += 16;
}
-static void si_ih_set_rptr(struct amdgpu_device *adev)
+static void si_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32(IH_RB_RPTR, ih->rptr);
}
static int si_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 6120ac3c7667..3618dc0c6804 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -193,14 +193,15 @@ static void tonga_ih_irq_disable(struct amdgpu_device *adev)
* Used by cz_irq_process(VI).
* Returns the value of the wptr.
*/
-static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
+static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
if (adev->irq.ih.use_bus_addr)
- wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
else
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -209,13 +210,13 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
* this should allow us to catchup.
*/
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
- adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+ ih->rptr = (wptr + 16) & ih->ptr_mask;
tmp = RREG32(mmIH_RB_CNTL);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/**
@@ -284,17 +285,18 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
*
* Set the IH ring buffer rptr.
*/
-static void tonga_ih_set_rptr(struct amdgpu_device *adev)
+static void tonga_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- if (adev->irq.ih.use_doorbell) {
+ if (ih->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- if (adev->irq.ih.use_bus_addr)
- adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
+ if (ih->use_bus_addr)
+ ih->ring[ih->rptr_offs] = ih->rptr;
else
- adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
- WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
+ adev->wb.wb[ih->rptr_offs] = ih->rptr;
+ WDOORBELL32(ih->doorbell_index, ih->rptr);
} else {
- WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32(mmIH_RB_RPTR, ih->rptr);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a9737adf8392..12d4e3ec851e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -191,14 +191,15 @@ static void vega10_ih_irq_disable(struct amdgpu_device *adev)
* ring buffer overflow and deal with it.
* Returns the value of the wptr.
*/
-static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
+static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
u32 wptr, tmp;
- if (adev->irq.ih.use_bus_addr)
- wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
+ if (ih->use_bus_addr)
+ wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
else
- wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+ wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -207,16 +208,16 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
* from the last not overwritten vector (wptr + 32). Hopefully
* this should allow us to catchup.
*/
- tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
+ tmp = (wptr + 32) & ih->ptr_mask;
dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
- wptr, adev->irq.ih.rptr, tmp);
- adev->irq.ih.rptr = tmp;
+ wptr, ih->rptr, tmp);
+ ih->rptr = tmp;
tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
}
- return (wptr & adev->irq.ih.ptr_mask);
+ return (wptr & ih->ptr_mask);
}
/**
@@ -353,17 +354,18 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
*
* Set the IH ring buffer rptr.
*/
-static void vega10_ih_set_rptr(struct amdgpu_device *adev)
+static void vega10_ih_set_rptr(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
{
- if (adev->irq.ih.use_doorbell) {
+ if (ih->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- if (adev->irq.ih.use_bus_addr)
- adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
+ if (ih->use_bus_addr)
+ ih->ring[ih->rptr_offs] = ih->rptr;
else
- adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
- WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
+ adev->wb.wb[ih->rptr_offs] = ih->rptr;
+ WDOORBELL32(ih->doorbell_index, ih->rptr);
} else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
}
}
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 8/9] drm/amdgpu: simplify IH programming
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-8-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2 Christian König
2018-09-25 9:54 ` [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace Huang Rui
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Calculate all the addresses and pointers in amdgpu_ih.c
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 34 +++++++++++++++++++++----------
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 23 ++++++++++++---------
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 ++++-----
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 11 +++++-----
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 9 ++++-----
drivers/gpu/drm/amd/amdgpu/si_ih.c | 9 ++++-----
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 27 +++++++------------------
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 36 +++++++++++----------------------
8 files changed, 73 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index fb8dd6179926..d0a5db777b6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
ih->use_bus_addr = use_bus_addr;
if (use_bus_addr) {
+ dma_addr_t dma_addr;
+
if (ih->ring)
return 0;
@@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
* add them to the end of the ring allocation.
*/
ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
- &ih->rb_dma_addr, GFP_KERNEL);
+ &dma_addr, GFP_KERNEL);
if (ih->ring == NULL)
return -ENOMEM;
memset((void *)ih->ring, 0, ih->ring_size + 8);
- ih->wptr_offs = (ih->ring_size / 4) + 0;
- ih->rptr_offs = (ih->ring_size / 4) + 1;
+ ih->gpu_addr = dma_addr;
+ ih->wptr_addr = dma_addr + ih->ring_size;
+ ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
+ ih->rptr_addr = dma_addr + ih->ring_size + 4;
+ ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
} else {
- r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
+ unsigned wptr_offs, rptr_offs;
+
+ r = amdgpu_device_wb_get(adev, &wptr_offs);
if (r)
return r;
- r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
+ r = amdgpu_device_wb_get(adev, &rptr_offs);
if (r) {
- amdgpu_device_wb_free(adev, ih->wptr_offs);
+ amdgpu_device_wb_free(adev, wptr_offs);
return r;
}
@@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
&ih->ring_obj, &ih->gpu_addr,
(void **)&ih->ring);
if (r) {
- amdgpu_device_wb_free(adev, ih->rptr_offs);
- amdgpu_device_wb_free(adev, ih->wptr_offs);
+ amdgpu_device_wb_free(adev, rptr_offs);
+ amdgpu_device_wb_free(adev, wptr_offs);
return r;
}
+
+ ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
+ ih->wptr_cpu = &adev->wb.wb[wptr_offs];
+ ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
+ ih->rptr_cpu = &adev->wb.wb[rptr_offs];
}
return 0;
}
@@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
* add them to the end of the ring allocation.
*/
dma_free_coherent(adev->dev, ih->ring_size + 8,
- (void *)ih->ring, ih->rb_dma_addr);
+ (void *)ih->ring, ih->gpu_addr);
ih->ring = NULL;
} else {
amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
(void **)&ih->ring);
- amdgpu_device_wb_free(adev, ih->wptr_offs);
- amdgpu_device_wb_free(adev, ih->rptr_offs);
+ amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
+ amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 61967e7b64a7..6af047b64cf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -31,20 +31,25 @@ struct amdgpu_iv_entry;
* R6xx+ IH ring
*/
struct amdgpu_ih_ring {
- struct amdgpu_bo *ring_obj;
- volatile uint32_t *ring;
- unsigned rptr;
unsigned ring_size;
- uint64_t gpu_addr;
uint32_t ptr_mask;
- atomic_t lock;
- bool enabled;
- unsigned wptr_offs;
- unsigned rptr_offs;
u32 doorbell_index;
bool use_doorbell;
bool use_bus_addr;
- dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
+
+ struct amdgpu_bo *ring_obj;
+ volatile uint32_t *ring;
+ uint64_t gpu_addr;
+
+ uint64_t wptr_addr;
+ volatile uint32_t *wptr_cpu;
+
+ uint64_t rptr_addr;
+ volatile uint32_t *rptr_cpu;
+
+ bool enabled;
+ unsigned rptr;
+ atomic_t lock;
const struct amdgpu_ih_funcs *funcs;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 341092768809..2358ab32c16c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int cik_ih_irq_init(struct amdgpu_device *adev)
{
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
int rb_bufsz;
u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
- u64 wptr_off;
/* disable irqs */
cik_ih_disable_interrupts(adev);
@@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)
ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
/* set the writeback address whether it's enabled or not */
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -188,7 +187,7 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 6ed750187ad7..2d2029cd15e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -103,9 +103,9 @@ static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int cz_ih_irq_init(struct amdgpu_device *adev)
{
- int rb_bufsz;
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
- u64 wptr_off;
+ int rb_bufsz;
/* disable irqs */
cz_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
/* set the writeback address whether it's enabled or not */
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -190,7 +189,7 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index c779d708c306..337fc38c6bca 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -103,9 +103,9 @@ static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int iceland_ih_irq_init(struct amdgpu_device *adev)
{
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
int rb_bufsz;
u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
- u64 wptr_off;
/* disable irqs */
iceland_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
/* set the writeback address whether it's enabled or not */
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
@@ -190,7 +189,7 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index a005824d8b9a..574efa2a4f0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -57,9 +57,9 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev)
static int si_ih_irq_init(struct amdgpu_device *adev)
{
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
int rb_bufsz;
u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
- u64 wptr_off;
si_ih_disable_interrupts(adev);
WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
@@ -76,9 +76,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
(rb_bufsz << 1) |
IH_WPTR_WRITEBACK_ENABLE;
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+ WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
WREG32(IH_RB_CNTL, ih_rb_cntl);
WREG32(IH_RB_RPTR, 0);
WREG32(IH_RB_WPTR, 0);
@@ -105,7 +104,7 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 3618dc0c6804..966c0782f743 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -99,9 +99,9 @@ static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int tonga_ih_irq_init(struct amdgpu_device *adev)
{
- int rb_bufsz;
u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
- u64 wptr_off;
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
+ int rb_bufsz;
/* disable irqs */
tonga_ih_disable_interrupts(adev);
@@ -118,10 +118,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
- if (adev->irq.ih.use_bus_addr)
- WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
- else
- WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
+ WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
@@ -136,12 +133,8 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
WREG32(mmIH_RB_CNTL, ih_rb_cntl);
/* set the writeback address whether it's enabled or not */
- if (adev->irq.ih.use_bus_addr)
- wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
- else
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+ WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
/* set rptr, wptr to 0 */
WREG32(mmIH_RB_RPTR, 0);
@@ -198,10 +191,7 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- if (adev->irq.ih.use_bus_addr)
- wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
- else
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -290,10 +280,7 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev,
{
if (ih->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- if (ih->use_bus_addr)
- ih->ring[ih->rptr_offs] = ih->rptr;
- else
- adev->wb.wb[ih->rptr_offs] = ih->rptr;
+ *ih->rptr_cpu = ih->rptr;
WDOORBELL32(ih->doorbell_index, ih->rptr);
} else {
WREG32(mmIH_RB_RPTR, ih->rptr);
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 12d4e3ec851e..b4330eccee04 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -86,11 +86,11 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int vega10_ih_irq_init(struct amdgpu_device *adev)
{
+ struct amdgpu_ih_ring *ih = &adev->irq.ih;
int ret = 0;
int rb_bufsz;
u32 ih_rb_cntl, ih_doorbell_rtpr;
u32 tmp;
- u64 wptr_off;
/* disable irqs */
vega10_ih_disable_interrupts(adev);
@@ -99,15 +99,11 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
- if (adev->irq.ih.use_bus_addr) {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
- } else {
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
- }
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI,
+ (adev->irq.ih.gpu_addr >> 40) & 0xff);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE,
+ ih->use_bus_addr ? 1 : 4);
rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
@@ -124,12 +120,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set the writeback address whether it's enabled or not */
- if (adev->irq.ih.use_bus_addr)
- wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
- else
- wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
+ lower_32_bits(ih->wptr_addr));
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
+ upper_32_bits(ih->wptr_addr) & 0xFF);
/* set rptr, wptr to 0 */
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
@@ -196,10 +190,7 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
{
u32 wptr, tmp;
- if (ih->use_bus_addr)
- wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
- else
- wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
+ wptr = le32_to_cpu(*ih->wptr_cpu);
if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -359,10 +350,7 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
{
if (ih->use_doorbell) {
/* XXX check if swapping is necessary on BE */
- if (ih->use_bus_addr)
- ih->ring[ih->rptr_offs] = ih->rptr;
- else
- adev->wb.wb[ih->rptr_offs] = ih->rptr;
+ *ih->rptr_cpu = ih->rptr;
WDOORBELL32(ih->doorbell_index, ih->rptr);
} else {
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 8/9] drm/amdgpu: simplify IH programming Christian König
@ 2018-09-24 12:38 ` Christian König
[not found] ` <20180924123820.1873-9-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-25 9:54 ` [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace Huang Rui
8 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-24 12:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
The entries are ignored for now, but it at least stops crashing the
hardware when somebody tries to push something to the other IH rings.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 4 +-
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 129 +++++++++++++++++++++++++-------
2 files changed, 106 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index 3cc0e7ce40a0..0c6af0b38490 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -93,8 +93,8 @@ struct amdgpu_irq {
/* status, etc. */
bool msi_enabled; /* msi enabled */
- /* interrupt ring */
- struct amdgpu_ih_ring ih;
+ /* interrupt rings */
+ struct amdgpu_ih_ring ih, ih1, ih2;
/* gen irq stuff */
struct irq_domain *domain; /* GPU irq controller domain */
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index b4330eccee04..2d2036e0c8b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -50,6 +50,16 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
adev->irq.ih.enabled = true;
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, RB_ENABLE, 1);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ adev->irq.ih1.enabled = true;
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, RB_ENABLE, 1);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ adev->irq.ih2.enabled = true;
}
/**
@@ -71,6 +81,47 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
adev->irq.ih.enabled = false;
adev->irq.ih.rptr = 0;
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, RB_ENABLE, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+ adev->irq.ih1.enabled = false;
+ adev->irq.ih1.rptr = 0;
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, RB_ENABLE, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+ adev->irq.ih2.enabled = false;
+ adev->irq.ih2.rptr = 0;
+}
+
+static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
+{
+ int rb_bufsz = order_base_2(ih->ring_size / 4);
+
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ MC_SPACE, ih->use_bus_addr ? 1 : 4);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ WPTR_OVERFLOW_CLEAR, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ WPTR_OVERFLOW_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
+ /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
+ * value is written to memory
+ */
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+ WPTR_WRITEBACK_ENABLE, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
+
+ return ih_rb_cntl;
}
/**
@@ -86,9 +137,8 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
*/
static int vega10_ih_irq_init(struct amdgpu_device *adev)
{
- struct amdgpu_ih_ring *ih = &adev->irq.ih;
+ struct amdgpu_ih_ring *ih;
int ret = 0;
- int rb_bufsz;
u32 ih_rb_cntl, ih_doorbell_rtpr;
u32 tmp;
@@ -97,26 +147,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
adev->nbio_funcs->ih_control(adev);
- ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+ ih = &adev->irq.ih;
/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
- WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI,
- (adev->irq.ih.gpu_addr >> 40) & 0xff);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE,
- ih->use_bus_addr ? 1 : 4);
- rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
- /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
-
- if (adev->irq.msi_enabled)
- ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+ ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+ ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
+ !!adev->irq.msi_enabled);
WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
/* set the writeback address whether it's enabled or not */
@@ -131,18 +170,49 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
if (adev->irq.ih.use_doorbell) {
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
- OFFSET, adev->irq.ih.doorbell_index);
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+ IH_DOORBELL_RPTR, OFFSET,
+ adev->irq.ih.doorbell_index);
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+ IH_DOORBELL_RPTR,
ENABLE, 1);
} else {
- ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
+ ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+ IH_DOORBELL_RPTR,
ENABLE, 0);
}
WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
adev->irq.ih.doorbell_index);
+ ih = &adev->irq.ih1;
+ /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
+ (ih->gpu_addr >> 40) & 0xff);
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+
+ ih = &adev->irq.ih2;
+ /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
+ (ih->gpu_addr >> 40) & 0xff);
+
+ ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+ ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+
+ /* set rptr, wptr to 0 */
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+ WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+
tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
CLIENT18_IS_STORM_CLIENT, 1);
@@ -333,7 +403,6 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
entry->src_data[2] = dw[6];
entry->src_data[3] = dw[7];
-
/* wptr/rptr are in bytes! */
adev->irq.ih.rptr += 32;
}
@@ -374,6 +443,14 @@ static int vega10_ih_sw_init(void *handle)
if (r)
return r;
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, 256 * 1024, true);
+ if (r)
+ return r;
+
+ r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, 256 * 1024, true);
+ if (r)
+ return r;
+
adev->irq.ih.use_doorbell = true;
adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
@@ -387,6 +464,8 @@ static int vega10_ih_sw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
amdgpu_irq_fini(adev);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
+ amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
amdgpu_ih_ring_fini(adev, &adev->irq.ih);
return 0;
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2018-09-24 12:38 ` [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2 Christian König
@ 2018-09-25 9:54 ` Huang Rui
8 siblings, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-25 9:54 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:12PM +0200, Christian König wrote:
> That is superflous here.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 2e87414422f9..e9bf70e2ac51 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -103,7 +103,7 @@ TRACE_EVENT(amdgpu_iv,
> __entry->src_data[2] = iv->src_data[2];
> __entry->src_data[3] = iv->src_data[3];
> ),
> - TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x\n",
> + TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
> __entry->client_id, __entry->src_id,
> __entry->ring_id, __entry->vmid,
> __entry->timestamp, __entry->pasid,
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/9] drm/amdgpu: make function pointers mandatory
[not found] ` <20180924123820.1873-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-25 10:03 ` Huang Rui
0 siblings, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-25 10:03 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:13PM +0200, Christian König wrote:
> We always want those to be setup correctly.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 20 ++++++++------------
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 20 ++++++++------------
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++++------------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 ++++++++------------
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 20 ++++++++------------
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 3 +--
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 3 +--
> 20 files changed, 55 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 44d10c2172f6..e75183e09820 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -468,8 +468,7 @@ static const struct amdgpu_ih_funcs cik_ih_funcs = {
>
> static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &cik_ih_funcs;
> + adev->irq.ih_funcs = &cik_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version cik_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 154b1499b07e..ee9d5c92edb1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1370,10 +1370,8 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
>
> static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mman.buffer_funcs == NULL) {
> - adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
> - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> - }
> + adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
> + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>
> static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
> @@ -1389,15 +1387,13 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
> struct drm_gpu_scheduler *sched;
> unsigned i;
>
> - if (adev->vm_manager.vm_pte_funcs == NULL) {
> - adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_rqs[i] =
> - &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> - }
> - adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> + adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_rqs[i] =
> + &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> + adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
>
> const struct amdgpu_ip_block_version cik_sdma_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 960c29e17da6..9385da1e1e40 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -449,8 +449,7 @@ static const struct amdgpu_ih_funcs cz_ih_funcs = {
>
> static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &cz_ih_funcs;
> + adev->irq.ih_funcs = &cz_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version cz_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 3916aa6cc4ec..89c09c396fe6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3570,8 +3570,7 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
>
> static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mode_info.funcs == NULL)
> - adev->mode_info.funcs = &dce_v10_0_display_funcs;
> + adev->mode_info.funcs = &dce_v10_0_display_funcs;
> }
>
> static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 4ffb612a4e53..cf6faaa05dbb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3702,8 +3702,7 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
>
> static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mode_info.funcs == NULL)
> - adev->mode_info.funcs = &dce_v11_0_display_funcs;
> + adev->mode_info.funcs = &dce_v11_0_display_funcs;
> }
>
> static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 480c5348a14f..371aa05bf537 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3376,8 +3376,7 @@ static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
>
> static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mode_info.funcs == NULL)
> - adev->mode_info.funcs = &dce_v6_0_display_funcs;
> + adev->mode_info.funcs = &dce_v6_0_display_funcs;
> }
>
> static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 797196476c94..30e76f2407c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3458,8 +3458,7 @@ static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
>
> static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mode_info.funcs == NULL)
> - adev->mode_info.funcs = &dce_v8_0_display_funcs;
> + adev->mode_info.funcs = &dce_v8_0_display_funcs;
> }
>
> static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 15257634a53a..2cc480d65394 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -649,8 +649,7 @@ static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
>
> static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mode_info.funcs == NULL)
> - adev->mode_info.funcs = &dce_virtual_display_funcs;
> + adev->mode_info.funcs = &dce_virtual_display_funcs;
> }
>
> static int dce_virtual_pageflip(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 4411463ca719..3b8ac4442f06 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1180,8 +1180,7 @@ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
>
> static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
> {
> - if (adev->gmc.gmc_funcs == NULL)
> - adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
> + adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
> }
>
> static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index ae776ce9a415..899634ce4238 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1388,8 +1388,7 @@ static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
>
> static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
> {
> - if (adev->gmc.gmc_funcs == NULL)
> - adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
> + adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
> }
>
> static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 53ae49b8bde8..79143ca7cfac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1733,8 +1733,7 @@ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
>
> static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
> {
> - if (adev->gmc.gmc_funcs == NULL)
> - adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
> + adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
> }
>
> static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index aad3c7c5fb3a..f35d7a554ad5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -593,8 +593,7 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
>
> static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
> {
> - if (adev->gmc.gmc_funcs == NULL)
> - adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
> + adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
> }
>
> static int gmc_v9_0_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 842c4b677b4d..45ef0a818e11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -447,8 +447,7 @@ static const struct amdgpu_ih_funcs iceland_ih_funcs = {
>
> static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &iceland_ih_funcs;
> + adev->irq.ih_funcs = &iceland_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version iceland_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index c403bdf8ad70..0c5a576dee13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1296,10 +1296,8 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
>
> static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mman.buffer_funcs == NULL) {
> - adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
> - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> - }
> + adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
> + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>
> static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
> @@ -1315,15 +1313,13 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
> struct drm_gpu_scheduler *sched;
> unsigned i;
>
> - if (adev->vm_manager.vm_pte_funcs == NULL) {
> - adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_rqs[i] =
> - &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> - }
> - adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> + adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_rqs[i] =
> + &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> + adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
>
> const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 2677d6a1bf42..2587b8de918a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1736,10 +1736,8 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
>
> static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mman.buffer_funcs == NULL) {
> - adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
> - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> - }
> + adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
> + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>
> static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
> @@ -1755,15 +1753,13 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> struct drm_gpu_scheduler *sched;
> unsigned i;
>
> - if (adev->vm_manager.vm_pte_funcs == NULL) {
> - adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_rqs[i] =
> - &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> - }
> - adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> + adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_rqs[i] =
> + &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> + adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
>
> const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 9da4a1bff5c5..a3e2ed15fff2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1807,10 +1807,8 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
>
> static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mman.buffer_funcs == NULL) {
> - adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
> - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> - }
> + adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
> + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>
> static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
> @@ -1826,15 +1824,13 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> struct drm_gpu_scheduler *sched;
> unsigned i;
>
> - if (adev->vm_manager.vm_pte_funcs == NULL) {
> - adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_rqs[i] =
> - &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> - }
> - adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> + adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_rqs[i] =
> + &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> + adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
>
> const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index fafaf259b17b..c3510a703f9f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -863,10 +863,8 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = {
>
> static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
> {
> - if (adev->mman.buffer_funcs == NULL) {
> - adev->mman.buffer_funcs = &si_dma_buffer_funcs;
> - adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> - }
> + adev->mman.buffer_funcs = &si_dma_buffer_funcs;
> + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>
> static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
> @@ -882,15 +880,13 @@ static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
> struct drm_gpu_scheduler *sched;
> unsigned i;
>
> - if (adev->vm_manager.vm_pte_funcs == NULL) {
> - adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_rqs[i] =
> - &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> - }
> - adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> + adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_rqs[i] =
> + &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> }
> + adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
>
> const struct amdgpu_ip_block_version si_dma_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 60dad63098a2..97711d327527 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -308,8 +308,7 @@ static const struct amdgpu_ih_funcs si_ih_funcs = {
>
> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &si_ih_funcs;
> + adev->irq.ih_funcs = &si_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version si_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 52853d8a8fdd..a79a3776888a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -513,8 +513,7 @@ static const struct amdgpu_ih_funcs tonga_ih_funcs = {
>
> static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &tonga_ih_funcs;
> + adev->irq.ih_funcs = &tonga_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version tonga_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index acbe5a770207..37487b4cbd6e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -494,8 +494,7 @@ static const struct amdgpu_ih_funcs vega10_ih_funcs = {
>
> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - if (adev->irq.ih_funcs == NULL)
> - adev->irq.ih_funcs = &vega10_ih_funcs;
> + adev->irq.ih_funcs = &vega10_ih_funcs;
> }
>
> const struct amdgpu_ip_block_version vega10_ih_ip_block =
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
[not found] ` <20180924123820.1873-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-25 10:28 ` Huang Rui
2018-09-25 11:01 ` Christian König
0 siblings, 1 reply; 26+ messages in thread
From: Huang Rui @ 2018-09-25 10:28 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote:
> Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Will we have multiple interrupt rings in new asic?
Thanks,
Ray
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++++++++++++++------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
> 9 files changed, 84 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index 4ed86218cef3..15fb0f9738ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -26,44 +26,20 @@
> #include "amdgpu_ih.h"
> #include "amdgpu_amdkfd.h"
>
> -/**
> - * amdgpu_ih_ring_alloc - allocate memory for the IH ring
> - *
> - * @adev: amdgpu_device pointer
> - *
> - * Allocate a ring buffer for the interrupt controller.
> - * Returns 0 for success, errors for failure.
> - */
> -static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
> -{
> - int r;
> -
> - /* Allocate ring buffer */
> - if (adev->irq.ih.ring_obj == NULL) {
> - r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
> - PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
> - &adev->irq.ih.ring_obj,
> - &adev->irq.ih.gpu_addr,
> - (void **)&adev->irq.ih.ring);
> - if (r) {
> - DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
> - return r;
> - }
> - }
> - return 0;
> -}
> -
> /**
> * amdgpu_ih_ring_init - initialize the IH state
> *
> * @adev: amdgpu_device pointer
> + * @ih: ih ring to initialize
> + * @ring_size: ring size to allocate
> + * @use_bus_addr: true when we can use dma_alloc_coherent
> *
> * Initializes the IH state and allocates a buffer
> * for the IH ring buffer.
> * Returns 0 for success, errors for failure.
> */
> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
> - bool use_bus_addr)
> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> + unsigned ring_size, bool use_bus_addr)
> {
> u32 rb_bufsz;
> int r;
> @@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
> /* Align ring size */
> rb_bufsz = order_base_2(ring_size / 4);
> ring_size = (1 << rb_bufsz) * 4;
> - adev->irq.ih.ring_size = ring_size;
> - adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
> - adev->irq.ih.rptr = 0;
> - adev->irq.ih.use_bus_addr = use_bus_addr;
> -
> - if (adev->irq.ih.use_bus_addr) {
> - if (!adev->irq.ih.ring) {
> - /* add 8 bytes for the rptr/wptr shadows and
> - * add them to the end of the ring allocation.
> - */
> - adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
> - adev->irq.ih.ring_size + 8,
> - &adev->irq.ih.rb_dma_addr);
> - if (adev->irq.ih.ring == NULL)
> - return -ENOMEM;
> - memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
> - adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
> - adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
> - }
> - return 0;
> + ih->ring_size = ring_size;
> + ih->ptr_mask = ih->ring_size - 1;
> + ih->rptr = 0;
> + ih->use_bus_addr = use_bus_addr;
> +
> + if (use_bus_addr) {
> + if (ih->ring)
> + return 0;
> +
> + /* add 8 bytes for the rptr/wptr shadows and
> + * add them to the end of the ring allocation.
> + */
> + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
> + &ih->rb_dma_addr, GFP_KERNEL);
> + if (ih->ring == NULL)
> + return -ENOMEM;
> +
> + memset((void *)ih->ring, 0, ih->ring_size + 8);
> + ih->wptr_offs = (ih->ring_size / 4) + 0;
> + ih->rptr_offs = (ih->ring_size / 4) + 1;
> } else {
> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
> + r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
> + if (r)
> + return r;
> +
> + r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
> if (r) {
> - dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> return r;
> }
>
> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
> + r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> + &ih->ring_obj, &ih->gpu_addr,
> + (void **)&ih->ring);
> if (r) {
> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
> - dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> return r;
> }
> -
> - return amdgpu_ih_ring_alloc(adev);
> }
> + return 0;
> }
>
> /**
> * amdgpu_ih_ring_fini - tear down the IH state
> *
> * @adev: amdgpu_device pointer
> + * @ih: ih ring to tear down
> *
> * Tears down the IH state and frees buffer
> * used for the IH ring buffer.
> */
> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
> {
> - if (adev->irq.ih.use_bus_addr) {
> - if (adev->irq.ih.ring) {
> - /* add 8 bytes for the rptr/wptr shadows and
> - * add them to the end of the ring allocation.
> - */
> - pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
> - (void *)adev->irq.ih.ring,
> - adev->irq.ih.rb_dma_addr);
> - adev->irq.ih.ring = NULL;
> - }
> + if (ih->use_bus_addr) {
> + if (!ih->ring)
> + return;
> +
> + /* add 8 bytes for the rptr/wptr shadows and
> + * add them to the end of the ring allocation.
> + */
> + dma_free_coherent(adev->dev, ih->ring_size + 8,
> + (void *)ih->ring, ih->rb_dma_addr);
> + ih->ring = NULL;
> } else {
> - amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
> - &adev->irq.ih.gpu_addr,
> - (void **)&adev->irq.ih.ring);
> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
> - amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
> + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
> + (void **)&ih->ring);
> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> }
> }
>
> @@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
> * amdgpu_ih_process - interrupt handler
> *
> * @adev: amdgpu_device pointer
> + * @ih: ih ring to process
> *
> * Interrupt hander (VI), walk the IH ring.
> * Returns irq process return code.
> */
> -int amdgpu_ih_process(struct amdgpu_device *adev)
> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
> {
> struct amdgpu_iv_entry entry;
> u32 wptr;
>
> - if (!adev->irq.ih.enabled || adev->shutdown)
> + if (!ih->enabled || adev->shutdown)
> return IRQ_NONE;
>
> wptr = amdgpu_ih_get_wptr(adev);
>
> restart_ih:
> /* is somebody else already processing irqs? */
> - if (atomic_xchg(&adev->irq.ih.lock, 1))
> + if (atomic_xchg(&ih->lock, 1))
> return IRQ_NONE;
>
> - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
> + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
>
> /* Order reading of wptr vs. reading of IH ring data */
> rmb();
>
> - while (adev->irq.ih.rptr != wptr) {
> - u32 ring_index = adev->irq.ih.rptr >> 2;
> + while (ih->rptr != wptr) {
> + u32 ring_index = ih->rptr >> 2;
>
> /* Prescreening of high-frequency interrupts */
> if (!amdgpu_ih_prescreen_iv(adev)) {
> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> + ih->rptr &= ih->ptr_mask;
> continue;
> }
>
> /* Before dispatching irq to IP blocks, send it to amdkfd */
> amdgpu_amdkfd_interrupt(adev,
> - (const void *) &adev->irq.ih.ring[ring_index]);
> + (const void *) &ih->ring[ring_index]);
>
> - entry.iv_entry = (const uint32_t *)
> - &adev->irq.ih.ring[ring_index];
> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> amdgpu_ih_decode_iv(adev, &entry);
> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> + ih->rptr &= ih->ptr_mask;
>
> amdgpu_irq_dispatch(adev, &entry);
> }
> amdgpu_ih_set_rptr(adev);
> - atomic_set(&adev->irq.ih.lock, 0);
> + atomic_set(&ih->lock, 0);
>
> /* make sure wptr hasn't changed while processing */
> wptr = amdgpu_ih_get_wptr(adev);
> - if (wptr != adev->irq.ih.rptr)
> + if (wptr != ih->rptr)
> goto restart_ih;
>
> return IRQ_HANDLED;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index 0d5b3f5201d2..3e55f985005c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
> #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
> #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
>
> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
> - bool use_bus_addr);
> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
> -int amdgpu_ih_process(struct amdgpu_device *adev);
> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> + unsigned ring_size, bool use_bus_addr);
> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
>
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index b927e8798534..aaa8545e458a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
> struct amdgpu_device *adev = dev->dev_private;
> irqreturn_t ret;
>
> - ret = amdgpu_ih_process(adev);
> + ret = amdgpu_ih_process(adev, &adev->irq.ih);
> if (ret == IRQ_HANDLED)
> pm_runtime_mark_last_busy(dev->dev);
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index e75183e09820..c37c4b76e7e9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> if (r)
> return r;
>
> @@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> amdgpu_irq_remove_domain(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 9385da1e1e40..306e0bd154fa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> if (r)
> return r;
>
> @@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> amdgpu_irq_remove_domain(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 45ef0a818e11..9005deeec612 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> if (r)
> return r;
>
> @@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> amdgpu_irq_remove_domain(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 97711d327527..acdf6075957a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> if (r)
> return r;
>
> @@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index a79a3776888a..83fdf810ffc7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
> if (r)
> return r;
>
> @@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> amdgpu_irq_remove_domain(adev);
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 37487b4cbd6e..a99f71797aa3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
> int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
> if (r)
> return r;
>
> @@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> - amdgpu_ih_ring_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>
> return 0;
> }
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
2018-09-25 10:28 ` Huang Rui
@ 2018-09-25 11:01 ` Christian König
[not found] ` <ea1b4ebf-c4ee-c03b-b3e7-6f66df831373-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-25 11:01 UTC (permalink / raw)
To: Huang Rui; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 25.09.2018 um 12:28 schrieb Huang Rui:
> On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote:
>> Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
>
> Will we have multiple interrupt rings in new asic?
Vega already has 3 of them, we just haven't activated the other yet.
Christian.
>
> Thanks,
> Ray
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++++++++++++++------------------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
>> 9 files changed, 84 insertions(+), 102 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>> index 4ed86218cef3..15fb0f9738ab 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>> @@ -26,44 +26,20 @@
>> #include "amdgpu_ih.h"
>> #include "amdgpu_amdkfd.h"
>>
>> -/**
>> - * amdgpu_ih_ring_alloc - allocate memory for the IH ring
>> - *
>> - * @adev: amdgpu_device pointer
>> - *
>> - * Allocate a ring buffer for the interrupt controller.
>> - * Returns 0 for success, errors for failure.
>> - */
>> -static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
>> -{
>> - int r;
>> -
>> - /* Allocate ring buffer */
>> - if (adev->irq.ih.ring_obj == NULL) {
>> - r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
>> - PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
>> - &adev->irq.ih.ring_obj,
>> - &adev->irq.ih.gpu_addr,
>> - (void **)&adev->irq.ih.ring);
>> - if (r) {
>> - DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
>> - return r;
>> - }
>> - }
>> - return 0;
>> -}
>> -
>> /**
>> * amdgpu_ih_ring_init - initialize the IH state
>> *
>> * @adev: amdgpu_device pointer
>> + * @ih: ih ring to initialize
>> + * @ring_size: ring size to allocate
>> + * @use_bus_addr: true when we can use dma_alloc_coherent
>> *
>> * Initializes the IH state and allocates a buffer
>> * for the IH ring buffer.
>> * Returns 0 for success, errors for failure.
>> */
>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
>> - bool use_bus_addr)
>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
>> + unsigned ring_size, bool use_bus_addr)
>> {
>> u32 rb_bufsz;
>> int r;
>> @@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
>> /* Align ring size */
>> rb_bufsz = order_base_2(ring_size / 4);
>> ring_size = (1 << rb_bufsz) * 4;
>> - adev->irq.ih.ring_size = ring_size;
>> - adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
>> - adev->irq.ih.rptr = 0;
>> - adev->irq.ih.use_bus_addr = use_bus_addr;
>> -
>> - if (adev->irq.ih.use_bus_addr) {
>> - if (!adev->irq.ih.ring) {
>> - /* add 8 bytes for the rptr/wptr shadows and
>> - * add them to the end of the ring allocation.
>> - */
>> - adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
>> - adev->irq.ih.ring_size + 8,
>> - &adev->irq.ih.rb_dma_addr);
>> - if (adev->irq.ih.ring == NULL)
>> - return -ENOMEM;
>> - memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
>> - adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
>> - adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
>> - }
>> - return 0;
>> + ih->ring_size = ring_size;
>> + ih->ptr_mask = ih->ring_size - 1;
>> + ih->rptr = 0;
>> + ih->use_bus_addr = use_bus_addr;
>> +
>> + if (use_bus_addr) {
>> + if (ih->ring)
>> + return 0;
>> +
>> + /* add 8 bytes for the rptr/wptr shadows and
>> + * add them to the end of the ring allocation.
>> + */
>> + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
>> + &ih->rb_dma_addr, GFP_KERNEL);
>> + if (ih->ring == NULL)
>> + return -ENOMEM;
>> +
>> + memset((void *)ih->ring, 0, ih->ring_size + 8);
>> + ih->wptr_offs = (ih->ring_size / 4) + 0;
>> + ih->rptr_offs = (ih->ring_size / 4) + 1;
>> } else {
>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
>> + r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
>> + if (r)
>> + return r;
>> +
>> + r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
>> if (r) {
>> - dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>> return r;
>> }
>>
>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
>> + r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> + &ih->ring_obj, &ih->gpu_addr,
>> + (void **)&ih->ring);
>> if (r) {
>> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
>> - dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>> return r;
>> }
>> -
>> - return amdgpu_ih_ring_alloc(adev);
>> }
>> + return 0;
>> }
>>
>> /**
>> * amdgpu_ih_ring_fini - tear down the IH state
>> *
>> * @adev: amdgpu_device pointer
>> + * @ih: ih ring to tear down
>> *
>> * Tears down the IH state and frees buffer
>> * used for the IH ring buffer.
>> */
>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
>> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
>> {
>> - if (adev->irq.ih.use_bus_addr) {
>> - if (adev->irq.ih.ring) {
>> - /* add 8 bytes for the rptr/wptr shadows and
>> - * add them to the end of the ring allocation.
>> - */
>> - pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
>> - (void *)adev->irq.ih.ring,
>> - adev->irq.ih.rb_dma_addr);
>> - adev->irq.ih.ring = NULL;
>> - }
>> + if (ih->use_bus_addr) {
>> + if (!ih->ring)
>> + return;
>> +
>> + /* add 8 bytes for the rptr/wptr shadows and
>> + * add them to the end of the ring allocation.
>> + */
>> + dma_free_coherent(adev->dev, ih->ring_size + 8,
>> + (void *)ih->ring, ih->rb_dma_addr);
>> + ih->ring = NULL;
>> } else {
>> - amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
>> - &adev->irq.ih.gpu_addr,
>> - (void **)&adev->irq.ih.ring);
>> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
>> - amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
>> + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
>> + (void **)&ih->ring);
>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
>> }
>> }
>>
>> @@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
>> * amdgpu_ih_process - interrupt handler
>> *
>> * @adev: amdgpu_device pointer
>> + * @ih: ih ring to process
>> *
>> * Interrupt hander (VI), walk the IH ring.
>> * Returns irq process return code.
>> */
>> -int amdgpu_ih_process(struct amdgpu_device *adev)
>> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
>> {
>> struct amdgpu_iv_entry entry;
>> u32 wptr;
>>
>> - if (!adev->irq.ih.enabled || adev->shutdown)
>> + if (!ih->enabled || adev->shutdown)
>> return IRQ_NONE;
>>
>> wptr = amdgpu_ih_get_wptr(adev);
>>
>> restart_ih:
>> /* is somebody else already processing irqs? */
>> - if (atomic_xchg(&adev->irq.ih.lock, 1))
>> + if (atomic_xchg(&ih->lock, 1))
>> return IRQ_NONE;
>>
>> - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
>> + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
>>
>> /* Order reading of wptr vs. reading of IH ring data */
>> rmb();
>>
>> - while (adev->irq.ih.rptr != wptr) {
>> - u32 ring_index = adev->irq.ih.rptr >> 2;
>> + while (ih->rptr != wptr) {
>> + u32 ring_index = ih->rptr >> 2;
>>
>> /* Prescreening of high-frequency interrupts */
>> if (!amdgpu_ih_prescreen_iv(adev)) {
>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
>> + ih->rptr &= ih->ptr_mask;
>> continue;
>> }
>>
>> /* Before dispatching irq to IP blocks, send it to amdkfd */
>> amdgpu_amdkfd_interrupt(adev,
>> - (const void *) &adev->irq.ih.ring[ring_index]);
>> + (const void *) &ih->ring[ring_index]);
>>
>> - entry.iv_entry = (const uint32_t *)
>> - &adev->irq.ih.ring[ring_index];
>> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
>> amdgpu_ih_decode_iv(adev, &entry);
>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
>> + ih->rptr &= ih->ptr_mask;
>>
>> amdgpu_irq_dispatch(adev, &entry);
>> }
>> amdgpu_ih_set_rptr(adev);
>> - atomic_set(&adev->irq.ih.lock, 0);
>> + atomic_set(&ih->lock, 0);
>>
>> /* make sure wptr hasn't changed while processing */
>> wptr = amdgpu_ih_get_wptr(adev);
>> - if (wptr != adev->irq.ih.rptr)
>> + if (wptr != ih->rptr)
>> goto restart_ih;
>>
>> return IRQ_HANDLED;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> index 0d5b3f5201d2..3e55f985005c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> @@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
>> #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
>> #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
>>
>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
>> - bool use_bus_addr);
>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
>> -int amdgpu_ih_process(struct amdgpu_device *adev);
>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
>> + unsigned ring_size, bool use_bus_addr);
>> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
>> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index b927e8798534..aaa8545e458a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
>> struct amdgpu_device *adev = dev->dev_private;
>> irqreturn_t ret;
>>
>> - ret = amdgpu_ih_process(adev);
>> + ret = amdgpu_ih_process(adev, &adev->irq.ih);
>> if (ret == IRQ_HANDLED)
>> pm_runtime_mark_last_busy(dev->dev);
>> return ret;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index e75183e09820..c37c4b76e7e9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>> if (r)
>> return r;
>>
>> @@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>> amdgpu_irq_remove_domain(adev);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index 9385da1e1e40..306e0bd154fa 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>> if (r)
>> return r;
>>
>> @@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>> amdgpu_irq_remove_domain(adev);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index 45ef0a818e11..9005deeec612 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>> if (r)
>> return r;
>>
>> @@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>> amdgpu_irq_remove_domain(adev);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index 97711d327527..acdf6075957a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>> if (r)
>> return r;
>>
>> @@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index a79a3776888a..83fdf810ffc7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
>> if (r)
>> return r;
>>
>> @@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>> amdgpu_irq_remove_domain(adev);
>>
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> index 37487b4cbd6e..a99f71797aa3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> @@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
>> int r;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> - r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
>> if (r)
>> return r;
>>
>> @@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>
>> amdgpu_irq_fini(adev);
>> - amdgpu_ih_ring_fini(adev);
>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>
>> return 0;
>> }
>> --
>> 2.14.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
[not found] ` <20180924123820.1873-6-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 6:05 ` Huang Rui
2018-09-26 8:09 ` Christian König
0 siblings, 1 reply; 26+ messages in thread
From: Huang Rui @ 2018-09-26 6:05 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote:
> One for the ring buffer and one for the IV handling.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't need
two common interrupt handle files. IH is actually the hw ip block name, and
the meaning is actually the same with irq. We can put all common irq handle
include ih ring init functions into irq.c. If you also agree, I will file
the patch.
Thanks,
Ray
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++++++++++-
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 ++++++--
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 ++++++--
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 ++++++--
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++++--
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 ++++++--
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 ++++++--
> 9 files changed, 52 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index 9ce8c93ec19b..d88f82321ee4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -45,22 +45,19 @@ struct amdgpu_ih_ring {
> bool use_doorbell;
> bool use_bus_addr;
> dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
> +
> + const struct amdgpu_ih_funcs *funcs;
> };
>
> /* provided by the ih block */
> struct amdgpu_ih_funcs {
> /* ring read/write ptr handling, called from interrupt context */
> u32 (*get_wptr)(struct amdgpu_device *adev);
> - bool (*prescreen_iv)(struct amdgpu_device *adev);
> - void (*decode_iv)(struct amdgpu_device *adev,
> - struct amdgpu_iv_entry *entry);
> void (*set_rptr)(struct amdgpu_device *adev);
> };
>
> -#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
> -#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
> -#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
> -#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
> +#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
> +#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
>
> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> unsigned ring_size, bool use_bus_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 52c17f6219a7..8e5ce25f3fe1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -163,14 +163,14 @@ static void amdgpu_irq_callback(struct amdgpu_device *adev,
> struct amdgpu_iv_entry entry;
>
> /* Prescreening of high-frequency interrupts */
> - if (!amdgpu_ih_prescreen_iv(adev))
> + if (!amdgpu_irq_prescreen_iv(adev))
> return;
>
> /* Before dispatching irq to IP blocks, send it to amdkfd */
> amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
>
> entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> - amdgpu_ih_decode_iv(adev, &entry);
> + amdgpu_irq_decode_iv(adev, &entry);
>
> amdgpu_irq_dispatch(adev, &entry);
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index f6ce171cb8aa..3cc0e7ce40a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -68,6 +68,12 @@ struct amdgpu_irq_client {
> struct amdgpu_irq_src **sources;
> };
>
> +struct amdgpu_irq_funcs {
> + bool (*prescreen_iv)(struct amdgpu_device *adev);
> + void (*decode_iv)(struct amdgpu_device *adev,
> + struct amdgpu_iv_entry *entry);
> +};
> +
> /* provided by interrupt generating IP blocks */
> struct amdgpu_irq_src_funcs {
> int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
> @@ -89,12 +95,12 @@ struct amdgpu_irq {
>
> /* interrupt ring */
> struct amdgpu_ih_ring ih;
> - const struct amdgpu_ih_funcs *ih_funcs;
>
> /* gen irq stuff */
> struct irq_domain *domain; /* GPU irq controller domain */
> unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
> uint32_t srbm_soft_reset;
> + const struct amdgpu_irq_funcs *funcs;
> };
>
> void amdgpu_irq_disable_all(struct amdgpu_device *adev);
> @@ -121,4 +127,7 @@ int amdgpu_irq_add_domain(struct amdgpu_device *adev);
> void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
> unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
>
> +#define amdgpu_irq_prescreen_iv(adev) (adev)->irq.funcs->prescreen_iv((adev))
> +#define amdgpu_irq_decode_iv(adev, iv) (adev)->irq.funcs->decode_iv((adev), (iv))
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index b5775c6a857b..161f0225749c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -461,14 +461,18 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs cik_ih_funcs = {
> .get_wptr = cik_ih_get_wptr,
> + .set_rptr = cik_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs cik_irq_funcs = {
> .prescreen_iv = cik_ih_prescreen_iv,
> .decode_iv = cik_ih_decode_iv,
> - .set_rptr = cik_ih_set_rptr
> };
>
> static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &cik_ih_funcs;
> + adev->irq.ih.funcs = &cik_ih_funcs;
> + adev->irq.funcs = &cik_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version cik_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index df5ac4d85a00..648ecd774611 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -442,14 +442,18 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs cz_ih_funcs = {
> .get_wptr = cz_ih_get_wptr,
> + .set_rptr = cz_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs cz_irq_funcs = {
> .prescreen_iv = cz_ih_prescreen_iv,
> .decode_iv = cz_ih_decode_iv,
> - .set_rptr = cz_ih_set_rptr
> };
>
> static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &cz_ih_funcs;
> + adev->irq.ih.funcs = &cz_ih_funcs;
> + adev->irq.funcs = &cz_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version cz_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index cf0fc61aebe6..6139186ccd36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -440,14 +440,18 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
> .get_wptr = iceland_ih_get_wptr,
> + .set_rptr = iceland_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs iceland_irq_funcs = {
> .prescreen_iv = iceland_ih_prescreen_iv,
> .decode_iv = iceland_ih_decode_iv,
> - .set_rptr = iceland_ih_set_rptr
> };
>
> static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &iceland_ih_funcs;
> + adev->irq.ih.funcs = &iceland_ih_funcs;
> + adev->irq.funcs = &iceland_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version iceland_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index b3d7d9f83202..16f212f3b534 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -301,14 +301,18 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs si_ih_funcs = {
> .get_wptr = si_ih_get_wptr,
> + .set_rptr = si_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs si_irq_funcs = {
> .prescreen_iv = si_ih_prescreen_iv,
> .decode_iv = si_ih_decode_iv,
> - .set_rptr = si_ih_set_rptr
> };
>
> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &si_ih_funcs;
> + adev->irq.ih.funcs = &si_ih_funcs;
> + adev->irq.funcs = &si_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version si_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 3abffd06b5c7..6120ac3c7667 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -506,14 +506,18 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
> .get_wptr = tonga_ih_get_wptr,
> + .set_rptr = tonga_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs tonga_irq_funcs = {
> .prescreen_iv = tonga_ih_prescreen_iv,
> .decode_iv = tonga_ih_decode_iv,
> - .set_rptr = tonga_ih_set_rptr
> };
>
> static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &tonga_ih_funcs;
> + adev->irq.ih.funcs = &tonga_ih_funcs;
> + adev->irq.funcs = &tonga_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version tonga_ih_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index a99f71797aa3..a9737adf8392 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -487,14 +487,18 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
>
> static const struct amdgpu_ih_funcs vega10_ih_funcs = {
> .get_wptr = vega10_ih_get_wptr,
> + .set_rptr = vega10_ih_set_rptr
> +};
> +
> +static const struct amdgpu_irq_funcs vega10_irq_funcs = {
> .prescreen_iv = vega10_ih_prescreen_iv,
> .decode_iv = vega10_ih_decode_iv,
> - .set_rptr = vega10_ih_set_rptr
> };
>
> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> {
> - adev->irq.ih_funcs = &vega10_ih_funcs;
> + adev->irq.ih.funcs = &vega10_ih_funcs;
> + adev->irq.funcs = &vega10_irq_funcs;
> }
>
> const struct amdgpu_ip_block_version vega10_ih_ip_block =
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c
[not found] ` <20180924123820.1873-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 6:13 ` Huang Rui
0 siblings, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-26 6:13 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:15PM +0200, Christian König wrote:
> Add a callback to amdgpu_ih_process to remove most of the IV logic.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 24 +++++-------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 4 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 31 ++++++++++++++++++++++++++++++-
> 3 files changed, 38 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index 15fb0f9738ab..8af67f649660 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -24,7 +24,6 @@
> #include <drm/drmP.h>
> #include "amdgpu.h"
> #include "amdgpu_ih.h"
> -#include "amdgpu_amdkfd.h"
>
> /**
> * amdgpu_ih_ring_init - initialize the IH state
> @@ -129,9 +128,10 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
> * Interrupt hander (VI), walk the IH ring.
> * Returns irq process return code.
> */
> -int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> + void (*callback)(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih))
> {
> - struct amdgpu_iv_entry entry;
> u32 wptr;
>
> if (!ih->enabled || adev->shutdown)
> @@ -150,24 +150,10 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
> rmb();
>
> while (ih->rptr != wptr) {
> - u32 ring_index = ih->rptr >> 2;
> -
> - /* Prescreening of high-frequency interrupts */
> - if (!amdgpu_ih_prescreen_iv(adev)) {
> - ih->rptr &= ih->ptr_mask;
> - continue;
> - }
> -
> - /* Before dispatching irq to IP blocks, send it to amdkfd */
> - amdgpu_amdkfd_interrupt(adev,
> - (const void *) &ih->ring[ring_index]);
> -
> - entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> - amdgpu_ih_decode_iv(adev, &entry);
> + callback(adev, ih);
> ih->rptr &= ih->ptr_mask;
> -
> - amdgpu_irq_dispatch(adev, &entry);
> }
> +
> amdgpu_ih_set_rptr(adev);
> atomic_set(&ih->lock, 0);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index 3e55f985005c..fd2bbaa20ab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -85,6 +85,8 @@ struct amdgpu_ih_funcs {
> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> unsigned ring_size, bool use_bus_addr);
> void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> -int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> +int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> + void (*callback)(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih));
>
> #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index aaa8545e458a..2fca08e130b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -51,6 +51,7 @@
> #include "atom.h"
> #include "amdgpu_connectors.h"
> #include "amdgpu_trace.h"
> +#include "amdgpu_amdkfd.h"
>
> #include <linux/pm_runtime.h>
>
> @@ -146,6 +147,34 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
> spin_unlock_irqrestore(&adev->irq.lock, irqflags);
> }
>
> +/**
> + * amdgpu_irq_callback - callback from the IH ring
> + *
> + * @adev: amdgpu device pointer
> + * @ih: amdgpu ih ring
> + *
> + * Callback from IH ring processing to handle the entry at the current position
> + * and advance the read pointer.
> + */
> +static void amdgpu_irq_callback(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> +{
> + u32 ring_index = ih->rptr >> 2;
> + struct amdgpu_iv_entry entry;
> +
> + /* Prescreening of high-frequency interrupts */
> + if (!amdgpu_ih_prescreen_iv(adev))
> + return;
> +
> + /* Before dispatching irq to IP blocks, send it to amdkfd */
> + amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
> +
> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> + amdgpu_ih_decode_iv(adev, &entry);
> +
> + amdgpu_irq_dispatch(adev, &entry);
> +}
> +
> /**
> * amdgpu_irq_handler - IRQ handler
> *
> @@ -163,7 +192,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
> struct amdgpu_device *adev = dev->dev_private;
> irqreturn_t ret;
>
> - ret = amdgpu_ih_process(adev, &adev->irq.ih);
> + ret = amdgpu_ih_process(adev, &adev->irq.ih, amdgpu_irq_callback);
> if (ret == IRQ_HANDLED)
> pm_runtime_mark_last_busy(dev->dev);
> return ret;
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h
[not found] ` <20180924123820.1873-5-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 6:14 ` Huang Rui
0 siblings, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-26 6:14 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:16PM +0200, Christian König wrote:
> Everything that isn't related to the IH ring.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 22 +-------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 10 ++++-----
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 25 ++++++++++++++++++++---
> drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 12 +++++------
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 +-
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 2 +-
> 35 files changed, 94 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index fd2bbaa20ab4..9ce8c93ec19b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -24,12 +24,8 @@
> #ifndef __AMDGPU_IH_H__
> #define __AMDGPU_IH_H__
>
> -#include "soc15_ih_clientid.h"
> -
> struct amdgpu_device;
> -
> -#define AMDGPU_IH_CLIENTID_LEGACY 0
> -#define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
> +struct amdgpu_iv_entry;
>
> /*
> * R6xx+ IH ring
> @@ -51,22 +47,6 @@ struct amdgpu_ih_ring {
> dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
> };
>
> -#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
> -
> -struct amdgpu_iv_entry {
> - unsigned client_id;
> - unsigned src_id;
> - unsigned ring_id;
> - unsigned vmid;
> - unsigned vmid_src;
> - uint64_t timestamp;
> - unsigned timestamp_src;
> - unsigned pasid;
> - unsigned pasid_src;
> - unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
> - const uint32_t *iv_entry;
> -};
> -
> /* provided by the ih block */
> struct amdgpu_ih_funcs {
> /* ring read/write ptr handling, called from interrupt context */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 2fca08e130b6..52c17f6219a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -124,7 +124,7 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
> int r;
>
> spin_lock_irqsave(&adev->irq.lock, irqflags);
> - for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> + for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
>
> @@ -302,7 +302,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
> cancel_work_sync(&adev->reset_work);
> }
>
> - for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> + for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
>
> @@ -342,7 +342,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev,
> unsigned client_id, unsigned src_id,
> struct amdgpu_irq_src *source)
> {
> - if (client_id >= AMDGPU_IH_CLIENTID_MAX)
> + if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
> return -EINVAL;
>
> if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
> @@ -396,7 +396,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
>
> trace_amdgpu_iv(entry);
>
> - if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
> + if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
> DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
> return;
> }
> @@ -469,7 +469,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
> {
> int i, j, k;
>
> - for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> + for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
> if (!adev->irq.client[i].sources)
> continue;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index 3375ad778edc..f6ce171cb8aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -25,19 +25,38 @@
> #define __AMDGPU_IRQ_H__
>
> #include <linux/irqdomain.h>
> +#include "soc15_ih_clientid.h"
> #include "amdgpu_ih.h"
>
> -#define AMDGPU_MAX_IRQ_SRC_ID 0x100
> +#define AMDGPU_MAX_IRQ_SRC_ID 0x100
> #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
>
> +#define AMDGPU_IRQ_CLIENTID_LEGACY 0
> +#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
> +
> +#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
> +
> struct amdgpu_device;
> -struct amdgpu_iv_entry;
>
> enum amdgpu_interrupt_state {
> AMDGPU_IRQ_STATE_DISABLE,
> AMDGPU_IRQ_STATE_ENABLE,
> };
>
> +struct amdgpu_iv_entry {
> + unsigned client_id;
> + unsigned src_id;
> + unsigned ring_id;
> + unsigned vmid;
> + unsigned vmid_src;
> + uint64_t timestamp;
> + unsigned timestamp_src;
> + unsigned pasid;
> + unsigned pasid_src;
> + unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
> + const uint32_t *iv_entry;
> +};
> +
> struct amdgpu_irq_src {
> unsigned num_types;
> atomic_t *enabled_types;
> @@ -63,7 +82,7 @@ struct amdgpu_irq {
> bool installed;
> spinlock_t lock;
> /* interrupt sources */
> - struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX];
> + struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
>
> /* status, etc. */
> bool msi_enabled; /* msi enabled */
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index d2469453dca2..79220a91abe3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -6277,12 +6277,12 @@ static int ci_dpm_sw_init(void *handle)
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
> &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
> &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index c37c4b76e7e9..b5775c6a857b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -276,7 +276,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
> dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
> dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>
> - entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
> entry->src_id = dw[0] & 0xff;
> entry->src_data[0] = dw[1] & 0xfffffff;
> entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index ee9d5c92edb1..b918c8886b75 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -970,19 +970,19 @@ static int cik_sdma_sw_init(void *handle)
> }
>
> /* SDMA trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
> &adev->sdma.trap_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 306e0bd154fa..df5ac4d85a00 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -255,7 +255,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
> dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
> dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>
> - entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
> entry->src_id = dw[0] & 0xff;
> entry->src_data[0] = dw[1] & 0xfffffff;
> entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 89c09c396fe6..4cfecdce29a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2746,19 +2746,19 @@ static int dce_v10_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> if (r)
> return r;
> }
>
> for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> if (r)
> return r;
> }
>
> /* HPD hotplug */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index cf6faaa05dbb..7c868916d90f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -2867,19 +2867,19 @@ static int dce_v11_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> if (r)
> return r;
> }
>
> for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> if (r)
> return r;
> }
>
> /* HPD hotplug */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 371aa05bf537..17eaaba36017 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2616,19 +2616,19 @@ static int dce_v6_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> if (r)
> return r;
> }
>
> for (i = 8; i < 20; i += 2) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> if (r)
> return r;
> }
>
> /* HPD hotplug */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 30e76f2407c2..8c0576978d36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -2643,19 +2643,19 @@ static int dce_v8_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> for (i = 0; i < adev->mode_info.num_crtc; i++) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
> if (r)
> return r;
> }
>
> for (i = 8; i < 20; i += 2) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
> if (r)
> return r;
> }
>
> /* HPD hotplug */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 2cc480d65394..fdace004544d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -372,7 +372,7 @@ static int dce_virtual_sw_init(void *handle)
> int r, i;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index de184a886057..7cda0031bd57 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3094,15 +3094,15 @@ static int gfx_v6_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int i, r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index fc39ebbc9d9f..90f030acb685 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4516,18 +4516,18 @@ static int gfx_v7_0_sw_init(void *handle)
> adev->gfx.mec.num_queue_per_pipe = 8;
>
> /* EOP Event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
> if (r)
> return r;
>
> /* Privileged reg */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
> &adev->gfx.priv_reg_irq);
> if (r)
> return r;
>
> /* Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
> &adev->gfx.priv_inst_irq);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 470dc80f4fe7..b6160de70d12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -2049,35 +2049,35 @@ static int gfx_v8_0_sw_init(void *handle)
> adev->gfx.mec.num_queue_per_pipe = 8;
>
> /* KIQ event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
> if (r)
> return r;
>
> /* EOP Event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
> if (r)
> return r;
>
> /* Privileged reg */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
> &adev->gfx.priv_reg_irq);
> if (r)
> return r;
>
> /* Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
> &adev->gfx.priv_inst_irq);
> if (r)
> return r;
>
> /* Add CP EDC/ECC irq */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
> &adev->gfx.cp_ecc_error_irq);
> if (r)
> return r;
>
> /* SQ interrupts. */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
> &adev->gfx.sq_irq);
> if (r) {
> DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 3b8ac4442f06..e1c2b4e9c7b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -859,11 +859,11 @@ static int gmc_v6_0_sw_init(void *handle)
> adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
> }
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 899634ce4238..910c4ce19cb3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -991,11 +991,11 @@ static int gmc_v7_0_sw_init(void *handle)
> adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
> }
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 79143ca7cfac..1d3265c97b70 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1095,11 +1095,11 @@ static int gmc_v8_0_sw_init(void *handle)
> adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
> }
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 9005deeec612..cf0fc61aebe6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -255,7 +255,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
> dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
> dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>
> - entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
> entry->src_id = dw[0] & 0xff;
> entry->src_data[0] = dw[1] & 0xfffffff;
> entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> index cb79a93c2eb7..d0e478f43443 100644
> --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> @@ -2995,12 +2995,12 @@ static int kv_dpm_sw_init(void *handle)
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
> &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
> &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 842567b53df5..64e875d528dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -580,11 +580,11 @@ int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
> {
> int r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
> if (r)
> return r;
>
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
> if (r) {
> amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 0c5a576dee13..cd781abc4953 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -898,19 +898,19 @@ static int sdma_v2_4_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* SDMA trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
> &adev->sdma.trap_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 2587b8de918a..6d5c8ac64874 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1177,19 +1177,19 @@ static int sdma_v3_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* SDMA trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
> &adev->sdma.trap_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
>
> /* SDMA Privileged inst */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
> &adev->sdma.illegal_inst_irq);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index c3510a703f9f..d4ceaf440f26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -502,12 +502,12 @@ static int si_dma_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* DMA0 trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
> if (r)
> return r;
>
> /* DMA1 trap event */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index 1de96995e690..da58040fdbdc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -7687,11 +7687,11 @@ static int si_dpm_sw_init(void *handle)
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
>
> - ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
> + ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index acdf6075957a..b3d7d9f83202 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -142,7 +142,7 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
> dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
> dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>
> - entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
> entry->src_id = dw[0] & 0xff;
> entry->src_data[0] = dw[1] & 0xfffffff;
> entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 83fdf810ffc7..3abffd06b5c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -266,7 +266,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
> dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
> dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>
> - entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
> entry->src_id = dw[0] & 0xff;
> entry->src_data[0] = dw[1] & 0xfffffff;
> entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 8a926d1df939..1fc17bf39fed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -108,7 +108,7 @@ static int uvd_v4_2_sw_init(void *handle)
> int r;
>
> /* UVD TRAP */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 50248059412e..fde6ad5ac9ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -105,7 +105,7 @@ static int uvd_v5_0_sw_init(void *handle)
> int r;
>
> /* UVD TRAP */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 6ae82cc2e55e..8ef4a5392112 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -393,14 +393,14 @@ static int uvd_v6_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* UVD TRAP */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
> if (r)
> return r;
>
> /* UVD ENC TRAP */
> if (uvd_v6_0_enc_support(adev)) {
> for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 7eaa54ba016b..ea28828360d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -417,7 +417,7 @@ static int vce_v2_0_sw_init(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> /* VCE */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index c8390f9adfd6..6dbd39730070 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -423,7 +423,7 @@ static int vce_v3_0_sw_init(void *handle)
> int r, i;
>
> /* VCE */
> - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
> + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 0f10d920a785..8c821854a19a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1198,7 +1198,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
> struct dc_interrupt_params int_params = {0};
> int r;
> int i;
> - unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
> + unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
>
> if (adev->asic_type == CHIP_VEGA10 ||
> adev->asic_type == CHIP_VEGA12 ||
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 04b7da0e39a6..32a8c10d6666 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4106,17 +4106,17 @@ static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
> source->funcs = &smu7_irq_funcs;
>
> amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> - AMDGPU_IH_CLIENTID_LEGACY,
> + AMDGPU_IRQ_CLIENTID_LEGACY,
> VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
> source);
> amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> - AMDGPU_IH_CLIENTID_LEGACY,
> + AMDGPU_IRQ_CLIENTID_LEGACY,
> VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
> source);
>
> /* Register CTF(GPIO_19) interrupt */
> amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> - AMDGPU_IH_CLIENTID_LEGACY,
> + AMDGPU_IRQ_CLIENTID_LEGACY,
> VISLANDS30_IV_SRCID_GPIO_19,
> source);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index 2aab1b475945..8ad4e6960efd 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -545,7 +545,7 @@ int phm_irq_process(struct amdgpu_device *adev,
> uint32_t client_id = entry->client_id;
> uint32_t src_id = entry->src_id;
>
> - if (client_id == AMDGPU_IH_CLIENTID_LEGACY) {
> + if (client_id == AMDGPU_IRQ_CLIENTID_LEGACY) {
> if (src_id == VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH)
> pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
> PCI_BUS_NUM(adev->pdev->devfn),
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr
[not found] ` <20180924123820.1873-7-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 7:36 ` Huang Rui
2018-09-26 7:40 ` Huang Rui
1 sibling, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-26 7:36 UTC (permalink / raw)
To: Christian K�nig; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:18PM +0200, Christian König wrote:
> Let's start to support multiple rings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 28 +++++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 32 +++++++++++++++++---------------
> 8 files changed, 75 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index 8af67f649660..fb8dd6179926 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -137,7 +137,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> if (!ih->enabled || adev->shutdown)
> return IRQ_NONE;
>
> - wptr = amdgpu_ih_get_wptr(adev);
> + wptr = amdgpu_ih_get_wptr(adev, ih);
>
> restart_ih:
> /* is somebody else already processing irqs? */
> @@ -154,11 +154,11 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> ih->rptr &= ih->ptr_mask;
> }
>
> - amdgpu_ih_set_rptr(adev);
> + amdgpu_ih_set_rptr(adev, ih);
> atomic_set(&ih->lock, 0);
>
> /* make sure wptr hasn't changed while processing */
> - wptr = amdgpu_ih_get_wptr(adev);
> + wptr = amdgpu_ih_get_wptr(adev, ih);
> if (wptr != ih->rptr)
> goto restart_ih;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index d88f82321ee4..61967e7b64a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -52,12 +52,12 @@ struct amdgpu_ih_ring {
> /* provided by the ih block */
> struct amdgpu_ih_funcs {
> /* ring read/write ptr handling, called from interrupt context */
> - u32 (*get_wptr)(struct amdgpu_device *adev);
> - void (*set_rptr)(struct amdgpu_device *adev);
> + u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> + void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> };
>
> -#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
> -#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
> +#define amdgpu_ih_get_wptr(adev, ih) (ih)->funcs->get_wptr((adev), (ih))
> +#define amdgpu_ih_set_rptr(adev, ih) (ih)->funcs->set_rptr((adev), (ih))
>
> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> unsigned ring_size, bool use_bus_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 161f0225749c..341092768809 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -183,11 +183,12 @@ static void cik_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cik_irq_process().
> * Returns the value of the wptr.
> */
> -static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
> @@ -196,13 +197,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /* CIK IV Ring
> @@ -294,9 +295,10 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void cik_ih_set_rptr(struct amdgpu_device *adev)
> +static void cik_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int cik_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 648ecd774611..6ed750187ad7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -185,11 +185,12 @@ static void cz_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -198,13 +199,13 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -273,9 +274,10 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void cz_ih_set_rptr(struct amdgpu_device *adev)
> +static void cz_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int cz_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 6139186ccd36..c779d708c306 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -185,11 +185,12 @@ static void iceland_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -198,13 +199,13 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -273,9 +274,10 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void iceland_ih_set_rptr(struct amdgpu_device *adev)
> +static void iceland_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int iceland_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 16f212f3b534..a005824d8b9a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -100,22 +100,23 @@ static void si_ih_irq_disable(struct amdgpu_device *adev)
> mdelay(1);
> }
>
> -static u32 si_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 si_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(IH_RB_CNTL);
> tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> WREG32(IH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -151,9 +152,10 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
> adev->irq.ih.rptr += 16;
> }
>
> -static void si_ih_set_rptr(struct amdgpu_device *adev)
> +static void si_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(IH_RB_RPTR, ih->rptr);
> }
>
> static int si_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 6120ac3c7667..3618dc0c6804 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -193,14 +193,15 @@ static void tonga_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> if (adev->irq.ih.use_bus_addr)
> - wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> else
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -209,13 +210,13 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -284,17 +285,18 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void tonga_ih_set_rptr(struct amdgpu_device *adev)
> +static void tonga_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - if (adev->irq.ih.use_doorbell) {
> + if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (adev->irq.ih.use_bus_addr)
> - adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> + if (ih->use_bus_addr)
> + ih->ring[ih->rptr_offs] = ih->rptr;
> else
> - adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> - WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
> + adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index a9737adf8392..12d4e3ec851e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -191,14 +191,15 @@ static void vega10_ih_irq_disable(struct amdgpu_device *adev)
> * ring buffer overflow and deal with it.
> * Returns the value of the wptr.
> */
> -static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - if (adev->irq.ih.use_bus_addr)
> - wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
> + if (ih->use_bus_addr)
> + wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> else
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -207,16 +208,16 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
> * from the last not overwritten vector (wptr + 32). Hopefully
> * this should allow us to catchup.
> */
> - tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
> + tmp = (wptr + 32) & ih->ptr_mask;
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, tmp);
> - adev->irq.ih.rptr = tmp;
> + wptr, ih->rptr, tmp);
> + ih->rptr = tmp;
>
> tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -353,17 +354,18 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void vega10_ih_set_rptr(struct amdgpu_device *adev)
> +static void vega10_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - if (adev->irq.ih.use_doorbell) {
> + if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (adev->irq.ih.use_bus_addr)
> - adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> + if (ih->use_bus_addr)
> + ih->ring[ih->rptr_offs] = ih->rptr;
> else
> - adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> - WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
> + adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> }
> }
>
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr
[not found] ` <20180924123820.1873-7-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 7:36 ` Huang Rui
@ 2018-09-26 7:40 ` Huang Rui
1 sibling, 0 replies; 26+ messages in thread
From: Huang Rui @ 2018-09-26 7:40 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Sep 24, 2018 at 02:38:18PM +0200, Christian König wrote:
> Let's start to support multiple rings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 16 +++++++++-------
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 28 +++++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 32 +++++++++++++++++---------------
> 8 files changed, 75 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index 8af67f649660..fb8dd6179926 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -137,7 +137,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> if (!ih->enabled || adev->shutdown)
> return IRQ_NONE;
>
> - wptr = amdgpu_ih_get_wptr(adev);
> + wptr = amdgpu_ih_get_wptr(adev, ih);
>
> restart_ih:
> /* is somebody else already processing irqs? */
> @@ -154,11 +154,11 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> ih->rptr &= ih->ptr_mask;
> }
>
> - amdgpu_ih_set_rptr(adev);
> + amdgpu_ih_set_rptr(adev, ih);
> atomic_set(&ih->lock, 0);
>
> /* make sure wptr hasn't changed while processing */
> - wptr = amdgpu_ih_get_wptr(adev);
> + wptr = amdgpu_ih_get_wptr(adev, ih);
> if (wptr != ih->rptr)
> goto restart_ih;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index d88f82321ee4..61967e7b64a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -52,12 +52,12 @@ struct amdgpu_ih_ring {
> /* provided by the ih block */
> struct amdgpu_ih_funcs {
> /* ring read/write ptr handling, called from interrupt context */
> - u32 (*get_wptr)(struct amdgpu_device *adev);
> - void (*set_rptr)(struct amdgpu_device *adev);
> + u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> + void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
> };
>
> -#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
> -#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
> +#define amdgpu_ih_get_wptr(adev, ih) (ih)->funcs->get_wptr((adev), (ih))
> +#define amdgpu_ih_set_rptr(adev, ih) (ih)->funcs->set_rptr((adev), (ih))
>
> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
> unsigned ring_size, bool use_bus_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 161f0225749c..341092768809 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -183,11 +183,12 @@ static void cik_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cik_irq_process().
> * Returns the value of the wptr.
> */
> -static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
> @@ -196,13 +197,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /* CIK IV Ring
> @@ -294,9 +295,10 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void cik_ih_set_rptr(struct amdgpu_device *adev)
> +static void cik_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int cik_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 648ecd774611..6ed750187ad7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -185,11 +185,12 @@ static void cz_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -198,13 +199,13 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -273,9 +274,10 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void cz_ih_set_rptr(struct amdgpu_device *adev)
> +static void cz_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int cz_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 6139186ccd36..c779d708c306 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -185,11 +185,12 @@ static void iceland_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -198,13 +199,13 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -273,9 +274,10 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void iceland_ih_set_rptr(struct amdgpu_device *adev)
> +static void iceland_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
>
> static int iceland_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 16f212f3b534..a005824d8b9a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -100,22 +100,23 @@ static void si_ih_irq_disable(struct amdgpu_device *adev)
> mdelay(1);
> }
>
> -static u32 si_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 si_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(IH_RB_CNTL);
> tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
> WREG32(IH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -151,9 +152,10 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
> adev->irq.ih.rptr += 16;
> }
>
> -static void si_ih_set_rptr(struct amdgpu_device *adev)
> +static void si_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(IH_RB_RPTR, ih->rptr);
> }
>
> static int si_ih_early_init(void *handle)
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 6120ac3c7667..3618dc0c6804 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -193,14 +193,15 @@ static void tonga_ih_irq_disable(struct amdgpu_device *adev)
> * Used by cz_irq_process(VI).
> * Returns the value of the wptr.
> */
> -static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> if (adev->irq.ih.use_bus_addr)
> - wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> else
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -209,13 +210,13 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
> * this should allow us to catchup.
> */
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
> - adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
> + wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
> + ih->rptr = (wptr + 16) & ih->ptr_mask;
> tmp = RREG32(mmIH_RB_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32(mmIH_RB_CNTL, tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -284,17 +285,18 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void tonga_ih_set_rptr(struct amdgpu_device *adev)
> +static void tonga_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - if (adev->irq.ih.use_doorbell) {
> + if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (adev->irq.ih.use_bus_addr)
> - adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> + if (ih->use_bus_addr)
> + ih->ring[ih->rptr_offs] = ih->rptr;
> else
> - adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> - WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
> + adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> - WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32(mmIH_RB_RPTR, ih->rptr);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index a9737adf8392..12d4e3ec851e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -191,14 +191,15 @@ static void vega10_ih_irq_disable(struct amdgpu_device *adev)
> * ring buffer overflow and deal with it.
> * Returns the value of the wptr.
> */
> -static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
> +static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> u32 wptr, tmp;
>
> - if (adev->irq.ih.use_bus_addr)
> - wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
> + if (ih->use_bus_addr)
> + wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> else
> - wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
> + wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
> @@ -207,16 +208,16 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
> * from the last not overwritten vector (wptr + 32). Hopefully
> * this should allow us to catchup.
> */
> - tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
> + tmp = (wptr + 32) & ih->ptr_mask;
> dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
> - wptr, adev->irq.ih.rptr, tmp);
> - adev->irq.ih.rptr = tmp;
> + wptr, ih->rptr, tmp);
> + ih->rptr = tmp;
>
> tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
> WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
> }
> - return (wptr & adev->irq.ih.ptr_mask);
> + return (wptr & ih->ptr_mask);
> }
>
> /**
> @@ -353,17 +354,18 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
> *
> * Set the IH ring buffer rptr.
> */
> -static void vega10_ih_set_rptr(struct amdgpu_device *adev)
> +static void vega10_ih_set_rptr(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> {
> - if (adev->irq.ih.use_doorbell) {
> + if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (adev->irq.ih.use_bus_addr)
> - adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> + if (ih->use_bus_addr)
> + ih->ring[ih->rptr_offs] = ih->rptr;
> else
> - adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
> - WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
> + adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> }
> }
>
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
2018-09-26 6:05 ` Huang Rui
@ 2018-09-26 8:09 ` Christian König
[not found] ` <39fb9a51-2e85-0828-a193-b54059dec405-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-26 8:09 UTC (permalink / raw)
To: Huang Rui; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 26.09.2018 um 08:05 schrieb Huang Rui:
> On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote:
>> One for the ring buffer and one for the IV handling.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
>
> How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't need
> two common interrupt handle files. IH is actually the hw ip block name, and
> the meaning is actually the same with irq. We can put all common irq handle
> include ih ring init functions into irq.c. If you also agree, I will file
> the patch.
I actually dropped this patch, but we certainly need two different files.
The one is for the IH ring buffer, which Vega10 actually has 3 of.
The other one is for the IRQ handling which does the tracking how often
interrupt sources are enabled, how to route them etc...
E.g. for that we would still have one instance per device.
Regards,
Christian.
>
> Thanks,
> Ray
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ++++-------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++++++++++-
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 ++++++--
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 ++++++--
>> 9 files changed, 52 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> index 9ce8c93ec19b..d88f82321ee4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>> @@ -45,22 +45,19 @@ struct amdgpu_ih_ring {
>> bool use_doorbell;
>> bool use_bus_addr;
>> dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
>> +
>> + const struct amdgpu_ih_funcs *funcs;
>> };
>>
>> /* provided by the ih block */
>> struct amdgpu_ih_funcs {
>> /* ring read/write ptr handling, called from interrupt context */
>> u32 (*get_wptr)(struct amdgpu_device *adev);
>> - bool (*prescreen_iv)(struct amdgpu_device *adev);
>> - void (*decode_iv)(struct amdgpu_device *adev,
>> - struct amdgpu_iv_entry *entry);
>> void (*set_rptr)(struct amdgpu_device *adev);
>> };
>>
>> -#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
>> -#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
>> -#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
>> -#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
>> +#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih.funcs->get_wptr((adev))
>> +#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih.funcs->set_rptr((adev))
>>
>> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
>> unsigned ring_size, bool use_bus_addr);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> index 52c17f6219a7..8e5ce25f3fe1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>> @@ -163,14 +163,14 @@ static void amdgpu_irq_callback(struct amdgpu_device *adev,
>> struct amdgpu_iv_entry entry;
>>
>> /* Prescreening of high-frequency interrupts */
>> - if (!amdgpu_ih_prescreen_iv(adev))
>> + if (!amdgpu_irq_prescreen_iv(adev))
>> return;
>>
>> /* Before dispatching irq to IP blocks, send it to amdkfd */
>> amdgpu_amdkfd_interrupt(adev, (const void *) &ih->ring[ring_index]);
>>
>> entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
>> - amdgpu_ih_decode_iv(adev, &entry);
>> + amdgpu_irq_decode_iv(adev, &entry);
>>
>> amdgpu_irq_dispatch(adev, &entry);
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>> index f6ce171cb8aa..3cc0e7ce40a0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>> @@ -68,6 +68,12 @@ struct amdgpu_irq_client {
>> struct amdgpu_irq_src **sources;
>> };
>>
>> +struct amdgpu_irq_funcs {
>> + bool (*prescreen_iv)(struct amdgpu_device *adev);
>> + void (*decode_iv)(struct amdgpu_device *adev,
>> + struct amdgpu_iv_entry *entry);
>> +};
>> +
>> /* provided by interrupt generating IP blocks */
>> struct amdgpu_irq_src_funcs {
>> int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
>> @@ -89,12 +95,12 @@ struct amdgpu_irq {
>>
>> /* interrupt ring */
>> struct amdgpu_ih_ring ih;
>> - const struct amdgpu_ih_funcs *ih_funcs;
>>
>> /* gen irq stuff */
>> struct irq_domain *domain; /* GPU irq controller domain */
>> unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
>> uint32_t srbm_soft_reset;
>> + const struct amdgpu_irq_funcs *funcs;
>> };
>>
>> void amdgpu_irq_disable_all(struct amdgpu_device *adev);
>> @@ -121,4 +127,7 @@ int amdgpu_irq_add_domain(struct amdgpu_device *adev);
>> void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
>> unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
>>
>> +#define amdgpu_irq_prescreen_iv(adev) (adev)->irq.funcs->prescreen_iv((adev))
>> +#define amdgpu_irq_decode_iv(adev, iv) (adev)->irq.funcs->decode_iv((adev), (iv))
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index b5775c6a857b..161f0225749c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -461,14 +461,18 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs cik_ih_funcs = {
>> .get_wptr = cik_ih_get_wptr,
>> + .set_rptr = cik_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs cik_irq_funcs = {
>> .prescreen_iv = cik_ih_prescreen_iv,
>> .decode_iv = cik_ih_decode_iv,
>> - .set_rptr = cik_ih_set_rptr
>> };
>>
>> static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &cik_ih_funcs;
>> + adev->irq.ih.funcs = &cik_ih_funcs;
>> + adev->irq.funcs = &cik_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version cik_ih_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index df5ac4d85a00..648ecd774611 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -442,14 +442,18 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs cz_ih_funcs = {
>> .get_wptr = cz_ih_get_wptr,
>> + .set_rptr = cz_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs cz_irq_funcs = {
>> .prescreen_iv = cz_ih_prescreen_iv,
>> .decode_iv = cz_ih_decode_iv,
>> - .set_rptr = cz_ih_set_rptr
>> };
>>
>> static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &cz_ih_funcs;
>> + adev->irq.ih.funcs = &cz_ih_funcs;
>> + adev->irq.funcs = &cz_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version cz_ih_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index cf0fc61aebe6..6139186ccd36 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -440,14 +440,18 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
>> .get_wptr = iceland_ih_get_wptr,
>> + .set_rptr = iceland_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs iceland_irq_funcs = {
>> .prescreen_iv = iceland_ih_prescreen_iv,
>> .decode_iv = iceland_ih_decode_iv,
>> - .set_rptr = iceland_ih_set_rptr
>> };
>>
>> static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &iceland_ih_funcs;
>> + adev->irq.ih.funcs = &iceland_ih_funcs;
>> + adev->irq.funcs = &iceland_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version iceland_ih_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index b3d7d9f83202..16f212f3b534 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -301,14 +301,18 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs si_ih_funcs = {
>> .get_wptr = si_ih_get_wptr,
>> + .set_rptr = si_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs si_irq_funcs = {
>> .prescreen_iv = si_ih_prescreen_iv,
>> .decode_iv = si_ih_decode_iv,
>> - .set_rptr = si_ih_set_rptr
>> };
>>
>> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &si_ih_funcs;
>> + adev->irq.ih.funcs = &si_ih_funcs;
>> + adev->irq.funcs = &si_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version si_ih_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index 3abffd06b5c7..6120ac3c7667 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -506,14 +506,18 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
>> .get_wptr = tonga_ih_get_wptr,
>> + .set_rptr = tonga_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs tonga_irq_funcs = {
>> .prescreen_iv = tonga_ih_prescreen_iv,
>> .decode_iv = tonga_ih_decode_iv,
>> - .set_rptr = tonga_ih_set_rptr
>> };
>>
>> static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &tonga_ih_funcs;
>> + adev->irq.ih.funcs = &tonga_ih_funcs;
>> + adev->irq.funcs = &tonga_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version tonga_ih_ip_block =
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> index a99f71797aa3..a9737adf8392 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> @@ -487,14 +487,18 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
>>
>> static const struct amdgpu_ih_funcs vega10_ih_funcs = {
>> .get_wptr = vega10_ih_get_wptr,
>> + .set_rptr = vega10_ih_set_rptr
>> +};
>> +
>> +static const struct amdgpu_irq_funcs vega10_irq_funcs = {
>> .prescreen_iv = vega10_ih_prescreen_iv,
>> .decode_iv = vega10_ih_decode_iv,
>> - .set_rptr = vega10_ih_set_rptr
>> };
>>
>> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>> {
>> - adev->irq.ih_funcs = &vega10_ih_funcs;
>> + adev->irq.ih.funcs = &vega10_ih_funcs;
>> + adev->irq.funcs = &vega10_irq_funcs;
>> }
>>
>> const struct amdgpu_ip_block_version vega10_ih_ip_block =
>> --
>> 2.14.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 8/9] drm/amdgpu: simplify IH programming
[not found] ` <20180924123820.1873-8-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 8:48 ` Huang, Ray
0 siblings, 0 replies; 26+ messages in thread
From: Huang, Ray @ 2018-09-26 8:48 UTC (permalink / raw)
To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Christian K?nig
> Sent: Monday, September 24, 2018 8:38 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 8/9] drm/amdgpu: simplify IH programming
>
> Calculate all the addresses and pointers in amdgpu_ih.c
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 34
> +++++++++++++++++++++----------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 23 ++++++++++++---------
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 ++++-----
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 11 +++++-----
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 9 ++++-----
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 9 ++++-----
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 27 +++++++------------------
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 36 +++++++++++---------------
> -------
> 8 files changed, 73 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> index fb8dd6179926..d0a5db777b6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> @@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ih_ring *ih,
> ih->use_bus_addr = use_bus_addr;
>
> if (use_bus_addr) {
> + dma_addr_t dma_addr;
> +
> if (ih->ring)
> return 0;
>
> @@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ih_ring *ih,
> * add them to the end of the ring allocation.
> */
> ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
> - &ih->rb_dma_addr, GFP_KERNEL);
> + &dma_addr, GFP_KERNEL);
> if (ih->ring == NULL)
> return -ENOMEM;
>
> memset((void *)ih->ring, 0, ih->ring_size + 8);
> - ih->wptr_offs = (ih->ring_size / 4) + 0;
> - ih->rptr_offs = (ih->ring_size / 4) + 1;
> + ih->gpu_addr = dma_addr;
I am thinking if program the dma_addr as the member of gpu_addr, it might cause confusion.
I know it can avoid the checking when we program the mmIH_RB_BASE. How about use another name for this member?
Thanks,
Ray
> + ih->wptr_addr = dma_addr + ih->ring_size;
> + ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
> + ih->rptr_addr = dma_addr + ih->ring_size + 4;
> + ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
> } else {
> - r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
> + unsigned wptr_offs, rptr_offs;
> +
> + r = amdgpu_device_wb_get(adev, &wptr_offs);
> if (r)
> return r;
>
> - r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
> + r = amdgpu_device_wb_get(adev, &rptr_offs);
> if (r) {
> - amdgpu_device_wb_free(adev, ih->wptr_offs);
> + amdgpu_device_wb_free(adev, wptr_offs);
> return r;
> }
>
> @@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev,
> struct amdgpu_ih_ring *ih,
> &ih->ring_obj, &ih->gpu_addr,
> (void **)&ih->ring);
> if (r) {
> - amdgpu_device_wb_free(adev, ih->rptr_offs);
> - amdgpu_device_wb_free(adev, ih->wptr_offs);
> + amdgpu_device_wb_free(adev, rptr_offs);
> + amdgpu_device_wb_free(adev, wptr_offs);
> return r;
> }
> +
> + ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
> + ih->wptr_cpu = &adev->wb.wb[wptr_offs];
> + ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
> + ih->rptr_cpu = &adev->wb.wb[rptr_offs];
> }
> return 0;
> }
> @@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device
> *adev, struct amdgpu_ih_ring *ih)
> * add them to the end of the ring allocation.
> */
> dma_free_coherent(adev->dev, ih->ring_size + 8,
> - (void *)ih->ring, ih->rb_dma_addr);
> + (void *)ih->ring, ih->gpu_addr);
> ih->ring = NULL;
> } else {
> amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
> (void **)&ih->ring);
> - amdgpu_device_wb_free(adev, ih->wptr_offs);
> - amdgpu_device_wb_free(adev, ih->rptr_offs);
> + amdgpu_device_wb_free(adev, (ih->wptr_addr - ih-
> >gpu_addr) / 4);
> + amdgpu_device_wb_free(adev, (ih->rptr_addr - ih-
> >gpu_addr) / 4);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index 61967e7b64a7..6af047b64cf0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -31,20 +31,25 @@ struct amdgpu_iv_entry;
> * R6xx+ IH ring
> */
> struct amdgpu_ih_ring {
> - struct amdgpu_bo *ring_obj;
> - volatile uint32_t *ring;
> - unsigned rptr;
> unsigned ring_size;
> - uint64_t gpu_addr;
> uint32_t ptr_mask;
> - atomic_t lock;
> - bool enabled;
> - unsigned wptr_offs;
> - unsigned rptr_offs;
> u32 doorbell_index;
> bool use_doorbell;
> bool use_bus_addr;
> - dma_addr_t rb_dma_addr; /* only used when
> use_bus_addr = true */
> +
> + struct amdgpu_bo *ring_obj;
> + volatile uint32_t *ring;
> + uint64_t gpu_addr;
> +
> + uint64_t wptr_addr;
> + volatile uint32_t *wptr_cpu;
> +
> + uint64_t rptr_addr;
> + volatile uint32_t *rptr_cpu;
> +
> + bool enabled;
> + unsigned rptr;
> + atomic_t lock;
>
> const struct amdgpu_ih_funcs *funcs;
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 341092768809..2358ab32c16c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int cik_ih_irq_init(struct amdgpu_device *adev) {
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> int rb_bufsz;
> u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
> - u64 wptr_off;
>
> /* disable irqs */
> cik_ih_disable_interrupts(adev);
> @@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)
> ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
>
> /* set the writeback address whether it's enabled or not */
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
> - WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
> - WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) &
> 0xFF);
> + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih-
> >wptr_addr));
> + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr)
> & 0xFF);
>
> WREG32(mmIH_RB_CNTL, ih_rb_cntl);
>
> @@ -188,7 +187,7 @@ static u32 cik_ih_get_wptr(struct amdgpu_device
> *adev, {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; diff --git
> a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 6ed750187ad7..2d2029cd15e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -103,9 +103,9 @@ static void cz_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int cz_ih_irq_init(struct amdgpu_device *adev) {
> - int rb_bufsz;
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
> - u64 wptr_off;
> + int rb_bufsz;
>
> /* disable irqs */
> cz_ih_disable_interrupts(adev);
> @@ -133,9 +133,8 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_WRITEBACK_ENABLE, 1);
>
> /* set the writeback address whether it's enabled or not */
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
> - WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
> - WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) &
> 0xFF);
> + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih-
> >wptr_addr));
> + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr)
> & 0xFF);
>
> WREG32(mmIH_RB_CNTL, ih_rb_cntl);
>
> @@ -190,7 +189,7 @@ static u32 cz_ih_get_wptr(struct amdgpu_device
> *adev, {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW,
> 0); diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index c779d708c306..337fc38c6bca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -103,9 +103,9 @@ static void iceland_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int iceland_ih_irq_init(struct amdgpu_device *adev) {
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> int rb_bufsz;
> u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
> - u64 wptr_off;
>
> /* disable irqs */
> iceland_ih_disable_interrupts(adev);
> @@ -133,9 +133,8 @@ static int iceland_ih_irq_init(struct amdgpu_device
> *adev)
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_WRITEBACK_ENABLE, 1);
>
> /* set the writeback address whether it's enabled or not */
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
> - WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
> - WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) &
> 0xFF);
> + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih-
> >wptr_addr));
> + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr)
> & 0xFF);
>
> WREG32(mmIH_RB_CNTL, ih_rb_cntl);
>
> @@ -190,7 +189,7 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device
> *adev, {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW,
> 0); diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index a005824d8b9a..574efa2a4f0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -57,9 +57,9 @@ static void si_ih_disable_interrupts(struct
> amdgpu_device *adev)
>
> static int si_ih_irq_init(struct amdgpu_device *adev) {
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> int rb_bufsz;
> u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
> - u64 wptr_off;
>
> si_ih_disable_interrupts(adev);
> WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); @@ -76,9
> +76,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
> (rb_bufsz << 1) |
> IH_WPTR_WRITEBACK_ENABLE;
>
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
> - WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
> - WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
> + WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
> + WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) &
> 0xFF);
> WREG32(IH_RB_CNTL, ih_rb_cntl);
> WREG32(IH_RB_RPTR, 0);
> WREG32(IH_RB_WPTR, 0);
> @@ -105,7 +104,7 @@ static u32 si_ih_get_wptr(struct amdgpu_device
> *adev, {
> u32 wptr, tmp;
>
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
> wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; diff --git
> a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 3618dc0c6804..966c0782f743 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -99,9 +99,9 @@ static void tonga_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int tonga_ih_irq_init(struct amdgpu_device *adev) {
> - int rb_bufsz;
> u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
> - u64 wptr_off;
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> + int rb_bufsz;
>
> /* disable irqs */
> tonga_ih_disable_interrupts(adev);
> @@ -118,10 +118,7 @@ static int tonga_ih_irq_init(struct amdgpu_device
> *adev)
> WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
>
> /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the
> ring buffer*/
> - if (adev->irq.ih.use_bus_addr)
> - WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
> - else
> - WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
> + WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
>
> rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
> ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL,
> WPTR_OVERFLOW_CLEAR, 1); @@ -136,12 +133,8 @@ static int
> tonga_ih_irq_init(struct amdgpu_device *adev)
> WREG32(mmIH_RB_CNTL, ih_rb_cntl);
>
> /* set the writeback address whether it's enabled or not */
> - if (adev->irq.ih.use_bus_addr)
> - wptr_off = adev->irq.ih.rb_dma_addr + (adev-
> >irq.ih.wptr_offs * 4);
> - else
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs *
> 4);
> - WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
> - WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) &
> 0xFF);
> + WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih-
> >wptr_addr));
> + WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr)
> & 0xFF);
>
> /* set rptr, wptr to 0 */
> WREG32(mmIH_RB_RPTR, 0);
> @@ -198,10 +191,7 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device
> *adev, {
> u32 wptr, tmp;
>
> - if (adev->irq.ih.use_bus_addr)
> - wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> - else
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW,
> 0); @@ -290,10 +280,7 @@ static void tonga_ih_set_rptr(struct
> amdgpu_device *adev, {
> if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (ih->use_bus_addr)
> - ih->ring[ih->rptr_offs] = ih->rptr;
> - else
> - adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + *ih->rptr_cpu = ih->rptr;
> WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> WREG32(mmIH_RB_RPTR, ih->rptr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 12d4e3ec851e..b4330eccee04 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -86,11 +86,11 @@ static void vega10_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int vega10_ih_irq_init(struct amdgpu_device *adev) {
> + struct amdgpu_ih_ring *ih = &adev->irq.ih;
> int ret = 0;
> int rb_bufsz;
> u32 ih_rb_cntl, ih_doorbell_rtpr;
> u32 tmp;
> - u64 wptr_off;
>
> /* disable irqs */
> vega10_ih_disable_interrupts(adev);
> @@ -99,15 +99,11 @@ static int vega10_ih_irq_init(struct amdgpu_device
> *adev)
>
> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
> /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the
> ring buffer*/
> - if (adev->irq.ih.use_bus_addr) {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev-
> >irq.ih.rb_dma_addr >> 8);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev-
> >irq.ih.rb_dma_addr >> 40) & 0xff);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> MC_SPACE, 1);
> - } else {
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev-
> >irq.ih.gpu_addr >> 8);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev-
> >irq.ih.gpu_addr >> 40) & 0xff);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> MC_SPACE, 4);
> - }
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev-
> >irq.ih.gpu_addr >> 8);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI,
> + (adev->irq.ih.gpu_addr >> 40) & 0xff);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE,
> + ih->use_bus_addr ? 1 : 4);
> rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_OVERFLOW_CLEAR, 1);
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_OVERFLOW_ENABLE, 1); @@ -124,12 +120,10 @@ static int
> vega10_ih_irq_init(struct amdgpu_device *adev)
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
>
> /* set the writeback address whether it's enabled or not */
> - if (adev->irq.ih.use_bus_addr)
> - wptr_off = adev->irq.ih.rb_dma_addr + (adev-
> >irq.ih.wptr_offs * 4);
> - else
> - wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs *
> 4);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
> lower_32_bits(wptr_off));
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
> upper_32_bits(wptr_off) & 0xFF);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
> + lower_32_bits(ih->wptr_addr));
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
> + upper_32_bits(ih->wptr_addr) & 0xFF);
>
> /* set rptr, wptr to 0 */
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); @@ -196,10 +190,7
> @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev, {
> u32 wptr, tmp;
>
> - if (ih->use_bus_addr)
> - wptr = le32_to_cpu(ih->ring[ih->wptr_offs]);
> - else
> - wptr = le32_to_cpu(adev->wb.wb[ih->wptr_offs]);
> + wptr = le32_to_cpu(*ih->wptr_cpu);
>
> if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
> wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW,
> 0); @@ -359,10 +350,7 @@ static void vega10_ih_set_rptr(struct
> amdgpu_device *adev, {
> if (ih->use_doorbell) {
> /* XXX check if swapping is necessary on BE */
> - if (ih->use_bus_addr)
> - ih->ring[ih->rptr_offs] = ih->rptr;
> - else
> - adev->wb.wb[ih->rptr_offs] = ih->rptr;
> + *ih->rptr_cpu = ih->rptr;
> WDOORBELL32(ih->doorbell_index, ih->rptr);
> } else {
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2
[not found] ` <20180924123820.1873-9-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 8:49 ` Huang, Ray
0 siblings, 0 replies; 26+ messages in thread
From: Huang, Ray @ 2018-09-26 8:49 UTC (permalink / raw)
To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Christian K?nig
> Sent: Monday, September 24, 2018 8:38 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2
>
> The entries are ignored for now, but it at least stops crashing the hardware
> when somebody tries to push something to the other IH rings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 4 +-
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 129
> +++++++++++++++++++++++++-------
> 2 files changed, 106 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index 3cc0e7ce40a0..0c6af0b38490 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -93,8 +93,8 @@ struct amdgpu_irq {
> /* status, etc. */
> bool msi_enabled; /* msi enabled */
>
> - /* interrupt ring */
> - struct amdgpu_ih_ring ih;
> + /* interrupt rings */
> + struct amdgpu_ih_ring ih, ih1, ih2;
>
> /* gen irq stuff */
> struct irq_domain *domain; /* GPU irq controller
> domain */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index b4330eccee04..2d2036e0c8b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -50,6 +50,16 @@ static void vega10_ih_enable_interrupts(struct
> amdgpu_device *adev)
> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR,
> 1);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> adev->irq.ih.enabled = true;
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 1);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + adev->irq.ih1.enabled = true;
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 1);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + adev->irq.ih2.enabled = true;
> }
>
> /**
> @@ -71,6 +81,47 @@ static void vega10_ih_disable_interrupts(struct
> amdgpu_device *adev)
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
> adev->irq.ih.enabled = false;
> adev->irq.ih.rptr = 0;
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> RB_ENABLE, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> + /* set rptr, wptr to 0 */
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> + adev->irq.ih1.enabled = false;
> + adev->irq.ih1.rptr = 0;
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> RB_ENABLE, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> + /* set rptr, wptr to 0 */
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> + adev->irq.ih2.enabled = false;
> + adev->irq.ih2.rptr = 0;
> +}
> +
> +static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t
> +ih_rb_cntl) {
> + int rb_bufsz = order_base_2(ih->ring_size / 4);
> +
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + MC_SPACE, ih->use_bus_addr ? 1 : 4);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + WPTR_OVERFLOW_CLEAR, 1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + WPTR_OVERFLOW_ENABLE, 1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE,
> rb_bufsz);
> + /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR
> register
> + * value is written to memory
> + */
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> + WPTR_WRITEBACK_ENABLE, 1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
> +
> + return ih_rb_cntl;
> }
>
> /**
> @@ -86,9 +137,8 @@ static void vega10_ih_disable_interrupts(struct
> amdgpu_device *adev)
> */
> static int vega10_ih_irq_init(struct amdgpu_device *adev) {
> - struct amdgpu_ih_ring *ih = &adev->irq.ih;
> + struct amdgpu_ih_ring *ih;
> int ret = 0;
> - int rb_bufsz;
> u32 ih_rb_cntl, ih_doorbell_rtpr;
> u32 tmp;
>
> @@ -97,26 +147,15 @@ static int vega10_ih_irq_init(struct amdgpu_device
> *adev)
>
> adev->nbio_funcs->ih_control(adev);
>
> - ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
> + ih = &adev->irq.ih;
> /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the
> ring buffer*/
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev-
> >irq.ih.gpu_addr >> 8);
> - WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI,
> - (adev->irq.ih.gpu_addr >> 40) & 0xff);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE,
> - ih->use_bus_addr ? 1 : 4);
> - rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_OVERFLOW_CLEAR, 1);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_OVERFLOW_ENABLE, 1);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE,
> rb_bufsz);
> - /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR
> register value is written to memory */
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> WPTR_WRITEBACK_ENABLE, 1);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
> -
> - if (adev->irq.msi_enabled)
> - ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> RPTR_REARM, 1);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40)
> & 0xff);
>
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
> + ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
> + !!adev->irq.msi_enabled);
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
>
> /* set the writeback address whether it's enabled or not */ @@ -
> 131,18 +170,49 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
>
> ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0,
> mmIH_DOORBELL_RPTR);
> if (adev->irq.ih.use_doorbell) {
> - ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> IH_DOORBELL_RPTR,
> - OFFSET, adev-
> >irq.ih.doorbell_index);
> - ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> IH_DOORBELL_RPTR,
> + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> + IH_DOORBELL_RPTR, OFFSET,
> + adev->irq.ih.doorbell_index);
> + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> + IH_DOORBELL_RPTR,
> ENABLE, 1);
> } else {
> - ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> IH_DOORBELL_RPTR,
> + ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
> + IH_DOORBELL_RPTR,
> ENABLE, 0);
> }
> WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
> ih_doorbell_rtpr);
> adev->nbio_funcs->ih_doorbell_range(adev, adev-
> >irq.ih.use_doorbell,
> adev->irq.ih.doorbell_index);
>
> + ih = &adev->irq.ih1;
> + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the
> ring buffer*/
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >>
> 8);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
> + (ih->gpu_addr >> 40) & 0xff);
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> + ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
> +
> + /* set rptr, wptr to 0 */
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
> +
> + ih = &adev->irq.ih2;
> + /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the
> ring buffer*/
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >>
> 8);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
> + (ih->gpu_addr >> 40) & 0xff);
> +
> + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> + ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
> +
> + /* set rptr, wptr to 0 */
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
> + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
> +
> tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
> tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
> CLIENT18_IS_STORM_CLIENT, 1);
> @@ -333,7 +403,6 @@ static void vega10_ih_decode_iv(struct
> amdgpu_device *adev,
> entry->src_data[2] = dw[6];
> entry->src_data[3] = dw[7];
>
> -
> /* wptr/rptr are in bytes! */
> adev->irq.ih.rptr += 32;
> }
> @@ -374,6 +443,14 @@ static int vega10_ih_sw_init(void *handle)
> if (r)
> return r;
>
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, 256 * 1024, true);
> + if (r)
> + return r;
> +
> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, 256 * 1024, true);
> + if (r)
> + return r;
> +
> adev->irq.ih.use_doorbell = true;
> adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
>
> @@ -387,6 +464,8 @@ static int vega10_ih_sw_fini(void *handle)
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> amdgpu_irq_fini(adev);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
> + amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
> amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>
> return 0;
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
[not found] ` <ea1b4ebf-c4ee-c03b-b3e7-6f66df831373-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-09-26 8:52 ` Huang, Ray
[not found] ` <BY2PR12MB0040B93400AD69D00699F870EC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Huang, Ray @ 2018-09-26 8:52 UTC (permalink / raw)
To: Koenig, Christian; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
> Sent: Tuesday, September 25, 2018 7:01 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
>
> Am 25.09.2018 um 12:28 schrieb Huang Rui:
> > On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote:
> >> Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
> >>
> >> Signed-off-by: Christian König <christian.koenig@amd.com>
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> >
> > Will we have multiple interrupt rings in new asic?
>
> Vega already has 3 of them, we just haven't activated the other yet.
>
Good to know. I just took a look at the spec. IH ring 1 is used for request log and IH ring 2 is used for translation & invalidation log.
They are to support the page migration feature. Do you plan to work on it?
Thanks,
Ray
> Christian.
>
> >
> > Thanks,
> > Ray
> >
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++++++++++++++---
> ---------------
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
> >> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
> >> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
> >> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
> >> drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
> >> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
> >> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
> >> 9 files changed, 84 insertions(+), 102 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >> index 4ed86218cef3..15fb0f9738ab 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >> @@ -26,44 +26,20 @@
> >> #include "amdgpu_ih.h"
> >> #include "amdgpu_amdkfd.h"
> >>
> >> -/**
> >> - * amdgpu_ih_ring_alloc - allocate memory for the IH ring
> >> - *
> >> - * @adev: amdgpu_device pointer
> >> - *
> >> - * Allocate a ring buffer for the interrupt controller.
> >> - * Returns 0 for success, errors for failure.
> >> - */
> >> -static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) -{
> >> - int r;
> >> -
> >> - /* Allocate ring buffer */
> >> - if (adev->irq.ih.ring_obj == NULL) {
> >> - r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
> >> - PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_GTT,
> >> - &adev->irq.ih.ring_obj,
> >> - &adev->irq.ih.gpu_addr,
> >> - (void **)&adev->irq.ih.ring);
> >> - if (r) {
> >> - DRM_ERROR("amdgpu: failed to create ih ring buffer
> (%d).\n", r);
> >> - return r;
> >> - }
> >> - }
> >> - return 0;
> >> -}
> >> -
> >> /**
> >> * amdgpu_ih_ring_init - initialize the IH state
> >> *
> >> * @adev: amdgpu_device pointer
> >> + * @ih: ih ring to initialize
> >> + * @ring_size: ring size to allocate
> >> + * @use_bus_addr: true when we can use dma_alloc_coherent
> >> *
> >> * Initializes the IH state and allocates a buffer
> >> * for the IH ring buffer.
> >> * Returns 0 for success, errors for failure.
> >> */
> >> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
> ring_size,
> >> - bool use_bus_addr)
> >> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
> amdgpu_ih_ring *ih,
> >> + unsigned ring_size, bool use_bus_addr)
> >> {
> >> u32 rb_bufsz;
> >> int r;
> >> @@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device
> *adev, unsigned ring_size,
> >> /* Align ring size */
> >> rb_bufsz = order_base_2(ring_size / 4);
> >> ring_size = (1 << rb_bufsz) * 4;
> >> - adev->irq.ih.ring_size = ring_size;
> >> - adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
> >> - adev->irq.ih.rptr = 0;
> >> - adev->irq.ih.use_bus_addr = use_bus_addr;
> >> -
> >> - if (adev->irq.ih.use_bus_addr) {
> >> - if (!adev->irq.ih.ring) {
> >> - /* add 8 bytes for the rptr/wptr shadows and
> >> - * add them to the end of the ring allocation.
> >> - */
> >> - adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
> >> - adev-
> >irq.ih.ring_size + 8,
> >> - &adev-
> >irq.ih.rb_dma_addr);
> >> - if (adev->irq.ih.ring == NULL)
> >> - return -ENOMEM;
> >> - memset((void *)adev->irq.ih.ring, 0, adev-
> >irq.ih.ring_size + 8);
> >> - adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) +
> 0;
> >> - adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) +
> 1;
> >> - }
> >> - return 0;
> >> + ih->ring_size = ring_size;
> >> + ih->ptr_mask = ih->ring_size - 1;
> >> + ih->rptr = 0;
> >> + ih->use_bus_addr = use_bus_addr;
> >> +
> >> + if (use_bus_addr) {
> >> + if (ih->ring)
> >> + return 0;
> >> +
> >> + /* add 8 bytes for the rptr/wptr shadows and
> >> + * add them to the end of the ring allocation.
> >> + */
> >> + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
> >> + &ih->rb_dma_addr, GFP_KERNEL);
> >> + if (ih->ring == NULL)
> >> + return -ENOMEM;
> >> +
> >> + memset((void *)ih->ring, 0, ih->ring_size + 8);
> >> + ih->wptr_offs = (ih->ring_size / 4) + 0;
> >> + ih->rptr_offs = (ih->ring_size / 4) + 1;
> >> } else {
> >> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
> >> + r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
> >> + if (r)
> >> + return r;
> >> +
> >> + r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
> >> if (r) {
> >> - dev_err(adev->dev, "(%d) ih wptr_offs wb alloc
> failed\n", r);
> >> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >> return r;
> >> }
> >>
> >> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
> >> + r = amdgpu_bo_create_kernel(adev, ih->ring_size,
> PAGE_SIZE,
> >> + AMDGPU_GEM_DOMAIN_GTT,
> >> + &ih->ring_obj, &ih->gpu_addr,
> >> + (void **)&ih->ring);
> >> if (r) {
> >> - amdgpu_device_wb_free(adev, adev-
> >irq.ih.wptr_offs);
> >> - dev_err(adev->dev, "(%d) ih rptr_offs wb alloc
> failed\n", r);
> >> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> >> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >> return r;
> >> }
> >> -
> >> - return amdgpu_ih_ring_alloc(adev);
> >> }
> >> + return 0;
> >> }
> >>
> >> /**
> >> * amdgpu_ih_ring_fini - tear down the IH state
> >> *
> >> * @adev: amdgpu_device pointer
> >> + * @ih: ih ring to tear down
> >> *
> >> * Tears down the IH state and frees buffer
> >> * used for the IH ring buffer.
> >> */
> >> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
> >> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
> >> +amdgpu_ih_ring *ih)
> >> {
> >> - if (adev->irq.ih.use_bus_addr) {
> >> - if (adev->irq.ih.ring) {
> >> - /* add 8 bytes for the rptr/wptr shadows and
> >> - * add them to the end of the ring allocation.
> >> - */
> >> - pci_free_consistent(adev->pdev, adev-
> >irq.ih.ring_size + 8,
> >> - (void *)adev->irq.ih.ring,
> >> - adev->irq.ih.rb_dma_addr);
> >> - adev->irq.ih.ring = NULL;
> >> - }
> >> + if (ih->use_bus_addr) {
> >> + if (!ih->ring)
> >> + return;
> >> +
> >> + /* add 8 bytes for the rptr/wptr shadows and
> >> + * add them to the end of the ring allocation.
> >> + */
> >> + dma_free_coherent(adev->dev, ih->ring_size + 8,
> >> + (void *)ih->ring, ih->rb_dma_addr);
> >> + ih->ring = NULL;
> >> } else {
> >> - amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
> >> - &adev->irq.ih.gpu_addr,
> >> - (void **)&adev->irq.ih.ring);
> >> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
> >> - amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
> >> + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
> >> + (void **)&ih->ring);
> >> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> >> }
> >> }
> >>
> >> @@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct
> amdgpu_device *adev)
> >> * amdgpu_ih_process - interrupt handler
> >> *
> >> * @adev: amdgpu_device pointer
> >> + * @ih: ih ring to process
> >> *
> >> * Interrupt hander (VI), walk the IH ring.
> >> * Returns irq process return code.
> >> */
> >> -int amdgpu_ih_process(struct amdgpu_device *adev)
> >> +int amdgpu_ih_process(struct amdgpu_device *adev, struct
> >> +amdgpu_ih_ring *ih)
> >> {
> >> struct amdgpu_iv_entry entry;
> >> u32 wptr;
> >>
> >> - if (!adev->irq.ih.enabled || adev->shutdown)
> >> + if (!ih->enabled || adev->shutdown)
> >> return IRQ_NONE;
> >>
> >> wptr = amdgpu_ih_get_wptr(adev);
> >>
> >> restart_ih:
> >> /* is somebody else already processing irqs? */
> >> - if (atomic_xchg(&adev->irq.ih.lock, 1))
> >> + if (atomic_xchg(&ih->lock, 1))
> >> return IRQ_NONE;
> >>
> >> - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr,
> wptr);
> >> + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
> >>
> >> /* Order reading of wptr vs. reading of IH ring data */
> >> rmb();
> >>
> >> - while (adev->irq.ih.rptr != wptr) {
> >> - u32 ring_index = adev->irq.ih.rptr >> 2;
> >> + while (ih->rptr != wptr) {
> >> + u32 ring_index = ih->rptr >> 2;
> >>
> >> /* Prescreening of high-frequency interrupts */
> >> if (!amdgpu_ih_prescreen_iv(adev)) {
> >> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> >> + ih->rptr &= ih->ptr_mask;
> >> continue;
> >> }
> >>
> >> /* Before dispatching irq to IP blocks, send it to amdkfd */
> >> amdgpu_amdkfd_interrupt(adev,
> >> - (const void *) &adev->irq.ih.ring[ring_index]);
> >> + (const void *) &ih->ring[ring_index]);
> >>
> >> - entry.iv_entry = (const uint32_t *)
> >> - &adev->irq.ih.ring[ring_index];
> >> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> >> amdgpu_ih_decode_iv(adev, &entry);
> >> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> >> + ih->rptr &= ih->ptr_mask;
> >>
> >> amdgpu_irq_dispatch(adev, &entry);
> >> }
> >> amdgpu_ih_set_rptr(adev);
> >> - atomic_set(&adev->irq.ih.lock, 0);
> >> + atomic_set(&ih->lock, 0);
> >>
> >> /* make sure wptr hasn't changed while processing */
> >> wptr = amdgpu_ih_get_wptr(adev);
> >> - if (wptr != adev->irq.ih.rptr)
> >> + if (wptr != ih->rptr)
> >> goto restart_ih;
> >>
> >> return IRQ_HANDLED;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> index 0d5b3f5201d2..3e55f985005c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> @@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
> >> #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs-
> >decode_iv((adev), (iv))
> >> #define amdgpu_ih_set_rptr(adev)
> >> (adev)->irq.ih_funcs->set_rptr((adev))
> >>
> >> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
> ring_size,
> >> - bool use_bus_addr);
> >> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev); -int
> >> amdgpu_ih_process(struct amdgpu_device *adev);
> >> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
> amdgpu_ih_ring *ih,
> >> + unsigned ring_size, bool use_bus_addr); void
> >> +amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
> >> +amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device
> >> +*adev, struct amdgpu_ih_ring *ih);
> >>
> >> #endif
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> index b927e8798534..aaa8545e458a 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> @@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
> >> struct amdgpu_device *adev = dev->dev_private;
> >> irqreturn_t ret;
> >>
> >> - ret = amdgpu_ih_process(adev);
> >> + ret = amdgpu_ih_process(adev, &adev->irq.ih);
> >> if (ret == IRQ_HANDLED)
> >> pm_runtime_mark_last_busy(dev->dev);
> >> return ret;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> index e75183e09820..c37c4b76e7e9 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> @@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >> if (r)
> >> return r;
> >>
> >> @@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >> amdgpu_irq_remove_domain(adev);
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> index 9385da1e1e40..306e0bd154fa 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> @@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >> if (r)
> >> return r;
> >>
> >> @@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >> amdgpu_irq_remove_domain(adev);
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> index 45ef0a818e11..9005deeec612 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> @@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >> if (r)
> >> return r;
> >>
> >> @@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >> amdgpu_irq_remove_domain(adev);
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> index 97711d327527..acdf6075957a 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> @@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >> if (r)
> >> return r;
> >>
> >> @@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>
> >> return 0;
> >> }
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> index a79a3776888a..83fdf810ffc7 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> @@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
> >> if (r)
> >> return r;
> >>
> >> @@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >> amdgpu_irq_remove_domain(adev);
> >>
> >> return 0;
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> index 37487b4cbd6e..a99f71797aa3 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> @@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
> >> int r;
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> - r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
> >> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
> >> if (r)
> >> return r;
> >>
> >> @@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
> >> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>
> >> amdgpu_irq_fini(adev);
> >> - amdgpu_ih_ring_fini(adev);
> >> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>
> >> return 0;
> >> }
> >> --
> >> 2.14.1
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
[not found] ` <BY2PR12MB0040B93400AD69D00699F870EC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-09-26 8:57 ` Christian König
[not found] ` <366f6d5f-67f8-0d86-274c-bf93a59c60d3-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Christian König @ 2018-09-26 8:57 UTC (permalink / raw)
To: Huang, Ray; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 26.09.2018 um 10:52 schrieb Huang, Ray:
>> -----Original Message-----
>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
>> Sent: Tuesday, September 25, 2018 7:01 PM
>> To: Huang, Ray <Ray.Huang@amd.com>
>> Cc: amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
>>
>> Am 25.09.2018 um 12:28 schrieb Huang Rui:
>>> On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote:
>>>> Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
>>>>
>>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> Reviewed-by: Huang Rui <ray.huang@amd.com>
>>>
>>> Will we have multiple interrupt rings in new asic?
>> Vega already has 3 of them, we just haven't activated the other yet.
>>
> Good to know. I just took a look at the spec. IH ring 1 is used for request log and IH ring 2 is used for translation & invalidation log.
> They are to support the page migration feature. Do you plan to work on it?
Yes, actually the IH is able to route any IV to any ring based on the
client ID, e.g. who is sending the IV.
So I'm currently looking into routing the VM faults to ring 2 as well.
That should allow us to better handle them and avoid overwhelming the
CPU with an interrupt storm in case of page faults.
Regards,
Christian.
>
> Thanks,
> Ray
>
>> Christian.
>>
>>> Thanks,
>>> Ray
>>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152 ++++++++++++++---
>> ---------------
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
>>>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
>>>> 9 files changed, 84 insertions(+), 102 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>>>> index 4ed86218cef3..15fb0f9738ab 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
>>>> @@ -26,44 +26,20 @@
>>>> #include "amdgpu_ih.h"
>>>> #include "amdgpu_amdkfd.h"
>>>>
>>>> -/**
>>>> - * amdgpu_ih_ring_alloc - allocate memory for the IH ring
>>>> - *
>>>> - * @adev: amdgpu_device pointer
>>>> - *
>>>> - * Allocate a ring buffer for the interrupt controller.
>>>> - * Returns 0 for success, errors for failure.
>>>> - */
>>>> -static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) -{
>>>> - int r;
>>>> -
>>>> - /* Allocate ring buffer */
>>>> - if (adev->irq.ih.ring_obj == NULL) {
>>>> - r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
>>>> - PAGE_SIZE,
>> AMDGPU_GEM_DOMAIN_GTT,
>>>> - &adev->irq.ih.ring_obj,
>>>> - &adev->irq.ih.gpu_addr,
>>>> - (void **)&adev->irq.ih.ring);
>>>> - if (r) {
>>>> - DRM_ERROR("amdgpu: failed to create ih ring buffer
>> (%d).\n", r);
>>>> - return r;
>>>> - }
>>>> - }
>>>> - return 0;
>>>> -}
>>>> -
>>>> /**
>>>> * amdgpu_ih_ring_init - initialize the IH state
>>>> *
>>>> * @adev: amdgpu_device pointer
>>>> + * @ih: ih ring to initialize
>>>> + * @ring_size: ring size to allocate
>>>> + * @use_bus_addr: true when we can use dma_alloc_coherent
>>>> *
>>>> * Initializes the IH state and allocates a buffer
>>>> * for the IH ring buffer.
>>>> * Returns 0 for success, errors for failure.
>>>> */
>>>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
>> ring_size,
>>>> - bool use_bus_addr)
>>>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
>> amdgpu_ih_ring *ih,
>>>> + unsigned ring_size, bool use_bus_addr)
>>>> {
>>>> u32 rb_bufsz;
>>>> int r;
>>>> @@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device
>> *adev, unsigned ring_size,
>>>> /* Align ring size */
>>>> rb_bufsz = order_base_2(ring_size / 4);
>>>> ring_size = (1 << rb_bufsz) * 4;
>>>> - adev->irq.ih.ring_size = ring_size;
>>>> - adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
>>>> - adev->irq.ih.rptr = 0;
>>>> - adev->irq.ih.use_bus_addr = use_bus_addr;
>>>> -
>>>> - if (adev->irq.ih.use_bus_addr) {
>>>> - if (!adev->irq.ih.ring) {
>>>> - /* add 8 bytes for the rptr/wptr shadows and
>>>> - * add them to the end of the ring allocation.
>>>> - */
>>>> - adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
>>>> - adev-
>>> irq.ih.ring_size + 8,
>>>> - &adev-
>>> irq.ih.rb_dma_addr);
>>>> - if (adev->irq.ih.ring == NULL)
>>>> - return -ENOMEM;
>>>> - memset((void *)adev->irq.ih.ring, 0, adev-
>>> irq.ih.ring_size + 8);
>>>> - adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) +
>> 0;
>>>> - adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) +
>> 1;
>>>> - }
>>>> - return 0;
>>>> + ih->ring_size = ring_size;
>>>> + ih->ptr_mask = ih->ring_size - 1;
>>>> + ih->rptr = 0;
>>>> + ih->use_bus_addr = use_bus_addr;
>>>> +
>>>> + if (use_bus_addr) {
>>>> + if (ih->ring)
>>>> + return 0;
>>>> +
>>>> + /* add 8 bytes for the rptr/wptr shadows and
>>>> + * add them to the end of the ring allocation.
>>>> + */
>>>> + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
>>>> + &ih->rb_dma_addr, GFP_KERNEL);
>>>> + if (ih->ring == NULL)
>>>> + return -ENOMEM;
>>>> +
>>>> + memset((void *)ih->ring, 0, ih->ring_size + 8);
>>>> + ih->wptr_offs = (ih->ring_size / 4) + 0;
>>>> + ih->rptr_offs = (ih->ring_size / 4) + 1;
>>>> } else {
>>>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
>>>> + r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
>>>> + if (r)
>>>> + return r;
>>>> +
>>>> + r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
>>>> if (r) {
>>>> - dev_err(adev->dev, "(%d) ih wptr_offs wb alloc
>> failed\n", r);
>>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>>>> return r;
>>>> }
>>>>
>>>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
>>>> + r = amdgpu_bo_create_kernel(adev, ih->ring_size,
>> PAGE_SIZE,
>>>> + AMDGPU_GEM_DOMAIN_GTT,
>>>> + &ih->ring_obj, &ih->gpu_addr,
>>>> + (void **)&ih->ring);
>>>> if (r) {
>>>> - amdgpu_device_wb_free(adev, adev-
>>> irq.ih.wptr_offs);
>>>> - dev_err(adev->dev, "(%d) ih rptr_offs wb alloc
>> failed\n", r);
>>>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
>>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>>>> return r;
>>>> }
>>>> -
>>>> - return amdgpu_ih_ring_alloc(adev);
>>>> }
>>>> + return 0;
>>>> }
>>>>
>>>> /**
>>>> * amdgpu_ih_ring_fini - tear down the IH state
>>>> *
>>>> * @adev: amdgpu_device pointer
>>>> + * @ih: ih ring to tear down
>>>> *
>>>> * Tears down the IH state and frees buffer
>>>> * used for the IH ring buffer.
>>>> */
>>>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
>>>> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
>>>> +amdgpu_ih_ring *ih)
>>>> {
>>>> - if (adev->irq.ih.use_bus_addr) {
>>>> - if (adev->irq.ih.ring) {
>>>> - /* add 8 bytes for the rptr/wptr shadows and
>>>> - * add them to the end of the ring allocation.
>>>> - */
>>>> - pci_free_consistent(adev->pdev, adev-
>>> irq.ih.ring_size + 8,
>>>> - (void *)adev->irq.ih.ring,
>>>> - adev->irq.ih.rb_dma_addr);
>>>> - adev->irq.ih.ring = NULL;
>>>> - }
>>>> + if (ih->use_bus_addr) {
>>>> + if (!ih->ring)
>>>> + return;
>>>> +
>>>> + /* add 8 bytes for the rptr/wptr shadows and
>>>> + * add them to the end of the ring allocation.
>>>> + */
>>>> + dma_free_coherent(adev->dev, ih->ring_size + 8,
>>>> + (void *)ih->ring, ih->rb_dma_addr);
>>>> + ih->ring = NULL;
>>>> } else {
>>>> - amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
>>>> - &adev->irq.ih.gpu_addr,
>>>> - (void **)&adev->irq.ih.ring);
>>>> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
>>>> - amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
>>>> + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
>>>> + (void **)&ih->ring);
>>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
>>>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
>>>> }
>>>> }
>>>>
>>>> @@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct
>> amdgpu_device *adev)
>>>> * amdgpu_ih_process - interrupt handler
>>>> *
>>>> * @adev: amdgpu_device pointer
>>>> + * @ih: ih ring to process
>>>> *
>>>> * Interrupt hander (VI), walk the IH ring.
>>>> * Returns irq process return code.
>>>> */
>>>> -int amdgpu_ih_process(struct amdgpu_device *adev)
>>>> +int amdgpu_ih_process(struct amdgpu_device *adev, struct
>>>> +amdgpu_ih_ring *ih)
>>>> {
>>>> struct amdgpu_iv_entry entry;
>>>> u32 wptr;
>>>>
>>>> - if (!adev->irq.ih.enabled || adev->shutdown)
>>>> + if (!ih->enabled || adev->shutdown)
>>>> return IRQ_NONE;
>>>>
>>>> wptr = amdgpu_ih_get_wptr(adev);
>>>>
>>>> restart_ih:
>>>> /* is somebody else already processing irqs? */
>>>> - if (atomic_xchg(&adev->irq.ih.lock, 1))
>>>> + if (atomic_xchg(&ih->lock, 1))
>>>> return IRQ_NONE;
>>>>
>>>> - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr,
>> wptr);
>>>> + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
>>>>
>>>> /* Order reading of wptr vs. reading of IH ring data */
>>>> rmb();
>>>>
>>>> - while (adev->irq.ih.rptr != wptr) {
>>>> - u32 ring_index = adev->irq.ih.rptr >> 2;
>>>> + while (ih->rptr != wptr) {
>>>> + u32 ring_index = ih->rptr >> 2;
>>>>
>>>> /* Prescreening of high-frequency interrupts */
>>>> if (!amdgpu_ih_prescreen_iv(adev)) {
>>>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
>>>> + ih->rptr &= ih->ptr_mask;
>>>> continue;
>>>> }
>>>>
>>>> /* Before dispatching irq to IP blocks, send it to amdkfd */
>>>> amdgpu_amdkfd_interrupt(adev,
>>>> - (const void *) &adev->irq.ih.ring[ring_index]);
>>>> + (const void *) &ih->ring[ring_index]);
>>>>
>>>> - entry.iv_entry = (const uint32_t *)
>>>> - &adev->irq.ih.ring[ring_index];
>>>> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
>>>> amdgpu_ih_decode_iv(adev, &entry);
>>>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
>>>> + ih->rptr &= ih->ptr_mask;
>>>>
>>>> amdgpu_irq_dispatch(adev, &entry);
>>>> }
>>>> amdgpu_ih_set_rptr(adev);
>>>> - atomic_set(&adev->irq.ih.lock, 0);
>>>> + atomic_set(&ih->lock, 0);
>>>>
>>>> /* make sure wptr hasn't changed while processing */
>>>> wptr = amdgpu_ih_get_wptr(adev);
>>>> - if (wptr != adev->irq.ih.rptr)
>>>> + if (wptr != ih->rptr)
>>>> goto restart_ih;
>>>>
>>>> return IRQ_HANDLED;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> index 0d5b3f5201d2..3e55f985005c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> @@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
>>>> #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs-
>>> decode_iv((adev), (iv))
>>>> #define amdgpu_ih_set_rptr(adev)
>>>> (adev)->irq.ih_funcs->set_rptr((adev))
>>>>
>>>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
>> ring_size,
>>>> - bool use_bus_addr);
>>>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev); -int
>>>> amdgpu_ih_process(struct amdgpu_device *adev);
>>>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
>> amdgpu_ih_ring *ih,
>>>> + unsigned ring_size, bool use_bus_addr); void
>>>> +amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
>>>> +amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device
>>>> +*adev, struct amdgpu_ih_ring *ih);
>>>>
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> index b927e8798534..aaa8545e458a 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> @@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
>>>> struct amdgpu_device *adev = dev->dev_private;
>>>> irqreturn_t ret;
>>>>
>>>> - ret = amdgpu_ih_process(adev);
>>>> + ret = amdgpu_ih_process(adev, &adev->irq.ih);
>>>> if (ret == IRQ_HANDLED)
>>>> pm_runtime_mark_last_busy(dev->dev);
>>>> return ret;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> index e75183e09820..c37c4b76e7e9 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> @@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>> amdgpu_irq_remove_domain(adev);
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> index 9385da1e1e40..306e0bd154fa 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> @@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>> amdgpu_irq_remove_domain(adev);
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> index 45ef0a818e11..9005deeec612 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> @@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>> amdgpu_irq_remove_domain(adev);
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> index 97711d327527..acdf6075957a 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> @@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>>
>>>> return 0;
>>>> }
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> index a79a3776888a..83fdf810ffc7 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> @@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>> amdgpu_irq_remove_domain(adev);
>>>>
>>>> return 0;
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> index 37487b4cbd6e..a99f71797aa3 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> @@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
>>>> int r;
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> - r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
>>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
>>>> if (r)
>>>> return r;
>>>>
>>>> @@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
>>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>
>>>> amdgpu_irq_fini(adev);
>>>> - amdgpu_ih_ring_fini(adev);
>>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
>>>>
>>>> return 0;
>>>> }
>>>> --
>>>> 2.14.1
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
[not found] ` <39fb9a51-2e85-0828-a193-b54059dec405-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-09-26 9:16 ` Huang, Ray
[not found] ` <BY2PR12MB00400B029B1F4C1256CE558AEC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 26+ messages in thread
From: Huang, Ray @ 2018-09-26 9:16 UTC (permalink / raw)
To: Koenig, Christian; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
> Sent: Wednesday, September 26, 2018 4:09 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
>
> Am 26.09.2018 um 08:05 schrieb Huang Rui:
> > On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote:
> >> One for the ring buffer and one for the IV handling.
> >>
> >> Signed-off-by: Christian König <christian.koenig@amd.com>
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> >
> > How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't
> > need two common interrupt handle files. IH is actually the hw ip block
> > name, and the meaning is actually the same with irq. We can put all
> > common irq handle include ih ring init functions into irq.c. If you
> > also agree, I will file the patch.
>
> I actually dropped this patch, but we certainly need two different files.
>
> The one is for the IH ring buffer, which Vega10 actually has 3 of.
>
> The other one is for the IRQ handling which does the tracking how often
> interrupt sources are enabled, how to route them etc...
>
> E.g. for that we would still have one instance per device.
>
So you want to separate the hardware-layer abstraction function and IRQ handling for upper-layer on different file?
That's also fine.
Thanks,
Ray
> Regards,
> Christian.
>
> >
> > Thanks,
> > Ray
> >
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ++++-------
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++++++++++-
> >> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 ++++++--
> >> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 ++++++--
> >> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 ++++++--
> >> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++++--
> >> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 ++++++--
> >> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 ++++++--
> >> 9 files changed, 52 insertions(+), 22 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> index 9ce8c93ec19b..d88f82321ee4 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >> @@ -45,22 +45,19 @@ struct amdgpu_ih_ring {
> >> bool use_doorbell;
> >> bool use_bus_addr;
> >> dma_addr_t rb_dma_addr; /* only used when
> use_bus_addr = true */
> >> +
> >> + const struct amdgpu_ih_funcs *funcs;
> >> };
> >>
> >> /* provided by the ih block */
> >> struct amdgpu_ih_funcs {
> >> /* ring read/write ptr handling, called from interrupt context */
> >> u32 (*get_wptr)(struct amdgpu_device *adev);
> >> - bool (*prescreen_iv)(struct amdgpu_device *adev);
> >> - void (*decode_iv)(struct amdgpu_device *adev,
> >> - struct amdgpu_iv_entry *entry);
> >> void (*set_rptr)(struct amdgpu_device *adev);
> >> };
> >>
> >> -#define amdgpu_ih_get_wptr(adev)
> >> (adev)->irq.ih_funcs->get_wptr((adev))
> >> -#define amdgpu_ih_prescreen_iv(adev)
> >> (adev)->irq.ih_funcs->prescreen_iv((adev))
> >> -#define amdgpu_ih_decode_iv(adev, iv)
> >> (adev)->irq.ih_funcs->decode_iv((adev), (iv)) -#define
> >> amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
> >> +#define amdgpu_ih_get_wptr(adev)
> >> +(adev)->irq.ih.funcs->get_wptr((adev))
> >> +#define amdgpu_ih_set_rptr(adev)
> >> +(adev)->irq.ih.funcs->set_rptr((adev))
> >>
> >> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
> amdgpu_ih_ring *ih,
> >> unsigned ring_size, bool use_bus_addr); diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> index 52c17f6219a7..8e5ce25f3fe1 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >> @@ -163,14 +163,14 @@ static void amdgpu_irq_callback(struct
> amdgpu_device *adev,
> >> struct amdgpu_iv_entry entry;
> >>
> >> /* Prescreening of high-frequency interrupts */
> >> - if (!amdgpu_ih_prescreen_iv(adev))
> >> + if (!amdgpu_irq_prescreen_iv(adev))
> >> return;
> >>
> >> /* Before dispatching irq to IP blocks, send it to amdkfd */
> >> amdgpu_amdkfd_interrupt(adev, (const void *)
> >> &ih->ring[ring_index]);
> >>
> >> entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> >> - amdgpu_ih_decode_iv(adev, &entry);
> >> + amdgpu_irq_decode_iv(adev, &entry);
> >>
> >> amdgpu_irq_dispatch(adev, &entry);
> >> }
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> >> index f6ce171cb8aa..3cc0e7ce40a0 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> >> @@ -68,6 +68,12 @@ struct amdgpu_irq_client {
> >> struct amdgpu_irq_src **sources;
> >> };
> >>
> >> +struct amdgpu_irq_funcs {
> >> + bool (*prescreen_iv)(struct amdgpu_device *adev);
> >> + void (*decode_iv)(struct amdgpu_device *adev,
> >> + struct amdgpu_iv_entry *entry); };
> >> +
> >> /* provided by interrupt generating IP blocks */
> >> struct amdgpu_irq_src_funcs {
> >> int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src
> >> *source, @@ -89,12 +95,12 @@ struct amdgpu_irq {
> >>
> >> /* interrupt ring */
> >> struct amdgpu_ih_ring ih;
> >> - const struct amdgpu_ih_funcs *ih_funcs;
> >>
> >> /* gen irq stuff */
> >> struct irq_domain *domain; /* GPU irq controller
> domain */
> >> unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
> >> uint32_t srbm_soft_reset;
> >> + const struct amdgpu_irq_funcs *funcs;
> >> };
> >>
> >> void amdgpu_irq_disable_all(struct amdgpu_device *adev); @@ -121,4
> >> +127,7 @@ int amdgpu_irq_add_domain(struct amdgpu_device *adev);
> >> void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
> >> unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev,
> >> unsigned src_id);
> >>
> >> +#define amdgpu_irq_prescreen_iv(adev)
> >> +(adev)->irq.funcs->prescreen_iv((adev))
> >> +#define amdgpu_irq_decode_iv(adev, iv)
> >> +(adev)->irq.funcs->decode_iv((adev), (iv))
> >> +
> >> #endif
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> index b5775c6a857b..161f0225749c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >> @@ -461,14 +461,18 @@ static const struct amd_ip_funcs
> >> cik_ih_ip_funcs = {
> >>
> >> static const struct amdgpu_ih_funcs cik_ih_funcs = {
> >> .get_wptr = cik_ih_get_wptr,
> >> + .set_rptr = cik_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs cik_irq_funcs = {
> >> .prescreen_iv = cik_ih_prescreen_iv,
> >> .decode_iv = cik_ih_decode_iv,
> >> - .set_rptr = cik_ih_set_rptr
> >> };
> >>
> >> static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &cik_ih_funcs;
> >> + adev->irq.ih.funcs = &cik_ih_funcs;
> >> + adev->irq.funcs = &cik_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version cik_ih_ip_block = diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> index df5ac4d85a00..648ecd774611 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >> @@ -442,14 +442,18 @@ static const struct amd_ip_funcs cz_ih_ip_funcs
> >> = {
> >>
> >> static const struct amdgpu_ih_funcs cz_ih_funcs = {
> >> .get_wptr = cz_ih_get_wptr,
> >> + .set_rptr = cz_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs cz_irq_funcs = {
> >> .prescreen_iv = cz_ih_prescreen_iv,
> >> .decode_iv = cz_ih_decode_iv,
> >> - .set_rptr = cz_ih_set_rptr
> >> };
> >>
> >> static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &cz_ih_funcs;
> >> + adev->irq.ih.funcs = &cz_ih_funcs;
> >> + adev->irq.funcs = &cz_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version cz_ih_ip_block = diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> index cf0fc61aebe6..6139186ccd36 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >> @@ -440,14 +440,18 @@ static const struct amd_ip_funcs
> >> iceland_ih_ip_funcs = {
> >>
> >> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
> >> .get_wptr = iceland_ih_get_wptr,
> >> + .set_rptr = iceland_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs iceland_irq_funcs = {
> >> .prescreen_iv = iceland_ih_prescreen_iv,
> >> .decode_iv = iceland_ih_decode_iv,
> >> - .set_rptr = iceland_ih_set_rptr
> >> };
> >>
> >> static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &iceland_ih_funcs;
> >> + adev->irq.ih.funcs = &iceland_ih_funcs;
> >> + adev->irq.funcs = &iceland_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version iceland_ih_ip_block = diff
> >> --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> index b3d7d9f83202..16f212f3b534 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >> @@ -301,14 +301,18 @@ static const struct amd_ip_funcs si_ih_ip_funcs
> >> = {
> >>
> >> static const struct amdgpu_ih_funcs si_ih_funcs = {
> >> .get_wptr = si_ih_get_wptr,
> >> + .set_rptr = si_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs si_irq_funcs = {
> >> .prescreen_iv = si_ih_prescreen_iv,
> >> .decode_iv = si_ih_decode_iv,
> >> - .set_rptr = si_ih_set_rptr
> >> };
> >>
> >> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &si_ih_funcs;
> >> + adev->irq.ih.funcs = &si_ih_funcs;
> >> + adev->irq.funcs = &si_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version si_ih_ip_block = diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> index 3abffd06b5c7..6120ac3c7667 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >> @@ -506,14 +506,18 @@ static const struct amd_ip_funcs
> >> tonga_ih_ip_funcs = {
> >>
> >> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
> >> .get_wptr = tonga_ih_get_wptr,
> >> + .set_rptr = tonga_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs tonga_irq_funcs = {
> >> .prescreen_iv = tonga_ih_prescreen_iv,
> >> .decode_iv = tonga_ih_decode_iv,
> >> - .set_rptr = tonga_ih_set_rptr
> >> };
> >>
> >> static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &tonga_ih_funcs;
> >> + adev->irq.ih.funcs = &tonga_ih_funcs;
> >> + adev->irq.funcs = &tonga_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version tonga_ih_ip_block = diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> index a99f71797aa3..a9737adf8392 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >> @@ -487,14 +487,18 @@ const struct amd_ip_funcs vega10_ih_ip_funcs
> =
> >> {
> >>
> >> static const struct amdgpu_ih_funcs vega10_ih_funcs = {
> >> .get_wptr = vega10_ih_get_wptr,
> >> + .set_rptr = vega10_ih_set_rptr
> >> +};
> >> +
> >> +static const struct amdgpu_irq_funcs vega10_irq_funcs = {
> >> .prescreen_iv = vega10_ih_prescreen_iv,
> >> .decode_iv = vega10_ih_decode_iv,
> >> - .set_rptr = vega10_ih_set_rptr
> >> };
> >>
> >> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
> >> {
> >> - adev->irq.ih_funcs = &vega10_ih_funcs;
> >> + adev->irq.ih.funcs = &vega10_ih_funcs;
> >> + adev->irq.funcs = &vega10_irq_funcs;
> >> }
> >>
> >> const struct amdgpu_ip_block_version vega10_ih_ip_block =
> >> --
> >> 2.14.1
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
[not found] ` <BY2PR12MB00400B029B1F4C1256CE558AEC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-09-26 9:18 ` Christian König
0 siblings, 0 replies; 26+ messages in thread
From: Christian König @ 2018-09-26 9:18 UTC (permalink / raw)
To: Huang, Ray; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 26.09.2018 um 11:16 schrieb Huang, Ray:
>> -----Original Message-----
>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
>> Sent: Wednesday, September 26, 2018 4:09 PM
>> To: Huang, Ray <Ray.Huang@amd.com>
>> Cc: amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
>>
>> Am 26.09.2018 um 08:05 schrieb Huang Rui:
>>> On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote:
>>>> One for the ring buffer and one for the IV handling.
>>>>
>>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> Reviewed-by: Huang Rui <ray.huang@amd.com>
>>>
>>> How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't
>>> need two common interrupt handle files. IH is actually the hw ip block
>>> name, and the meaning is actually the same with irq. We can put all
>>> common irq handle include ih ring init functions into irq.c. If you
>>> also agree, I will file the patch.
>> I actually dropped this patch, but we certainly need two different files.
>>
>> The one is for the IH ring buffer, which Vega10 actually has 3 of.
>>
>> The other one is for the IRQ handling which does the tracking how often
>> interrupt sources are enabled, how to route them etc...
>>
>> E.g. for that we would still have one instance per device.
>>
> So you want to separate the hardware-layer abstraction function and IRQ handling for upper-layer on different file?
Yes, exactly.
> That's also fine.
I'm just not sure about the naming of files, functions and structures.
Any better suggestion would be welcome.
Christian.
>
> Thanks,
> Ray
>
>> Regards,
>> Christian.
>>
>>> Thanks,
>>> Ray
>>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 11 ++++-------
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 11 ++++++++++-
>>>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 ++++++--
>>>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 ++++++--
>>>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 ++++++--
>>>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++++--
>>>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 ++++++--
>>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 ++++++--
>>>> 9 files changed, 52 insertions(+), 22 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> index 9ce8c93ec19b..d88f82321ee4 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
>>>> @@ -45,22 +45,19 @@ struct amdgpu_ih_ring {
>>>> bool use_doorbell;
>>>> bool use_bus_addr;
>>>> dma_addr_t rb_dma_addr; /* only used when
>> use_bus_addr = true */
>>>> +
>>>> + const struct amdgpu_ih_funcs *funcs;
>>>> };
>>>>
>>>> /* provided by the ih block */
>>>> struct amdgpu_ih_funcs {
>>>> /* ring read/write ptr handling, called from interrupt context */
>>>> u32 (*get_wptr)(struct amdgpu_device *adev);
>>>> - bool (*prescreen_iv)(struct amdgpu_device *adev);
>>>> - void (*decode_iv)(struct amdgpu_device *adev,
>>>> - struct amdgpu_iv_entry *entry);
>>>> void (*set_rptr)(struct amdgpu_device *adev);
>>>> };
>>>>
>>>> -#define amdgpu_ih_get_wptr(adev)
>>>> (adev)->irq.ih_funcs->get_wptr((adev))
>>>> -#define amdgpu_ih_prescreen_iv(adev)
>>>> (adev)->irq.ih_funcs->prescreen_iv((adev))
>>>> -#define amdgpu_ih_decode_iv(adev, iv)
>>>> (adev)->irq.ih_funcs->decode_iv((adev), (iv)) -#define
>>>> amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
>>>> +#define amdgpu_ih_get_wptr(adev)
>>>> +(adev)->irq.ih.funcs->get_wptr((adev))
>>>> +#define amdgpu_ih_set_rptr(adev)
>>>> +(adev)->irq.ih.funcs->set_rptr((adev))
>>>>
>>>> int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
>> amdgpu_ih_ring *ih,
>>>> unsigned ring_size, bool use_bus_addr); diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> index 52c17f6219a7..8e5ce25f3fe1 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
>>>> @@ -163,14 +163,14 @@ static void amdgpu_irq_callback(struct
>> amdgpu_device *adev,
>>>> struct amdgpu_iv_entry entry;
>>>>
>>>> /* Prescreening of high-frequency interrupts */
>>>> - if (!amdgpu_ih_prescreen_iv(adev))
>>>> + if (!amdgpu_irq_prescreen_iv(adev))
>>>> return;
>>>>
>>>> /* Before dispatching irq to IP blocks, send it to amdkfd */
>>>> amdgpu_amdkfd_interrupt(adev, (const void *)
>>>> &ih->ring[ring_index]);
>>>>
>>>> entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
>>>> - amdgpu_ih_decode_iv(adev, &entry);
>>>> + amdgpu_irq_decode_iv(adev, &entry);
>>>>
>>>> amdgpu_irq_dispatch(adev, &entry);
>>>> }
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>>>> index f6ce171cb8aa..3cc0e7ce40a0 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
>>>> @@ -68,6 +68,12 @@ struct amdgpu_irq_client {
>>>> struct amdgpu_irq_src **sources;
>>>> };
>>>>
>>>> +struct amdgpu_irq_funcs {
>>>> + bool (*prescreen_iv)(struct amdgpu_device *adev);
>>>> + void (*decode_iv)(struct amdgpu_device *adev,
>>>> + struct amdgpu_iv_entry *entry); };
>>>> +
>>>> /* provided by interrupt generating IP blocks */
>>>> struct amdgpu_irq_src_funcs {
>>>> int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src
>>>> *source, @@ -89,12 +95,12 @@ struct amdgpu_irq {
>>>>
>>>> /* interrupt ring */
>>>> struct amdgpu_ih_ring ih;
>>>> - const struct amdgpu_ih_funcs *ih_funcs;
>>>>
>>>> /* gen irq stuff */
>>>> struct irq_domain *domain; /* GPU irq controller
>> domain */
>>>> unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
>>>> uint32_t srbm_soft_reset;
>>>> + const struct amdgpu_irq_funcs *funcs;
>>>> };
>>>>
>>>> void amdgpu_irq_disable_all(struct amdgpu_device *adev); @@ -121,4
>>>> +127,7 @@ int amdgpu_irq_add_domain(struct amdgpu_device *adev);
>>>> void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
>>>> unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev,
>>>> unsigned src_id);
>>>>
>>>> +#define amdgpu_irq_prescreen_iv(adev)
>>>> +(adev)->irq.funcs->prescreen_iv((adev))
>>>> +#define amdgpu_irq_decode_iv(adev, iv)
>>>> +(adev)->irq.funcs->decode_iv((adev), (iv))
>>>> +
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> index b5775c6a857b..161f0225749c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>>>> @@ -461,14 +461,18 @@ static const struct amd_ip_funcs
>>>> cik_ih_ip_funcs = {
>>>>
>>>> static const struct amdgpu_ih_funcs cik_ih_funcs = {
>>>> .get_wptr = cik_ih_get_wptr,
>>>> + .set_rptr = cik_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs cik_irq_funcs = {
>>>> .prescreen_iv = cik_ih_prescreen_iv,
>>>> .decode_iv = cik_ih_decode_iv,
>>>> - .set_rptr = cik_ih_set_rptr
>>>> };
>>>>
>>>> static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &cik_ih_funcs;
>>>> + adev->irq.ih.funcs = &cik_ih_funcs;
>>>> + adev->irq.funcs = &cik_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version cik_ih_ip_block = diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> index df5ac4d85a00..648ecd774611 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>>>> @@ -442,14 +442,18 @@ static const struct amd_ip_funcs cz_ih_ip_funcs
>>>> = {
>>>>
>>>> static const struct amdgpu_ih_funcs cz_ih_funcs = {
>>>> .get_wptr = cz_ih_get_wptr,
>>>> + .set_rptr = cz_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs cz_irq_funcs = {
>>>> .prescreen_iv = cz_ih_prescreen_iv,
>>>> .decode_iv = cz_ih_decode_iv,
>>>> - .set_rptr = cz_ih_set_rptr
>>>> };
>>>>
>>>> static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &cz_ih_funcs;
>>>> + adev->irq.ih.funcs = &cz_ih_funcs;
>>>> + adev->irq.funcs = &cz_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version cz_ih_ip_block = diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> index cf0fc61aebe6..6139186ccd36 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>>>> @@ -440,14 +440,18 @@ static const struct amd_ip_funcs
>>>> iceland_ih_ip_funcs = {
>>>>
>>>> static const struct amdgpu_ih_funcs iceland_ih_funcs = {
>>>> .get_wptr = iceland_ih_get_wptr,
>>>> + .set_rptr = iceland_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs iceland_irq_funcs = {
>>>> .prescreen_iv = iceland_ih_prescreen_iv,
>>>> .decode_iv = iceland_ih_decode_iv,
>>>> - .set_rptr = iceland_ih_set_rptr
>>>> };
>>>>
>>>> static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &iceland_ih_funcs;
>>>> + adev->irq.ih.funcs = &iceland_ih_funcs;
>>>> + adev->irq.funcs = &iceland_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version iceland_ih_ip_block = diff
>>>> --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> index b3d7d9f83202..16f212f3b534 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>>>> @@ -301,14 +301,18 @@ static const struct amd_ip_funcs si_ih_ip_funcs
>>>> = {
>>>>
>>>> static const struct amdgpu_ih_funcs si_ih_funcs = {
>>>> .get_wptr = si_ih_get_wptr,
>>>> + .set_rptr = si_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs si_irq_funcs = {
>>>> .prescreen_iv = si_ih_prescreen_iv,
>>>> .decode_iv = si_ih_decode_iv,
>>>> - .set_rptr = si_ih_set_rptr
>>>> };
>>>>
>>>> static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &si_ih_funcs;
>>>> + adev->irq.ih.funcs = &si_ih_funcs;
>>>> + adev->irq.funcs = &si_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version si_ih_ip_block = diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> index 3abffd06b5c7..6120ac3c7667 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>>>> @@ -506,14 +506,18 @@ static const struct amd_ip_funcs
>>>> tonga_ih_ip_funcs = {
>>>>
>>>> static const struct amdgpu_ih_funcs tonga_ih_funcs = {
>>>> .get_wptr = tonga_ih_get_wptr,
>>>> + .set_rptr = tonga_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs tonga_irq_funcs = {
>>>> .prescreen_iv = tonga_ih_prescreen_iv,
>>>> .decode_iv = tonga_ih_decode_iv,
>>>> - .set_rptr = tonga_ih_set_rptr
>>>> };
>>>>
>>>> static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &tonga_ih_funcs;
>>>> + adev->irq.ih.funcs = &tonga_ih_funcs;
>>>> + adev->irq.funcs = &tonga_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version tonga_ih_ip_block = diff --git
>>>> a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> index a99f71797aa3..a9737adf8392 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> @@ -487,14 +487,18 @@ const struct amd_ip_funcs vega10_ih_ip_funcs
>> =
>>>> {
>>>>
>>>> static const struct amdgpu_ih_funcs vega10_ih_funcs = {
>>>> .get_wptr = vega10_ih_get_wptr,
>>>> + .set_rptr = vega10_ih_set_rptr
>>>> +};
>>>> +
>>>> +static const struct amdgpu_irq_funcs vega10_irq_funcs = {
>>>> .prescreen_iv = vega10_ih_prescreen_iv,
>>>> .decode_iv = vega10_ih_decode_iv,
>>>> - .set_rptr = vega10_ih_set_rptr
>>>> };
>>>>
>>>> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
>>>> {
>>>> - adev->irq.ih_funcs = &vega10_ih_funcs;
>>>> + adev->irq.ih.funcs = &vega10_ih_funcs;
>>>> + adev->irq.funcs = &vega10_irq_funcs;
>>>> }
>>>>
>>>> const struct amdgpu_ip_block_version vega10_ih_ip_block =
>>>> --
>>>> 2.14.1
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* RE: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
[not found] ` <366f6d5f-67f8-0d86-274c-bf93a59c60d3-5C7GfCeVMHo@public.gmane.org>
@ 2018-09-26 10:36 ` Huang, Ray
0 siblings, 0 replies; 26+ messages in thread
From: Huang, Ray @ 2018-09-26 10:36 UTC (permalink / raw)
To: Koenig, Christian; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: Koenig, Christian
> Sent: Wednesday, September 26, 2018 4:58 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
>
> Am 26.09.2018 um 10:52 schrieb Huang, Ray:
> >> -----Original Message-----
> >> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
> >> Sent: Tuesday, September 25, 2018 7:01 PM
> >> To: Huang, Ray <Ray.Huang@amd.com>
> >> Cc: amd-gfx@lists.freedesktop.org
> >> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
> >>
> >> Am 25.09.2018 um 12:28 schrieb Huang Rui:
> >>> On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote:
> >>>> Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings.
> >>>>
> >>>> Signed-off-by: Christian König <christian.koenig@amd.com>
> >>> Reviewed-by: Huang Rui <ray.huang@amd.com>
> >>>
> >>> Will we have multiple interrupt rings in new asic?
> >> Vega already has 3 of them, we just haven't activated the other yet.
> >>
> > Good to know. I just took a look at the spec. IH ring 1 is used for request log
> and IH ring 2 is used for translation & invalidation log.
> > They are to support the page migration feature. Do you plan to work on it?
>
> Yes, actually the IH is able to route any IV to any ring based on the client ID,
> e.g. who is sending the IV.
>
> So I'm currently looking into routing the VM faults to ring 2 as well.
> That should allow us to better handle them and avoid overwhelming the CPU
> with an interrupt storm in case of page faults.
I see, thanks for explanation
Thanks,
Ray
>
> Regards,
> Christian.
>
> >
> > Thanks,
> > Ray
> >
> >> Christian.
> >>
> >>> Thanks,
> >>> Ray
> >>>
> >>>> ---
> >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 152
> ++++++++++++++---
> >> ---------------
> >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8 +-
> >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
> >>>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-
> >>>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-
> >>>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-
> >>>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 +-
> >>>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-
> >>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +-
> >>>> 9 files changed, 84 insertions(+), 102 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >>>> index 4ed86218cef3..15fb0f9738ab 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
> >>>> @@ -26,44 +26,20 @@
> >>>> #include "amdgpu_ih.h"
> >>>> #include "amdgpu_amdkfd.h"
> >>>>
> >>>> -/**
> >>>> - * amdgpu_ih_ring_alloc - allocate memory for the IH ring
> >>>> - *
> >>>> - * @adev: amdgpu_device pointer
> >>>> - *
> >>>> - * Allocate a ring buffer for the interrupt controller.
> >>>> - * Returns 0 for success, errors for failure.
> >>>> - */
> >>>> -static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev) -{
> >>>> - int r;
> >>>> -
> >>>> - /* Allocate ring buffer */
> >>>> - if (adev->irq.ih.ring_obj == NULL) {
> >>>> - r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
> >>>> - PAGE_SIZE,
> >> AMDGPU_GEM_DOMAIN_GTT,
> >>>> - &adev->irq.ih.ring_obj,
> >>>> - &adev->irq.ih.gpu_addr,
> >>>> - (void **)&adev->irq.ih.ring);
> >>>> - if (r) {
> >>>> - DRM_ERROR("amdgpu: failed to create ih ring buffer
> >> (%d).\n", r);
> >>>> - return r;
> >>>> - }
> >>>> - }
> >>>> - return 0;
> >>>> -}
> >>>> -
> >>>> /**
> >>>> * amdgpu_ih_ring_init - initialize the IH state
> >>>> *
> >>>> * @adev: amdgpu_device pointer
> >>>> + * @ih: ih ring to initialize
> >>>> + * @ring_size: ring size to allocate
> >>>> + * @use_bus_addr: true when we can use dma_alloc_coherent
> >>>> *
> >>>> * Initializes the IH state and allocates a buffer
> >>>> * for the IH ring buffer.
> >>>> * Returns 0 for success, errors for failure.
> >>>> */
> >>>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
> >> ring_size,
> >>>> - bool use_bus_addr)
> >>>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
> >> amdgpu_ih_ring *ih,
> >>>> + unsigned ring_size, bool use_bus_addr)
> >>>> {
> >>>> u32 rb_bufsz;
> >>>> int r;
> >>>> @@ -71,70 +47,76 @@ int amdgpu_ih_ring_init(struct amdgpu_device
> >> *adev, unsigned ring_size,
> >>>> /* Align ring size */
> >>>> rb_bufsz = order_base_2(ring_size / 4);
> >>>> ring_size = (1 << rb_bufsz) * 4;
> >>>> - adev->irq.ih.ring_size = ring_size;
> >>>> - adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
> >>>> - adev->irq.ih.rptr = 0;
> >>>> - adev->irq.ih.use_bus_addr = use_bus_addr;
> >>>> -
> >>>> - if (adev->irq.ih.use_bus_addr) {
> >>>> - if (!adev->irq.ih.ring) {
> >>>> - /* add 8 bytes for the rptr/wptr shadows and
> >>>> - * add them to the end of the ring allocation.
> >>>> - */
> >>>> - adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
> >>>> - adev-
> >>> irq.ih.ring_size + 8,
> >>>> - &adev-
> >>> irq.ih.rb_dma_addr);
> >>>> - if (adev->irq.ih.ring == NULL)
> >>>> - return -ENOMEM;
> >>>> - memset((void *)adev->irq.ih.ring, 0, adev-
> >>> irq.ih.ring_size + 8);
> >>>> - adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) +
> >> 0;
> >>>> - adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) +
> >> 1;
> >>>> - }
> >>>> - return 0;
> >>>> + ih->ring_size = ring_size;
> >>>> + ih->ptr_mask = ih->ring_size - 1;
> >>>> + ih->rptr = 0;
> >>>> + ih->use_bus_addr = use_bus_addr;
> >>>> +
> >>>> + if (use_bus_addr) {
> >>>> + if (ih->ring)
> >>>> + return 0;
> >>>> +
> >>>> + /* add 8 bytes for the rptr/wptr shadows and
> >>>> + * add them to the end of the ring allocation.
> >>>> + */
> >>>> + ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
> >>>> + &ih->rb_dma_addr, GFP_KERNEL);
> >>>> + if (ih->ring == NULL)
> >>>> + return -ENOMEM;
> >>>> +
> >>>> + memset((void *)ih->ring, 0, ih->ring_size + 8);
> >>>> + ih->wptr_offs = (ih->ring_size / 4) + 0;
> >>>> + ih->rptr_offs = (ih->ring_size / 4) + 1;
> >>>> } else {
> >>>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs);
> >>>> + r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
> >>>> + if (r)
> >>>> + return r;
> >>>> +
> >>>> + r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
> >>>> if (r) {
> >>>> - dev_err(adev->dev, "(%d) ih wptr_offs wb alloc
> >> failed\n", r);
> >>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >>>> return r;
> >>>> }
> >>>>
> >>>> - r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs);
> >>>> + r = amdgpu_bo_create_kernel(adev, ih->ring_size,
> >> PAGE_SIZE,
> >>>> + AMDGPU_GEM_DOMAIN_GTT,
> >>>> + &ih->ring_obj, &ih->gpu_addr,
> >>>> + (void **)&ih->ring);
> >>>> if (r) {
> >>>> - amdgpu_device_wb_free(adev, adev-
> >>> irq.ih.wptr_offs);
> >>>> - dev_err(adev->dev, "(%d) ih rptr_offs wb alloc
> >> failed\n", r);
> >>>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> >>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >>>> return r;
> >>>> }
> >>>> -
> >>>> - return amdgpu_ih_ring_alloc(adev);
> >>>> }
> >>>> + return 0;
> >>>> }
> >>>>
> >>>> /**
> >>>> * amdgpu_ih_ring_fini - tear down the IH state
> >>>> *
> >>>> * @adev: amdgpu_device pointer
> >>>> + * @ih: ih ring to tear down
> >>>> *
> >>>> * Tears down the IH state and frees buffer
> >>>> * used for the IH ring buffer.
> >>>> */
> >>>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
> >>>> +void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
> >>>> +amdgpu_ih_ring *ih)
> >>>> {
> >>>> - if (adev->irq.ih.use_bus_addr) {
> >>>> - if (adev->irq.ih.ring) {
> >>>> - /* add 8 bytes for the rptr/wptr shadows and
> >>>> - * add them to the end of the ring allocation.
> >>>> - */
> >>>> - pci_free_consistent(adev->pdev, adev-
> >>> irq.ih.ring_size + 8,
> >>>> - (void *)adev->irq.ih.ring,
> >>>> - adev->irq.ih.rb_dma_addr);
> >>>> - adev->irq.ih.ring = NULL;
> >>>> - }
> >>>> + if (ih->use_bus_addr) {
> >>>> + if (!ih->ring)
> >>>> + return;
> >>>> +
> >>>> + /* add 8 bytes for the rptr/wptr shadows and
> >>>> + * add them to the end of the ring allocation.
> >>>> + */
> >>>> + dma_free_coherent(adev->dev, ih->ring_size + 8,
> >>>> + (void *)ih->ring, ih->rb_dma_addr);
> >>>> + ih->ring = NULL;
> >>>> } else {
> >>>> - amdgpu_bo_free_kernel(&adev->irq.ih.ring_obj,
> >>>> - &adev->irq.ih.gpu_addr,
> >>>> - (void **)&adev->irq.ih.ring);
> >>>> - amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs);
> >>>> - amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs);
> >>>> + amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
> >>>> + (void **)&ih->ring);
> >>>> + amdgpu_device_wb_free(adev, ih->wptr_offs);
> >>>> + amdgpu_device_wb_free(adev, ih->rptr_offs);
> >>>> }
> >>>> }
> >>>>
> >>>> @@ -142,56 +124,56 @@ void amdgpu_ih_ring_fini(struct
> >> amdgpu_device *adev)
> >>>> * amdgpu_ih_process - interrupt handler
> >>>> *
> >>>> * @adev: amdgpu_device pointer
> >>>> + * @ih: ih ring to process
> >>>> *
> >>>> * Interrupt hander (VI), walk the IH ring.
> >>>> * Returns irq process return code.
> >>>> */
> >>>> -int amdgpu_ih_process(struct amdgpu_device *adev)
> >>>> +int amdgpu_ih_process(struct amdgpu_device *adev, struct
> >>>> +amdgpu_ih_ring *ih)
> >>>> {
> >>>> struct amdgpu_iv_entry entry;
> >>>> u32 wptr;
> >>>>
> >>>> - if (!adev->irq.ih.enabled || adev->shutdown)
> >>>> + if (!ih->enabled || adev->shutdown)
> >>>> return IRQ_NONE;
> >>>>
> >>>> wptr = amdgpu_ih_get_wptr(adev);
> >>>>
> >>>> restart_ih:
> >>>> /* is somebody else already processing irqs? */
> >>>> - if (atomic_xchg(&adev->irq.ih.lock, 1))
> >>>> + if (atomic_xchg(&ih->lock, 1))
> >>>> return IRQ_NONE;
> >>>>
> >>>> - DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr,
> >> wptr);
> >>>> + DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
> >>>>
> >>>> /* Order reading of wptr vs. reading of IH ring data */
> >>>> rmb();
> >>>>
> >>>> - while (adev->irq.ih.rptr != wptr) {
> >>>> - u32 ring_index = adev->irq.ih.rptr >> 2;
> >>>> + while (ih->rptr != wptr) {
> >>>> + u32 ring_index = ih->rptr >> 2;
> >>>>
> >>>> /* Prescreening of high-frequency interrupts */
> >>>> if (!amdgpu_ih_prescreen_iv(adev)) {
> >>>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> >>>> + ih->rptr &= ih->ptr_mask;
> >>>> continue;
> >>>> }
> >>>>
> >>>> /* Before dispatching irq to IP blocks, send it to amdkfd */
> >>>> amdgpu_amdkfd_interrupt(adev,
> >>>> - (const void *) &adev->irq.ih.ring[ring_index]);
> >>>> + (const void *) &ih->ring[ring_index]);
> >>>>
> >>>> - entry.iv_entry = (const uint32_t *)
> >>>> - &adev->irq.ih.ring[ring_index];
> >>>> + entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
> >>>> amdgpu_ih_decode_iv(adev, &entry);
> >>>> - adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
> >>>> + ih->rptr &= ih->ptr_mask;
> >>>>
> >>>> amdgpu_irq_dispatch(adev, &entry);
> >>>> }
> >>>> amdgpu_ih_set_rptr(adev);
> >>>> - atomic_set(&adev->irq.ih.lock, 0);
> >>>> + atomic_set(&ih->lock, 0);
> >>>>
> >>>> /* make sure wptr hasn't changed while processing */
> >>>> wptr = amdgpu_ih_get_wptr(adev);
> >>>> - if (wptr != adev->irq.ih.rptr)
> >>>> + if (wptr != ih->rptr)
> >>>> goto restart_ih;
> >>>>
> >>>> return IRQ_HANDLED;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >>>> index 0d5b3f5201d2..3e55f985005c 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> >>>> @@ -82,9 +82,9 @@ struct amdgpu_ih_funcs {
> >>>> #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs-
> >>> decode_iv((adev), (iv))
> >>>> #define amdgpu_ih_set_rptr(adev)
> >>>> (adev)->irq.ih_funcs->set_rptr((adev))
> >>>>
> >>>> -int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned
> >> ring_size,
> >>>> - bool use_bus_addr);
> >>>> -void amdgpu_ih_ring_fini(struct amdgpu_device *adev); -int
> >>>> amdgpu_ih_process(struct amdgpu_device *adev);
> >>>> +int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct
> >> amdgpu_ih_ring *ih,
> >>>> + unsigned ring_size, bool use_bus_addr); void
> >>>> +amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct
> >>>> +amdgpu_ih_ring *ih); int amdgpu_ih_process(struct amdgpu_device
> >>>> +*adev, struct amdgpu_ih_ring *ih);
> >>>>
> >>>> #endif
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >>>> index b927e8798534..aaa8545e458a 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> >>>> @@ -163,7 +163,7 @@ irqreturn_t amdgpu_irq_handler(int irq, void
> *arg)
> >>>> struct amdgpu_device *adev = dev->dev_private;
> >>>> irqreturn_t ret;
> >>>>
> >>>> - ret = amdgpu_ih_process(adev);
> >>>> + ret = amdgpu_ih_process(adev, &adev->irq.ih);
> >>>> if (ret == IRQ_HANDLED)
> >>>> pm_runtime_mark_last_busy(dev->dev);
> >>>> return ret;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >>>> index e75183e09820..c37c4b76e7e9 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> >>>> @@ -318,7 +318,7 @@ static int cik_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -332,7 +332,7 @@ static int cik_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>> amdgpu_irq_remove_domain(adev);
> >>>>
> >>>> return 0;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >>>> index 9385da1e1e40..306e0bd154fa 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> >>>> @@ -297,7 +297,7 @@ static int cz_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -311,7 +311,7 @@ static int cz_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>> amdgpu_irq_remove_domain(adev);
> >>>>
> >>>> return 0;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >>>> index 45ef0a818e11..9005deeec612 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> >>>> @@ -297,7 +297,7 @@ static int iceland_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -311,7 +311,7 @@ static int iceland_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>> amdgpu_irq_remove_domain(adev);
> >>>>
> >>>> return 0;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >>>> index 97711d327527..acdf6075957a 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> >>>> @@ -170,7 +170,7 @@ static int si_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -182,7 +182,7 @@ static int si_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>>
> >>>> return 0;
> >>>> }
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >>>> index a79a3776888a..83fdf810ffc7 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> >>>> @@ -317,7 +317,7 @@ static int tonga_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -334,7 +334,7 @@ static int tonga_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>> amdgpu_irq_remove_domain(adev);
> >>>>
> >>>> return 0;
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >>>> index 37487b4cbd6e..a99f71797aa3 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> >>>> @@ -380,7 +380,7 @@ static int vega10_ih_sw_init(void *handle)
> >>>> int r;
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> - r = amdgpu_ih_ring_init(adev, 256 * 1024, true);
> >>>> + r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
> >>>> if (r)
> >>>> return r;
> >>>>
> >>>> @@ -397,7 +397,7 @@ static int vega10_ih_sw_fini(void *handle)
> >>>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >>>>
> >>>> amdgpu_irq_fini(adev);
> >>>> - amdgpu_ih_ring_fini(adev);
> >>>> + amdgpu_ih_ring_fini(adev, &adev->irq.ih);
> >>>>
> >>>> return 0;
> >>>> }
> >>>> --
> >>>> 2.14.1
> >>>>
> >>>> _______________________________________________
> >>>> amd-gfx mailing list
> >>>> amd-gfx@lists.freedesktop.org
> >>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2018-09-26 10:36 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-24 12:38 [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace Christian König
[not found] ` <20180924123820.1873-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-24 12:38 ` [PATCH 2/9] drm/amdgpu: make function pointers mandatory Christian König
[not found] ` <20180924123820.1873-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-25 10:03 ` Huang Rui
2018-09-24 12:38 ` [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c Christian König
[not found] ` <20180924123820.1873-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-25 10:28 ` Huang Rui
2018-09-25 11:01 ` Christian König
[not found] ` <ea1b4ebf-c4ee-c03b-b3e7-6f66df831373-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-09-26 8:52 ` Huang, Ray
[not found] ` <BY2PR12MB0040B93400AD69D00699F870EC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-09-26 8:57 ` Christian König
[not found] ` <366f6d5f-67f8-0d86-274c-bf93a59c60d3-5C7GfCeVMHo@public.gmane.org>
2018-09-26 10:36 ` Huang, Ray
2018-09-24 12:38 ` [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c Christian König
[not found] ` <20180924123820.1873-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 6:13 ` Huang Rui
2018-09-24 12:38 ` [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h Christian König
[not found] ` <20180924123820.1873-5-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 6:14 ` Huang Rui
2018-09-24 12:38 ` [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs Christian König
[not found] ` <20180924123820.1873-6-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 6:05 ` Huang Rui
2018-09-26 8:09 ` Christian König
[not found] ` <39fb9a51-2e85-0828-a193-b54059dec405-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-09-26 9:16 ` Huang, Ray
[not found] ` <BY2PR12MB00400B029B1F4C1256CE558AEC150-K//h7OWB4q7Zvl48JdS6+wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-09-26 9:18 ` Christian König
2018-09-24 12:38 ` [PATCH 7/9] drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr Christian König
[not found] ` <20180924123820.1873-7-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 7:36 ` Huang Rui
2018-09-26 7:40 ` Huang Rui
2018-09-24 12:38 ` [PATCH 8/9] drm/amdgpu: simplify IH programming Christian König
[not found] ` <20180924123820.1873-8-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 8:48 ` Huang, Ray
2018-09-24 12:38 ` [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2 Christian König
[not found] ` <20180924123820.1873-9-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-09-26 8:49 ` Huang, Ray
2018-09-25 9:54 ` [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace Huang Rui
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.