[PATCH v8 0/8] Asynchronous flip implementation for i915

[PATCH v8 0/8] Asynchronous flip implementation for i915

[Karthik B S]

Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.

Asynchronous page flips will also boost the FPS of Mesa benchmarks.

v2: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v3: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v4: -Made changes to fix the sequence and time stamp issue as per the
     comments received on the previous version.
    -Timestamps are calculated using the flip done time stamp and current
     timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
     for timestamp calculations.
    -Event is sent from the interrupt handler immediately using this
     updated timestamps and sequence.
    -Added more state checks as async flip should only allow change in plane
     surface address and nothing else should be allowed to change.
    -Added a separate plane hook for async flip.
    -Need to find a way to reject fbc enabling if it comes as part of this
     flip as bspec states that changes to FBC are not allowed.

v5: -Fixed the Checkpatch and sparse warnings.

v6: -Reverted back to the old timestamping code as per the feedback received.
    -Added documentation.

v7: -Changes in intel_atomic_check_async()
    -Add vfunc for skl_program_async_surface_address()

v8: -Add WA for older platforms with double buffered
     async address update enable bit.

Test-with: <20200908061001.20302-1-karthik.b.s@intel.com>

Karthik B S (8):
  drm/i915: Add enable/disable flip done and flip done handler
  drm/i915: Add support for async flips in I915
  drm/i915: Add checks specific to async flips
  drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
  drm/i915: Add dedicated plane hook for async flip case
  drm/i915: WA for platforms with double buffered adress update enable
    bit
  Documentation/gpu: Add asynchronous flip documentation for i915
  drm/i915: Enable async flips in i915

 Documentation/gpu/i915.rst                    |   6 +
 .../gpu/drm/i915/display/intel_atomic_plane.c |   7 +
 drivers/gpu/drm/i915/display/intel_display.c  | 201 ++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  30 +++
 drivers/gpu/drm/i915/i915_irq.c               |  52 +++++
 drivers/gpu/drm/i915/i915_irq.h               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 8 files changed, 302 insertions(+)

-- 
2.22.0

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[Intel-gfx] [PATCH v8 0/8] Asynchronous flip implementation for i915

[Karthik B S]

Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.

Asynchronous page flips will also boost the FPS of Mesa benchmarks.

v2: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v3: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v4: -Made changes to fix the sequence and time stamp issue as per the
     comments received on the previous version.
    -Timestamps are calculated using the flip done time stamp and current
     timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
     for timestamp calculations.
    -Event is sent from the interrupt handler immediately using this
     updated timestamps and sequence.
    -Added more state checks as async flip should only allow change in plane
     surface address and nothing else should be allowed to change.
    -Added a separate plane hook for async flip.
    -Need to find a way to reject fbc enabling if it comes as part of this
     flip as bspec states that changes to FBC are not allowed.

v5: -Fixed the Checkpatch and sparse warnings.

v6: -Reverted back to the old timestamping code as per the feedback received.
    -Added documentation.

v7: -Changes in intel_atomic_check_async()
    -Add vfunc for skl_program_async_surface_address()

v8: -Add WA for older platforms with double buffered
     async address update enable bit.

Test-with: <20200908061001.20302-1-karthik.b.s@intel.com>

Karthik B S (8):
  drm/i915: Add enable/disable flip done and flip done handler
  drm/i915: Add support for async flips in I915
  drm/i915: Add checks specific to async flips
  drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
  drm/i915: Add dedicated plane hook for async flip case
  drm/i915: WA for platforms with double buffered adress update enable
    bit
  Documentation/gpu: Add asynchronous flip documentation for i915
  drm/i915: Enable async flips in i915

 Documentation/gpu/i915.rst                    |   6 +
 .../gpu/drm/i915/display/intel_atomic_plane.c |   7 +
 drivers/gpu/drm/i915/display/intel_display.c  | 201 ++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  30 +++
 drivers/gpu/drm/i915/i915_irq.c               |  52 +++++
 drivers/gpu/drm/i915/i915_irq.h               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 8 files changed, 302 insertions(+)

-- 
2.22.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.

Enable the flip done interrupt in IER.

Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt

Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.

v2: -Change function name from icl_* to skl_* (Paulo)
    -Move flip handler to this patch (Paulo)
    -Remove vblank_put() (Paulo)
    -Enable flip done interrupt for gen9+ only (Paulo)
    -Enable flip done interrupt in power_well_post_enable hook (Paulo)
    -Removed the event check in flip done handler to handle async
     flips without pageflip events.

v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
    -Make the pending vblank event NULL in the beginning of
     flip_done_handler to remove sporadic WARN_ON that is seen.

v4: -Calculate timestamps using flip done time stamp and current
     timestamp for async flips (Ville)

v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
     static.(Reported-by: kernel test robot <lkp@intel.com>)
    -Fix the typo in commit message.

v6: -Revert back to old time stamping code.
    -Remove the break while calling skl_enable_flip_done. (Paulo)

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  8 +++
 drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.h              |  2 +
 3 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ec148a8da2c2..48712fb0a251 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	intel_dbuf_pre_plane_update(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_enable_flip_done(&crtc->base);
+	}
+
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.commit_modeset_enables(state);
 
@@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_disable_flip_done(&crtc->base);
+
 		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f113fe44572b..6cc129b031d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 			     u32 crc4) {}
 #endif
 
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+			      unsigned int pipe)
+{
+	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+	struct drm_crtc_state *crtc_state = crtc->base.state;
+	struct drm_pending_vblank_event *e = crtc_state->event;
+	struct drm_device *dev = &dev_priv->drm;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev->event_lock, irqflags);
+
+	crtc_state->event = NULL;
+
+	drm_crtc_send_vblank_event(&crtc->base, e);
+
+	spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
 
 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
@@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
 
+		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+			flip_done_handler(dev_priv, pipe);
+
 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
@@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 	enum pipe pipe;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	if (!intel_irqs_enabled(dev_priv)) {
@@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
 					   GEN8_PIPE_FIFO_UNDERRUN;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	de_port_enables = de_port_masked;
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
 int i965_enable_vblank(struct drm_crtc *crtc);
 int ilk_enable_vblank(struct drm_crtc *crtc);
 int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
 void i8xx_disable_vblank(struct drm_crtc *crtc);
 void i915gm_disable_vblank(struct drm_crtc *crtc);
 void i965_disable_vblank(struct drm_crtc *crtc);
 void ilk_disable_vblank(struct drm_crtc *crtc);
 void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
 
 void gen2_irq_reset(struct intel_uncore *uncore);
 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
-- 
2.22.0

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[Intel-gfx] [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.

Enable the flip done interrupt in IER.

Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt

Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.

v2: -Change function name from icl_* to skl_* (Paulo)
    -Move flip handler to this patch (Paulo)
    -Remove vblank_put() (Paulo)
    -Enable flip done interrupt for gen9+ only (Paulo)
    -Enable flip done interrupt in power_well_post_enable hook (Paulo)
    -Removed the event check in flip done handler to handle async
     flips without pageflip events.

v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
    -Make the pending vblank event NULL in the beginning of
     flip_done_handler to remove sporadic WARN_ON that is seen.

v4: -Calculate timestamps using flip done time stamp and current
     timestamp for async flips (Ville)

v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
     static.(Reported-by: kernel test robot <lkp@intel.com>)
    -Fix the typo in commit message.

v6: -Revert back to old time stamping code.
    -Remove the break while calling skl_enable_flip_done. (Paulo)

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  8 +++
 drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.h              |  2 +
 3 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ec148a8da2c2..48712fb0a251 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	intel_dbuf_pre_plane_update(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_enable_flip_done(&crtc->base);
+	}
+
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.commit_modeset_enables(state);
 
@@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_disable_flip_done(&crtc->base);
+
 		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f113fe44572b..6cc129b031d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 			     u32 crc4) {}
 #endif
 
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+			      unsigned int pipe)
+{
+	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+	struct drm_crtc_state *crtc_state = crtc->base.state;
+	struct drm_pending_vblank_event *e = crtc_state->event;
+	struct drm_device *dev = &dev_priv->drm;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev->event_lock, irqflags);
+
+	crtc_state->event = NULL;
+
+	drm_crtc_send_vblank_event(&crtc->base, e);
+
+	spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
 
 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
@@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
 
+		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+			flip_done_handler(dev_priv, pipe);
+
 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
@@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 	enum pipe pipe;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	if (!intel_irqs_enabled(dev_priv)) {
@@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
 					   GEN8_PIPE_FIFO_UNDERRUN;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	de_port_enables = de_port_masked;
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
 int i965_enable_vblank(struct drm_crtc *crtc);
 int ilk_enable_vblank(struct drm_crtc *crtc);
 int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
 void i8xx_disable_vblank(struct drm_crtc *crtc);
 void i915gm_disable_vblank(struct drm_crtc *crtc);
 void i965_disable_vblank(struct drm_crtc *crtc);
 void ilk_disable_vblank(struct drm_crtc *crtc);
 void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
 
 void gen2_irq_reset(struct intel_uncore *uncore);
 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
-- 
2.22.0

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[PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Karthik B S]

Set the Async Address Update Enable bit in plane ctl
when async flip is requested.

v2: -Move the Async flip enablement to individual patch (Paulo)

v3: -Rebased.

v4: -Add separate plane hook for async flip case (Ville)

v5: -Rebased.

v6: -Move the plane hook to separate patch. (Paulo)
    -Remove the early return in skl_plane_ctl. (Paulo)

v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 48712fb0a251..2902fefd217f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 plane_ctl = 0;
 
+	if (crtc_state->uapi.async_flip)
+		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		return plane_ctl;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90a05e37ba2f..1c4ddd4deba0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6923,6 +6923,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
-- 
2.22.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Karthik B S]

Set the Async Address Update Enable bit in plane ctl
when async flip is requested.

v2: -Move the Async flip enablement to individual patch (Paulo)

v3: -Rebased.

v4: -Add separate plane hook for async flip case (Ville)

v5: -Rebased.

v6: -Move the plane hook to separate patch. (Paulo)
    -Remove the early return in skl_plane_ctl. (Paulo)

v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 48712fb0a251..2902fefd217f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 plane_ctl = 0;
 
+	if (crtc_state->uapi.async_flip)
+		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		return plane_ctl;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90a05e37ba2f..1c4ddd4deba0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6923,6 +6923,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Karthik B S]

If flip is requested on any other plane, reject it.

Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.

If any of these are modified, reject async flip.

v2: -Replace DRM_ERROR (Paulo)
    -Add check for changes in OFFSET, FBC, RC(Paulo)

v3: -Removed TODO as benchmarking tests have been run now.

v4: -Added more state checks for async flip (Ville)
    -Moved intel_atomic_check_async to the end of intel_atomic_check
     as the plane checks needs to pass before this. (Ville)
    -Removed crtc_state->enable_fbc check. (Ville)
    -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
     flip case as scanline counter is not reliable here.

v5: -Fix typo and other check patch errors seen in CI
     in 'intel_atomic_check_async' function.

v6: -Don't call intel_atomic_check_async multiple times. (Ville)
    -Remove the check for n_planes in intel_atomic_check_async
    -Added documentation for async flips. (Paulo)

v7: -Replace 'intel_plane' with 'plane'. (Ville)
    -Replace all uapi.foo as hw.foo. (Ville)
    -Do not use intel_wm_need_update function. (Ville)
    -Add destination coordinate check. (Ville)
    -Do not allow async flip with linear buffer
     on older hw as it has issues with this. (Ville)
    -Remove break after intel_atomic_check_async. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2902fefd217f..a0c17d94daf3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
 	return false;
 }
 
+/**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+	struct intel_plane_state *new_plane_state, *old_plane_state;
+	struct intel_crtc *crtc;
+	struct intel_plane *plane;
+	int i;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (needs_modeset(new_crtc_state)) {
+			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
+			return -EINVAL;
+		}
+
+		if (!new_crtc_state->hw.active) {
+			DRM_DEBUG_KMS("CRTC inactive\n");
+			return -EINVAL;
+		}
+		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+					     new_plane_state, i) {
+		/*TODO: Async flip is only supported through the page flip IOCTL
+		 * as of now. So support currently added for primary plane only.
+		 * Support for other planes should be added when async flip is
+		 * enabled in the atomic IOCTL path.
+		 */
+		if (plane->id != PLANE_PRIMARY)
+			return -EINVAL;
+
+		/*FIXME: This check is kept generic for all gen <= 10 platforms.
+		 * Need to verify this for all gen9 and gen10 platforms to enable
+		 * this selectively if required.
+		 */
+		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+		    INTEL_GEN(dev_priv) <= 10) {
+			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->color_plane[0].x !=
+		    new_plane_state->color_plane[0].x ||
+		    old_plane_state->color_plane[0].y !=
+		    new_plane_state->color_plane[0].y) {
+			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->modifier !=
+		    new_plane_state->hw.fb->modifier) {
+			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->format !=
+		    new_plane_state->hw.fb->format) {
+			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.rotation !=
+		    new_plane_state->hw.rotation) {
+			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->width !=
+		    new_plane_state->hw.fb->width ||
+		    old_plane_state->hw.fb->height !=
+		    new_plane_state->hw.fb->height) {
+			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
+		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
+		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
+		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
+		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
+		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
+		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
+		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
+			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
+			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.pixel_blend_mode !=
+		    new_plane_state->hw.pixel_blend_mode) {
+			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
+			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
+			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
 /**
  * intel_atomic_check - validate state object
  * @dev: drm device
@@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
 				       "[modeset]" : "[fastset]");
 	}
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip) {
+			ret = intel_atomic_check_async(state);
+			if (ret)
+				goto fail;
+		}
+	}
 	return 0;
 
  fail:
-- 
2.22.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[Intel-gfx] [PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Karthik B S]

If flip is requested on any other plane, reject it.

Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.

If any of these are modified, reject async flip.

v2: -Replace DRM_ERROR (Paulo)
    -Add check for changes in OFFSET, FBC, RC(Paulo)

v3: -Removed TODO as benchmarking tests have been run now.

v4: -Added more state checks for async flip (Ville)
    -Moved intel_atomic_check_async to the end of intel_atomic_check
     as the plane checks needs to pass before this. (Ville)
    -Removed crtc_state->enable_fbc check. (Ville)
    -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
     flip case as scanline counter is not reliable here.

v5: -Fix typo and other check patch errors seen in CI
     in 'intel_atomic_check_async' function.

v6: -Don't call intel_atomic_check_async multiple times. (Ville)
    -Remove the check for n_planes in intel_atomic_check_async
    -Added documentation for async flips. (Paulo)

v7: -Replace 'intel_plane' with 'plane'. (Ville)
    -Replace all uapi.foo as hw.foo. (Ville)
    -Do not use intel_wm_need_update function. (Ville)
    -Add destination coordinate check. (Ville)
    -Do not allow async flip with linear buffer
     on older hw as it has issues with this. (Ville)
    -Remove break after intel_atomic_check_async. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2902fefd217f..a0c17d94daf3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
 	return false;
 }
 
+/**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+	struct intel_plane_state *new_plane_state, *old_plane_state;
+	struct intel_crtc *crtc;
+	struct intel_plane *plane;
+	int i;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (needs_modeset(new_crtc_state)) {
+			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
+			return -EINVAL;
+		}
+
+		if (!new_crtc_state->hw.active) {
+			DRM_DEBUG_KMS("CRTC inactive\n");
+			return -EINVAL;
+		}
+		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+					     new_plane_state, i) {
+		/*TODO: Async flip is only supported through the page flip IOCTL
+		 * as of now. So support currently added for primary plane only.
+		 * Support for other planes should be added when async flip is
+		 * enabled in the atomic IOCTL path.
+		 */
+		if (plane->id != PLANE_PRIMARY)
+			return -EINVAL;
+
+		/*FIXME: This check is kept generic for all gen <= 10 platforms.
+		 * Need to verify this for all gen9 and gen10 platforms to enable
+		 * this selectively if required.
+		 */
+		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+		    INTEL_GEN(dev_priv) <= 10) {
+			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->color_plane[0].x !=
+		    new_plane_state->color_plane[0].x ||
+		    old_plane_state->color_plane[0].y !=
+		    new_plane_state->color_plane[0].y) {
+			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->modifier !=
+		    new_plane_state->hw.fb->modifier) {
+			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->format !=
+		    new_plane_state->hw.fb->format) {
+			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.rotation !=
+		    new_plane_state->hw.rotation) {
+			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->width !=
+		    new_plane_state->hw.fb->width ||
+		    old_plane_state->hw.fb->height !=
+		    new_plane_state->hw.fb->height) {
+			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
+		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
+		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
+		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
+		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
+		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
+		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
+		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
+			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
+			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.pixel_blend_mode !=
+		    new_plane_state->hw.pixel_blend_mode) {
+			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
+			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
+			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
 /**
  * intel_atomic_check - validate state object
  * @dev: drm device
@@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
 				       "[modeset]" : "[fastset]");
 	}
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip) {
+			ret = intel_atomic_check_async(state);
+			if (ret)
+				goto fail;
+		}
+	}
 	return 0;
 
  fail:
-- 
2.22.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.

v2: -Moved the async check above vblank_get as it
     was causing issues for PSR.

v3: -No need to wait for vblank to pass, as this wait was causing a
     16ms delay once every few flips.

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

v7: -No need of irq disable if we are not doing vblank evade. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5ac0dbf0e03d..f0c89418d2e1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	DEFINE_WAIT(wait);
 	u32 psr_status;
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	vblank_start = adjusted_mode->crtc_vblank_start;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
-- 
2.22.0

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[Intel-gfx] [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.

v2: -Moved the async check above vblank_get as it
     was causing issues for PSR.

v3: -No need to wait for vblank to pass, as this wait was causing a
     16ms delay once every few flips.

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

v7: -No need of irq disable if we are not doing vblank evade. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5ac0dbf0e03d..f0c89418d2e1 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	DEFINE_WAIT(wait);
 	u32 psr_status;
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	vblank_start = adjusted_mode->crtc_vblank_start;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
-- 
2.22.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.

v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
    -Add a vfunc for skl_program_async_surface_address
     and call it from intel_update_plane. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
 .../drm/i915/display/intel_display_types.h    |  3 +++
 drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a..fdc633020255 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_update_plane(&plane->base, crtc);
+
+	if (crtc_state->uapi.async_flip) {
+		plane->program_async_surface_address(plane,
+						     crtc_state, plane_state);
+		return;
+	}
+
 	plane->update_plane(plane, crtc_state, plane_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b2d0edacc58c..d2ae781e4d81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1190,6 +1190,9 @@ struct intel_plane {
 			   struct intel_plane_state *plane_state);
 	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
 			 const struct intel_plane_state *plane_state);
+	void (*program_async_surface_address)(struct intel_plane *plane,
+					      const struct intel_crtc_state *crtc_state,
+					      const struct intel_plane_state *plane_state);
 };
 
 struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f0c89418d2e1..69407dfcebf6 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
 			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 }
 
+static void
+skl_program_async_surface_address(struct intel_plane *plane,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	unsigned long irqflags;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	u32 surf_addr = plane_state->color_plane[0].offset;
+	u32 plane_ctl = plane_state->ctl;
+
+	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+			  intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
 static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
@@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->get_hw_state = skl_plane_get_hw_state;
 	plane->check_plane = skl_plane_check;
 	plane->min_cdclk = skl_plane_min_cdclk;
+	plane->program_async_surface_address = skl_program_async_surface_address;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		formats = icl_get_plane_formats(dev_priv, pipe,
-- 
2.22.0

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[Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.

v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
    -Add a vfunc for skl_program_async_surface_address
     and call it from intel_update_plane. (Ville)

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
 .../drm/i915/display/intel_display_types.h    |  3 +++
 drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a..fdc633020255 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_update_plane(&plane->base, crtc);
+
+	if (crtc_state->uapi.async_flip) {
+		plane->program_async_surface_address(plane,
+						     crtc_state, plane_state);
+		return;
+	}
+
 	plane->update_plane(plane, crtc_state, plane_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b2d0edacc58c..d2ae781e4d81 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1190,6 +1190,9 @@ struct intel_plane {
 			   struct intel_plane_state *plane_state);
 	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
 			 const struct intel_plane_state *plane_state);
+	void (*program_async_surface_address)(struct intel_plane *plane,
+					      const struct intel_crtc_state *crtc_state,
+					      const struct intel_plane_state *plane_state);
 };
 
 struct intel_watermark_params {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index f0c89418d2e1..69407dfcebf6 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
 			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 }
 
+static void
+skl_program_async_surface_address(struct intel_plane *plane,
+				  const struct intel_crtc_state *crtc_state,
+				  const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	unsigned long irqflags;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	u32 surf_addr = plane_state->color_plane[0].offset;
+	u32 plane_ctl = plane_state->ctl;
+
+	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+			  intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
 static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
@@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->get_hw_state = skl_plane_get_hw_state;
 	plane->check_plane = skl_plane_check;
 	plane->min_cdclk = skl_plane_min_cdclk;
+	plane->program_async_surface_address = skl_program_async_surface_address;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		formats = icl_get_plane_formats(dev_priv, pipe,
-- 
2.22.0

_______________________________________________
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[PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Karthik B S]

In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0c17d94daf3..b7e24dff0772 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 	intel_crtc_enable_pipe_crc(crtc);
 }
 
+static void skl_toggle_async_sync(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc,
+				  struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *plane;
+	struct intel_plane_state *new_plane_state;
+	u32 update_mask = new_crtc_state->update_planes;
+	u32 plane_ctl, surf_addr;
+	enum plane_id plane_id;
+	unsigned long irqflags;
+	enum pipe pipe;
+	int i;
+
+	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+		if (crtc->pipe != plane->pipe ||
+		    !(update_mask & BIT(plane->id)))
+			continue;
+
+		plane_id = plane->id;
+		pipe = plane->pipe;
+
+		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
+		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
+
+		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
+
+		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
+		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	}
+
+	intel_wait_for_vblank(dev_priv, crtc->pipe);
+}
+
 static void intel_update_crtc(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc)
 {
@@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	else
 		intel_fbc_enable(state, crtc);
 
+	/* WA for older platforms where async address update enable bit
+	 * is double buffered.
+	 */
+	if (old_crtc_state->uapi.async_flip &&
+	    !new_crtc_state->uapi.async_flip &&
+	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
+		skl_toggle_async_sync(state, crtc, new_crtc_state);
+
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(new_crtc_state);
 
-- 
2.22.0

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[Intel-gfx] [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Karthik B S]

In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a0c17d94daf3..b7e24dff0772 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 	intel_crtc_enable_pipe_crc(crtc);
 }
 
+static void skl_toggle_async_sync(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc,
+				  struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *plane;
+	struct intel_plane_state *new_plane_state;
+	u32 update_mask = new_crtc_state->update_planes;
+	u32 plane_ctl, surf_addr;
+	enum plane_id plane_id;
+	unsigned long irqflags;
+	enum pipe pipe;
+	int i;
+
+	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+		if (crtc->pipe != plane->pipe ||
+		    !(update_mask & BIT(plane->id)))
+			continue;
+
+		plane_id = plane->id;
+		pipe = plane->pipe;
+
+		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
+		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
+
+		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
+
+		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
+		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	}
+
+	intel_wait_for_vblank(dev_priv, crtc->pipe);
+}
+
 static void intel_update_crtc(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc)
 {
@@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	else
 		intel_fbc_enable(state, crtc);
 
+	/* WA for older platforms where async address update enable bit
+	 * is double buffered.
+	 */
+	if (old_crtc_state->uapi.async_flip &&
+	    !new_crtc_state->uapi.async_flip &&
+	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
+		skl_toggle_async_sync(state, crtc, new_crtc_state);
+
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(new_crtc_state);
 
-- 
2.22.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 7/8] Documentation/gpu: Add asynchronous flip documentation for i915

[Karthik B S]

Add the details of the implementation of asynchronous flips for i915.

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 Documentation/gpu/i915.rst | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..84ead508f7ad 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
    :internal:
 
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+   :doc: asynchronous flip implementation
+
 Output Probing
 --------------
 
-- 
2.22.0

_______________________________________________
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[Intel-gfx] [PATCH v8 7/8] Documentation/gpu: Add asynchronous flip documentation for i915

[Karthik B S]

Add the details of the implementation of asynchronous flips for i915.

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 Documentation/gpu/i915.rst | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..84ead508f7ad 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
    :internal:
 
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+   :doc: asynchronous flip implementation
+
 Output Probing
 --------------
 
-- 
2.22.0

_______________________________________________
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[PATCH v8 8/8] drm/i915: Enable async flips in i915

[Karthik B S]

Enable asynchronous flips in i915 for gen9+ platforms.

v2: -Async flip enablement should be a stand alone patch (Paulo)

v3: -Move the patch to the end of the series (Paulo)

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b7e24dff0772..453ab23d5451 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18019,6 +18019,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
 
 	mode_config->funcs = &intel_mode_funcs;
 
+	if (INTEL_GEN(i915) >= 9)
+		mode_config->async_page_flip = true;
+
 	/*
 	 * Maximum framebuffer dimensions, chosen to match
 	 * the maximum render engine surface size on gen4+.
-- 
2.22.0

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[Intel-gfx] [PATCH v8 8/8] drm/i915: Enable async flips in i915

[Karthik B S]

Enable asynchronous flips in i915 for gen9+ platforms.

v2: -Async flip enablement should be a stand alone patch (Paulo)

v3: -Move the patch to the end of the series (Paulo)

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

v7: -Rebased.

v8: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b7e24dff0772..453ab23d5451 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18019,6 +18019,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
 
 	mode_config->funcs = &intel_mode_funcs;
 
+	if (INTEL_GEN(i915) >= 9)
+		mode_config->async_page_flip = true;
+
 	/*
 	 * Maximum framebuffer dimensions, chosen to match
 	 * the maximum render engine surface size on gen4+.
-- 
2.22.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev8)

[Patchwork]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev8)
URL   : https://patchwork.freedesktop.org/series/74386/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
41e215a678e3 drm/i915: Add enable/disable flip done and flip done handler
6cbc7da6e9d7 drm/i915: Add support for async flips in I915
dd3af66e26c3 drm/i915: Add checks specific to async flips
42a5bdc0f23e drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
bd90b9b59356 drm/i915: Add dedicated plane hook for async flip case
f034c8bbe82e drm/i915: WA for platforms with double buffered adress update enable bit
-:4: WARNING:TYPO_SPELLING: 'adress' may be misspelled - perhaps 'address'?
#4: 
Subject: [PATCH] drm/i915: WA for platforms with double buffered adress update

total: 0 errors, 1 warnings, 0 checks, 56 lines checked
91a266c111fe Documentation/gpu: Add asynchronous flip documentation for i915
7e2163c101ad drm/i915: Enable async flips in i915


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev8)

[Patchwork]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev8)
URL   : https://patchwork.freedesktop.org/series/74386/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1311:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✓ Fi.CI.BAT: success for Asynchronous flip implementation for i915 (rev8)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7693 bytes --]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev8)
URL   : https://patchwork.freedesktop.org/series/74386/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9004 -> Patchwork_18488
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/index.html

Known issues
------------

  Here are the changes found in Patchwork_18488 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_tiled_fence_blits@basic:
    - fi-tgl-y:           [PASS][1] -> [DMESG-WARN][2] ([i915#402])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-tgl-y/igt@gem_tiled_fence_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-tgl-y/igt@gem_tiled_fence_blits@basic.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-apl-guc/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-apl-guc/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_psr@cursor_plane_move:
    - fi-tgl-y:           [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-tgl-y/igt@kms_psr@cursor_plane_move.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-tgl-y/igt@kms_psr@cursor_plane_move.html

  
#### Possible fixes ####

  * igt@gem_flink_basic@basic:
    - fi-tgl-y:           [DMESG-WARN][13] ([i915#402]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-tgl-y/igt@gem_flink_basic@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-tgl-y/igt@gem_flink_basic@basic.html

  * igt@i915_selftest@live@active:
    - {fi-ehl-1}:         [DMESG-FAIL][15] ([i915#541]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-ehl-1/igt@i915_selftest@live@active.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-ehl-1/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@coherency:
    - fi-gdg-551:         [DMESG-FAIL][17] ([i915#1748]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-gdg-551/igt@i915_selftest@live@coherency.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-gdg-551/igt@i915_selftest@live@coherency.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-y:           [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-tgl-y/igt@kms_busy@basic@flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-tgl-y/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][23] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-kbl-x1275:       [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-kbl-x1275:       [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (45 -> 39)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5781 -> IGTPW_4966
  * Linux: CI_DRM_9004 -> Patchwork_18488

  CI-20190529: 20190529
  CI_DRM_9004: fd4f896ce2e2180433dc0b8ba89d8c9e1f8238ab @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4966: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4966/index.html
  IGT_5781: 66766dd7cd99465d977ac07db8a2413dbbfe8d84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18488: 7e2163c101ade5ede625d5379a5521344678eb7d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7e2163c101ad drm/i915: Enable async flips in i915
91a266c111fe Documentation/gpu: Add asynchronous flip documentation for i915
f034c8bbe82e drm/i915: WA for platforms with double buffered adress update enable bit
bd90b9b59356 drm/i915: Add dedicated plane hook for async flip case
42a5bdc0f23e drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
dd3af66e26c3 drm/i915: Add checks specific to async flips
6cbc7da6e9d7 drm/i915: Add support for async flips in I915
41e215a678e3 drm/i915: Add enable/disable flip done and flip done handler

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/index.html

[-- Attachment #1.2: Type: text/html, Size: 10075 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✓ Fi.CI.IGT: success for Asynchronous flip implementation for i915 (rev8)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 24193 bytes --]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev8)
URL   : https://patchwork.freedesktop.org/series/74386/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9004_full -> Patchwork_18488_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18488_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@kms_async_flips@alternate-sync-async-flip} (NEW):
    - shard-skl:          NOTRUN -> [FAIL][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl5/igt@kms_async_flips@alternate-sync-async-flip.html

  * {igt@kms_async_flips@async-flip-with-page-flip-events} (NEW):
    - shard-glk:          NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-glk2/igt@kms_async_flips@async-flip-with-page-flip-events.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9004_full and Patchwork_18488_full:

### New IGT tests (4) ###

  * igt@kms_async_flips@alternate-sync-async-flip:
    - Statuses : 1 fail(s) 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 3.03] s

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - Statuses : 2 fail(s) 4 pass(s) 2 skip(s)
    - Exec time: [0.0, 3.00] s

  * igt@kms_async_flips@invalid-async-flip:
    - Statuses : 1 dmesg-warn(s) 5 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.21] s

  * igt@kms_async_flips@test-time-stamp:
    - Statuses : 6 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.05] s

  

Known issues
------------

  Here are the changes found in Patchwork_18488_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb2/igt@feature_discovery@psr2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb8/igt@feature_discovery@psr2.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-skl:          [PASS][5] -> [TIMEOUT][6] ([i915#1958] / [i915#2424])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl4/igt@gem_userptr_blits@sync-unmap-cycles.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl9/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-skl:          [PASS][7] -> [SKIP][8] ([fdo#109271]) +17 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl9/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl2/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_color@pipe-b-legacy-gamma:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([i915#71])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl6/igt@kms_color@pipe-b-legacy-gamma.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl4/igt@kms_color@pipe-b-legacy-gamma.html
    - shard-kbl:          [PASS][11] -> [FAIL][12] ([i915#71])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl1/igt@kms_color@pipe-b-legacy-gamma.html
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#71])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-glk7/igt@kms_color@pipe-b-legacy-gamma.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-glk3/igt@kms_color@pipe-b-legacy-gamma.html
    - shard-apl:          [PASS][15] -> [FAIL][16] ([i915#1635] / [i915#71])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl6/igt@kms_color@pipe-b-legacy-gamma.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl6/igt@kms_color@pipe-b-legacy-gamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#54])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][19] -> [FAIL][20] ([i915#96])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([i915#1982])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-glk5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-glk1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html

  * igt@kms_flip@2x-flip-vs-suspend@bc-vga1-hdmi-a1:
    - shard-hsw:          [PASS][23] -> [INCOMPLETE][24] ([i915#2055])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend@bc-vga1-hdmi-a1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-hsw4/igt@kms_flip@2x-flip-vs-suspend@bc-vga1-hdmi-a1.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible@a-dp1:
    - shard-kbl:          [PASS][25] -> [DMESG-WARN][26] ([i915#1982])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl3/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-dp1.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([i915#79])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-skl:          [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +37 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl10/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl7/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_flip@modeset-vs-vblank-race@c-hdmi-a2:
    - shard-glk:          [PASS][31] -> [FAIL][32] ([i915#407])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-glk2/igt@kms_flip@modeset-vs-vblank-race@c-hdmi-a2.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-glk3/igt@kms_flip@modeset-vs-vblank-race@c-hdmi-a2.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-iclb:         [PASS][37] -> [FAIL][38] ([fdo#109052]) +5 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb8/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb2/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html

  * igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format:
    - shard-tglb:         [PASS][39] -> [FAIL][40] ([i915#1214]) +7 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-tglb5/igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-tglb6/igt@kms_plane_scaling@pipe-d-scaler-with-pixel-format.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109441]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@sprite_mmap_gtt:
    - shard-skl:          [PASS][43] -> [CRASH][44] ([i915#2212])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl8/igt@kms_psr@sprite_mmap_gtt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl2/igt@kms_psr@sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-a-accuracy-idle:
    - shard-tglb:         [PASS][45] -> [DMESG-WARN][46] ([i915#1982]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-tglb7/igt@kms_vblank@pipe-a-accuracy-idle.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-tglb6/igt@kms_vblank@pipe-a-accuracy-idle.html

  * igt@kms_vblank@pipe-c-wait-idle:
    - shard-apl:          [PASS][47] -> [DMESG-WARN][48] ([i915#1635] / [i915#1982])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl4/igt@kms_vblank@pipe-c-wait-idle.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl3/igt@kms_vblank@pipe-c-wait-idle.html

  
#### Possible fixes ####

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-apl:          [FAIL][49] ([i915#1635] / [i915#2389]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl2/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl3/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-skl:          [DMESG-WARN][51] ([i915#1436] / [i915#716]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl7/igt@gen9_exec_parse@allowed-all.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl7/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc5-psr:
    - shard-iclb:         [FAIL][53] ([i915#1899]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb3/igt@i915_pm_dc@dc5-psr.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb7/igt@i915_pm_dc@dc5-psr.html

  * igt@i915_selftest@mock@contexts:
    - shard-skl:          [INCOMPLETE][55] ([i915#198] / [i915#2278]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl4/igt@i915_selftest@mock@contexts.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl1/igt@i915_selftest@mock@contexts.html
    - shard-apl:          [INCOMPLETE][57] ([i915#1635] / [i915#2278]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl2/igt@i915_selftest@mock@contexts.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl6/igt@i915_selftest@mock@contexts.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [INCOMPLETE][59] ([i915#155] / [i915#636]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl4/igt@i915_suspend@forcewake.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl6/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +6 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge:
    - shard-glk:          [DMESG-WARN][63] ([i915#1982]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-glk9/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
    - shard-skl:          [FAIL][65] ([i915#52] / [i915#54]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl8/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl1/igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][67] ([i915#2055]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-hsw4/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-hsw8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [FAIL][69] ([i915#2122]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
    - shard-skl:          [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +37 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
    - shard-tglb:         [DMESG-WARN][73] ([i915#1982]) -> [PASS][74] +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][75] ([i915#1188]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][77] ([fdo#108145] / [i915#265]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][79] ([fdo#109441]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-skl:          [WARN][81] ([i915#2100]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl7/igt@kms_setmode@clone-exclusive-crtc.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl7/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-c:
    - shard-skl:          [SKIP][83] ([fdo#109271]) -> [PASS][84] +5 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl7/igt@kms_universal_plane@disable-primary-vs-flip-pipe-c.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl5/igt@kms_universal_plane@disable-primary-vs-flip-pipe-c.html

  * igt@kms_vblank@pipe-c-wait-forked-busy:
    - shard-apl:          [DMESG-WARN][85] ([i915#1635] / [i915#1982]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl7/igt@kms_vblank@pipe-c-wait-forked-busy.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - shard-kbl:          [INCOMPLETE][87] ([i915#1731]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-kbl7/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-kbl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  
#### Warnings ####

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-tglb:         [DMESG-WARN][89] ([i915#2411]) -> [INCOMPLETE][90] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#456])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-tglb2/igt@i915_pm_backlight@fade_with_suspend.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@kms_content_protection@srm:
    - shard-apl:          [TIMEOUT][91] ([i915#1319] / [i915#1635] / [i915#1958]) -> [FAIL][92] ([fdo#110321] / [i915#1635])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-apl6/igt@kms_content_protection@srm.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-apl3/igt@kms_content_protection@srm.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - shard-skl:          [DMESG-WARN][93] ([i915#1982]) -> [SKIP][94] ([fdo#109271])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][95] ([i915#1226]) -> [SKIP][96] ([fdo#109349])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [FAIL][97] ([i915#2122]) -> [DMESG-WARN][98] ([i915#1982])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          [DMESG-FAIL][99] ([fdo#108145] / [i915#1982]) -> [FAIL][100] ([fdo#108145] / [i915#265])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@runner@aborted:
    - shard-skl:          ([FAIL][101], [FAIL][102], [FAIL][103]) ([i915#1436] / [i915#2439]) -> [FAIL][104] ([i915#1436])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl7/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl4/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9004/shard-skl7/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/shard-skl2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1214]: https://gitlab.freedesktop.org/drm/intel/issues/1214
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2100]: https://gitlab.freedesktop.org/drm/intel/issues/2100
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2212]: https://gitlab.freedesktop.org/drm/intel/issues/2212
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#71]: https://gitlab.freedesktop.org/drm/intel/issues/71
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * IGT: IGT_5781 -> IGTPW_4966
  * Linux: CI_DRM_9004 -> Patchwork_18488

  CI-20190529: 20190529
  CI_DRM_9004: fd4f896ce2e2180433dc0b8ba89d8c9e1f8238ab @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4966: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4966/index.html
  IGT_5781: 66766dd7cd99465d977ac07db8a2413dbbfe8d84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18488: 7e2163c101ade5ede625d5379a5521344678eb7d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18488/index.html

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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:26AM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
> 
> Enable the flip done interrupt in IER.
> 
> Enable flip done function is called before writing the
> surface address register as the write to this register triggers
> the flip done interrupt
> 
> Flip done handler is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
> The interrupt is disabled after the event is sent.
> 
> v2: -Change function name from icl_* to skl_* (Paulo)
>     -Move flip handler to this patch (Paulo)
>     -Remove vblank_put() (Paulo)
>     -Enable flip done interrupt for gen9+ only (Paulo)
>     -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>     -Removed the event check in flip done handler to handle async
>      flips without pageflip events.
> 
> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>     -Make the pending vblank event NULL in the beginning of
>      flip_done_handler to remove sporadic WARN_ON that is seen.
> 
> v4: -Calculate timestamps using flip done time stamp and current
>      timestamp for async flips (Ville)
> 
> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>      static.(Reported-by: kernel test robot <lkp@intel.com>)
>     -Fix the typo in commit message.
> 
> v6: -Revert back to old time stamping code.
>     -Remove the break while calling skl_enable_flip_done. (Paulo)
> 
> v7: -Rebased.
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>  drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_irq.h              |  2 +
>  3 files changed, 62 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ec148a8da2c2..48712fb0a251 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  	intel_dbuf_pre_plane_update(state);
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_enable_flip_done(&crtc->base);
> +	}
> +
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.commit_modeset_enables(state);
>  
> @@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_disable_flip_done(&crtc->base);
> +
>  		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
>  		    !new_crtc_state->preload_luts &&
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f113fe44572b..6cc129b031d3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  			     u32 crc4) {}
>  #endif
>  
> +static void flip_done_handler(struct drm_i915_private *dev_priv,

Pls use
struct drm_i915_private *i915
in new code.

> +			      unsigned int pipe)

enum pipe pipe

> +{
> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +	struct drm_crtc_state *crtc_state = crtc->base.state;
> +	struct drm_pending_vblank_event *e = crtc_state->event;
> +	struct drm_device *dev = &dev_priv->drm;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev->event_lock, irqflags);
> +
> +	crtc_state->event = NULL;
> +
> +	drm_crtc_send_vblank_event(&crtc->base, e);
> +
> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
> +}
>  
>  static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  				     enum pipe pipe)
> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  		if (iir & GEN8_PIPE_VBLANK)
>  			intel_handle_vblank(dev_priv, pipe);
>  
> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> +			flip_done_handler(dev_priv, pipe);
> +
>  		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>  			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  
> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +void skl_enable_flip_done(struct drm_crtc *crtc)

Pls use
struct intel_crtc *crtc
instead

> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  /* Called from drm generic code, passed 'crtc' which
>   * we use as a pipe index
>   */
> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +void skl_disable_flip_done(struct drm_crtc *crtc)

struct intel_crtc *crtc
here too

> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

s/dev_priv/i915/

> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>  	enum pipe pipe;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	if (!intel_irqs_enabled(dev_priv)) {
> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>  					   GEN8_PIPE_FIFO_UNDERRUN;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	de_port_enables = de_port_masked;
>  	if (IS_GEN9_LP(dev_priv))
>  		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..2f10c8135116 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>  int i965_enable_vblank(struct drm_crtc *crtc);
>  int ilk_enable_vblank(struct drm_crtc *crtc);
>  int bdw_enable_vblank(struct drm_crtc *crtc);
> +void skl_enable_flip_done(struct drm_crtc *crtc);

I wouldn't mix these with the vblank hooks like this.

With those this patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  void i8xx_disable_vblank(struct drm_crtc *crtc);
>  void i915gm_disable_vblank(struct drm_crtc *crtc);
>  void i965_disable_vblank(struct drm_crtc *crtc);
>  void ilk_disable_vblank(struct drm_crtc *crtc);
>  void bdw_disable_vblank(struct drm_crtc *crtc);
> +void skl_disable_flip_done(struct drm_crtc *crtc);
>  
>  void gen2_irq_reset(struct intel_uncore *uncore);
>  void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:26AM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
> 
> Enable the flip done interrupt in IER.
> 
> Enable flip done function is called before writing the
> surface address register as the write to this register triggers
> the flip done interrupt
> 
> Flip done handler is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
> The interrupt is disabled after the event is sent.
> 
> v2: -Change function name from icl_* to skl_* (Paulo)
>     -Move flip handler to this patch (Paulo)
>     -Remove vblank_put() (Paulo)
>     -Enable flip done interrupt for gen9+ only (Paulo)
>     -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>     -Removed the event check in flip done handler to handle async
>      flips without pageflip events.
> 
> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>     -Make the pending vblank event NULL in the beginning of
>      flip_done_handler to remove sporadic WARN_ON that is seen.
> 
> v4: -Calculate timestamps using flip done time stamp and current
>      timestamp for async flips (Ville)
> 
> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>      static.(Reported-by: kernel test robot <lkp@intel.com>)
>     -Fix the typo in commit message.
> 
> v6: -Revert back to old time stamping code.
>     -Remove the break while calling skl_enable_flip_done. (Paulo)
> 
> v7: -Rebased.
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>  drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_irq.h              |  2 +
>  3 files changed, 62 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ec148a8da2c2..48712fb0a251 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  	intel_dbuf_pre_plane_update(state);
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_enable_flip_done(&crtc->base);
> +	}
> +
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.commit_modeset_enables(state);
>  
> @@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_disable_flip_done(&crtc->base);
> +
>  		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
>  		    !new_crtc_state->preload_luts &&
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f113fe44572b..6cc129b031d3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  			     u32 crc4) {}
>  #endif
>  
> +static void flip_done_handler(struct drm_i915_private *dev_priv,

Pls use
struct drm_i915_private *i915
in new code.

> +			      unsigned int pipe)

enum pipe pipe

> +{
> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +	struct drm_crtc_state *crtc_state = crtc->base.state;
> +	struct drm_pending_vblank_event *e = crtc_state->event;
> +	struct drm_device *dev = &dev_priv->drm;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev->event_lock, irqflags);
> +
> +	crtc_state->event = NULL;
> +
> +	drm_crtc_send_vblank_event(&crtc->base, e);
> +
> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
> +}
>  
>  static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  				     enum pipe pipe)
> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  		if (iir & GEN8_PIPE_VBLANK)
>  			intel_handle_vblank(dev_priv, pipe);
>  
> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> +			flip_done_handler(dev_priv, pipe);
> +
>  		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>  			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  
> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +void skl_enable_flip_done(struct drm_crtc *crtc)

Pls use
struct intel_crtc *crtc
instead

> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  /* Called from drm generic code, passed 'crtc' which
>   * we use as a pipe index
>   */
> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +void skl_disable_flip_done(struct drm_crtc *crtc)

struct intel_crtc *crtc
here too

> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

s/dev_priv/i915/

> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>  	enum pipe pipe;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	if (!intel_irqs_enabled(dev_priv)) {
> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>  					   GEN8_PIPE_FIFO_UNDERRUN;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	de_port_enables = de_port_masked;
>  	if (IS_GEN9_LP(dev_priv))
>  		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..2f10c8135116 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>  int i965_enable_vblank(struct drm_crtc *crtc);
>  int ilk_enable_vblank(struct drm_crtc *crtc);
>  int bdw_enable_vblank(struct drm_crtc *crtc);
> +void skl_enable_flip_done(struct drm_crtc *crtc);

I wouldn't mix these with the vblank hooks like this.

With those this patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  void i8xx_disable_vblank(struct drm_crtc *crtc);
>  void i915gm_disable_vblank(struct drm_crtc *crtc);
>  void i965_disable_vblank(struct drm_crtc *crtc);
>  void ilk_disable_vblank(struct drm_crtc *crtc);
>  void bdw_disable_vblank(struct drm_crtc *crtc);
> +void skl_disable_flip_done(struct drm_crtc *crtc);
>  
>  void gen2_irq_reset(struct intel_uncore *uncore);
>  void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:27AM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
> 
> v2: -Move the Async flip enablement to individual patch (Paulo)
> 
> v3: -Rebased.
> 
> v4: -Add separate plane hook for async flip case (Ville)
> 
> v5: -Rebased.
> 
> v6: -Move the plane hook to separate patch. (Paulo)
>     -Remove the early return in skl_plane_ctl. (Paulo)
> 
> v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 48712fb0a251..2902fefd217f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 plane_ctl = 0;
>  
> +	if (crtc_state->uapi.async_flip)
> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> +
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		return plane_ctl;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90a05e37ba2f..1c4ddd4deba0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6923,6 +6923,7 @@ enum {
>  #define   PLANE_CTL_TILED_X			(1 << 10)
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:27AM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
> 
> v2: -Move the Async flip enablement to individual patch (Paulo)
> 
> v3: -Rebased.
> 
> v4: -Add separate plane hook for async flip case (Ville)
> 
> v5: -Rebased.
> 
> v6: -Move the plane hook to separate patch. (Paulo)
>     -Remove the early return in skl_plane_ctl. (Paulo)
> 
> v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 48712fb0a251..2902fefd217f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	u32 plane_ctl = 0;
>  
> +	if (crtc_state->uapi.async_flip)
> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> +
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>  		return plane_ctl;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90a05e37ba2f..1c4ddd4deba0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6923,6 +6923,7 @@ enum {
>  #define   PLANE_CTL_TILED_X			(1 << 10)
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:28AM +0530, Karthik B S wrote:
> If flip is requested on any other plane, reject it.
> 
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
> 
> If any of these are modified, reject async flip.
> 
> v2: -Replace DRM_ERROR (Paulo)
>     -Add check for changes in OFFSET, FBC, RC(Paulo)
> 
> v3: -Removed TODO as benchmarking tests have been run now.
> 
> v4: -Added more state checks for async flip (Ville)
>     -Moved intel_atomic_check_async to the end of intel_atomic_check
>      as the plane checks needs to pass before this. (Ville)
>     -Removed crtc_state->enable_fbc check. (Ville)
>     -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>      flip case as scanline counter is not reliable here.
> 
> v5: -Fix typo and other check patch errors seen in CI
>      in 'intel_atomic_check_async' function.
> 
> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>     -Remove the check for n_planes in intel_atomic_check_async
>     -Added documentation for async flips. (Paulo)
> 
> v7: -Replace 'intel_plane' with 'plane'. (Ville)
>     -Replace all uapi.foo as hw.foo. (Ville)
>     -Do not use intel_wm_need_update function. (Ville)
>     -Add destination coordinate check. (Ville)
>     -Do not allow async flip with linear buffer
>      on older hw as it has issues with this. (Ville)
>     -Remove break after intel_atomic_check_async. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
>  1 file changed, 143 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2902fefd217f..a0c17d94daf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>  	return false;
>  }
>  
> +/**
> + * DOC: asynchronous flip implementation
> + *
> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
> + * Correspondingly, support is currently added for primary plane only.
> + *
> + * Async flip can only change the plane surface address, so anything else
> + * changing is rejected from the intel_atomic_check_async() function.
> + * Once this check is cleared, flip done interrupt is enabled using
> + * the skl_enable_flip_done() function.
> + *
> + * As soon as the surface address register is written, flip done interrupt is
> + * generated and the requested events are sent to the usersapce in the interrupt
> + * handler itself. The timestamp and sequence sent during the flip done event
> + * correspond to the last vblank and have no relation to the actual time when
> + * the flip done event was sent.
> + */
> +
> +static int intel_atomic_check_async(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> +	struct intel_plane_state *new_plane_state, *old_plane_state;
> +	struct intel_crtc *crtc;
> +	struct intel_plane *plane;
> +	int i;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		if (needs_modeset(new_crtc_state)) {
> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");

Per-device debugs pls. drm_dbg_kms() etc.

> +			return -EINVAL;
> +		}
> +
> +		if (!new_crtc_state->hw.active) {
> +			DRM_DEBUG_KMS("CRTC inactive\n");
> +			return -EINVAL;
> +		}
> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
> +					     new_plane_state, i) {
> +		/*TODO: Async flip is only supported through the page flip IOCTL

Comment formatting is wrong.

> +		 * as of now. So support currently added for primary plane only.
> +		 * Support for other planes should be added when async flip is
> +		 * enabled in the atomic IOCTL path.

Obviously only for hw that actually supports it. Which I think
means vlv/chv and icl+.

> +		 */
> +		if (plane->id != PLANE_PRIMARY)
> +			return -EINVAL;
> +
> +		/*FIXME: This check is kept generic for all gen <= 10 platforms.

More bad formatting.

> +		 * Need to verify this for all gen9 and gen10 platforms to enable
> +		 * this selectively if required.
> +		 */
> +		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
> +		    INTEL_GEN(dev_priv) <= 10) {

I would drop the gen check for the time being. Much easier for
bisection if we don't enable random features for random platforms in
the initial enabling patch.

Hmm. We're also missing a check for CCS. CCS does not support async
flips iirc. So I recommand only explicitly allowing X/Y/Yf tile here
(assuming all those are supposed to work), reject everything else.

> +			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->color_plane[0].x !=
> +		    new_plane_state->color_plane[0].x ||
> +		    old_plane_state->color_plane[0].y !=
> +		    new_plane_state->color_plane[0].y) {
> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->modifier !=
> +		    new_plane_state->hw.fb->modifier) {
> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->format !=
> +		    new_plane_state->hw.fb->format) {
> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.rotation !=
> +		    new_plane_state->hw.rotation) {
> +			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->width !=
> +		    new_plane_state->hw.fb->width ||
> +		    old_plane_state->hw.fb->height !=
> +		    new_plane_state->hw.fb->height) {

FB size is irrelevant. This check can be dropped.

But stride will need to be checked. Looks like that one is missing.
Though we should check plane_state->color_plane[0].stride instead
of the original fb stride, since the former is what we actually program
into the hw.

> +			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
> +		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
> +		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
> +		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
> +		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
> +		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
> +		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
> +		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
> +			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");

These should check the uapi.src/dst rectangles instead.
In fact I think just two drm_rect_equals() calls will do here,
and then I think we can also drop the color_plane[0].x/y checks
above since they should be the same as checking the src.x1/y1.

> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.pixel_blend_mode !=
> +		    new_plane_state->hw.pixel_blend_mode) {
> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
>  /**
>   * intel_atomic_check - validate state object
>   * @dev: drm device
> @@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
>  				       "[modeset]" : "[fastset]");
>  	}
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip) {
> +			ret = intel_atomic_check_async(state);
> +			if (ret)
> +				goto fail;
> +		}
> +	}

I would put this before the state dump above. Could even stick it into
the same loop I guess.

>  	return 0;
>  
>   fail:
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:28AM +0530, Karthik B S wrote:
> If flip is requested on any other plane, reject it.
> 
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
> 
> If any of these are modified, reject async flip.
> 
> v2: -Replace DRM_ERROR (Paulo)
>     -Add check for changes in OFFSET, FBC, RC(Paulo)
> 
> v3: -Removed TODO as benchmarking tests have been run now.
> 
> v4: -Added more state checks for async flip (Ville)
>     -Moved intel_atomic_check_async to the end of intel_atomic_check
>      as the plane checks needs to pass before this. (Ville)
>     -Removed crtc_state->enable_fbc check. (Ville)
>     -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>      flip case as scanline counter is not reliable here.
> 
> v5: -Fix typo and other check patch errors seen in CI
>      in 'intel_atomic_check_async' function.
> 
> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>     -Remove the check for n_planes in intel_atomic_check_async
>     -Added documentation for async flips. (Paulo)
> 
> v7: -Replace 'intel_plane' with 'plane'. (Ville)
>     -Replace all uapi.foo as hw.foo. (Ville)
>     -Do not use intel_wm_need_update function. (Ville)
>     -Add destination coordinate check. (Ville)
>     -Do not allow async flip with linear buffer
>      on older hw as it has issues with this. (Ville)
>     -Remove break after intel_atomic_check_async. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
>  1 file changed, 143 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2902fefd217f..a0c17d94daf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>  	return false;
>  }
>  
> +/**
> + * DOC: asynchronous flip implementation
> + *
> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
> + * Correspondingly, support is currently added for primary plane only.
> + *
> + * Async flip can only change the plane surface address, so anything else
> + * changing is rejected from the intel_atomic_check_async() function.
> + * Once this check is cleared, flip done interrupt is enabled using
> + * the skl_enable_flip_done() function.
> + *
> + * As soon as the surface address register is written, flip done interrupt is
> + * generated and the requested events are sent to the usersapce in the interrupt
> + * handler itself. The timestamp and sequence sent during the flip done event
> + * correspond to the last vblank and have no relation to the actual time when
> + * the flip done event was sent.
> + */
> +
> +static int intel_atomic_check_async(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> +	struct intel_plane_state *new_plane_state, *old_plane_state;
> +	struct intel_crtc *crtc;
> +	struct intel_plane *plane;
> +	int i;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		if (needs_modeset(new_crtc_state)) {
> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");

Per-device debugs pls. drm_dbg_kms() etc.

> +			return -EINVAL;
> +		}
> +
> +		if (!new_crtc_state->hw.active) {
> +			DRM_DEBUG_KMS("CRTC inactive\n");
> +			return -EINVAL;
> +		}
> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
> +					     new_plane_state, i) {
> +		/*TODO: Async flip is only supported through the page flip IOCTL

Comment formatting is wrong.

> +		 * as of now. So support currently added for primary plane only.
> +		 * Support for other planes should be added when async flip is
> +		 * enabled in the atomic IOCTL path.

Obviously only for hw that actually supports it. Which I think
means vlv/chv and icl+.

> +		 */
> +		if (plane->id != PLANE_PRIMARY)
> +			return -EINVAL;
> +
> +		/*FIXME: This check is kept generic for all gen <= 10 platforms.

More bad formatting.

> +		 * Need to verify this for all gen9 and gen10 platforms to enable
> +		 * this selectively if required.
> +		 */
> +		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
> +		    INTEL_GEN(dev_priv) <= 10) {

I would drop the gen check for the time being. Much easier for
bisection if we don't enable random features for random platforms in
the initial enabling patch.

Hmm. We're also missing a check for CCS. CCS does not support async
flips iirc. So I recommand only explicitly allowing X/Y/Yf tile here
(assuming all those are supposed to work), reject everything else.

> +			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->color_plane[0].x !=
> +		    new_plane_state->color_plane[0].x ||
> +		    old_plane_state->color_plane[0].y !=
> +		    new_plane_state->color_plane[0].y) {
> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->modifier !=
> +		    new_plane_state->hw.fb->modifier) {
> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->format !=
> +		    new_plane_state->hw.fb->format) {
> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.rotation !=
> +		    new_plane_state->hw.rotation) {
> +			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.fb->width !=
> +		    new_plane_state->hw.fb->width ||
> +		    old_plane_state->hw.fb->height !=
> +		    new_plane_state->hw.fb->height) {

FB size is irrelevant. This check can be dropped.

But stride will need to be checked. Looks like that one is missing.
Though we should check plane_state->color_plane[0].stride instead
of the original fb stride, since the former is what we actually program
into the hw.

> +			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
> +		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
> +		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
> +		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
> +		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
> +		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
> +		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
> +		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
> +			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");

These should check the uapi.src/dst rectangles instead.
In fact I think just two drm_rect_equals() calls will do here,
and then I think we can also drop the color_plane[0].x/y checks
above since they should be the same as checking the src.x1/y1.

> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.pixel_blend_mode !=
> +		    new_plane_state->hw.pixel_blend_mode) {
> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
>  /**
>   * intel_atomic_check - validate state object
>   * @dev: drm device
> @@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
>  				       "[modeset]" : "[fastset]");
>  	}
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip) {
> +			ret = intel_atomic_check_async(state);
> +			if (ret)
> +				goto fail;
> +		}
> +	}

I would put this before the state dump above. Could even stick it into
the same loop I guess.

>  	return 0;
>  
>   fail:
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:29AM +0530, Karthik B S wrote:
> Since the flip done event will be sent in the flip_done_handler,
> no need to add the event to the list and delay it for later.
> 
> v2: -Moved the async check above vblank_get as it
>      was causing issues for PSR.
> 
> v3: -No need to wait for vblank to pass, as this wait was causing a
>      16ms delay once every few flips.
> 
> v4: -Rebased.
> 
> v5: -Rebased.
> 
> v6: -Rebased.
> 
> v7: -No need of irq disable if we are not doing vblank evade. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 5ac0dbf0e03d..f0c89418d2e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  	DEFINE_WAIT(wait);
>  	u32 psr_status;
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		return;
> +
>  	vblank_start = adjusted_mode->crtc_vblank_start;
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>  		vblank_start = DIV_ROUND_UP(vblank_start, 2);
> @@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  
>  	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		return;

The pipe update tracepoints will be inconsistent if you put this here.
I guess we don't really need the pipe update tracepoints for async
flips. We might want to add a separate tracepoint for async flip itself,
or perhaps convey the sync vs. async information via the current
plane update tracepoint.

With this moved to before the tracepoint
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	/* We're still in the vblank-evade critical section, this can't race.
>  	 * Would be slightly nice to just grab the vblank count and arm the
>  	 * event outside of the critical section - the spinlock might spin for a
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:29AM +0530, Karthik B S wrote:
> Since the flip done event will be sent in the flip_done_handler,
> no need to add the event to the list and delay it for later.
> 
> v2: -Moved the async check above vblank_get as it
>      was causing issues for PSR.
> 
> v3: -No need to wait for vblank to pass, as this wait was causing a
>      16ms delay once every few flips.
> 
> v4: -Rebased.
> 
> v5: -Rebased.
> 
> v6: -Rebased.
> 
> v7: -No need of irq disable if we are not doing vblank evade. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 5ac0dbf0e03d..f0c89418d2e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  	DEFINE_WAIT(wait);
>  	u32 psr_status;
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		return;
> +
>  	vblank_start = adjusted_mode->crtc_vblank_start;
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>  		vblank_start = DIV_ROUND_UP(vblank_start, 2);
> @@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  
>  	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		return;

The pipe update tracepoints will be inconsistent if you put this here.
I guess we don't really need the pipe update tracepoints for async
flips. We might want to add a separate tracepoint for async flip itself,
or perhaps convey the sync vs. async information via the current
plane update tracepoint.

With this moved to before the tracepoint
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	/* We're still in the vblank-evade critical section, this can't race.
>  	 * Would be slightly nice to just grab the vblank count and arm the
>  	 * event outside of the critical section - the spinlock might spin for a
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
> 
> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>     -Add a vfunc for skl_program_async_surface_address
>      and call it from intel_update_plane. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>  .../drm/i915/display/intel_display_types.h    |  3 +++
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 79032701873a..fdc633020255 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
> +
> +	if (crtc_state->uapi.async_flip) {
> +		plane->program_async_surface_address(plane,
> +						     crtc_state, plane_state);
> +		return;
> +	}

if
	.async_flip()
else
	.update_plane()

should do

> +
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b2d0edacc58c..d2ae781e4d81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1190,6 +1190,9 @@ struct intel_plane {
>  			   struct intel_plane_state *plane_state);
>  	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>  			 const struct intel_plane_state *plane_state);
> +	void (*program_async_surface_address)(struct intel_plane *plane,

That's a mouthful. I'd simplify it to eg. just .async_flip().

> +					      const struct intel_crtc_state *crtc_state,
> +					      const struct intel_plane_state *plane_state);
>  };
>  
>  struct intel_watermark_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f0c89418d2e1..69407dfcebf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>  			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>  }
>  
> +static void
> +skl_program_async_surface_address(struct intel_plane *plane,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	unsigned long irqflags;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	u32 surf_addr = plane_state->color_plane[0].offset;
> +	u32 plane_ctl = plane_state->ctl;
> +
> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> +
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
>  static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
>  	plane->min_cdclk = skl_plane_min_cdclk;
> +	plane->program_async_surface_address = skl_program_async_surface_address;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
> 
> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>     -Add a vfunc for skl_program_async_surface_address
>      and call it from intel_update_plane. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>  .../drm/i915/display/intel_display_types.h    |  3 +++
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 79032701873a..fdc633020255 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
> +
> +	if (crtc_state->uapi.async_flip) {
> +		plane->program_async_surface_address(plane,
> +						     crtc_state, plane_state);
> +		return;
> +	}

if
	.async_flip()
else
	.update_plane()

should do

> +
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b2d0edacc58c..d2ae781e4d81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1190,6 +1190,9 @@ struct intel_plane {
>  			   struct intel_plane_state *plane_state);
>  	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>  			 const struct intel_plane_state *plane_state);
> +	void (*program_async_surface_address)(struct intel_plane *plane,

That's a mouthful. I'd simplify it to eg. just .async_flip().

> +					      const struct intel_crtc_state *crtc_state,
> +					      const struct intel_plane_state *plane_state);
>  };
>  
>  struct intel_watermark_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f0c89418d2e1..69407dfcebf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>  			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>  }
>  
> +static void
> +skl_program_async_surface_address(struct intel_plane *plane,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	unsigned long irqflags;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	u32 surf_addr = plane_state->color_plane[0].offset;
> +	u32 plane_ctl = plane_state->ctl;
> +
> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> +
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
>  static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
>  	plane->min_cdclk = skl_plane_min_cdclk;
> +	plane->program_async_surface_address = skl_program_async_surface_address;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:31AM +0530, Karthik B S wrote:
> In Gen 9 and Gen 10 platforms, async address update enable bit is
> double buffered. Due to this, during the transition from async flip
> to sync flip we have to wait until this bit is updated before continuing
> with the normal commit for sync flip.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a0c17d94daf3..b7e24dff0772 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>  	intel_crtc_enable_pipe_crc(crtc);
>  }
>  
> +static void skl_toggle_async_sync(struct intel_atomic_state *state,

skl_disable_async_flip_wa() maybe?

> +				  struct intel_crtc *crtc,
> +				  struct intel_crtc_state *new_crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *plane;
> +	struct intel_plane_state *new_plane_state;
> +	u32 update_mask = new_crtc_state->update_planes;
> +	u32 plane_ctl, surf_addr;
> +	enum plane_id plane_id;
> +	unsigned long irqflags;
> +	enum pipe pipe;

Most of these things are only needed within the loop, so that's where
the declarations should be.

> +	int i;
> +
> +	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> +		if (crtc->pipe != plane->pipe ||
> +		    !(update_mask & BIT(plane->id)))
> +			continue;
> +
> +		plane_id = plane->id;
> +		pipe = plane->pipe;
> +

I'd take the lock here so the rmw is fully protected.

> +		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
> +		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
> +
> +		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
> +
> +		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
> +		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +	}
> +
> +	intel_wait_for_vblank(dev_priv, crtc->pipe);
> +}
> +
>  static void intel_update_crtc(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc)
>  {
> @@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>  	else
>  		intel_fbc_enable(state, crtc);
>  
> +	/* WA for older platforms where async address update enable bit

s/older//

> +	 * is double buffered.

"is double buffered and only latched at start of vblank" or
something. Otherwise one is left wondering what the fuss is about.

> +	 */

Multiline comment format should be
/*
 * blah
 * blah
 */

> +	if (old_crtc_state->uapi.async_flip &&
> +	    !new_crtc_state->uapi.async_flip &&
> +	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)

IS_GEN_RANGE(9, 10) or whatever it's called.

I guess we might want to put this call into intel_pre_plane_update()
since that's where all kinds of similar wait_for_vblank w/as live.

> +		skl_toggle_async_sync(state, crtc, new_crtc_state);
> +
>  	/* Perform vblank evasion around commit operation */
>  	intel_pipe_update_start(new_crtc_state);
>  
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:31AM +0530, Karthik B S wrote:
> In Gen 9 and Gen 10 platforms, async address update enable bit is
> double buffered. Due to this, during the transition from async flip
> to sync flip we have to wait until this bit is updated before continuing
> with the normal commit for sync flip.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a0c17d94daf3..b7e24dff0772 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>  	intel_crtc_enable_pipe_crc(crtc);
>  }
>  
> +static void skl_toggle_async_sync(struct intel_atomic_state *state,

skl_disable_async_flip_wa() maybe?

> +				  struct intel_crtc *crtc,
> +				  struct intel_crtc_state *new_crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_plane *plane;
> +	struct intel_plane_state *new_plane_state;
> +	u32 update_mask = new_crtc_state->update_planes;
> +	u32 plane_ctl, surf_addr;
> +	enum plane_id plane_id;
> +	unsigned long irqflags;
> +	enum pipe pipe;

Most of these things are only needed within the loop, so that's where
the declarations should be.

> +	int i;
> +
> +	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
> +		if (crtc->pipe != plane->pipe ||
> +		    !(update_mask & BIT(plane->id)))
> +			continue;
> +
> +		plane_id = plane->id;
> +		pipe = plane->pipe;
> +

I'd take the lock here so the rmw is fully protected.

> +		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
> +		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
> +
> +		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
> +
> +		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
> +		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +	}
> +
> +	intel_wait_for_vblank(dev_priv, crtc->pipe);
> +}
> +
>  static void intel_update_crtc(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc)
>  {
> @@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>  	else
>  		intel_fbc_enable(state, crtc);
>  
> +	/* WA for older platforms where async address update enable bit

s/older//

> +	 * is double buffered.

"is double buffered and only latched at start of vblank" or
something. Otherwise one is left wondering what the fuss is about.

> +	 */

Multiline comment format should be
/*
 * blah
 * blah
 */

> +	if (old_crtc_state->uapi.async_flip &&
> +	    !new_crtc_state->uapi.async_flip &&
> +	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)

IS_GEN_RANGE(9, 10) or whatever it's called.

I guess we might want to put this call into intel_pre_plane_update()
since that's where all kinds of similar wait_for_vblank w/as live.

> +		skl_toggle_async_sync(state, crtc, new_crtc_state);
> +
>  	/* Perform vblank evasion around commit operation */
>  	intel_pipe_update_start(new_crtc_state);
>  
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
> 
> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>     -Add a vfunc for skl_program_async_surface_address
>      and call it from intel_update_plane. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>  .../drm/i915/display/intel_display_types.h    |  3 +++
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 79032701873a..fdc633020255 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
> +
> +	if (crtc_state->uapi.async_flip) {

Hmm. Now I'm starting to wonder how this is actually going to interact
with legacy cursor updates. The crtc_state we use there I think comes
from the previous update and so will have this flag set it if was an
async flip. Which means the cursor ioctl will oops.

We may want the igt to check this particular combination of ioctls
actually.

> +		plane->program_async_surface_address(plane,
> +						     crtc_state, plane_state);
> +		return;
> +	}
> +
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b2d0edacc58c..d2ae781e4d81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1190,6 +1190,9 @@ struct intel_plane {
>  			   struct intel_plane_state *plane_state);
>  	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>  			 const struct intel_plane_state *plane_state);
> +	void (*program_async_surface_address)(struct intel_plane *plane,
> +					      const struct intel_crtc_state *crtc_state,
> +					      const struct intel_plane_state *plane_state);
>  };
>  
>  struct intel_watermark_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f0c89418d2e1..69407dfcebf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>  			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>  }
>  
> +static void
> +skl_program_async_surface_address(struct intel_plane *plane,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	unsigned long irqflags;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	u32 surf_addr = plane_state->color_plane[0].offset;
> +	u32 plane_ctl = plane_state->ctl;
> +
> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> +
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
>  static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
>  	plane->min_cdclk = skl_plane_min_cdclk;
> +	plane->program_async_surface_address = skl_program_async_surface_address;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Ville Syrjälä]

On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
> 
> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>     -Add a vfunc for skl_program_async_surface_address
>      and call it from intel_update_plane. (Ville)
> 
> v8: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>  .../drm/i915/display/intel_display_types.h    |  3 +++
>  drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 79032701873a..fdc633020255 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	trace_intel_update_plane(&plane->base, crtc);
> +
> +	if (crtc_state->uapi.async_flip) {

Hmm. Now I'm starting to wonder how this is actually going to interact
with legacy cursor updates. The crtc_state we use there I think comes
from the previous update and so will have this flag set it if was an
async flip. Which means the cursor ioctl will oops.

We may want the igt to check this particular combination of ioctls
actually.

> +		plane->program_async_surface_address(plane,
> +						     crtc_state, plane_state);
> +		return;
> +	}
> +
>  	plane->update_plane(plane, crtc_state, plane_state);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b2d0edacc58c..d2ae781e4d81 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1190,6 +1190,9 @@ struct intel_plane {
>  			   struct intel_plane_state *plane_state);
>  	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>  			 const struct intel_plane_state *plane_state);
> +	void (*program_async_surface_address)(struct intel_plane *plane,
> +					      const struct intel_crtc_state *crtc_state,
> +					      const struct intel_plane_state *plane_state);
>  };
>  
>  struct intel_watermark_params {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f0c89418d2e1..69407dfcebf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>  			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>  }
>  
> +static void
> +skl_program_async_surface_address(struct intel_plane *plane,
> +				  const struct intel_crtc_state *crtc_state,
> +				  const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	unsigned long irqflags;
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = plane->pipe;
> +	u32 surf_addr = plane_state->color_plane[0].offset;
> +	u32 plane_ctl = plane_state->ctl;
> +
> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> +
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
>  static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	plane->get_hw_state = skl_plane_get_hw_state;
>  	plane->check_plane = skl_plane_check;
>  	plane->min_cdclk = skl_plane_min_cdclk;
> +	plane->program_async_surface_address = skl_program_async_surface_address;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		formats = icl_get_plane_formats(dev_priv, pipe,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

On 9/15/2020 7:17 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:26AM +0530, Karthik B S wrote:
>> Add enable/disable flip done functions and the flip done handler
>> function which handles the flip done interrupt.
>>
>> Enable the flip done interrupt in IER.
>>
>> Enable flip done function is called before writing the
>> surface address register as the write to this register triggers
>> the flip done interrupt
>>
>> Flip done handler is used to send the page flip event as soon as the
>> surface address is written as per the requirement of async flips.
>> The interrupt is disabled after the event is sent.
>>
>> v2: -Change function name from icl_* to skl_* (Paulo)
>>      -Move flip handler to this patch (Paulo)
>>      -Remove vblank_put() (Paulo)
>>      -Enable flip done interrupt for gen9+ only (Paulo)
>>      -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>      -Removed the event check in flip done handler to handle async
>>       flips without pageflip events.
>>
>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>      -Make the pending vblank event NULL in the beginning of
>>       flip_done_handler to remove sporadic WARN_ON that is seen.
>>
>> v4: -Calculate timestamps using flip done time stamp and current
>>       timestamp for async flips (Ville)
>>
>> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>>       static.(Reported-by: kernel test robot <lkp@intel.com>)
>>      -Fix the typo in commit message.
>>
>> v6: -Revert back to old time stamping code.
>>      -Remove the break while calling skl_enable_flip_done. (Paulo)
>>
>> v7: -Rebased.
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>>   drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_irq.h              |  2 +
>>   3 files changed, 62 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index ec148a8da2c2..48712fb0a251 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   
>>   	intel_dbuf_pre_plane_update(state);
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_enable_flip_done(&crtc->base);
>> +	}
>> +
>>   	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>   	dev_priv->display.commit_modeset_enables(state);
>>   
>> @@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_disable_flip_done(&crtc->base);
>> +
>>   		if (new_crtc_state->hw.active &&
>>   		    !needs_modeset(new_crtc_state) &&
>>   		    !new_crtc_state->preload_luts &&
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index f113fe44572b..6cc129b031d3 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   			     u32 crc4) {}
>>   #endif
>>   
>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
> 
> Pls use
> struct drm_i915_private *i915
> in new code.

Thanks for the review.
Sure. I'll change this.
> 
>> +			      unsigned int pipe)
> 
> enum pipe pipe
> 

Noted.
>> +{
>> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>> +	struct drm_crtc_state *crtc_state = crtc->base.state;
>> +	struct drm_pending_vblank_event *e = crtc_state->event;
>> +	struct drm_device *dev = &dev_priv->drm;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev->event_lock, irqflags);
>> +
>> +	crtc_state->event = NULL;
>> +
>> +	drm_crtc_send_vblank_event(&crtc->base, e);
>> +
>> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
>> +}
>>   
>>   static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   				     enum pipe pipe)
>> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   		if (iir & GEN8_PIPE_VBLANK)
>>   			intel_handle_vblank(dev_priv, pipe);
>>   
>> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>> +			flip_done_handler(dev_priv, pipe);
>> +
>>   		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>   			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>   
>> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>   	return 0;
>>   }
>>   
>> +void skl_enable_flip_done(struct drm_crtc *crtc)
> 
> Pls use
> struct intel_crtc *crtc
> instead
> 

Sure. I'll update this.
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   /* Called from drm generic code, passed 'crtc' which
>>    * we use as a pipe index
>>    */
>> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>   	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>   }
>>   
>> +void skl_disable_flip_done(struct drm_crtc *crtc)
> 
> struct intel_crtc *crtc
> here too
> 

Sure. I'll update this.
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 
> s/dev_priv/i915/
> 

I'll update this.
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_uncore *uncore = &dev_priv->uncore;
>> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>   	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>   	enum pipe pipe;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	spin_lock_irq(&dev_priv->irq_lock);
>>   
>>   	if (!intel_irqs_enabled(dev_priv)) {
>> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>   	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>   					   GEN8_PIPE_FIFO_UNDERRUN;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	de_port_enables = de_port_masked;
>>   	if (IS_GEN9_LP(dev_priv))
>>   		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index 25f25cd95818..2f10c8135116 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>   int i965_enable_vblank(struct drm_crtc *crtc);
>>   int ilk_enable_vblank(struct drm_crtc *crtc);
>>   int bdw_enable_vblank(struct drm_crtc *crtc);
>> +void skl_enable_flip_done(struct drm_crtc *crtc);
> 
> I wouldn't mix these with the vblank hooks like this.
> 

Sure. I'll separate them out.
> With those this patch is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks for the RB.

Thanks,
Karthik.B.S
> 
>>   void i8xx_disable_vblank(struct drm_crtc *crtc);
>>   void i915gm_disable_vblank(struct drm_crtc *crtc);
>>   void i965_disable_vblank(struct drm_crtc *crtc);
>>   void ilk_disable_vblank(struct drm_crtc *crtc);
>>   void bdw_disable_vblank(struct drm_crtc *crtc);
>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>   
>>   void gen2_irq_reset(struct intel_uncore *uncore);
>>   void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 1/8] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

On 9/15/2020 7:17 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:26AM +0530, Karthik B S wrote:
>> Add enable/disable flip done functions and the flip done handler
>> function which handles the flip done interrupt.
>>
>> Enable the flip done interrupt in IER.
>>
>> Enable flip done function is called before writing the
>> surface address register as the write to this register triggers
>> the flip done interrupt
>>
>> Flip done handler is used to send the page flip event as soon as the
>> surface address is written as per the requirement of async flips.
>> The interrupt is disabled after the event is sent.
>>
>> v2: -Change function name from icl_* to skl_* (Paulo)
>>      -Move flip handler to this patch (Paulo)
>>      -Remove vblank_put() (Paulo)
>>      -Enable flip done interrupt for gen9+ only (Paulo)
>>      -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>      -Removed the event check in flip done handler to handle async
>>       flips without pageflip events.
>>
>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>      -Make the pending vblank event NULL in the beginning of
>>       flip_done_handler to remove sporadic WARN_ON that is seen.
>>
>> v4: -Calculate timestamps using flip done time stamp and current
>>       timestamp for async flips (Ville)
>>
>> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>>       static.(Reported-by: kernel test robot <lkp@intel.com>)
>>      -Fix the typo in commit message.
>>
>> v6: -Revert back to old time stamping code.
>>      -Remove the break while calling skl_enable_flip_done. (Paulo)
>>
>> v7: -Rebased.
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>>   drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_irq.h              |  2 +
>>   3 files changed, 62 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index ec148a8da2c2..48712fb0a251 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15606,6 +15606,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   
>>   	intel_dbuf_pre_plane_update(state);
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_enable_flip_done(&crtc->base);
>> +	}
>> +
>>   	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>   	dev_priv->display.commit_modeset_enables(state);
>>   
>> @@ -15627,6 +15632,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_disable_flip_done(&crtc->base);
>> +
>>   		if (new_crtc_state->hw.active &&
>>   		    !needs_modeset(new_crtc_state) &&
>>   		    !new_crtc_state->preload_luts &&
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index f113fe44572b..6cc129b031d3 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   			     u32 crc4) {}
>>   #endif
>>   
>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
> 
> Pls use
> struct drm_i915_private *i915
> in new code.

Thanks for the review.
Sure. I'll change this.
> 
>> +			      unsigned int pipe)
> 
> enum pipe pipe
> 

Noted.
>> +{
>> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>> +	struct drm_crtc_state *crtc_state = crtc->base.state;
>> +	struct drm_pending_vblank_event *e = crtc_state->event;
>> +	struct drm_device *dev = &dev_priv->drm;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev->event_lock, irqflags);
>> +
>> +	crtc_state->event = NULL;
>> +
>> +	drm_crtc_send_vblank_event(&crtc->base, e);
>> +
>> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
>> +}
>>   
>>   static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   				     enum pipe pipe)
>> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   		if (iir & GEN8_PIPE_VBLANK)
>>   			intel_handle_vblank(dev_priv, pipe);
>>   
>> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>> +			flip_done_handler(dev_priv, pipe);
>> +
>>   		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>   			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>   
>> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>   	return 0;
>>   }
>>   
>> +void skl_enable_flip_done(struct drm_crtc *crtc)
> 
> Pls use
> struct intel_crtc *crtc
> instead
> 

Sure. I'll update this.
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   /* Called from drm generic code, passed 'crtc' which
>>    * we use as a pipe index
>>    */
>> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>   	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>   }
>>   
>> +void skl_disable_flip_done(struct drm_crtc *crtc)
> 
> struct intel_crtc *crtc
> here too
> 

Sure. I'll update this.
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 
> s/dev_priv/i915/
> 

I'll update this.
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_uncore *uncore = &dev_priv->uncore;
>> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>   	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>   	enum pipe pipe;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	spin_lock_irq(&dev_priv->irq_lock);
>>   
>>   	if (!intel_irqs_enabled(dev_priv)) {
>> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>   	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>   					   GEN8_PIPE_FIFO_UNDERRUN;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	de_port_enables = de_port_masked;
>>   	if (IS_GEN9_LP(dev_priv))
>>   		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index 25f25cd95818..2f10c8135116 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>   int i965_enable_vblank(struct drm_crtc *crtc);
>>   int ilk_enable_vblank(struct drm_crtc *crtc);
>>   int bdw_enable_vblank(struct drm_crtc *crtc);
>> +void skl_enable_flip_done(struct drm_crtc *crtc);
> 
> I wouldn't mix these with the vblank hooks like this.
> 

Sure. I'll separate them out.
> With those this patch is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks for the RB.

Thanks,
Karthik.B.S
> 
>>   void i8xx_disable_vblank(struct drm_crtc *crtc);
>>   void i915gm_disable_vblank(struct drm_crtc *crtc);
>>   void i965_disable_vblank(struct drm_crtc *crtc);
>>   void ilk_disable_vblank(struct drm_crtc *crtc);
>>   void bdw_disable_vblank(struct drm_crtc *crtc);
>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>   
>>   void gen2_irq_reset(struct intel_uncore *uncore);
>>   void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Karthik B S]

On 9/15/2020 7:18 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:27AM +0530, Karthik B S wrote:
>> Set the Async Address Update Enable bit in plane ctl
>> when async flip is requested.
>>
>> v2: -Move the Async flip enablement to individual patch (Paulo)
>>
>> v3: -Rebased.
>>
>> v4: -Add separate plane hook for async flip case (Ville)
>>
>> v5: -Rebased.
>>
>> v6: -Move the plane hook to separate patch. (Paulo)
>>      -Remove the early return in skl_plane_ctl. (Paulo)
>>
>> v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks for the RB.

Thanks,
Karthik.B.S
> 
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 48712fb0a251..2902fefd217f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>>   	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>>   	u32 plane_ctl = 0;
>>   
>> +	if (crtc_state->uapi.async_flip)
>> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
>> +
>>   	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>>   		return plane_ctl;
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 90a05e37ba2f..1c4ddd4deba0 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6923,6 +6923,7 @@ enum {
>>   #define   PLANE_CTL_TILED_X			(1 << 10)
>>   #define   PLANE_CTL_TILED_Y			(4 << 10)
>>   #define   PLANE_CTL_TILED_YF			(5 << 10)
>> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>>   #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>>   #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>>   #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 2/8] drm/i915: Add support for async flips in I915

[Karthik B S]

On 9/15/2020 7:18 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:27AM +0530, Karthik B S wrote:
>> Set the Async Address Update Enable bit in plane ctl
>> when async flip is requested.
>>
>> v2: -Move the Async flip enablement to individual patch (Paulo)
>>
>> v3: -Rebased.
>>
>> v4: -Add separate plane hook for async flip case (Ville)
>>
>> v5: -Rebased.
>>
>> v6: -Move the plane hook to separate patch. (Paulo)
>>      -Remove the early return in skl_plane_ctl. (Paulo)
>>
>> v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks for the RB.

Thanks,
Karthik.B.S
> 
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 48712fb0a251..2902fefd217f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4785,6 +4785,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>>   	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>>   	u32 plane_ctl = 0;
>>   
>> +	if (crtc_state->uapi.async_flip)
>> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
>> +
>>   	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>>   		return plane_ctl;
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 90a05e37ba2f..1c4ddd4deba0 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6923,6 +6923,7 @@ enum {
>>   #define   PLANE_CTL_TILED_X			(1 << 10)
>>   #define   PLANE_CTL_TILED_Y			(4 << 10)
>>   #define   PLANE_CTL_TILED_YF			(5 << 10)
>> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>>   #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>>   #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>>   #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Karthik B S]

On 9/15/2020 7:33 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:28AM +0530, Karthik B S wrote:
>> If flip is requested on any other plane, reject it.
>>
>> Make sure there is no change in fbc, offset and framebuffer modifiers
>> when async flip is requested.
>>
>> If any of these are modified, reject async flip.
>>
>> v2: -Replace DRM_ERROR (Paulo)
>>      -Add check for changes in OFFSET, FBC, RC(Paulo)
>>
>> v3: -Removed TODO as benchmarking tests have been run now.
>>
>> v4: -Added more state checks for async flip (Ville)
>>      -Moved intel_atomic_check_async to the end of intel_atomic_check
>>       as the plane checks needs to pass before this. (Ville)
>>      -Removed crtc_state->enable_fbc check. (Ville)
>>      -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>>       flip case as scanline counter is not reliable here.
>>
>> v5: -Fix typo and other check patch errors seen in CI
>>       in 'intel_atomic_check_async' function.
>>
>> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>>      -Remove the check for n_planes in intel_atomic_check_async
>>      -Added documentation for async flips. (Paulo)
>>
>> v7: -Replace 'intel_plane' with 'plane'. (Ville)
>>      -Replace all uapi.foo as hw.foo. (Ville)
>>      -Do not use intel_wm_need_update function. (Ville)
>>      -Add destination coordinate check. (Ville)
>>      -Do not allow async flip with linear buffer
>>       on older hw as it has issues with this. (Ville)
>>      -Remove break after intel_atomic_check_async. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
>>   1 file changed, 143 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 2902fefd217f..a0c17d94daf3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>>   	return false;
>>   }
>>   
>> +/**
>> + * DOC: asynchronous flip implementation
>> + *
>> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
>> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
>> + * Correspondingly, support is currently added for primary plane only.
>> + *
>> + * Async flip can only change the plane surface address, so anything else
>> + * changing is rejected from the intel_atomic_check_async() function.
>> + * Once this check is cleared, flip done interrupt is enabled using
>> + * the skl_enable_flip_done() function.
>> + *
>> + * As soon as the surface address register is written, flip done interrupt is
>> + * generated and the requested events are sent to the usersapce in the interrupt
>> + * handler itself. The timestamp and sequence sent during the flip done event
>> + * correspond to the last vblank and have no relation to the actual time when
>> + * the flip done event was sent.
>> + */
>> +
>> +static int intel_atomic_check_async(struct intel_atomic_state *state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>> +	struct intel_plane_state *new_plane_state, *old_plane_state;
>> +	struct intel_crtc *crtc;
>> +	struct intel_plane *plane;
>> +	int i;
>> +
>> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> +					    new_crtc_state, i) {
>> +		if (needs_modeset(new_crtc_state)) {
>> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
> 
> Per-device debugs pls. drm_dbg_kms() etc.
> 

Thanks for the review.
Sure, I'll update this.
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (!new_crtc_state->hw.active) {
>> +			DRM_DEBUG_KMS("CRTC inactive\n");
>> +			return -EINVAL;
>> +		}
>> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
>> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
>> +					     new_plane_state, i) {
>> +		/*TODO: Async flip is only supported through the page flip IOCTL
> 
> Comment formatting is wrong.
> 

I'll fix this.
>> +		 * as of now. So support currently added for primary plane only.
>> +		 * Support for other planes should be added when async flip is
>> +		 * enabled in the atomic IOCTL path.
> 
> Obviously only for hw that actually supports it. Which I think
> means vlv/chv and icl+.
> 

Sure, I'll add this in the comment.
>> +		 */
>> +		if (plane->id != PLANE_PRIMARY)
>> +			return -EINVAL;
>> +
>> +		/*FIXME: This check is kept generic for all gen <= 10 platforms.
> 
> More bad formatting.
> 

I'll fix this.
>> +		 * Need to verify this for all gen9 and gen10 platforms to enable
>> +		 * this selectively if required.
>> +		 */
>> +		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
>> +		    INTEL_GEN(dev_priv) <= 10) {
> 
> I would drop the gen check for the time being. Much easier for
> bisection if we don't enable random features for random platforms in
> the initial enabling patch.
> 

Sure, I'll remove the gen check.
> Hmm. We're also missing a check for CCS. CCS does not support async
> flips iirc. So I recommand only explicitly allowing X/Y/Yf tile here
> (assuming all those are supposed to work), reject everything else.
> 

Sure, I'll modify the check accordingly.
>> +			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->color_plane[0].x !=
>> +		    new_plane_state->color_plane[0].x ||
>> +		    old_plane_state->color_plane[0].y !=
>> +		    new_plane_state->color_plane[0].y) {
>> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->modifier !=
>> +		    new_plane_state->hw.fb->modifier) {
>> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->format !=
>> +		    new_plane_state->hw.fb->format) {
>> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.rotation !=
>> +		    new_plane_state->hw.rotation) {
>> +			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->width !=
>> +		    new_plane_state->hw.fb->width ||
>> +		    old_plane_state->hw.fb->height !=
>> +		    new_plane_state->hw.fb->height) {
> 
> FB size is irrelevant. This check can be dropped.
> 

Sure, I'll remove this.
> But stride will need to be checked. Looks like that one is missing.
> Though we should check plane_state->color_plane[0].stride instead
> of the original fb stride, since the former is what we actually program
> into the hw.
> 

Sure, I'll update accordingly.
>> +			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
>> +		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
>> +		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
>> +		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
>> +		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
>> +		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
>> +		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
>> +		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
>> +			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
> 
> These should check the uapi.src/dst rectangles instead.
> In fact I think just two drm_rect_equals() calls will do here,
> and then I think we can also drop the color_plane[0].x/y checks
> above since they should be the same as checking the src.x1/y1.
> 

Sure, I'll make these changes.
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
>> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.pixel_blend_mode !=
>> +		    new_plane_state->hw.pixel_blend_mode) {
>> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
>> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
>> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   /**
>>    * intel_atomic_check - validate state object
>>    * @dev: drm device
>> @@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
>>   				       "[modeset]" : "[fastset]");
>>   	}
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip) {
>> +			ret = intel_atomic_check_async(state);
>> +			if (ret)
>> +				goto fail;
>> +		}
>> +	}
> 
> I would put this before the state dump above. Could even stick it into
> the same loop I guess.
> 

Sure, I'll move this into the above loop.

Thanks,
Karthik.B.S
>>   	return 0;
>>   
>>    fail:
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 3/8] drm/i915: Add checks specific to async flips

[Karthik B S]

On 9/15/2020 7:33 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:28AM +0530, Karthik B S wrote:
>> If flip is requested on any other plane, reject it.
>>
>> Make sure there is no change in fbc, offset and framebuffer modifiers
>> when async flip is requested.
>>
>> If any of these are modified, reject async flip.
>>
>> v2: -Replace DRM_ERROR (Paulo)
>>      -Add check for changes in OFFSET, FBC, RC(Paulo)
>>
>> v3: -Removed TODO as benchmarking tests have been run now.
>>
>> v4: -Added more state checks for async flip (Ville)
>>      -Moved intel_atomic_check_async to the end of intel_atomic_check
>>       as the plane checks needs to pass before this. (Ville)
>>      -Removed crtc_state->enable_fbc check. (Ville)
>>      -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>>       flip case as scanline counter is not reliable here.
>>
>> v5: -Fix typo and other check patch errors seen in CI
>>       in 'intel_atomic_check_async' function.
>>
>> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>>      -Remove the check for n_planes in intel_atomic_check_async
>>      -Added documentation for async flips. (Paulo)
>>
>> v7: -Replace 'intel_plane' with 'plane'. (Ville)
>>      -Replace all uapi.foo as hw.foo. (Ville)
>>      -Do not use intel_wm_need_update function. (Ville)
>>      -Add destination coordinate check. (Ville)
>>      -Do not allow async flip with linear buffer
>>       on older hw as it has issues with this. (Ville)
>>      -Remove break after intel_atomic_check_async. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 143 +++++++++++++++++++
>>   1 file changed, 143 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 2902fefd217f..a0c17d94daf3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14876,6 +14876,142 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>>   	return false;
>>   }
>>   
>> +/**
>> + * DOC: asynchronous flip implementation
>> + *
>> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
>> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
>> + * Correspondingly, support is currently added for primary plane only.
>> + *
>> + * Async flip can only change the plane surface address, so anything else
>> + * changing is rejected from the intel_atomic_check_async() function.
>> + * Once this check is cleared, flip done interrupt is enabled using
>> + * the skl_enable_flip_done() function.
>> + *
>> + * As soon as the surface address register is written, flip done interrupt is
>> + * generated and the requested events are sent to the usersapce in the interrupt
>> + * handler itself. The timestamp and sequence sent during the flip done event
>> + * correspond to the last vblank and have no relation to the actual time when
>> + * the flip done event was sent.
>> + */
>> +
>> +static int intel_atomic_check_async(struct intel_atomic_state *state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>> +	struct intel_plane_state *new_plane_state, *old_plane_state;
>> +	struct intel_crtc *crtc;
>> +	struct intel_plane *plane;
>> +	int i;
>> +
>> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> +					    new_crtc_state, i) {
>> +		if (needs_modeset(new_crtc_state)) {
>> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
> 
> Per-device debugs pls. drm_dbg_kms() etc.
> 

Thanks for the review.
Sure, I'll update this.
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (!new_crtc_state->hw.active) {
>> +			DRM_DEBUG_KMS("CRTC inactive\n");
>> +			return -EINVAL;
>> +		}
>> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
>> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
>> +					     new_plane_state, i) {
>> +		/*TODO: Async flip is only supported through the page flip IOCTL
> 
> Comment formatting is wrong.
> 

I'll fix this.
>> +		 * as of now. So support currently added for primary plane only.
>> +		 * Support for other planes should be added when async flip is
>> +		 * enabled in the atomic IOCTL path.
> 
> Obviously only for hw that actually supports it. Which I think
> means vlv/chv and icl+.
> 

Sure, I'll add this in the comment.
>> +		 */
>> +		if (plane->id != PLANE_PRIMARY)
>> +			return -EINVAL;
>> +
>> +		/*FIXME: This check is kept generic for all gen <= 10 platforms.
> 
> More bad formatting.
> 

I'll fix this.
>> +		 * Need to verify this for all gen9 and gen10 platforms to enable
>> +		 * this selectively if required.
>> +		 */
>> +		if (new_plane_state->hw.fb->modifier == DRM_FORMAT_MOD_LINEAR &&
>> +		    INTEL_GEN(dev_priv) <= 10) {
> 
> I would drop the gen check for the time being. Much easier for
> bisection if we don't enable random features for random platforms in
> the initial enabling patch.
> 

Sure, I'll remove the gen check.
> Hmm. We're also missing a check for CCS. CCS does not support async
> flips iirc. So I recommand only explicitly allowing X/Y/Yf tile here
> (assuming all those are supposed to work), reject everything else.
> 

Sure, I'll modify the check accordingly.
>> +			DRM_DEBUG_KMS("Linear memory does not support async flips on gen <= 10\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->color_plane[0].x !=
>> +		    new_plane_state->color_plane[0].x ||
>> +		    old_plane_state->color_plane[0].y !=
>> +		    new_plane_state->color_plane[0].y) {
>> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->modifier !=
>> +		    new_plane_state->hw.fb->modifier) {
>> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->format !=
>> +		    new_plane_state->hw.fb->format) {
>> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.rotation !=
>> +		    new_plane_state->hw.rotation) {
>> +			DRM_DEBUG_KMS("Rotation cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.fb->width !=
>> +		    new_plane_state->hw.fb->width ||
>> +		    old_plane_state->hw.fb->height !=
>> +		    new_plane_state->hw.fb->height) {
> 
> FB size is irrelevant. This check can be dropped.
> 

Sure, I'll remove this.
> But stride will need to be checked. Looks like that one is missing.
> Though we should check plane_state->color_plane[0].stride instead
> of the original fb stride, since the former is what we actually program
> into the hw.
> 

Sure, I'll update accordingly.
>> +			DRM_DEBUG_KMS("Framebuffer dimensions cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.src_w != new_plane_state->uapi.src_w ||
>> +		    old_plane_state->uapi.src_h != new_plane_state->uapi.src_h ||
>> +		    old_plane_state->uapi.src_x != new_plane_state->uapi.src_x ||
>> +		    old_plane_state->uapi.src_y != new_plane_state->uapi.src_y ||
>> +		    old_plane_state->uapi.crtc_w != new_plane_state->uapi.crtc_w ||
>> +		    old_plane_state->uapi.crtc_h != new_plane_state->uapi.crtc_h ||
>> +		    old_plane_state->uapi.crtc_x != new_plane_state->uapi.crtc_x ||
>> +		    old_plane_state->uapi.crtc_y != new_plane_state->uapi.crtc_y) {
>> +			DRM_DEBUG_KMS("Plane size/co-ordinates cannot be changed in async flip\n");
> 
> These should check the uapi.src/dst rectangles instead.
> In fact I think just two drm_rect_equals() calls will do here,
> and then I think we can also drop the color_plane[0].x/y checks
> above since they should be the same as checking the src.x1/y1.
> 

Sure, I'll make these changes.
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
>> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.pixel_blend_mode !=
>> +		    new_plane_state->hw.pixel_blend_mode) {
>> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
>> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
>> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   /**
>>    * intel_atomic_check - validate state object
>>    * @dev: drm device
>> @@ -15053,6 +15189,13 @@ static int intel_atomic_check(struct drm_device *dev,
>>   				       "[modeset]" : "[fastset]");
>>   	}
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip) {
>> +			ret = intel_atomic_check_async(state);
>> +			if (ret)
>> +				goto fail;
>> +		}
>> +	}
> 
> I would put this before the state dump above. Could even stick it into
> the same loop I guess.
> 

Sure, I'll move this into the above loop.

Thanks,
Karthik.B.S
>>   	return 0;
>>   
>>    fail:
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

On 9/15/2020 7:37 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:29AM +0530, Karthik B S wrote:
>> Since the flip done event will be sent in the flip_done_handler,
>> no need to add the event to the list and delay it for later.
>>
>> v2: -Moved the async check above vblank_get as it
>>       was causing issues for PSR.
>>
>> v3: -No need to wait for vblank to pass, as this wait was causing a
>>       16ms delay once every few flips.
>>
>> v4: -Rebased.
>>
>> v5: -Rebased.
>>
>> v6: -Rebased.
>>
>> v7: -No need of irq disable if we are not doing vblank evade. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index 5ac0dbf0e03d..f0c89418d2e1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>>   	DEFINE_WAIT(wait);
>>   	u32 psr_status;
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		return;
>> +
>>   	vblank_start = adjusted_mode->crtc_vblank_start;
>>   	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>>   		vblank_start = DIV_ROUND_UP(vblank_start, 2);
>> @@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>>   
>>   	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		return;
> 
> The pipe update tracepoints will be inconsistent if you put this here.
> I guess we don't really need the pipe update tracepoints for async
> flips. We might want to add a separate tracepoint for async flip itself,
> or perhaps convey the sync vs. async information via the current
> plane update tracepoint.
> 

Thanks for the review.
Sure, I'll move this before the tracepoint.

> With this moved to before the tracepoint
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 

Thanks for the RB.

Thanks,
Karthik.B.S
>> +
>>   	/* We're still in the vblank-evade critical section, this can't race.
>>   	 * Would be slightly nice to just grab the vblank count and arm the
>>   	 * event outside of the critical section - the spinlock might spin for a
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 4/8] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

On 9/15/2020 7:37 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:29AM +0530, Karthik B S wrote:
>> Since the flip done event will be sent in the flip_done_handler,
>> no need to add the event to the list and delay it for later.
>>
>> v2: -Moved the async check above vblank_get as it
>>       was causing issues for PSR.
>>
>> v3: -No need to wait for vblank to pass, as this wait was causing a
>>       16ms delay once every few flips.
>>
>> v4: -Rebased.
>>
>> v5: -Rebased.
>>
>> v6: -Rebased.
>>
>> v7: -No need of irq disable if we are not doing vblank evade. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index 5ac0dbf0e03d..f0c89418d2e1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>>   	DEFINE_WAIT(wait);
>>   	u32 psr_status;
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		return;
>> +
>>   	vblank_start = adjusted_mode->crtc_vblank_start;
>>   	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>>   		vblank_start = DIV_ROUND_UP(vblank_start, 2);
>> @@ -202,6 +205,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>>   
>>   	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		return;
> 
> The pipe update tracepoints will be inconsistent if you put this here.
> I guess we don't really need the pipe update tracepoints for async
> flips. We might want to add a separate tracepoint for async flip itself,
> or perhaps convey the sync vs. async information via the current
> plane update tracepoint.
> 

Thanks for the review.
Sure, I'll move this before the tracepoint.

> With this moved to before the tracepoint
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 

Thanks for the RB.

Thanks,
Karthik.B.S
>> +
>>   	/* We're still in the vblank-evade critical section, this can't race.
>>   	 * Would be slightly nice to just grab the vblank count and arm the
>>   	 * event outside of the critical section - the spinlock might spin for a
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/15/2020 7:40 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>> This hook is added to avoid writing other plane registers in case of
>> async flips, so that we do not write the double buffered registers
>> during async surface address update.
>>
>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>      -Add a vfunc for skl_program_async_surface_address
>>       and call it from intel_update_plane. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>   3 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 79032701873a..fdc633020255 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   
>>   	trace_intel_update_plane(&plane->base, crtc);
>> +
>> +	if (crtc_state->uapi.async_flip) {
>> +		plane->program_async_surface_address(plane,
>> +						     crtc_state, plane_state);
>> +		return;
>> +	}
> 
> if
> 	.async_flip()
> else
> 	.update_plane()
> 
> should do
> 

Thanks for the review.
Sure, I'll update this.
>> +
>>   	plane->update_plane(plane, crtc_state, plane_state);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b2d0edacc58c..d2ae781e4d81 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>   			   struct intel_plane_state *plane_state);
>>   	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>   			 const struct intel_plane_state *plane_state);
>> +	void (*program_async_surface_address)(struct intel_plane *plane,
> 
> That's a mouthful. I'd simplify it to eg. just .async_flip().
> 

Sure, I'll change the name.

Thanks,
Karthik.B.S
>> +					      const struct intel_crtc_state *crtc_state,
>> +					      const struct intel_plane_state *plane_state);
>>   };
>>   
>>   struct intel_watermark_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index f0c89418d2e1..69407dfcebf6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>   			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>   }
>>   
>> +static void
>> +skl_program_async_surface_address(struct intel_plane *plane,
>> +				  const struct intel_crtc_state *crtc_state,
>> +				  const struct intel_plane_state *plane_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> +	unsigned long irqflags;
>> +	enum plane_id plane_id = plane->id;
>> +	enum pipe pipe = plane->pipe;
>> +	u32 surf_addr = plane_state->color_plane[0].offset;
>> +	u32 plane_ctl = plane_state->ctl;
>> +
>> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +
>> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +}
>> +
>>   static void
>>   skl_program_plane(struct intel_plane *plane,
>>   		  const struct intel_crtc_state *crtc_state,
>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>   	plane->get_hw_state = skl_plane_get_hw_state;
>>   	plane->check_plane = skl_plane_check;
>>   	plane->min_cdclk = skl_plane_min_cdclk;
>> +	plane->program_async_surface_address = skl_program_async_surface_address;
>>   
>>   	if (INTEL_GEN(dev_priv) >= 11)
>>   		formats = icl_get_plane_formats(dev_priv, pipe,
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/15/2020 7:40 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>> This hook is added to avoid writing other plane registers in case of
>> async flips, so that we do not write the double buffered registers
>> during async surface address update.
>>
>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>      -Add a vfunc for skl_program_async_surface_address
>>       and call it from intel_update_plane. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>   3 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 79032701873a..fdc633020255 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   
>>   	trace_intel_update_plane(&plane->base, crtc);
>> +
>> +	if (crtc_state->uapi.async_flip) {
>> +		plane->program_async_surface_address(plane,
>> +						     crtc_state, plane_state);
>> +		return;
>> +	}
> 
> if
> 	.async_flip()
> else
> 	.update_plane()
> 
> should do
> 

Thanks for the review.
Sure, I'll update this.
>> +
>>   	plane->update_plane(plane, crtc_state, plane_state);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b2d0edacc58c..d2ae781e4d81 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>   			   struct intel_plane_state *plane_state);
>>   	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>   			 const struct intel_plane_state *plane_state);
>> +	void (*program_async_surface_address)(struct intel_plane *plane,
> 
> That's a mouthful. I'd simplify it to eg. just .async_flip().
> 

Sure, I'll change the name.

Thanks,
Karthik.B.S
>> +					      const struct intel_crtc_state *crtc_state,
>> +					      const struct intel_plane_state *plane_state);
>>   };
>>   
>>   struct intel_watermark_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index f0c89418d2e1..69407dfcebf6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>   			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>   }
>>   
>> +static void
>> +skl_program_async_surface_address(struct intel_plane *plane,
>> +				  const struct intel_crtc_state *crtc_state,
>> +				  const struct intel_plane_state *plane_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> +	unsigned long irqflags;
>> +	enum plane_id plane_id = plane->id;
>> +	enum pipe pipe = plane->pipe;
>> +	u32 surf_addr = plane_state->color_plane[0].offset;
>> +	u32 plane_ctl = plane_state->ctl;
>> +
>> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +
>> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +}
>> +
>>   static void
>>   skl_program_plane(struct intel_plane *plane,
>>   		  const struct intel_crtc_state *crtc_state,
>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>   	plane->get_hw_state = skl_plane_get_hw_state;
>>   	plane->check_plane = skl_plane_check;
>>   	plane->min_cdclk = skl_plane_min_cdclk;
>> +	plane->program_async_surface_address = skl_program_async_surface_address;
>>   
>>   	if (INTEL_GEN(dev_priv) >= 11)
>>   		formats = icl_get_plane_formats(dev_priv, pipe,
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Karthik B S]

On 9/15/2020 7:49 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:31AM +0530, Karthik B S wrote:
>> In Gen 9 and Gen 10 platforms, async address update enable bit is
>> double buffered. Due to this, during the transition from async flip
>> to sync flip we have to wait until this bit is updated before continuing
>> with the normal commit for sync flip.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
>>   1 file changed, 44 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index a0c17d94daf3..b7e24dff0772 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>>   	intel_crtc_enable_pipe_crc(crtc);
>>   }
>>   
>> +static void skl_toggle_async_sync(struct intel_atomic_state *state,
> 
> skl_disable_async_flip_wa() maybe?
> 

Thanks for the review.
I'll change the name.
>> +				  struct intel_crtc *crtc,
>> +				  struct intel_crtc_state *new_crtc_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> +	struct intel_plane *plane;
>> +	struct intel_plane_state *new_plane_state;
>> +	u32 update_mask = new_crtc_state->update_planes;
>> +	u32 plane_ctl, surf_addr;
>> +	enum plane_id plane_id;
>> +	unsigned long irqflags;
>> +	enum pipe pipe;
> 
> Most of these things are only needed within the loop, so that's where
> the declarations should be.
> 

Sure, I'll move it inside the loop.
>> +	int i;
>> +
>> +	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
>> +		if (crtc->pipe != plane->pipe ||
>> +		    !(update_mask & BIT(plane->id)))
>> +			continue;
>> +
>> +		plane_id = plane->id;
>> +		pipe = plane->pipe;
>> +
> 
> I'd take the lock here so the rmw is fully protected.
> 

Sure, I'll move it here.
>> +		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
>> +		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
>> +
>> +		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
>> +
>> +		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
>> +		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +	}
>> +
>> +	intel_wait_for_vblank(dev_priv, crtc->pipe);
>> +}
>> +
>>   static void intel_update_crtc(struct intel_atomic_state *state,
>>   			      struct intel_crtc *crtc)
>>   {
>> @@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>>   	else
>>   		intel_fbc_enable(state, crtc);
>>   
>> +	/* WA for older platforms where async address update enable bit
> 
> s/older//
> 

Noted.
>> +	 * is double buffered.
> 
> "is double buffered and only latched at start of vblank" or
> something. Otherwise one is left wondering what the fuss is about.
> 

Sure, I'll update this.
>> +	 */
> 
> Multiline comment format should be
> /*
>   * blah
>   * blah
>   */
> 

I'll fix this.
>> +	if (old_crtc_state->uapi.async_flip &&
>> +	    !new_crtc_state->uapi.async_flip &&
>> +	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
> 
> IS_GEN_RANGE(9, 10) or whatever it's called.
> 

Sure, I'll update this.
> I guess we might want to put this call into intel_pre_plane_update()
> since that's where all kinds of similar wait_for_vblank w/as live.
> 

Sure, I'll move this to intel_pre_plane_update()

Thanks,
Karthik.B.S
>> +		skl_toggle_async_sync(state, crtc, new_crtc_state);
>> +
>>   	/* Perform vblank evasion around commit operation */
>>   	intel_pipe_update_start(new_crtc_state);
>>   
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 6/8] drm/i915: WA for platforms with double buffered adress update enable bit

[Karthik B S]

On 9/15/2020 7:49 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:31AM +0530, Karthik B S wrote:
>> In Gen 9 and Gen 10 platforms, async address update enable bit is
>> double buffered. Due to this, during the transition from async flip
>> to sync flip we have to wait until this bit is updated before continuing
>> with the normal commit for sync flip.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++++++++++++
>>   1 file changed, 44 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index a0c17d94daf3..b7e24dff0772 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15360,6 +15360,42 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>>   	intel_crtc_enable_pipe_crc(crtc);
>>   }
>>   
>> +static void skl_toggle_async_sync(struct intel_atomic_state *state,
> 
> skl_disable_async_flip_wa() maybe?
> 

Thanks for the review.
I'll change the name.
>> +				  struct intel_crtc *crtc,
>> +				  struct intel_crtc_state *new_crtc_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> +	struct intel_plane *plane;
>> +	struct intel_plane_state *new_plane_state;
>> +	u32 update_mask = new_crtc_state->update_planes;
>> +	u32 plane_ctl, surf_addr;
>> +	enum plane_id plane_id;
>> +	unsigned long irqflags;
>> +	enum pipe pipe;
> 
> Most of these things are only needed within the loop, so that's where
> the declarations should be.
> 

Sure, I'll move it inside the loop.
>> +	int i;
>> +
>> +	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
>> +		if (crtc->pipe != plane->pipe ||
>> +		    !(update_mask & BIT(plane->id)))
>> +			continue;
>> +
>> +		plane_id = plane->id;
>> +		pipe = plane->pipe;
>> +
> 
> I'd take the lock here so the rmw is fully protected.
> 

Sure, I'll move it here.
>> +		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
>> +		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
>> +
>> +		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
>> +
>> +		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
>> +		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +	}
>> +
>> +	intel_wait_for_vblank(dev_priv, crtc->pipe);
>> +}
>> +
>>   static void intel_update_crtc(struct intel_atomic_state *state,
>>   			      struct intel_crtc *crtc)
>>   {
>> @@ -15387,6 +15423,14 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>>   	else
>>   		intel_fbc_enable(state, crtc);
>>   
>> +	/* WA for older platforms where async address update enable bit
> 
> s/older//
> 

Noted.
>> +	 * is double buffered.
> 
> "is double buffered and only latched at start of vblank" or
> something. Otherwise one is left wondering what the fuss is about.
> 

Sure, I'll update this.
>> +	 */
> 
> Multiline comment format should be
> /*
>   * blah
>   * blah
>   */
> 

I'll fix this.
>> +	if (old_crtc_state->uapi.async_flip &&
>> +	    !new_crtc_state->uapi.async_flip &&
>> +	    INTEL_GEN(dev_priv) <= 10 && INTEL_GEN(dev_priv) >= 9)
> 
> IS_GEN_RANGE(9, 10) or whatever it's called.
> 

Sure, I'll update this.
> I guess we might want to put this call into intel_pre_plane_update()
> since that's where all kinds of similar wait_for_vblank w/as live.
> 

Sure, I'll move this to intel_pre_plane_update()

Thanks,
Karthik.B.S
>> +		skl_toggle_async_sync(state, crtc, new_crtc_state);
>> +
>>   	/* Perform vblank evasion around commit operation */
>>   	intel_pipe_update_start(new_crtc_state);
>>   
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>> This hook is added to avoid writing other plane registers in case of
>> async flips, so that we do not write the double buffered registers
>> during async surface address update.
>>
>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>      -Add a vfunc for skl_program_async_surface_address
>>       and call it from intel_update_plane. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>   3 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 79032701873a..fdc633020255 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   
>>   	trace_intel_update_plane(&plane->base, crtc);
>> +
>> +	if (crtc_state->uapi.async_flip) {
> 
> Hmm. Now I'm starting to wonder how this is actually going to interact
> with legacy cursor updates. The crtc_state we use there I think comes
> from the previous update and so will have this flag set it if was an
> async flip. Which means the cursor ioctl will oops.
> 
> We may want the igt to check this particular combination of ioctls
> actually.
> 

I tried this out locally by using the DRM_IOCTL_MODE_CURSOR ioctl after 
an async flip. And looks like its working fine. During the cursor commit 
it actually takes the 'else' path.

I'll send out the new version of the IGT shortly with this subtest 
added. Please let me know if I'm missing something there.

Thanks,
Karthik.B.S
>> +		plane->program_async_surface_address(plane,
>> +						     crtc_state, plane_state);
>> +		return;
>> +	}
>> +
>>   	plane->update_plane(plane, crtc_state, plane_state);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b2d0edacc58c..d2ae781e4d81 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>   			   struct intel_plane_state *plane_state);
>>   	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>   			 const struct intel_plane_state *plane_state);
>> +	void (*program_async_surface_address)(struct intel_plane *plane,
>> +					      const struct intel_crtc_state *crtc_state,
>> +					      const struct intel_plane_state *plane_state);
>>   };
>>   
>>   struct intel_watermark_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index f0c89418d2e1..69407dfcebf6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>   			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>   }
>>   
>> +static void
>> +skl_program_async_surface_address(struct intel_plane *plane,
>> +				  const struct intel_crtc_state *crtc_state,
>> +				  const struct intel_plane_state *plane_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> +	unsigned long irqflags;
>> +	enum plane_id plane_id = plane->id;
>> +	enum pipe pipe = plane->pipe;
>> +	u32 surf_addr = plane_state->color_plane[0].offset;
>> +	u32 plane_ctl = plane_state->ctl;
>> +
>> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +
>> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +}
>> +
>>   static void
>>   skl_program_plane(struct intel_plane *plane,
>>   		  const struct intel_crtc_state *crtc_state,
>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>   	plane->get_hw_state = skl_plane_get_hw_state;
>>   	plane->check_plane = skl_plane_check;
>>   	plane->min_cdclk = skl_plane_min_cdclk;
>> +	plane->program_async_surface_address = skl_program_async_surface_address;
>>   
>>   	if (INTEL_GEN(dev_priv) >= 11)
>>   		formats = icl_get_plane_formats(dev_priv, pipe,
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>> This hook is added to avoid writing other plane registers in case of
>> async flips, so that we do not write the double buffered registers
>> during async surface address update.
>>
>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>      -Add a vfunc for skl_program_async_surface_address
>>       and call it from intel_update_plane. (Ville)
>>
>> v8: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>   3 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 79032701873a..fdc633020255 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>   
>>   	trace_intel_update_plane(&plane->base, crtc);
>> +
>> +	if (crtc_state->uapi.async_flip) {
> 
> Hmm. Now I'm starting to wonder how this is actually going to interact
> with legacy cursor updates. The crtc_state we use there I think comes
> from the previous update and so will have this flag set it if was an
> async flip. Which means the cursor ioctl will oops.
> 
> We may want the igt to check this particular combination of ioctls
> actually.
> 

I tried this out locally by using the DRM_IOCTL_MODE_CURSOR ioctl after 
an async flip. And looks like its working fine. During the cursor commit 
it actually takes the 'else' path.

I'll send out the new version of the IGT shortly with this subtest 
added. Please let me know if I'm missing something there.

Thanks,
Karthik.B.S
>> +		plane->program_async_surface_address(plane,
>> +						     crtc_state, plane_state);
>> +		return;
>> +	}
>> +
>>   	plane->update_plane(plane, crtc_state, plane_state);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b2d0edacc58c..d2ae781e4d81 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>   			   struct intel_plane_state *plane_state);
>>   	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>   			 const struct intel_plane_state *plane_state);
>> +	void (*program_async_surface_address)(struct intel_plane *plane,
>> +					      const struct intel_crtc_state *crtc_state,
>> +					      const struct intel_plane_state *plane_state);
>>   };
>>   
>>   struct intel_watermark_params {
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index f0c89418d2e1..69407dfcebf6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>   			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>   }
>>   
>> +static void
>> +skl_program_async_surface_address(struct intel_plane *plane,
>> +				  const struct intel_crtc_state *crtc_state,
>> +				  const struct intel_plane_state *plane_state)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>> +	unsigned long irqflags;
>> +	enum plane_id plane_id = plane->id;
>> +	enum pipe pipe = plane->pipe;
>> +	u32 surf_addr = plane_state->color_plane[0].offset;
>> +	u32 plane_ctl = plane_state->ctl;
>> +
>> +	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +
>> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +}
>> +
>>   static void
>>   skl_program_plane(struct intel_plane *plane,
>>   		  const struct intel_crtc_state *crtc_state,
>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>>   	plane->get_hw_state = skl_plane_get_hw_state;
>>   	plane->check_plane = skl_plane_check;
>>   	plane->min_cdclk = skl_plane_min_cdclk;
>> +	plane->program_async_surface_address = skl_program_async_surface_address;
>>   
>>   	if (INTEL_GEN(dev_priv) >= 11)
>>   		formats = icl_get_plane_formats(dev_priv, pipe,
>> -- 
>> 2.22.0
> 
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Re: [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/16/2020 6:30 PM, Karthik B S wrote:
> 
> 
> On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
>> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>>> This hook is added to avoid writing other plane registers in case of
>>> async flips, so that we do not write the double buffered registers
>>> during async surface address update.
>>>
>>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>>      -Add a vfunc for skl_program_async_surface_address
>>>       and call it from intel_update_plane. (Ville)
>>>
>>> v8: -Rebased.
>>>
>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>> ---
>>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>>   3 files changed, 34 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> index 79032701873a..fdc633020255 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>       trace_intel_update_plane(&plane->base, crtc);
>>> +
>>> +    if (crtc_state->uapi.async_flip) {
>>
>> Hmm. Now I'm starting to wonder how this is actually going to interact
>> with legacy cursor updates. The crtc_state we use there I think comes
>> from the previous update and so will have this flag set it if was an
>> async flip. Which means the cursor ioctl will oops.
>>
>> We may want the igt to check this particular combination of ioctls
>> actually.
>>
> 
> I tried this out locally by using the DRM_IOCTL_MODE_CURSOR ioctl after 
> an async flip. And looks like its working fine. During the cursor commit 
> it actually takes the 'else' path.
> 
> I'll send out the new version of the IGT shortly with this subtest 
> added. Please let me know if I'm missing something there.
> 

I've pushed the IGT with the cursor subtest added.
https://patchwork.freedesktop.org/series/79701/

Thanks,
Karthik.B.S
> Thanks,
> Karthik.B.S
>>> +        plane->program_async_surface_address(plane,
>>> +                             crtc_state, plane_state);
>>> +        return;
>>> +    }
>>> +
>>>       plane->update_plane(plane, crtc_state, plane_state);
>>>   }
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index b2d0edacc58c..d2ae781e4d81 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>>                  struct intel_plane_state *plane_state);
>>>       int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>>                const struct intel_plane_state *plane_state);
>>> +    void (*program_async_surface_address)(struct intel_plane *plane,
>>> +                          const struct intel_crtc_state *crtc_state,
>>> +                          const struct intel_plane_state *plane_state);
>>>   };
>>>   struct intel_watermark_params {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
>>> b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> index f0c89418d2e1..69407dfcebf6 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>>                 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>>   }
>>> +static void
>>> +skl_program_async_surface_address(struct intel_plane *plane,
>>> +                  const struct intel_crtc_state *crtc_state,
>>> +                  const struct intel_plane_state *plane_state)
>>> +{
>>> +    struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>>> +    unsigned long irqflags;
>>> +    enum plane_id plane_id = plane->id;
>>> +    enum pipe pipe = plane->pipe;
>>> +    u32 surf_addr = plane_state->color_plane[0].offset;
>>> +    u32 plane_ctl = plane_state->ctl;
>>> +
>>> +    plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>>> +
>>> +    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>>> +
>>> +    intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>>> +    intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>>> +              intel_plane_ggtt_offset(plane_state) + surf_addr);
>>> +
>>> +    spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>>> +}
>>> +
>>>   static void
>>>   skl_program_plane(struct intel_plane *plane,
>>>             const struct intel_crtc_state *crtc_state,
>>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct 
>>> drm_i915_private *dev_priv,
>>>       plane->get_hw_state = skl_plane_get_hw_state;
>>>       plane->check_plane = skl_plane_check;
>>>       plane->min_cdclk = skl_plane_min_cdclk;
>>> +    plane->program_async_surface_address = 
>>> skl_program_async_surface_address;
>>>       if (INTEL_GEN(dev_priv) >= 11)
>>>           formats = icl_get_plane_formats(dev_priv, pipe,
>>> -- 
>>> 2.22.0
>>
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Re: [Intel-gfx] [PATCH v8 5/8] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/16/2020 6:30 PM, Karthik B S wrote:
> 
> 
> On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
>> On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
>>> This hook is added to avoid writing other plane registers in case of
>>> async flips, so that we do not write the double buffered registers
>>> during async surface address update.
>>>
>>> v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
>>>      -Add a vfunc for skl_program_async_surface_address
>>>       and call it from intel_update_plane. (Ville)
>>>
>>> v8: -Rebased.
>>>
>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>>> ---
>>>   .../gpu/drm/i915/display/intel_atomic_plane.c |  7 ++++++
>>>   .../drm/i915/display/intel_display_types.h    |  3 +++
>>>   drivers/gpu/drm/i915/display/intel_sprite.c   | 24 +++++++++++++++++++
>>>   3 files changed, 34 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> index 79032701873a..fdc633020255 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>> @@ -408,6 +408,13 @@ void intel_update_plane(struct intel_plane *plane,
>>>       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>>>       trace_intel_update_plane(&plane->base, crtc);
>>> +
>>> +    if (crtc_state->uapi.async_flip) {
>>
>> Hmm. Now I'm starting to wonder how this is actually going to interact
>> with legacy cursor updates. The crtc_state we use there I think comes
>> from the previous update and so will have this flag set it if was an
>> async flip. Which means the cursor ioctl will oops.
>>
>> We may want the igt to check this particular combination of ioctls
>> actually.
>>
> 
> I tried this out locally by using the DRM_IOCTL_MODE_CURSOR ioctl after 
> an async flip. And looks like its working fine. During the cursor commit 
> it actually takes the 'else' path.
> 
> I'll send out the new version of the IGT shortly with this subtest 
> added. Please let me know if I'm missing something there.
> 

I've pushed the IGT with the cursor subtest added.
https://patchwork.freedesktop.org/series/79701/

Thanks,
Karthik.B.S
> Thanks,
> Karthik.B.S
>>> +        plane->program_async_surface_address(plane,
>>> +                             crtc_state, plane_state);
>>> +        return;
>>> +    }
>>> +
>>>       plane->update_plane(plane, crtc_state, plane_state);
>>>   }
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index b2d0edacc58c..d2ae781e4d81 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1190,6 +1190,9 @@ struct intel_plane {
>>>                  struct intel_plane_state *plane_state);
>>>       int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
>>>                const struct intel_plane_state *plane_state);
>>> +    void (*program_async_surface_address)(struct intel_plane *plane,
>>> +                          const struct intel_crtc_state *crtc_state,
>>> +                          const struct intel_plane_state *plane_state);
>>>   };
>>>   struct intel_watermark_params {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
>>> b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> index f0c89418d2e1..69407dfcebf6 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>> @@ -609,6 +609,29 @@ icl_program_input_csc(struct intel_plane *plane,
>>>                 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>>   }
>>> +static void
>>> +skl_program_async_surface_address(struct intel_plane *plane,
>>> +                  const struct intel_crtc_state *crtc_state,
>>> +                  const struct intel_plane_state *plane_state)
>>> +{
>>> +    struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>>> +    unsigned long irqflags;
>>> +    enum plane_id plane_id = plane->id;
>>> +    enum pipe pipe = plane->pipe;
>>> +    u32 surf_addr = plane_state->color_plane[0].offset;
>>> +    u32 plane_ctl = plane_state->ctl;
>>> +
>>> +    plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>>> +
>>> +    spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>>> +
>>> +    intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>>> +    intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>>> +              intel_plane_ggtt_offset(plane_state) + surf_addr);
>>> +
>>> +    spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>>> +}
>>> +
>>>   static void
>>>   skl_program_plane(struct intel_plane *plane,
>>>             const struct intel_crtc_state *crtc_state,
>>> @@ -3096,6 +3119,7 @@ skl_universal_plane_create(struct 
>>> drm_i915_private *dev_priv,
>>>       plane->get_hw_state = skl_plane_get_hw_state;
>>>       plane->check_plane = skl_plane_check;
>>>       plane->min_cdclk = skl_plane_min_cdclk;
>>> +    plane->program_async_surface_address = 
>>> skl_program_async_surface_address;
>>>       if (INTEL_GEN(dev_priv) >= 11)
>>>           formats = icl_get_plane_formats(dev_priv, pipe,
>>> -- 
>>> 2.22.0
>>
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