* [PATCH 0/1] Add Zihintpause support
@ 2022-05-10 6:42 Dao Lu
2022-05-10 6:42 ` [PATCH 1/1] " Dao Lu
0 siblings, 1 reply; 7+ messages in thread
From: Dao Lu @ 2022-05-10 6:42 UTC (permalink / raw)
To: qemu-devel
Cc: Dao Lu, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V TCG CPUs
This patch adds RISC-V Zihintpause support. The extension is set to be enabled
by default and opcode has been added to insn32.decode.
Added trans_pause for TCG to mainly be a no-op and break reservation.
The change can also be found in:
https://github.com/dlu42/qemu/tree/zihintpause_support_v1
Tested along with pause support added to cpu_relax function for linux, the
changes I made to linux to test can be found here:
https://github.com/dlu42/linux/tree/pause_support_v1
Dao Lu (1):
Add Zihintpause support
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++++++-
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
4 files changed, 27 insertions(+), 1 deletion(-)
--
2.36.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/1] Add Zihintpause support
2022-05-10 6:42 [PATCH 0/1] Add Zihintpause support Dao Lu
@ 2022-05-10 6:42 ` Dao Lu
2022-05-10 15:43 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Dao Lu @ 2022-05-10 6:42 UTC (permalink / raw)
To: qemu-devel
Cc: Dao Lu, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V TCG CPUs
Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld
by default.
Signed-off-by: Dao Lu <daolu@rivosinc.com>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++++++-
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
4 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee215..183fb37fdf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
@@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
* extensions by an underscore.
*/
struct isa_ext_data isa_edata_arr[] = {
+ ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
ISA_EDATA_ENTRY(zfh, ext_zfh),
ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
ISA_EDATA_ENTRY(zfinx, ext_zfinx),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe6c9a2c92..e466a04a59 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -394,6 +394,7 @@ struct RISCVCPUConfig {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_zihintpause;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4033565393..595fdcdad8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
-fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+
+{
+ pause 0000 0001 0000 00000 000 00000 0001111
+ fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+}
+
fence_i ---- ---- ---- ----- 001 ----- 0001111
csrrw ............ ..... 001 ..... 1110011 @csr
csrrs ............ ..... 010 ..... 1110011 @csr
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index f1342f30f8..528c30c9a2 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -18,6 +18,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_ZIHINTPAUSE(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zihintpause) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_illegal(DisasContext *ctx, arg_empty *a)
{
gen_exception_illegal(ctx);
@@ -796,6 +802,18 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
}
+static bool trans_pause(DisasContext *ctx, arg_pause *a)
+{
+ REQUIRE_ZIHINTPAUSE(ctx);
+
+ /*
+ * PAUSE is a no-op in QEMU,
+ * however we need to clear the reservation
+ */
+ tcg_gen_movi_tl(load_res, -1);
+
+ return true;
+}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
--
2.36.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] Add Zihintpause support
2022-05-10 6:42 ` [PATCH 1/1] " Dao Lu
@ 2022-05-10 15:43 ` Richard Henderson
2022-05-10 17:42 ` Dao Lu
2022-05-12 10:51 ` Heiko Stübner
2022-05-12 12:20 ` Tsukasa OI
2 siblings, 1 reply; 7+ messages in thread
From: Richard Henderson @ 2022-05-10 15:43 UTC (permalink / raw)
To: Dao Lu, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs
On 5/9/22 23:42, Dao Lu wrote:
> +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> +{
> + REQUIRE_ZIHINTPAUSE(ctx);
> +
> + /*
> + * PAUSE is a no-op in QEMU,
> + * however we need to clear the reservation
> + */
> + tcg_gen_movi_tl(load_res, -1);
I recommend ending the TB and returning to the main loop. When running in round-robin
mode, this will yield to the next cpu.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] Add Zihintpause support
2022-05-10 15:43 ` Richard Henderson
@ 2022-05-10 17:42 ` Dao Lu
0 siblings, 0 replies; 7+ messages in thread
From: Dao Lu @ 2022-05-10 17:42 UTC (permalink / raw)
To: Richard Henderson
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V TCG CPUs
[-- Attachment #1: Type: text/plain, Size: 1318 bytes --]
Thanks Richard! I have fixed it following your advice:
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 528c30c9a2..acd2548e9b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -808,9 +808,13 @@ static bool trans_pause(DisasContext *ctx, arg_pause
*a)
/*
* PAUSE is a no-op in QEMU,
- * however we need to clear the reservation
+ * however we need to clear the reservation,
+ * end the TB and return to main loop
*/
tcg_gen_movi_tl(load_res, -1);
+ gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
I will wait a bit to see if there are any more comments.
On Tue, May 10, 2022 at 8:43 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 5/9/22 23:42, Dao Lu wrote:
> > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > +{
> > + REQUIRE_ZIHINTPAUSE(ctx);
> > +
> > + /*
> > + * PAUSE is a no-op in QEMU,
> > + * however we need to clear the reservation
> > + */
> > + tcg_gen_movi_tl(load_res, -1);
>
> I recommend ending the TB and returning to the main loop. When running in
> round-robin
> mode, this will yield to the next cpu.
>
>
> r~
>
[-- Attachment #2: Type: text/html, Size: 1836 bytes --]
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] Add Zihintpause support
2022-05-10 6:42 ` [PATCH 1/1] " Dao Lu
2022-05-10 15:43 ` Richard Henderson
@ 2022-05-12 10:51 ` Heiko Stübner
2022-05-12 12:20 ` Tsukasa OI
2 siblings, 0 replies; 7+ messages in thread
From: Heiko Stübner @ 2022-05-12 10:51 UTC (permalink / raw)
To: qemu-devel
Cc: Dao Lu, Palmer Dabbelt, Alistair Francis, Bin Meng,
open list:RISC-V TCG CPUs, Dao Lu
Am Dienstag, 10. Mai 2022, 08:42:31 CEST schrieb Dao Lu:
> Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld
> by default.
>
> Signed-off-by: Dao Lu <daolu@rivosinc.com>
This patch with your fixup applied to it and of course
a matching kernel:
Tested-by: Heiko Stuebner <heiko@sntech.de>
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++++++-
> target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> 4 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..183fb37fdf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> * extensions by an underscore.
> */
> struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> ISA_EDATA_ENTRY(zfh, ext_zfh),
> ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fe6c9a2c92..e466a04a59 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zihintpause;
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 4033565393..595fdcdad8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> sra 0100000 ..... ..... 101 ..... 0110011 @r
> or 0000000 ..... ..... 110 ..... 0110011 @r
> and 0000000 ..... ..... 111 ..... 0110011 @r
> -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +
> +{
> + pause 0000 0001 0000 00000 000 00000 0001111
> + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +}
> +
> fence_i ---- ---- ---- ----- 001 ----- 0001111
> csrrw ............ ..... 001 ..... 1110011 @csr
> csrrs ............ ..... 010 ..... 1110011 @csr
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..528c30c9a2 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -18,6 +18,12 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#define REQUIRE_ZIHINTPAUSE(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zihintpause) { \
> + return false; \
> + } \
> +} while (0)
> +
> static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> {
> gen_exception_illegal(ctx);
> @@ -796,6 +802,18 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> }
>
> +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> +{
> + REQUIRE_ZIHINTPAUSE(ctx);
> +
> + /*
> + * PAUSE is a no-op in QEMU,
> + * however we need to clear the reservation
> + */
> + tcg_gen_movi_tl(load_res, -1);
> +
> + return true;
> +}
>
> static bool trans_fence(DisasContext *ctx, arg_fence *a)
> {
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] Add Zihintpause support
2022-05-10 6:42 ` [PATCH 1/1] " Dao Lu
2022-05-10 15:43 ` Richard Henderson
2022-05-12 10:51 ` Heiko Stübner
@ 2022-05-12 12:20 ` Tsukasa OI
2022-05-12 17:57 ` Dao Lu
2 siblings, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2022-05-12 12:20 UTC (permalink / raw)
To: Dao Lu
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs
On 2022/05/10 15:42, Dao Lu wrote:
> Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld
> by default.
>
> Signed-off-by: Dao Lu <daolu@rivosinc.com>
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 7 ++++++-
> target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> 4 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..183fb37fdf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
This is not your fault but mixed upper camel case and lower case is not a
good situation (e.g. "Zihintpause" and "zba"). I will raise a separate
issue on qemu-riscv mailing list (no changes requested).
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> * extensions by an underscore.
> */
> struct isa_ext_data isa_edata_arr[] = {
> + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> ISA_EDATA_ENTRY(zfh, ext_zfh),
> ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fe6c9a2c92..e466a04a59 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zihintpause;
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 4033565393..595fdcdad8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> sra 0100000 ..... ..... 101 ..... 0110011 @r
> or 0000000 ..... ..... 110 ..... 0110011 @r
> and 0000000 ..... ..... 111 ..... 0110011 @r
> -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +
> +{
> + pause 0000 0001 0000 00000 000 00000 0001111
> + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> +}
> +
> fence_i ---- ---- ---- ----- 001 ----- 0001111
> csrrw ............ ..... 001 ..... 1110011 @csr
> csrrs ............ ..... 010 ..... 1110011 @csr
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index f1342f30f8..528c30c9a2 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -18,6 +18,12 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#define REQUIRE_ZIHINTPAUSE(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zihintpause) { \
> + return false; \
> + } \
> +} while (0)
I think this macro is too much for one instruction. How about expanding
this on `trans_pause' function like `trans_fence_i'?
Other than that, it LGTM.
Tsukasa,
> +
> static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> {
> gen_exception_illegal(ctx);
> @@ -796,6 +802,18 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> }
>
> +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> +{
> + REQUIRE_ZIHINTPAUSE(ctx);
> +
> + /*
> + * PAUSE is a no-op in QEMU,
> + * however we need to clear the reservation
> + */
> + tcg_gen_movi_tl(load_res, -1);
> +
> + return true;
> +}
>
> static bool trans_fence(DisasContext *ctx, arg_fence *a)
> {
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] Add Zihintpause support
2022-05-12 12:20 ` Tsukasa OI
@ 2022-05-12 17:57 ` Dao Lu
0 siblings, 0 replies; 7+ messages in thread
From: Dao Lu @ 2022-05-12 17:57 UTC (permalink / raw)
To: Tsukasa OI
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V TCG CPUs
Thanks to Heiko and Tsukasa.
I have made the following changes:
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index acd2548e9b..ca75e05f4b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -18,12 +18,6 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#define REQUIRE_ZIHINTPAUSE(ctx) do { \
- if (!ctx->cfg_ptr->ext_zihintpause) { \
- return false; \
- } \
-} while (0)
-
static bool trans_illegal(DisasContext *ctx, arg_empty *a)
{
gen_exception_illegal(ctx);
@@ -804,7 +798,9 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
static bool trans_pause(DisasContext *ctx, arg_pause *a)
{
- REQUIRE_ZIHINTPAUSE(ctx);
+ if (!ctx->cfg_ptr->ext_zihintpause) {
+ return false;
+ }
/*
* PAUSE is a no-op in QEMU,
On Thu, May 12, 2022 at 5:20 AM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> On 2022/05/10 15:42, Dao Lu wrote:
> > Added support for RISC-V PAUSE instruction from Zihintpause extension, enabeld
> > by default.
> >
> > Signed-off-by: Dao Lu <daolu@rivosinc.com>
> > ---
> > target/riscv/cpu.c | 2 ++
> > target/riscv/cpu.h | 1 +
> > target/riscv/insn32.decode | 7 ++++++-
> > target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++
> > 4 files changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index ccacdee215..183fb37fdf 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -825,6 +825,7 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> > + DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
>
> This is not your fault but mixed upper camel case and lower case is not a
> good situation (e.g. "Zihintpause" and "zba"). I will raise a separate
> issue on qemu-riscv mailing list (no changes requested).
>
>
> > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> > DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> > DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
> > @@ -996,6 +997,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
> > * extensions by an underscore.
> > */
> > struct isa_ext_data isa_edata_arr[] = {
> > + ISA_EDATA_ENTRY(zihintpause, ext_zihintpause),
> > ISA_EDATA_ENTRY(zfh, ext_zfh),
> > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
> > ISA_EDATA_ENTRY(zfinx, ext_zfinx),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index fe6c9a2c92..e466a04a59 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -394,6 +394,7 @@ struct RISCVCPUConfig {
> > bool ext_counters;
> > bool ext_ifencei;
> > bool ext_icsr;
> > + bool ext_zihintpause;
> > bool ext_svinval;
> > bool ext_svnapot;
> > bool ext_svpbmt;
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index 4033565393..595fdcdad8 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
> > sra 0100000 ..... ..... 101 ..... 0110011 @r
> > or 0000000 ..... ..... 110 ..... 0110011 @r
> > and 0000000 ..... ..... 111 ..... 0110011 @r
> > -fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > +
> > +{
> > + pause 0000 0001 0000 00000 000 00000 0001111
> > + fence ---- pred:4 succ:4 ----- 000 ----- 0001111
> > +}
> > +
> > fence_i ---- ---- ---- ----- 001 ----- 0001111
> > csrrw ............ ..... 001 ..... 1110011 @csr
> > csrrs ............ ..... 010 ..... 1110011 @csr
> > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> > index f1342f30f8..528c30c9a2 100644
> > --- a/target/riscv/insn_trans/trans_rvi.c.inc
> > +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> > @@ -18,6 +18,12 @@
> > * this program. If not, see <http://www.gnu.org/licenses/>.
> > */
> >
> > +#define REQUIRE_ZIHINTPAUSE(ctx) do { \
> > + if (!ctx->cfg_ptr->ext_zihintpause) { \
> > + return false; \
> > + } \
> > +} while (0)
>
> I think this macro is too much for one instruction. How about expanding
> this on `trans_pause' function like `trans_fence_i'?
>
> Other than that, it LGTM.
>
> Tsukasa,
>
> > +
> > static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> > {
> > gen_exception_illegal(ctx);
> > @@ -796,6 +802,18 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
> > return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
> > }
> >
> > +static bool trans_pause(DisasContext *ctx, arg_pause *a)
> > +{
> > + REQUIRE_ZIHINTPAUSE(ctx);
> > +
> > + /*
> > + * PAUSE is a no-op in QEMU,
> > + * however we need to clear the reservation
> > + */
> > + tcg_gen_movi_tl(load_res, -1);
> > +
> > + return true;
> > +}
> >
> > static bool trans_fence(DisasContext *ctx, arg_fence *a)
> > {
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-05-12 17:58 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 6:42 [PATCH 0/1] Add Zihintpause support Dao Lu
2022-05-10 6:42 ` [PATCH 1/1] " Dao Lu
2022-05-10 15:43 ` Richard Henderson
2022-05-10 17:42 ` Dao Lu
2022-05-12 10:51 ` Heiko Stübner
2022-05-12 12:20 ` Tsukasa OI
2022-05-12 17:57 ` Dao Lu
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