From: Geert Uytterhoeven <geert@linux-m68k.org> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Rob Herring <robh+dt@kernel.org>, Damien Le Moal <damien.lemoal@wdc.com>, Lewis Hanly <lewis.hanly@microchip.com>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Conor Dooley <conor.dooley@microchip.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Date: Thu, 16 Dec 2021 14:37:33 +0100 [thread overview] Message-ID: <405f7ebe588e269ffd428b818c0ff1f472a00ea8.1639660956.git.geert@linux-m68k.org> (raw) In-Reply-To: <cover.1639660956.git.geert@linux-m68k.org> To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0caca0ccf6711ded..e2efcf08210926f8 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert@linux-m68k.org> To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Rob Herring <robh+dt@kernel.org>, Damien Le Moal <damien.lemoal@wdc.com>, Lewis Hanly <lewis.hanly@microchip.com>, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>, Conor Dooley <conor.dooley@microchip.com>, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven <geert@linux-m68k.org> Subject: [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Date: Thu, 16 Dec 2021 14:37:33 +0100 [thread overview] Message-ID: <405f7ebe588e269ffd428b818c0ff1f472a00ea8.1639660956.git.geert@linux-m68k.org> (raw) In-Reply-To: <cover.1639660956.git.geert@linux-m68k.org> To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- v2: - Add Reviewed-by. --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 0caca0ccf6711ded..e2efcf08210926f8 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>; @@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>, -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-16 13:37 UTC|newest] Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-08 10:40 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Biju Das 2021-12-16 13:43 ` Geert Uytterhoeven 2021-12-16 13:43 ` Geert Uytterhoeven 2021-12-16 13:41 ` Geert Uytterhoeven 2021-12-16 13:41 ` Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-08 10:40 ` Biju Das 2021-12-08 10:40 ` [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Biju Das 2021-12-08 10:40 ` Biju Das 2021-12-10 14:44 ` Biju Das 2021-12-10 14:44 ` Biju Das 2021-12-14 19:21 ` Rob Herring 2021-12-14 19:21 ` Rob Herring 2021-12-14 19:31 ` Biju Das 2021-12-14 19:31 ` Biju Das 2021-12-13 16:46 ` Steven Price 2021-12-13 16:46 ` Steven Price 2021-12-14 19:25 ` Rob Herring 2021-12-14 19:25 ` Rob Herring 2021-12-08 10:40 ` [PATCH v3 2/3] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das 2021-12-08 10:40 ` [PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das 2021-12-16 13:46 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven 2021-12-16 13:46 ` Geert Uytterhoeven 2021-12-16 13:46 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 14:00 ` Daniel Stone 2021-12-16 14:00 ` Daniel Stone 2021-12-16 14:02 ` Biju Das 2021-12-16 14:02 ` Biju Das 2021-12-15 15:46 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Miquel Raynal 2021-12-16 13:43 ` Geert Uytterhoeven 2021-12-16 13:43 ` Geert Uytterhoeven 2021-12-16 13:41 ` Geert Uytterhoeven 2021-12-16 13:41 ` Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-15 15:46 ` Miquel Raynal 2021-12-15 15:46 ` [PATCH v4 1/4] dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller Miquel Raynal 2021-12-15 15:46 ` Miquel Raynal 2021-12-16 20:23 ` Rob Herring 2021-12-16 20:23 ` Rob Herring 2021-12-15 15:46 ` [PATCH v4 2/4] mtd: rawnand: rzn1: Add new NAND controller driver Miquel Raynal 2021-12-15 15:46 ` Miquel Raynal 2021-12-15 20:35 ` kernel test robot 2021-12-15 20:35 ` kernel test robot 2021-12-15 20:35 ` kernel test robot 2021-12-15 15:46 ` [PATCH v4 3/4] MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller Miquel Raynal 2021-12-15 15:46 ` Miquel Raynal 2021-12-15 15:46 ` [PATCH v4 4/4] ARM: dts: r9a06g032: Describe " Miquel Raynal 2021-12-15 15:46 ` Miquel Raynal 2021-12-16 9:13 ` Geert Uytterhoeven 2021-12-16 9:13 ` Geert Uytterhoeven 2021-12-16 13:47 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:47 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:48 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 14:39 ` Conor.Dooley 2021-12-16 14:39 ` Conor.Dooley 2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 14:47 ` Conor.Dooley 2021-12-16 14:47 ` Conor.Dooley 2021-12-16 13:37 ` [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 08/11] riscv: dts: sifive: " Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven [this message] 2021-12-16 13:37 ` [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:37 ` [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven 2021-12-16 13:37 ` Geert Uytterhoeven 2021-12-16 13:41 [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Geert Uytterhoeven 2021-12-16 13:41 ` [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive, plic: " Geert Uytterhoeven 2021-12-16 13:41 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts Geert Uytterhoeven 2021-12-16 13:41 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive, plic: " Geert Uytterhoeven 2021-12-16 21:29 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: " Rob Herring 2021-12-16 21:29 ` Rob Herring 2021-12-16 13:41 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples Geert Uytterhoeven 2021-12-16 13:41 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive, plic: " Geert Uytterhoeven 2021-12-16 21:29 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive,plic: " Rob Herring 2021-12-16 21:29 ` Rob Herring 2021-12-16 21:28 ` [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Rob Herring 2021-12-16 21:28 ` Rob Herring 2021-12-17 8:02 ` Geert Uytterhoeven 2021-12-17 8:02 ` Geert Uytterhoeven 2021-12-16 13:43 [PATCH v2 0/2] dt-bindings: timer: sifive,clint: " Geert Uytterhoeven 2021-12-16 13:43 ` [PATCH v2 0/2] dt-bindings: timer: sifive, clint: " Geert Uytterhoeven 2021-12-16 13:43 ` [PATCH v2 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts Geert Uytterhoeven 2021-12-16 13:43 ` [PATCH v2 1/2] dt-bindings: timer: sifive, clint: " Geert Uytterhoeven 2021-12-16 21:30 ` [PATCH v2 1/2] dt-bindings: timer: sifive,clint: " Rob Herring 2021-12-16 21:30 ` Rob Herring 2021-12-16 13:43 ` [PATCH v2 2/2] dt-bindings: timer: sifive,clint: Group interrupt tuples Geert Uytterhoeven 2021-12-16 13:43 ` [PATCH v2 2/2] dt-bindings: timer: sifive, clint: " Geert Uytterhoeven 2021-12-16 21:30 ` [PATCH v2 2/2] dt-bindings: timer: sifive,clint: " Rob Herring 2021-12-16 21:30 ` [PATCH v2 2/2] dt-bindings: timer: sifive, clint: " Rob Herring 2021-12-20 12:20 ` [PATCH v2 0/2] dt-bindings: timer: sifive,clint: Miscellaneous improvements Daniel Lezcano 2021-12-20 12:20 ` Daniel Lezcano 2021-12-20 12:22 ` Daniel Lezcano 2021-12-20 12:22 ` Daniel Lezcano
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