* [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-15 3:41 ` Liu, Jingqi
` (2 more replies)
2022-07-11 10:44 ` [PATCH 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Hesham Almatary via
` (6 subsequent siblings)
7 siblings, 3 replies; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
From: Brice Goglin <Brice.Goglin@inria.fr>
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by having multiple best initiators for a single
memory target.
This patch allows -numa without initiator=X when hmat=on by keeping
the default value MAX_NODES in numa_state->nodes[i].initiator.
All places reading numa_state->nodes[i].initiator already check
whether it's different from MAX_NODES before using it.
Tested with
qemu-system-x86_64 -accel kvm \
-machine pc,hmat=on \
-drive if=pflash,format=raw,file=./OVMF.fd \
-drive media=disk,format=qcow2,file=efi.qcow2 \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
which reports NUMA node2 at same distance from both node0 and node1 as seen in lstopo:
Machine (2966MB total) + Package P#0
NUMANode P#2 (979MB)
Group0
NUMANode P#0 (980MB)
Core P#0 + PU P#0
Core P#1 + PU P#1
Group0
NUMANode P#1 (1007MB)
Core P#2 + PU P#2
Core P#3 + PU P#3
Before this patch, we had to add ",initiator=X" to "-numa node,nodeid=2,memdev=ram2".
The lstopo output difference between initiator=1 and no initiator is:
@@ -1,10 +1,10 @@
Machine (2966MB total) + Package P#0
+ NUMANode P#2 (979MB)
Group0
NUMANode P#0 (980MB)
Core P#0 + PU P#0
Core P#1 + PU P#1
Group0
NUMANode P#1 (1007MB)
- NUMANode P#2 (979MB)
Core P#2 + PU P#2
Core P#3 + PU P#3
Corresponding changes in the HMAT MPDA structure:
@@ -49,10 +49,10 @@
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
-[080h 0128 2] Flags (decoded below) : 0001
- Processor Proximity Domain Valid : 1
+[080h 0128 2] Flags (decoded below) : 0000
+ Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
-[084h 0132 4] Attached Initiator Proximity Domain : 00000001
+[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
Final HMAT SLLB structures:
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
---
hw/core/machine.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index a673302cce..d4d7e77401 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
for (i = 0; i < numa_state->num_nodes; i++) {
if (numa_info[i].initiator == MAX_NODES) {
- error_report("The initiator of NUMA node %d is missing, use "
- "'-numa node,initiator' option to declare it", i);
- exit(1);
+ continue;
}
if (!numa_info[numa_info[i].initiator].present) {
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-11 10:44 ` [PATCH 1/8] hmat acpi: Don't require initiator value in -numa Hesham Almatary via
@ 2022-07-15 3:41 ` Liu, Jingqi
2022-07-18 3:17 ` Liu, Jingqi
2022-07-18 13:54 ` Igor Mammedov
2 siblings, 0 replies; 20+ messages in thread
From: Liu, Jingqi @ 2022-07-15 3:41 UTC (permalink / raw)
To: Hesham Almatary, jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
[-- Attachment #1: Type: text/plain, Size: 7589 bytes --]
Hello,
On 7/11/2022 6:44 PM, Hesham Almatary via wrote:
> From: Brice Goglin<Brice.Goglin@inria.fr>
>
> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
> has a "Processor Proximity Domain Valid" flag that is currently
> always set because Qemu -numa requires an initiator=X value
> when hmat=on. Unsetting this flag allows to create more complex
> memory topologies by having multiple best initiators for a single
> memory target.
It would be better if you can explicitly provide cases in this description
for creating more complex memory topologies without initiator=X.
Thanks,
Jingqi
> This patch allows -numa without initiator=X when hmat=on by keeping
> the default value MAX_NODES in numa_state->nodes[i].initiator.
> All places reading numa_state->nodes[i].initiator already check
> whether it's different from MAX_NODES before using it.
>
> Tested with
> qemu-system-x86_64 -accel kvm \
> -machine pc,hmat=on \
> -drive if=pflash,format=raw,file=./OVMF.fd \
> -drive media=disk,format=qcow2,file=efi.qcow2 \
> -smp 4 \
> -m 3G \
> -object memory-backend-ram,size=1G,id=ram0 \
> -object memory-backend-ram,size=1G,id=ram1 \
> -object memory-backend-ram,size=1G,id=ram2 \
> -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
> -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
> -numa node,nodeid=2,memdev=ram2 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
> which reports NUMA node2 at same distance from both node0 and node1 as seen in lstopo:
> Machine (2966MB total) + Package P#0
> NUMANode P#2 (979MB)
> Group0
> NUMANode P#0 (980MB)
> Core P#0 + PU P#0
> Core P#1 + PU P#1
> Group0
> NUMANode P#1 (1007MB)
> Core P#2 + PU P#2
> Core P#3 + PU P#3
>
> Before this patch, we had to add ",initiator=X" to "-numa node,nodeid=2,memdev=ram2".
> The lstopo output difference between initiator=1 and no initiator is:
> @@ -1,10 +1,10 @@
> Machine (2966MB total) + Package P#0
> + NUMANode P#2 (979MB)
> Group0
> NUMANode P#0 (980MB)
> Core P#0 + PU P#0
> Core P#1 + PU P#1
> Group0
> NUMANode P#1 (1007MB)
> - NUMANode P#2 (979MB)
> Core P#2 + PU P#2
> Core P#3 + PU P#3
>
> Corresponding changes in the HMAT MPDA structure:
> @@ -49,10 +49,10 @@
> [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
> [07Ah 0122 2] Reserved : 0000
> [07Ch 0124 4] Length : 00000028
> -[080h 0128 2] Flags (decoded below) : 0001
> - Processor Proximity Domain Valid : 1
> +[080h 0128 2] Flags (decoded below) : 0000
> + Processor Proximity Domain Valid : 0
> [082h 0130 2] Reserved1 : 0000
> -[084h 0132 4] Attached Initiator Proximity Domain : 00000001
> +[084h 0132 4] Attached Initiator Proximity Domain : 00000080
> [088h 0136 4] Memory Proximity Domain : 00000002
> [08Ch 0140 4] Reserved2 : 00000000
> [090h 0144 8] Reserved3 : 0000000000000000
>
> Final HMAT SLLB structures:
> [0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0A2h 0162 2] Reserved : 0000
> [0A4h 0164 4] Length : 00000040
> [0A8h 0168 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0A9h 0169 1] Data Type : 00
> [0AAh 0170 2] Reserved1 : 0000
> [0ACh 0172 4] Initiator Proximity Domains # : 00000002
> [0B0h 0176 4] Target Proximity Domains # : 00000003
> [0B4h 0180 4] Reserved2 : 00000000
> [0B8h 0184 8] Entry Base Unit : 0000000000002710
> [0C0h 0192 4] Initiator Proximity Domain List : 00000000
> [0C4h 0196 4] Initiator Proximity Domain List : 00000001
> [0C8h 0200 4] Target Proximity Domain List : 00000000
> [0CCh 0204 4] Target Proximity Domain List : 00000001
> [0D0h 0208 4] Target Proximity Domain List : 00000002
> [0D4h 0212 2] Entry : 0001
> [0D6h 0214 2] Entry : 0002
> [0D8h 0216 2] Entry : 0003
> [0DAh 0218 2] Entry : 0002
> [0DCh 0220 2] Entry : 0001
> [0DEh 0222 2] Entry : 0003
>
> [0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0E2h 0226 2] Reserved : 0000
> [0E4h 0228 4] Length : 00000040
> [0E8h 0232 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0E9h 0233 1] Data Type : 03
> [0EAh 0234 2] Reserved1 : 0000
> [0ECh 0236 4] Initiator Proximity Domains # : 00000002
> [0F0h 0240 4] Target Proximity Domains # : 00000003
> [0F4h 0244 4] Reserved2 : 00000000
> [0F8h 0248 8] Entry Base Unit : 0000000000000001
> [100h 0256 4] Initiator Proximity Domain List : 00000000
> [104h 0260 4] Initiator Proximity Domain List : 00000001
> [108h 0264 4] Target Proximity Domain List : 00000000
> [10Ch 0268 4] Target Proximity Domain List : 00000001
> [110h 0272 4] Target Proximity Domain List : 00000002
> [114h 0276 2] Entry : 000A
> [116h 0278 2] Entry : 0005
> [118h 0280 2] Entry : 0001
> [11Ah 0282 2] Entry : 0005
> [11Ch 0284 2] Entry : 000A
> [11Eh 0286 2] Entry : 0001
>
> Signed-off-by: Brice Goglin<Brice.Goglin@inria.fr>
> ---
> hw/core/machine.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index a673302cce..d4d7e77401 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
>
> for (i = 0; i < numa_state->num_nodes; i++) {
> if (numa_info[i].initiator == MAX_NODES) {
> - error_report("The initiator of NUMA node %d is missing, use "
> - "'-numa node,initiator' option to declare it", i);
> - exit(1);
> + continue;
> }
>
> if (!numa_info[numa_info[i].initiator].present) {
[-- Attachment #2: Type: text/html, Size: 7992 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-11 10:44 ` [PATCH 1/8] hmat acpi: Don't require initiator value in -numa Hesham Almatary via
2022-07-15 3:41 ` Liu, Jingqi
@ 2022-07-18 3:17 ` Liu, Jingqi
2022-07-18 5:43 ` Brice Goglin
2022-07-18 13:54 ` Igor Mammedov
2 siblings, 1 reply; 20+ messages in thread
From: Liu, Jingqi @ 2022-07-18 3:17 UTC (permalink / raw)
To: Hesham Almatary, jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
On 7/11/2022 6:44 PM, Hesham Almatary via wrote:
> From: Brice Goglin <Brice.Goglin@inria.fr>
>
> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
> has a "Processor Proximity Domain Valid" flag that is currently
> always set because Qemu -numa requires an initiator=X value
> when hmat=on. Unsetting this flag allows to create more complex
> memory topologies by having multiple best initiators for a single
> memory target.
Do you mean the memory-only numa node requires an initiator=X value ?
It would be better if you can explicitly provide cases in the description
for creating more complex memory topologies without initiator=X.
Thanks,
Jingqi
> This patch allows -numa without initiator=X when hmat=on by keeping
> the default value MAX_NODES in numa_state->nodes[i].initiator.
> All places reading numa_state->nodes[i].initiator already check
> whether it's different from MAX_NODES before using it.
>
> Tested with
> qemu-system-x86_64 -accel kvm \
> -machine pc,hmat=on \
> -drive if=pflash,format=raw,file=./OVMF.fd \
> -drive media=disk,format=qcow2,file=efi.qcow2 \
> -smp 4 \
> -m 3G \
> -object memory-backend-ram,size=1G,id=ram0 \
> -object memory-backend-ram,size=1G,id=ram1 \
> -object memory-backend-ram,size=1G,id=ram2 \
> -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
> -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
> -numa node,nodeid=2,memdev=ram2 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
> which reports NUMA node2 at same distance from both node0 and node1 as seen in lstopo:
> Machine (2966MB total) + Package P#0
> NUMANode P#2 (979MB)
> Group0
> NUMANode P#0 (980MB)
> Core P#0 + PU P#0
> Core P#1 + PU P#1
> Group0
> NUMANode P#1 (1007MB)
> Core P#2 + PU P#2
> Core P#3 + PU P#3
>
> Before this patch, we had to add ",initiator=X" to "-numa node,nodeid=2,memdev=ram2".
> The lstopo output difference between initiator=1 and no initiator is:
> @@ -1,10 +1,10 @@
> Machine (2966MB total) + Package P#0
> + NUMANode P#2 (979MB)
> Group0
> NUMANode P#0 (980MB)
> Core P#0 + PU P#0
> Core P#1 + PU P#1
> Group0
> NUMANode P#1 (1007MB)
> - NUMANode P#2 (979MB)
> Core P#2 + PU P#2
> Core P#3 + PU P#3
>
> Corresponding changes in the HMAT MPDA structure:
> @@ -49,10 +49,10 @@
> [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
> [07Ah 0122 2] Reserved : 0000
> [07Ch 0124 4] Length : 00000028
> -[080h 0128 2] Flags (decoded below) : 0001
> - Processor Proximity Domain Valid : 1
> +[080h 0128 2] Flags (decoded below) : 0000
> + Processor Proximity Domain Valid : 0
> [082h 0130 2] Reserved1 : 0000
> -[084h 0132 4] Attached Initiator Proximity Domain : 00000001
> +[084h 0132 4] Attached Initiator Proximity Domain : 00000080
> [088h 0136 4] Memory Proximity Domain : 00000002
> [08Ch 0140 4] Reserved2 : 00000000
> [090h 0144 8] Reserved3 : 0000000000000000
>
> Final HMAT SLLB structures:
> [0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0A2h 0162 2] Reserved : 0000
> [0A4h 0164 4] Length : 00000040
> [0A8h 0168 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0A9h 0169 1] Data Type : 00
> [0AAh 0170 2] Reserved1 : 0000
> [0ACh 0172 4] Initiator Proximity Domains # : 00000002
> [0B0h 0176 4] Target Proximity Domains # : 00000003
> [0B4h 0180 4] Reserved2 : 00000000
> [0B8h 0184 8] Entry Base Unit : 0000000000002710
> [0C0h 0192 4] Initiator Proximity Domain List : 00000000
> [0C4h 0196 4] Initiator Proximity Domain List : 00000001
> [0C8h 0200 4] Target Proximity Domain List : 00000000
> [0CCh 0204 4] Target Proximity Domain List : 00000001
> [0D0h 0208 4] Target Proximity Domain List : 00000002
> [0D4h 0212 2] Entry : 0001
> [0D6h 0214 2] Entry : 0002
> [0D8h 0216 2] Entry : 0003
> [0DAh 0218 2] Entry : 0002
> [0DCh 0220 2] Entry : 0001
> [0DEh 0222 2] Entry : 0003
>
> [0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0E2h 0226 2] Reserved : 0000
> [0E4h 0228 4] Length : 00000040
> [0E8h 0232 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0E9h 0233 1] Data Type : 03
> [0EAh 0234 2] Reserved1 : 0000
> [0ECh 0236 4] Initiator Proximity Domains # : 00000002
> [0F0h 0240 4] Target Proximity Domains # : 00000003
> [0F4h 0244 4] Reserved2 : 00000000
> [0F8h 0248 8] Entry Base Unit : 0000000000000001
> [100h 0256 4] Initiator Proximity Domain List : 00000000
> [104h 0260 4] Initiator Proximity Domain List : 00000001
> [108h 0264 4] Target Proximity Domain List : 00000000
> [10Ch 0268 4] Target Proximity Domain List : 00000001
> [110h 0272 4] Target Proximity Domain List : 00000002
> [114h 0276 2] Entry : 000A
> [116h 0278 2] Entry : 0005
> [118h 0280 2] Entry : 0001
> [11Ah 0282 2] Entry : 0005
> [11Ch 0284 2] Entry : 000A
> [11Eh 0286 2] Entry : 0001
>
> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
> ---
> hw/core/machine.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index a673302cce..d4d7e77401 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
>
> for (i = 0; i < numa_state->num_nodes; i++) {
> if (numa_info[i].initiator == MAX_NODES) {
> - error_report("The initiator of NUMA node %d is missing, use "
> - "'-numa node,initiator' option to declare it", i);
> - exit(1);
> + continue;
> }
>
> if (!numa_info[numa_info[i].initiator].present) {
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-18 3:17 ` Liu, Jingqi
@ 2022-07-18 5:43 ` Brice Goglin
2022-07-19 4:33 ` Liu, Jingqi
0 siblings, 1 reply; 20+ messages in thread
From: Brice Goglin @ 2022-07-18 5:43 UTC (permalink / raw)
To: Liu, Jingqi, Hesham Almatary, jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, mst
[-- Attachment #1.1: Type: text/plain, Size: 9740 bytes --]
Le 18/07/2022 à 05:17, Liu, Jingqi a écrit :
>
> On 7/11/2022 6:44 PM, Hesham Almatary via wrote:
>> From: Brice Goglin <Brice.Goglin@inria.fr>
>>
>> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
>> has a "Processor Proximity Domain Valid" flag that is currently
>> always set because Qemu -numa requires an initiator=X value
>> when hmat=on. Unsetting this flag allows to create more complex
>> memory topologies by having multiple best initiators for a single
>> memory target.
>
> Do you mean the memory-only numa node requires an initiator=X value ?
>
> It would be better if you can explicitly provide cases in the description
>
> for creating more complex memory topologies without initiator=X.
Hello
I wrote this text so I am going to reply. All nodes currently require an
initiator= attribute. For CPU-node, that's usually OK. However it forces
all nodes to have a best initiator that is exactly one single node. This
prevents creating a topology where some memory has for best initiator
the sum of 2 nodes for instance. There's an example below in the
description. A real-world example would be a Xeon server with SNC
enabled: there are 2 DDR per socket, one per SNC, but a single NVDIMM
per socket covering both SNC. That NVDIMM node cannot have a single
initiator value since its best initiator is both SNC. That's similar to
the example below in the description
Brice
>
> Thanks,
>
> Jingqi
>
>> This patch allows -numa without initiator=X when hmat=on by keeping
>> the default value MAX_NODES in numa_state->nodes[i].initiator.
>> All places reading numa_state->nodes[i].initiator already check
>> whether it's different from MAX_NODES before using it.
>>
>> Tested with
>> qemu-system-x86_64 -accel kvm \
>> -machine pc,hmat=on \
>> -drive if=pflash,format=raw,file=./OVMF.fd \
>> -drive media=disk,format=qcow2,file=efi.qcow2 \
>> -smp 4 \
>> -m 3G \
>> -object memory-backend-ram,size=1G,id=ram0 \
>> -object memory-backend-ram,size=1G,id=ram1 \
>> -object memory-backend-ram,size=1G,id=ram2 \
>> -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
>> -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
>> -numa node,nodeid=2,memdev=ram2 \
>> -numa
>> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
>> \
>> -numa
>> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>> \
>> -numa
>> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
>> \
>> -numa
>> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>> \
>> -numa
>> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
>> \
>> -numa
>> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>> \
>> -numa
>> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
>> \
>> -numa
>> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>> \
>> -numa
>> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
>> \
>> -numa
>> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>> \
>> -numa
>> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
>> \
>> -numa
>> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>> which reports NUMA node2 at same distance from both node0 and node1
>> as seen in lstopo:
>> Machine (2966MB total) + Package P#0
>> NUMANode P#2 (979MB)
>> Group0
>> NUMANode P#0 (980MB)
>> Core P#0 + PU P#0
>> Core P#1 + PU P#1
>> Group0
>> NUMANode P#1 (1007MB)
>> Core P#2 + PU P#2
>> Core P#3 + PU P#3
>>
>> Before this patch, we had to add ",initiator=X" to "-numa
>> node,nodeid=2,memdev=ram2".
>> The lstopo output difference between initiator=1 and no initiator is:
>> @@ -1,10 +1,10 @@
>> Machine (2966MB total) + Package P#0
>> + NUMANode P#2 (979MB)
>> Group0
>> NUMANode P#0 (980MB)
>> Core P#0 + PU P#0
>> Core P#1 + PU P#1
>> Group0
>> NUMANode P#1 (1007MB)
>> - NUMANode P#2 (979MB)
>> Core P#2 + PU P#2
>> Core P#3 + PU P#3
>>
>> Corresponding changes in the HMAT MPDA structure:
>> @@ -49,10 +49,10 @@
>> [078h 0120 2] Structure Type : 0000 [Memory
>> Proximity Domain Attributes]
>> [07Ah 0122 2] Reserved : 0000
>> [07Ch 0124 4] Length : 00000028
>> -[080h 0128 2] Flags (decoded below) : 0001
>> - Processor Proximity Domain Valid : 1
>> +[080h 0128 2] Flags (decoded below) : 0000
>> + Processor Proximity Domain Valid : 0
>> [082h 0130 2] Reserved1 : 0000
>> -[084h 0132 4] Attached Initiator Proximity Domain : 00000001
>> +[084h 0132 4] Attached Initiator Proximity Domain : 00000080
>> [088h 0136 4] Memory Proximity Domain : 00000002
>> [08Ch 0140 4] Reserved2 : 00000000
>> [090h 0144 8] Reserved3 : 0000000000000000
>>
>> Final HMAT SLLB structures:
>> [0A0h 0160 2] Structure Type : 0001 [System Locality
>> Latency and Bandwidth Information]
>> [0A2h 0162 2] Reserved : 0000
>> [0A4h 0164 4] Length : 00000040
>> [0A8h 0168 1] Flags (decoded below) : 00
>> Memory Hierarchy : 0
>> [0A9h 0169 1] Data Type : 00
>> [0AAh 0170 2] Reserved1 : 0000
>> [0ACh 0172 4] Initiator Proximity Domains # : 00000002
>> [0B0h 0176 4] Target Proximity Domains # : 00000003
>> [0B4h 0180 4] Reserved2 : 00000000
>> [0B8h 0184 8] Entry Base Unit : 0000000000002710
>> [0C0h 0192 4] Initiator Proximity Domain List : 00000000
>> [0C4h 0196 4] Initiator Proximity Domain List : 00000001
>> [0C8h 0200 4] Target Proximity Domain List : 00000000
>> [0CCh 0204 4] Target Proximity Domain List : 00000001
>> [0D0h 0208 4] Target Proximity Domain List : 00000002
>> [0D4h 0212 2] Entry : 0001
>> [0D6h 0214 2] Entry : 0002
>> [0D8h 0216 2] Entry : 0003
>> [0DAh 0218 2] Entry : 0002
>> [0DCh 0220 2] Entry : 0001
>> [0DEh 0222 2] Entry : 0003
>>
>> [0E0h 0224 2] Structure Type : 0001 [System Locality
>> Latency and Bandwidth Information]
>> [0E2h 0226 2] Reserved : 0000
>> [0E4h 0228 4] Length : 00000040
>> [0E8h 0232 1] Flags (decoded below) : 00
>> Memory Hierarchy : 0
>> [0E9h 0233 1] Data Type : 03
>> [0EAh 0234 2] Reserved1 : 0000
>> [0ECh 0236 4] Initiator Proximity Domains # : 00000002
>> [0F0h 0240 4] Target Proximity Domains # : 00000003
>> [0F4h 0244 4] Reserved2 : 00000000
>> [0F8h 0248 8] Entry Base Unit : 0000000000000001
>> [100h 0256 4] Initiator Proximity Domain List : 00000000
>> [104h 0260 4] Initiator Proximity Domain List : 00000001
>> [108h 0264 4] Target Proximity Domain List : 00000000
>> [10Ch 0268 4] Target Proximity Domain List : 00000001
>> [110h 0272 4] Target Proximity Domain List : 00000002
>> [114h 0276 2] Entry : 000A
>> [116h 0278 2] Entry : 0005
>> [118h 0280 2] Entry : 0001
>> [11Ah 0282 2] Entry : 0005
>> [11Ch 0284 2] Entry : 000A
>> [11Eh 0286 2] Entry : 0001
>>
>> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
>> ---
>> hw/core/machine.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index a673302cce..d4d7e77401 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState
>> *numa_state)
>> for (i = 0; i < numa_state->num_nodes; i++) {
>> if (numa_info[i].initiator == MAX_NODES) {
>> - error_report("The initiator of NUMA node %d is missing,
>> use "
>> - "'-numa node,initiator' option to declare
>> it", i);
>> - exit(1);
>> + continue;
>> }
>> if (!numa_info[numa_info[i].initiator].present) {
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-18 5:43 ` Brice Goglin
@ 2022-07-19 4:33 ` Liu, Jingqi
0 siblings, 0 replies; 20+ messages in thread
From: Liu, Jingqi @ 2022-07-19 4:33 UTC (permalink / raw)
To: Brice Goglin, Hesham Almatary, jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, mst
On 7/18/2022 1:43 PM, Brice Goglin wrote:
>
> Le 18/07/2022 à 05:17, Liu, Jingqi a écrit :
>>
>> On 7/11/2022 6:44 PM, Hesham Almatary via wrote:
>>> From: Brice Goglin <Brice.Goglin@inria.fr>
>>>
>>> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
>>> has a "Processor Proximity Domain Valid" flag that is currently
>>> always set because Qemu -numa requires an initiator=X value
>>> when hmat=on. Unsetting this flag allows to create more complex
>>> memory topologies by having multiple best initiators for a single
>>> memory target.
>>
>> Do you mean the memory-only numa node requires an initiator=X value ?
>>
>> It would be better if you can explicitly provide cases in the
>> description
>>
>> for creating more complex memory topologies without initiator=X.
>
>
> Hello
>
> I wrote this text so I am going to reply. All nodes currently require
> an initiator= attribute. For CPU-node, that's usually OK. However it
> forces all nodes to have a best initiator that is exactly one single
> node. This prevents creating a topology where some memory has for best
> initiator the sum of 2 nodes for instance. There's an example below in
> the description. A real-world example would be a Xeon server with SNC
> enabled: there are 2 DDR per socket, one per SNC, but a single NVDIMM
> per socket covering both SNC. That NVDIMM node cannot have a single
> initiator value since its best initiator is both SNC. That's similar
> to the example below in the description
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
Got it. Thanks for your detailed example. It looks reasonable.
Jingqi
>
> Brice
>
>
>
>>
>> Thanks,
>>
>> Jingqi
>>
>>> This patch allows -numa without initiator=X when hmat=on by keeping
>>> the default value MAX_NODES in numa_state->nodes[i].initiator.
>>> All places reading numa_state->nodes[i].initiator already check
>>> whether it's different from MAX_NODES before using it.
>>>
>>> Tested with
>>> qemu-system-x86_64 -accel kvm \
>>> -machine pc,hmat=on \
>>> -drive if=pflash,format=raw,file=./OVMF.fd \
>>> -drive media=disk,format=qcow2,file=efi.qcow2 \
>>> -smp 4 \
>>> -m 3G \
>>> -object memory-backend-ram,size=1G,id=ram0 \
>>> -object memory-backend-ram,size=1G,id=ram1 \
>>> -object memory-backend-ram,size=1G,id=ram2 \
>>> -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
>>> -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
>>> -numa node,nodeid=2,memdev=ram2 \
>>> -numa
>>> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
>>> \
>>> -numa
>>> hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>>> \
>>> -numa
>>> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
>>> \
>>> -numa
>>> hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>>> \
>>> -numa
>>> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
>>> \
>>> -numa
>>> hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
>>> \
>>> -numa
>>> hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>>> which reports NUMA node2 at same distance from both node0 and node1
>>> as seen in lstopo:
>>> Machine (2966MB total) + Package P#0
>>> NUMANode P#2 (979MB)
>>> Group0
>>> NUMANode P#0 (980MB)
>>> Core P#0 + PU P#0
>>> Core P#1 + PU P#1
>>> Group0
>>> NUMANode P#1 (1007MB)
>>> Core P#2 + PU P#2
>>> Core P#3 + PU P#3
>>>
>>> Before this patch, we had to add ",initiator=X" to "-numa
>>> node,nodeid=2,memdev=ram2".
>>> The lstopo output difference between initiator=1 and no initiator is:
>>> @@ -1,10 +1,10 @@
>>> Machine (2966MB total) + Package P#0
>>> + NUMANode P#2 (979MB)
>>> Group0
>>> NUMANode P#0 (980MB)
>>> Core P#0 + PU P#0
>>> Core P#1 + PU P#1
>>> Group0
>>> NUMANode P#1 (1007MB)
>>> - NUMANode P#2 (979MB)
>>> Core P#2 + PU P#2
>>> Core P#3 + PU P#3
>>>
>>> Corresponding changes in the HMAT MPDA structure:
>>> @@ -49,10 +49,10 @@
>>> [078h 0120 2] Structure Type : 0000 [Memory
>>> Proximity Domain Attributes]
>>> [07Ah 0122 2] Reserved : 0000
>>> [07Ch 0124 4] Length : 00000028
>>> -[080h 0128 2] Flags (decoded below) : 0001
>>> - Processor Proximity Domain Valid : 1
>>> +[080h 0128 2] Flags (decoded below) : 0000
>>> + Processor Proximity Domain Valid : 0
>>> [082h 0130 2] Reserved1 : 0000
>>> -[084h 0132 4] Attached Initiator Proximity Domain : 00000001
>>> +[084h 0132 4] Attached Initiator Proximity Domain : 00000080
>>> [088h 0136 4] Memory Proximity Domain : 00000002
>>> [08Ch 0140 4] Reserved2 : 00000000
>>> [090h 0144 8] Reserved3 : 0000000000000000
>>>
>>> Final HMAT SLLB structures:
>>> [0A0h 0160 2] Structure Type : 0001 [System Locality
>>> Latency and Bandwidth Information]
>>> [0A2h 0162 2] Reserved : 0000
>>> [0A4h 0164 4] Length : 00000040
>>> [0A8h 0168 1] Flags (decoded below) : 00
>>> Memory Hierarchy : 0
>>> [0A9h 0169 1] Data Type : 00
>>> [0AAh 0170 2] Reserved1 : 0000
>>> [0ACh 0172 4] Initiator Proximity Domains # : 00000002
>>> [0B0h 0176 4] Target Proximity Domains # : 00000003
>>> [0B4h 0180 4] Reserved2 : 00000000
>>> [0B8h 0184 8] Entry Base Unit : 0000000000002710
>>> [0C0h 0192 4] Initiator Proximity Domain List : 00000000
>>> [0C4h 0196 4] Initiator Proximity Domain List : 00000001
>>> [0C8h 0200 4] Target Proximity Domain List : 00000000
>>> [0CCh 0204 4] Target Proximity Domain List : 00000001
>>> [0D0h 0208 4] Target Proximity Domain List : 00000002
>>> [0D4h 0212 2] Entry : 0001
>>> [0D6h 0214 2] Entry : 0002
>>> [0D8h 0216 2] Entry : 0003
>>> [0DAh 0218 2] Entry : 0002
>>> [0DCh 0220 2] Entry : 0001
>>> [0DEh 0222 2] Entry : 0003
>>>
>>> [0E0h 0224 2] Structure Type : 0001 [System Locality
>>> Latency and Bandwidth Information]
>>> [0E2h 0226 2] Reserved : 0000
>>> [0E4h 0228 4] Length : 00000040
>>> [0E8h 0232 1] Flags (decoded below) : 00
>>> Memory Hierarchy : 0
>>> [0E9h 0233 1] Data Type : 03
>>> [0EAh 0234 2] Reserved1 : 0000
>>> [0ECh 0236 4] Initiator Proximity Domains # : 00000002
>>> [0F0h 0240 4] Target Proximity Domains # : 00000003
>>> [0F4h 0244 4] Reserved2 : 00000000
>>> [0F8h 0248 8] Entry Base Unit : 0000000000000001
>>> [100h 0256 4] Initiator Proximity Domain List : 00000000
>>> [104h 0260 4] Initiator Proximity Domain List : 00000001
>>> [108h 0264 4] Target Proximity Domain List : 00000000
>>> [10Ch 0268 4] Target Proximity Domain List : 00000001
>>> [110h 0272 4] Target Proximity Domain List : 00000002
>>> [114h 0276 2] Entry : 000A
>>> [116h 0278 2] Entry : 0005
>>> [118h 0280 2] Entry : 0001
>>> [11Ah 0282 2] Entry : 0005
>>> [11Ch 0284 2] Entry : 000A
>>> [11Eh 0286 2] Entry : 0001
>>>
>>> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
>>> ---
>>> hw/core/machine.c | 4 +---
>>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>>
>>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>>> index a673302cce..d4d7e77401 100644
>>> --- a/hw/core/machine.c
>>> +++ b/hw/core/machine.c
>>> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState
>>> *numa_state)
>>> for (i = 0; i < numa_state->num_nodes; i++) {
>>> if (numa_info[i].initiator == MAX_NODES) {
>>> - error_report("The initiator of NUMA node %d is missing,
>>> use "
>>> - "'-numa node,initiator' option to declare
>>> it", i);
>>> - exit(1);
>>> + continue;
>>> }
>>> if (!numa_info[numa_info[i].initiator].present) {
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-11 10:44 ` [PATCH 1/8] hmat acpi: Don't require initiator value in -numa Hesham Almatary via
2022-07-15 3:41 ` Liu, Jingqi
2022-07-18 3:17 ` Liu, Jingqi
@ 2022-07-18 13:54 ` Igor Mammedov
2022-07-18 13:57 ` Hesham Almatary via
2 siblings, 1 reply; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 13:54 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:29 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> From: Brice Goglin <Brice.Goglin@inria.fr>
>
> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
> has a "Processor Proximity Domain Valid" flag that is currently
> always set because Qemu -numa requires an initiator=X value
> when hmat=on. Unsetting this flag allows to create more complex
> memory topologies by having multiple best initiators for a single
> memory target.
>
> This patch allows -numa without initiator=X when hmat=on by keeping
> the default value MAX_NODES in numa_state->nodes[i].initiator.
> All places reading numa_state->nodes[i].initiator already check
> whether it's different from MAX_NODES before using it.
[...]
>
> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
when re-posting patches from someone else, I think one is supposed to add
his/her own SoB at the end
> ---
> hw/core/machine.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index a673302cce..d4d7e77401 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
>
> for (i = 0; i < numa_state->num_nodes; i++) {
> if (numa_info[i].initiator == MAX_NODES) {
> - error_report("The initiator of NUMA node %d is missing, use "
> - "'-numa node,initiator' option to declare it", i);
> - exit(1);
> + continue;
> }
>
> if (!numa_info[numa_info[i].initiator].present) {
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa
2022-07-18 13:54 ` Igor Mammedov
@ 2022-07-18 13:57 ` Hesham Almatary via
0 siblings, 0 replies; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-18 13:57 UTC (permalink / raw)
To: Igor Mammedov
Cc: qemu-devel, yangyicong, chenxiang66, linuxarm, qemu-arm,
peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On 7/18/2022 2:54 PM, Igor Mammedov wrote:
> On Mon, 11 Jul 2022 11:44:29 +0100
> Hesham Almatary <hesham.almatary@huawei.com> wrote:
>
>> From: Brice Goglin <Brice.Goglin@inria.fr>
>>
>> The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
>> has a "Processor Proximity Domain Valid" flag that is currently
>> always set because Qemu -numa requires an initiator=X value
>> when hmat=on. Unsetting this flag allows to create more complex
>> memory topologies by having multiple best initiators for a single
>> memory target.
>>
>> This patch allows -numa without initiator=X when hmat=on by keeping
>> the default value MAX_NODES in numa_state->nodes[i].initiator.
>> All places reading numa_state->nodes[i].initiator already check
>> whether it's different from MAX_NODES before using it.
> [...]
>> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
> when re-posting patches from someone else, I think one is supposed to add
> his/her own SoB at the end
>
Sure, I can do that in v2. I wasn't sure as I haven't modified any of these patches.
>> ---
>> hw/core/machine.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index a673302cce..d4d7e77401 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -1173,9 +1173,7 @@ static void numa_validate_initiator(NumaState *numa_state)
>>
>> for (i = 0; i < numa_state->num_nodes; i++) {
>> if (numa_info[i].initiator == MAX_NODES) {
>> - error_report("The initiator of NUMA node %d is missing, use "
>> - "'-numa node,initiator' option to declare it", i);
>> - exit(1);
>> + continue;
>> }
>>
>> if (!numa_info[numa_info[i].initiator].present) {
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
2022-07-11 10:44 ` [PATCH 1/8] hmat acpi: Don't require initiator value in -numa Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-11 10:44 ` [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators Hesham Almatary via
` (5 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
From: Brice Goglin <Brice.Goglin@inria.fr>
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/FACP.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.acpihmat-noinitiator | 0
tests/data/acpi/q35/SRAT.acpihmat-noinitiator | 0
tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++
6 files changed, 5 insertions(+)
create mode 100644 tests/data/acpi/q35/APIC.acpihmat-noinitiator
create mode 100644 tests/data/acpi/q35/DSDT.acpihmat-noinitiator
create mode 100644 tests/data/acpi/q35/FACP.acpihmat-noinitiator
create mode 100644 tests/data/acpi/q35/HMAT.acpihmat-noinitiator
create mode 100644 tests/data/acpi/q35/SRAT.acpihmat-noinitiator
diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/FACP.acpihmat-noinitiator b/tests/data/acpi/q35/FACP.acpihmat-noinitiator
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..ae025e3a3e 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,6 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
+"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
+"tests/data/acpi/q35/FACP.acpihmat-noinitiator",
+"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
+"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
2022-07-11 10:44 ` [PATCH 1/8] hmat acpi: Don't require initiator value in -numa Hesham Almatary via
2022-07-11 10:44 ` [PATCH 2/8] tests: acpi: add and whitelist *.hmat-noinitiator expected blobs Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-18 14:19 ` Igor Mammedov
2022-07-11 10:44 ` [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators Hesham Almatary via
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
From: Brice Goglin <Brice.Goglin@inria.fr>
expected HMAT:
[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Attached Initiator Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Attached Initiator Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
---
tests/qtest/bios-tables-test.c | 46 ++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 359916c228..f02b386d75 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,50 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
test_acpi_tcg_acpi_hmat(MACHINE_PC);
}
+static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".acpihmat-noinitiator";
+ test_acpi_one(" -machine hmat=on"
+ " -smp 4"
+ " -m 128M"
+ " -object memory-backend-ram,size=32M,id=ram0"
+ " -object memory-backend-ram,size=32M,id=ram1"
+ " -object memory-backend-ram,size=64M,id=ram2"
+ " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
+ " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
+ " -numa node,nodeid=2,memdev=ram2"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-latency,latency=10"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=10485760"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-latency,latency=20"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=5242880"
+ " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+ "data-type=access-latency,latency=30"
+ " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=1048576"
+ " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+ "data-type=access-latency,latency=20"
+ " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=5242880"
+ " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+ "data-type=access-latency,latency=10"
+ " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=10485760"
+ " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+ "data-type=access-latency,latency=30"
+ " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=1048576",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_erst(const char *machine)
{
gchar *tmp_path = g_dir_make_tmp("qemu-test-erst.XXXXXX", NULL);
@@ -1803,6 +1847,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
+ qtest_add_func("acpi/q35/acpihmat-noinitiator",
+ test_acpi_q35_tcg_acpi_hmat_noinitiator);
qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst);
qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst);
qtest_add_func("acpi/q35/applesmc", test_acpi_q35_applesmc);
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators
2022-07-11 10:44 ` [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators Hesham Almatary via
@ 2022-07-18 14:19 ` Igor Mammedov
0 siblings, 0 replies; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 14:19 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:31 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> From: Brice Goglin <Brice.Goglin@inria.fr>
>
> expected HMAT:
>
> [000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
> [004h 0004 4] Table Length : 00000120
> [008h 0008 1] Revision : 02
> [009h 0009 1] Checksum : 4F
> [00Ah 0010 6] Oem ID : "BOCHS "
> [010h 0016 8] Oem Table ID : "BXPC "
> [018h 0024 4] Oem Revision : 00000001
> [01Ch 0028 4] Asl Compiler ID : "BXPC"
> [020h 0032 4] Asl Compiler Revision : 00000001
>
> [024h 0036 4] Reserved : 00000000
>
> [028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
> [02Ah 0042 2] Reserved : 0000
> [02Ch 0044 4] Length : 00000028
> [030h 0048 2] Flags (decoded below) : 0001
> Processor Proximity Domain Valid : 1
> [032h 0050 2] Reserved1 : 0000
> [034h 0052 4] Attached Initiator Proximity Domain : 00000000
> [038h 0056 4] Memory Proximity Domain : 00000000
> [03Ch 0060 4] Reserved2 : 00000000
> [040h 0064 8] Reserved3 : 0000000000000000
> [048h 0072 8] Reserved4 : 0000000000000000
>
> [050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
> [052h 0082 2] Reserved : 0000
> [054h 0084 4] Length : 00000028
> [058h 0088 2] Flags (decoded below) : 0001
> Processor Proximity Domain Valid : 1
> [05Ah 0090 2] Reserved1 : 0000
> [05Ch 0092 4] Attached Initiator Proximity Domain : 00000001
> [060h 0096 4] Memory Proximity Domain : 00000001
> [064h 0100 4] Reserved2 : 00000000
> [068h 0104 8] Reserved3 : 0000000000000000
> [070h 0112 8] Reserved4 : 0000000000000000
>
> [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
> [07Ah 0122 2] Reserved : 0000
> [07Ch 0124 4] Length : 00000028
> [080h 0128 2] Flags (decoded below) : 0000
> Processor Proximity Domain Valid : 0
> [082h 0130 2] Reserved1 : 0000
> [084h 0132 4] Attached Initiator Proximity Domain : 00000080
> [088h 0136 4] Memory Proximity Domain : 00000002
> [08Ch 0140 4] Reserved2 : 00000000
> [090h 0144 8] Reserved3 : 0000000000000000
> [098h 0152 8] Reserved4 : 0000000000000000
>
> [0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0A2h 0162 2] Reserved : 0000
> [0A4h 0164 4] Length : 00000040
> [0A8h 0168 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0A9h 0169 1] Data Type : 00
> [0AAh 0170 2] Reserved1 : 0000
> [0ACh 0172 4] Initiator Proximity Domains # : 00000002
> [0B0h 0176 4] Target Proximity Domains # : 00000003
> [0B4h 0180 4] Reserved2 : 00000000
> [0B8h 0184 8] Entry Base Unit : 0000000000002710
> [0C0h 0192 4] Initiator Proximity Domain List : 00000000
> [0C4h 0196 4] Initiator Proximity Domain List : 00000001
> [0C8h 0200 4] Target Proximity Domain List : 00000000
> [0CCh 0204 4] Target Proximity Domain List : 00000001
> [0D0h 0208 4] Target Proximity Domain List : 00000002
> [0D4h 0212 2] Entry : 0001
> [0D6h 0214 2] Entry : 0002
> [0D8h 0216 2] Entry : 0003
> [0DAh 0218 2] Entry : 0002
> [0DCh 0220 2] Entry : 0001
> [0DEh 0222 2] Entry : 0003
>
> [0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
> [0E2h 0226 2] Reserved : 0000
> [0E4h 0228 4] Length : 00000040
> [0E8h 0232 1] Flags (decoded below) : 00
> Memory Hierarchy : 0
> [0E9h 0233 1] Data Type : 03
> [0EAh 0234 2] Reserved1 : 0000
> [0ECh 0236 4] Initiator Proximity Domains # : 00000002
> [0F0h 0240 4] Target Proximity Domains # : 00000003
> [0F4h 0244 4] Reserved2 : 00000000
> [0F8h 0248 8] Entry Base Unit : 0000000000000001
> [100h 0256 4] Initiator Proximity Domain List : 00000000
> [104h 0260 4] Initiator Proximity Domain List : 00000001
> [108h 0264 4] Target Proximity Domain List : 00000000
> [10Ch 0268 4] Target Proximity Domain List : 00000001
> [110h 0272 4] Target Proximity Domain List : 00000002
> [114h 0276 2] Entry : 000A
> [116h 0278 2] Entry : 0005
> [118h 0280 2] Entry : 0001
> [11Ah 0282 2] Entry : 0005
> [11Ch 0284 2] Entry : 000A
> [11Eh 0286 2] Entry : 0001
>
> Raw Table Data: Length 288 (0x120)
>
> 0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
> 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
> 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
> 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
> 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
> 0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
> 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
> 0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
> 0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
> 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
> 00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
> 00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
> 00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
> 00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
> 00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
> 00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
> 0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
> 0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
>
> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
> ---
> tests/qtest/bios-tables-test.c | 46 ++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 359916c228..f02b386d75 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -1461,6 +1461,50 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
> test_acpi_tcg_acpi_hmat(MACHINE_PC);
> }
>
> +static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
> +{
> + test_data data;
> +
> + memset(&data, 0, sizeof(data));
> + data.machine = MACHINE_Q35;
> + data.variant = ".acpihmat-noinitiator";
> + test_acpi_one(" -machine hmat=on"
> + " -smp 4"
> + " -m 128M"
> + " -object memory-backend-ram,size=32M,id=ram0"
> + " -object memory-backend-ram,size=32M,id=ram1"
> + " -object memory-backend-ram,size=64M,id=ram2"
> + " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
> + " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
don't use legacy syntax, see test_acpi_tcg_dimm_pxm() for example
> + " -numa node,nodeid=2,memdev=ram2"
> + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> + "data-type=access-latency,latency=10"
> + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=10485760"
> + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> + "data-type=access-latency,latency=20"
> + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=5242880"
> + " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> + "data-type=access-latency,latency=30"
> + " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=1048576"
> + " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> + "data-type=access-latency,latency=20"
> + " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=5242880"
> + " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> + "data-type=access-latency,latency=10"
> + " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=10485760"
> + " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> + "data-type=access-latency,latency=30"
> + " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=1048576",
> + &data);
> + free_test_data(&data);
> +}
> +
> static void test_acpi_erst(const char *machine)
> {
> gchar *tmp_path = g_dir_make_tmp("qemu-test-erst.XXXXXX", NULL);
> @@ -1803,6 +1847,8 @@ int main(int argc, char *argv[])
> qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
> qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
> qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
> + qtest_add_func("acpi/q35/acpihmat-noinitiator",
> + test_acpi_q35_tcg_acpi_hmat_noinitiator);
> qtest_add_func("acpi/piix4/acpierst", test_acpi_piix4_acpi_erst);
> qtest_add_func("acpi/q35/acpierst", test_acpi_q35_acpi_erst);
> qtest_add_func("acpi/q35/applesmc", test_acpi_q35_applesmc);
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
` (2 preceding siblings ...)
2022-07-11 10:44 ` [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-18 14:08 ` Igor Mammedov
2022-07-11 10:44 ` [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files Hesham Almatary via
` (3 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
From: Brice Goglin <Brice.Goglin@inria.fr>
expected HMAT:
[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Attached Initiator Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Attached Initiator Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 0 -> 8553 bytes
tests/data/acpi/q35/FACP.acpihmat-noinitiator | Bin 0 -> 244 bytes
tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 5 -----
6 files changed, 5 deletions(-)
diff --git a/tests/data/acpi/q35/APIC.acpihmat-noinitiator b/tests/data/acpi/q35/APIC.acpihmat-noinitiator
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..d904d4a70ddecbb79a83a267af8e26f925e9f4c6 100644
GIT binary patch
literal 144
zcmZ<^@N}NQz`(%h?d0$55v<@85#X!<1dKp25F11@Fg*ANra6G>KwJ(+MhMNs1fiLk
tK{O)|Nb<lx5Xr;^#2^NU#mWk#c|j~rP8f>|r~o3y%?)O;u>A)b0RWi;3;_TD
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/DSDT.acpihmat-noinitiator b/tests/data/acpi/q35/DSDT.acpihmat-noinitiator
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c767d11cb1d088f613c49e55a7139cccababf66c 100644
GIT binary patch
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literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/FACP.acpihmat-noinitiator b/tests/data/acpi/q35/FACP.acpihmat-noinitiator
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a8f6a8961109d01059aceef9f1869cde09a2f10c 100644
GIT binary patch
literal 244
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YBHITON2VDSAnpK(F*YFF1LDH~0P8Id0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/HMAT.acpihmat-noinitiator b/tests/data/acpi/q35/HMAT.acpihmat-noinitiator
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6494d11b9fff54f8c403ec9e4893fdff72bde9c9 100644
GIT binary patch
literal 288
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I&r86*0dKzu0RR91
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/q35/SRAT.acpihmat-noinitiator b/tests/data/acpi/q35/SRAT.acpihmat-noinitiator
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..a11d3119ab3538d9cf821a4fe0fccb0f1dc96359 100644
GIT binary patch
literal 312
zcmWFzatyIxWME)?>E!S15v<@85#X!<1VAAM5F12;FdPVA@EK9%8JW=d%*cF34Y)~A
u1{YiayE>qSVDJGh4QBww88zTMCa6LfjpA-b4Y)81R2_^)QwNnLKmh<Kp$P#1
literal 0
HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index ae025e3a3e..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,6 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/APIC.acpihmat-noinitiator",
-"tests/data/acpi/q35/DSDT.acpihmat-noinitiator",
-"tests/data/acpi/q35/FACP.acpihmat-noinitiator",
-"tests/data/acpi/q35/HMAT.acpihmat-noinitiator",
-"tests/data/acpi/q35/SRAT.acpihmat-noinitiator",
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators
2022-07-11 10:44 ` [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators Hesham Almatary via
@ 2022-07-18 14:08 ` Igor Mammedov
0 siblings, 0 replies; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 14:08 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:32 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> From: Brice Goglin <Brice.Goglin@inria.fr>
>
[...]
> Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
> ---
> tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes
[...]
> tests/data/acpi/q35/FACP.acpihmat-noinitiator | Bin 0 -> 244 bytes
drop these 2 tables, they are the same as default ones (i.e.without suffix)
so test will fallback to default ones when there is no matching file with suffix.
also fixup 2/8 to account for that
> tests/data/acpi/q35/HMAT.acpihmat-noinitiator | Bin 0 -> 288 bytes
> tests/data/acpi/q35/SRAT.acpihmat-noinitiator | Bin 0 -> 312 bytes
> tests/qtest/bios-tables-test-allowed-diff.h | 5 -----
> 6 files changed, 5 deletions(-)
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
` (3 preceding siblings ...)
2022-07-11 10:44 ` [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-18 14:10 ` Igor Mammedov
2022-07-11 10:44 ` [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine Hesham Almatary via
` (2 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
---
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/FACP.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++
5 files changed, 4 insertions(+)
create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
create mode 100644 tests/data/acpi/virt/FACP.acpihmatvirt
create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt b/tests/data/acpi/virt/DSDT.acpihmatvirt
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/FACP.acpihmatvirt b/tests/data/acpi/virt/FACP.acpihmatvirt
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt b/tests/data/acpi/virt/HMAT.acpihmatvirt
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt b/tests/data/acpi/virt/SRAT.acpihmatvirt
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..44594cae59 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,5 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/virt/DSDT.acpihmatvirt",
+"tests/data/acpi/virt/FACP.acpihmatvirt",
+"tests/data/acpi/virt/HMAT.acpihmatvirt",
+"tests/data/acpi/virt/SRAT.acpihmatvirt",
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files
2022-07-11 10:44 ` [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files Hesham Almatary via
@ 2022-07-18 14:10 ` Igor Mammedov
0 siblings, 0 replies; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 14:10 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:33 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
> ---
> tests/data/acpi/virt/DSDT.acpihmatvirt | 0
> tests/data/acpi/virt/FACP.acpihmatvirt | 0
> tests/data/acpi/virt/HMAT.acpihmatvirt | 0
> tests/data/acpi/virt/SRAT.acpihmatvirt | 0
> tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++
> 5 files changed, 4 insertions(+)
> create mode 100644 tests/data/acpi/virt/DSDT.acpihmatvirt
> create mode 100644 tests/data/acpi/virt/FACP.acpihmatvirt
> create mode 100644 tests/data/acpi/virt/HMAT.acpihmatvirt
> create mode 100644 tests/data/acpi/virt/SRAT.acpihmatvirt
>
> diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt b/tests/data/acpi/virt/DSDT.acpihmatvirt
> new file mode 100644
> index 0000000000..e69de29bb2
> diff --git a/tests/data/acpi/virt/FACP.acpihmatvirt b/tests/data/acpi/virt/FACP.acpihmatvirt
probably the same as 4/8
include variant table only if it differs from default one
> new file mode 100644
> index 0000000000..e69de29bb2
> diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt b/tests/data/acpi/virt/HMAT.acpihmatvirt
> new file mode 100644
> index 0000000000..e69de29bb2
> diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt b/tests/data/acpi/virt/SRAT.acpihmatvirt
> new file mode 100644
> index 0000000000..e69de29bb2
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
> index dfb8523c8b..44594cae59 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1 +1,5 @@
> /* List of comma-separated changed AML files to ignore */
> +"tests/data/acpi/virt/DSDT.acpihmatvirt",
> +"tests/data/acpi/virt/FACP.acpihmatvirt",
> +"tests/data/acpi/virt/HMAT.acpihmatvirt",
> +"tests/data/acpi/virt/SRAT.acpihmatvirt",
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
` (4 preceding siblings ...)
2022-07-11 10:44 ` [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-18 14:12 ` Igor Mammedov
2022-07-11 10:44 ` [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Hesham Almatary via
2022-07-11 10:44 ` [PATCH 8/8] tests: virt: Update expected *.acpihmatvirt tables Hesham Almatary via
7 siblings, 1 reply; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
From: Xiang Chen <chenxiang66@hisilicon.com>
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
hw/arm/Kconfig | 1 +
hw/arm/virt-acpi-build.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 15fa79afd3..17fcde8e1c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -30,6 +30,7 @@ config ARM_VIRT
select ACPI_VIOT
select VIRTIO_MEM_SUPPORTED
select ACPI_CXL
+ select ACPI_HMAT
config CHEETAH
bool
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 449fab0080..f19b55e486 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -42,6 +42,7 @@
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/generic_event_device.h"
#include "hw/acpi/tpm.h"
+#include "hw/acpi/hmat.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
@@ -990,6 +991,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
build_slit(tables_blob, tables->linker, ms, vms->oem_id,
vms->oem_table_id);
}
+
+ if (ms->numa_state->hmat_enabled) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_hmat(tables_blob, tables->linker, ms->numa_state,
+ vms->oem_id, vms->oem_table_id);
+ }
}
if (ms->nvdimms_state->is_enabled) {
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine
2022-07-11 10:44 ` [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine Hesham Almatary via
@ 2022-07-18 14:12 ` Igor Mammedov
0 siblings, 0 replies; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 14:12 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:34 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> From: Xiang Chen <chenxiang66@hisilicon.com>
>
> Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
> HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
>
> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/virt-acpi-build.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 15fa79afd3..17fcde8e1c 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -30,6 +30,7 @@ config ARM_VIRT
> select ACPI_VIOT
> select VIRTIO_MEM_SUPPORTED
> select ACPI_CXL
> + select ACPI_HMAT
>
> config CHEETAH
> bool
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 449fab0080..f19b55e486 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -42,6 +42,7 @@
> #include "hw/acpi/memory_hotplug.h"
> #include "hw/acpi/generic_event_device.h"
> #include "hw/acpi/tpm.h"
> +#include "hw/acpi/hmat.h"
> #include "hw/pci/pcie_host.h"
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_bus.h"
> @@ -990,6 +991,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
> build_slit(tables_blob, tables->linker, ms, vms->oem_id,
> vms->oem_table_id);
> }
> +
> + if (ms->numa_state->hmat_enabled) {
> + acpi_add_table(table_offsets, tables_blob);
> + build_hmat(tables_blob, tables->linker, ms->numa_state,
> + vms->oem_id, vms->oem_table_id);
> + }
> }
>
> if (ms->nvdimms_state->is_enabled) {
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
` (5 preceding siblings ...)
2022-07-11 10:44 ` [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
2022-07-18 14:19 ` Igor Mammedov
2022-07-11 10:44 ` [PATCH 8/8] tests: virt: Update expected *.acpihmatvirt tables Hesham Almatary via
7 siblings, 1 reply; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.
Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_EFI.fd \
-kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
-drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
-device virtio-rng-pci \
-net user,hostfwd=tcp::10022-:22 -net nic \
-device intel-hda -device hda-duplex -nographic \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
---
tests/qtest/bios-tables-test.c | 55 ++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index f02b386d75..ed843c2abf 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1461,6 +1461,59 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
test_acpi_tcg_acpi_hmat(MACHINE_PC);
}
+static void test_acpi_virt_tcg_acpi_hmat(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ data.variant = ".acpihmatvirt";
+
+ test_acpi_one(" -machine hmat=on"
+ " -cpu cortex-a57"
+ " -smp 4"
+ " -m 256M"
+ " -object memory-backend-ram,size=64M,id=ram0"
+ " -object memory-backend-ram,size=64M,id=ram1"
+ " -object memory-backend-ram,size=128M,id=ram2"
+ " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
+ " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
+ " -numa node,nodeid=2,memdev=ram2"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-latency,latency=10"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=10485760"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-latency,latency=20"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=5242880"
+ " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+ "data-type=access-latency,latency=30"
+ " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=1048576"
+ " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+ "data-type=access-latency,latency=20"
+ " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=5242880"
+ " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+ "data-type=access-latency,latency=10"
+ " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=10485760"
+ " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+ "data-type=access-latency,latency=30"
+ " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=1048576",
+ &data);
+
+ free_test_data(&data);
+}
+
static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
{
test_data data;
@@ -1875,6 +1928,8 @@ int main(int argc, char *argv[])
} else if (strcmp(arch, "aarch64") == 0) {
if (has_tcg) {
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
+ qtest_add_func("acpi/virt/acpihmatvirt",
+ test_acpi_virt_tcg_acpi_hmat);
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
2022-07-11 10:44 ` [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Hesham Almatary via
@ 2022-07-18 14:19 ` Igor Mammedov
0 siblings, 0 replies; 20+ messages in thread
From: Igor Mammedov @ 2022-07-18 14:19 UTC (permalink / raw)
To: Hesham Almatary
Cc: jonathan.cameron, qemu-devel, yangyicong, chenxiang66, linuxarm,
qemu-arm, peter.maydell, wangyanan55, marcel.apfelbaum, eduardo,
Brice.Goglin, mst
On Mon, 11 Jul 2022 11:44:35 +0100
Hesham Almatary <hesham.almatary@huawei.com> wrote:
> This patch imitates the "tests: acpi: q35: add test for hmat nodes
> without initiators" commit to test numa nodes with different HMAT
> attributes, but on AArch64/virt.
>
> Tested with:
> qemu-system-aarch64 -accel tcg \
> -machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \
> -bios qemu-efi-aarch64/QEMU_EFI.fd \
> -kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
> -drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
> -device virtio-rng-pci \
> -net user,hostfwd=tcp::10022-:22 -net nic \
> -device intel-hda -device hda-duplex -nographic \
> -smp 4 \
> -m 3G \
> -object memory-backend-ram,size=1G,id=ram0 \
> -object memory-backend-ram,size=1G,id=ram1 \
> -object memory-backend-ram,size=1G,id=ram2 \
> -numa node,nodeid=0,memdev=ram0,cpus=0-1 \
> -numa node,nodeid=1,memdev=ram1,cpus=2-3 \
> -numa node,nodeid=2,memdev=ram2 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \
> -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
> -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \
> -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
>
> Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
> ---
> tests/qtest/bios-tables-test.c | 55 ++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index f02b386d75..ed843c2abf 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -1461,6 +1461,59 @@ static void test_acpi_piix4_tcg_acpi_hmat(void)
> test_acpi_tcg_acpi_hmat(MACHINE_PC);
> }
>
> +static void test_acpi_virt_tcg_acpi_hmat(void)
> +{
> + test_data data = {
> + .machine = "virt",
> + .tcg_only = true,
> + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
> + .ram_start = 0x40000000ULL,
> + .scan_len = 128ULL * 1024 * 1024,
> + };
> +
> + data.variant = ".acpihmatvirt";
> +
> + test_acpi_one(" -machine hmat=on"
> + " -cpu cortex-a57"
> + " -smp 4"
> + " -m 256M"
> + " -object memory-backend-ram,size=64M,id=ram0"
> + " -object memory-backend-ram,size=64M,id=ram1"
> + " -object memory-backend-ram,size=128M,id=ram2"
> + " -numa node,nodeid=0,memdev=ram0,cpus=0-1"
> + " -numa node,nodeid=1,memdev=ram1,cpus=2-3"
don't use legacy syntax, see test_acpi_tcg_dimm_pxm() for example
> + " -numa node,nodeid=2,memdev=ram2"
> + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> + "data-type=access-latency,latency=10"
> + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=10485760"
> + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> + "data-type=access-latency,latency=20"
> + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=5242880"
> + " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> + "data-type=access-latency,latency=30"
> + " -numa hmat-lb,initiator=0,target=2,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=1048576"
> + " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> + "data-type=access-latency,latency=20"
> + " -numa hmat-lb,initiator=1,target=0,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=5242880"
> + " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> + "data-type=access-latency,latency=10"
> + " -numa hmat-lb,initiator=1,target=1,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=10485760"
> + " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> + "data-type=access-latency,latency=30"
> + " -numa hmat-lb,initiator=1,target=2,hierarchy=memory,"
> + "data-type=access-bandwidth,bandwidth=1048576",
> + &data);
> +
> + free_test_data(&data);
> +}
> +
> static void test_acpi_q35_tcg_acpi_hmat_noinitiator(void)
> {
> test_data data;
> @@ -1875,6 +1928,8 @@ int main(int argc, char *argv[])
> } else if (strcmp(arch, "aarch64") == 0) {
> if (has_tcg) {
> qtest_add_func("acpi/virt", test_acpi_virt_tcg);
> + qtest_add_func("acpi/virt/acpihmatvirt",
> + test_acpi_virt_tcg_acpi_hmat);
> qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
> qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
> qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 8/8] tests: virt: Update expected *.acpihmatvirt tables
2022-07-11 10:44 [PATCH 0/8] AArch64/HMAT support and tests Hesham Almatary via
` (6 preceding siblings ...)
2022-07-11 10:44 ` [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators Hesham Almatary via
@ 2022-07-11 10:44 ` Hesham Almatary via
7 siblings, 0 replies; 20+ messages in thread
From: Hesham Almatary via @ 2022-07-11 10:44 UTC (permalink / raw)
To: jonathan.cameron, qemu-devel
Cc: yangyicong, chenxiang66, linuxarm, qemu-arm, peter.maydell,
imammedo, wangyanan55, marcel.apfelbaum, eduardo, Brice.Goglin,
mst
* Expected ACPI Data Table [HMAT]
[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Processor Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Processor Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Processor Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Processor Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Processor Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
* Expected ACPI Data Table [FACP]
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[004h 0004 4] Table Length : 0000010C
[008h 0008 1] Revision : 05
[009h 0009 1] Checksum : 55
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] FACS Address : 00000000
[028h 0040 4] DSDT Address : 00000000
[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 00 [Unspecified]
[02Eh 0046 2] SCI Interrupt : 0000
[030h 0048 4] SMI Command Port : 00000000
[034h 0052 1] ACPI Enable Value : 00
[035h 0053 1] ACPI Disable Value : 00
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
[038h 0056 4] PM1A Event Block Address : 00000000
[03Ch 0060 4] PM1B Event Block Address : 00000000
[040h 0064 4] PM1A Control Block Address : 00000000
[044h 0068 4] PM1B Control Block Address : 00000000
[048h 0072 4] PM2 Control Block Address : 00000000
[04Ch 0076 4] PM Timer Block Address : 00000000
[050h 0080 4] GPE0 Block Address : 00000000
[054h 0084 4] GPE1 Block Address : 00000000
[058h 0088 1] PM1 Event Block Length : 00
[059h 0089 1] PM1 Control Block Length : 00
[05Ah 0090 1] PM2 Control Block Length : 00
[05Bh 0091 1] PM Timer Block Length : 00
[05Ch 0092 1] GPE0 Block Length : 00
[05Dh 0093 1] GPE1 Block Length : 00
[05Eh 0094 1] GPE1 Base Offset : 00
[05Fh 0095 1] _CST Support : 00
[060h 0096 2] C2 Latency : 0000
[062h 0098 2] C3 Latency : 0000
[064h 0100 2] CPU Cache Size : 0000
[066h 0102 2] Cache Flush Stride : 0000
[068h 0104 1] Duty Cycle Offset : 00
[069h 0105 1] Duty Cycle Width : 00
[06Ah 0106 1] RTC Day Alarm Index : 00
[06Bh 0107 1] RTC Month Alarm Index : 00
[06Ch 0108 1] RTC Century Index : 00
[06Dh 0109 2] Boot Flags (decoded below) : 0000
Legacy Devices Supported (V2) : 0
8042 Present on ports 60/64 (V2) : 0
VGA Not Present (V4) : 0
MSI Not Supported (V4) : 0
PCIe ASPM Not Supported (V4) : 0
CMOS RTC Not Present (V5) : 0
[06Fh 0111 1] Reserved : 00
[070h 0112 4] Flags (decoded below) : 00100000
WBINVD instruction is operational (V1) : 0
WBINVD flushes all caches (V1) : 0
All CPUs support C1 (V1) : 0
C2 works on MP system (V1) : 0
Control Method Power Button (V1) : 0
Control Method Sleep Button (V1) : 0
RTC wake not in fixed reg space (V1) : 0
RTC can wake system from S4 (V1) : 0
32-bit PM Timer (V1) : 0
Docking Supported (V1) : 0
Reset Register Supported (V2) : 0
Sealed Case (V3) : 0
Headless - No Video (V3) : 0
Use native instr after SLP_TYPx (V3) : 0
PCIEXP_WAK Bits Supported (V4) : 0
Use Platform Timer (V4) : 0
RTC_STS valid on S4 wake (V4) : 0
Remote Power-on capable (V4) : 0
Use APIC Cluster Model (V4) : 0
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 00 [SystemMemory]
[075h 0117 1] Bit Width : 00
[076h 0118 1] Bit Offset : 00
[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
[078h 0120 8] Address : 0000000000000000
[080h 0128 1] Value to cause reset : 00
[081h 0129 2] ARM Flags (decoded below) : 0003
PSCI Compliant : 1
Must use HVC for PSCI : 1
[083h 0131 1] FADT Minor Revision : 01
[084h 0132 8] FACS Address : 0000000000000000
[08Ch 0140 8] DSDT Address : 0000000000000000
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 00 [SystemMemory]
[095h 0149 1] Bit Width : 00
[096h 0150 1] Bit Offset : 00
[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
[098h 0152 8] Address : 0000000000000000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 00 [SystemMemory]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
[0ACh 0172 1] Space ID : 00 [SystemMemory]
[0ADh 0173 1] Bit Width : 00
[0AEh 0174 1] Bit Offset : 00
[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
[0B0h 0176 8] Address : 0000000000000000
[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
[0B8h 0184 1] Space ID : 00 [SystemMemory]
[0B9h 0185 1] Bit Width : 00
[0BAh 0186 1] Bit Offset : 00
[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
[0BCh 0188 8] Address : 0000000000000000
[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
[0C4h 0196 1] Space ID : 00 [SystemMemory]
[0C5h 0197 1] Bit Width : 00
[0C6h 0198 1] Bit Offset : 00
[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
[0C8h 0200 8] Address : 0000000000000000
[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
[0D0h 0208 1] Space ID : 00 [SystemMemory]
[0D1h 0209 1] Bit Width : 00
[0D2h 0210 1] Bit Offset : 00
[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
[0D4h 0212 8] Address : 0000000000000000
[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
[0DCh 0220 1] Space ID : 00 [SystemMemory]
[0DDh 0221 1] Bit Width : 00
[0DEh 0222 1] Bit Offset : 00
[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
[0E0h 0224 8] Address : 0000000000000000
[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
[0E8h 0232 1] Space ID : 00 [SystemMemory]
[0E9h 0233 1] Bit Width : 00
[0EAh 0234 1] Bit Offset : 00
[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
[0ECh 0236 8] Address : 0000000000000000
[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
[0F4h 0244 1] Space ID : 00 [SystemMemory]
[0F5h 0245 1] Bit Width : 00
[0F6h 0246 1] Bit Offset : 00
[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
[0F8h 0248 8] Address : 0000000000000000
[100h 0256 12] Sleep Status Register : [Generic Address Structure]
[100h 0256 1] Space ID : 00 [SystemMemory]
[101h 0257 1] Bit Width : 00
[102h 0258 1] Bit Offset : 00
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
[104h 0260 8] Address : 0000000000000000
/**** ACPI table terminates in the middle of a data structure! (dump table) */
Raw Table Data: Length 268 (0x10C)
0000: 46 41 43 50 0C 01 00 00 05 55 42 4F 43 48 53 20 // FACP.....UBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............
* Expected ACPI Data Table [SRAT]
[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
[004h 0004 4] Table Length : 0000006A
[008h 0008 1] Revision : 03
[009h 0009 1] Checksum : 65
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Table Revision : 00000001
[028h 0040 8] Reserved : 0000000000000000
[030h 0048 1] Subtable Type : 03 [GICC Affinity]
[031h 0049 1] Length : 12
[032h 0050 4] Proximity Domain : 00000000
[036h 0054 4] Acpi Processor UID : 00000000
[03Ah 0058 4] Flags (decoded below) : 00000001
Enabled : 1
[03Eh 0062 4] Clock Domain : 00000000
[042h 0066 1] Subtable Type : 01 [Memory Affinity]
[043h 0067 1] Length : 28
[044h 0068 4] Proximity Domain : 00000000
[048h 0072 2] Reserved1 : 0000
[04Ah 0074 8] Base Address : 0000000040000000
[052h 0082 8] Address Length : 0000000008000000
[05Ah 0090 4] Reserved2 : 00000000
[05Eh 0094 4] Flags (decoded below) : 00000001
Enabled : 1
Hot Pluggable : 0
Non-Volatile : 0
[062h 0098 8] Reserved3 : 0000000000000000
Raw Table Data: Length 106 (0x6A)
0000: 53 52 41 54 6A 00 00 00 03 65 42 4F 43 48 53 20 // SRATj....eBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@..
0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................
0060: 00 00 00 00 00 00 00 00 00 00 // ..........
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
---
tests/data/acpi/virt/DSDT.acpihmatvirt | Bin 0 -> 5282 bytes
tests/data/acpi/virt/FACP.acpihmatvirt | Bin 0 -> 268 bytes
tests/data/acpi/virt/HMAT.acpihmatvirt | Bin 0 -> 288 bytes
tests/data/acpi/virt/SRAT.acpihmatvirt | Bin 0 -> 240 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 4 ----
5 files changed, 4 deletions(-)
diff --git a/tests/data/acpi/virt/DSDT.acpihmatvirt b/tests/data/acpi/virt/DSDT.acpihmatvirt
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..aee6ba017cd730948bfa93e91551eb10a6809293 100644
GIT binary patch
literal 5282
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diff --git a/tests/data/acpi/virt/FACP.acpihmatvirt b/tests/data/acpi/virt/FACP.acpihmatvirt
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1f764220f8533c427168e80ccf298604826a00b4 100644
GIT binary patch
literal 268
ycmZ>BbPnKQWME(ob@F%i2v%^42yj*a0-z8Bhz+8t3j|P&V`iYf6{t24%>w}Cy9NOO
literal 0
HcmV?d00001
diff --git a/tests/data/acpi/virt/HMAT.acpihmatvirt b/tests/data/acpi/virt/HMAT.acpihmatvirt
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6494d11b9fff54f8c403ec9e4893fdff72bde9c9 100644
GIT binary patch
literal 288
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HcmV?d00001
diff --git a/tests/data/acpi/virt/SRAT.acpihmatvirt b/tests/data/acpi/virt/SRAT.acpihmatvirt
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..691ef56e34bc84509270db316d908f5979c209bb 100644
GIT binary patch
literal 240
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HcmV?d00001
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 44594cae59..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,5 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/DSDT.acpihmatvirt",
-"tests/data/acpi/virt/FACP.acpihmatvirt",
-"tests/data/acpi/virt/HMAT.acpihmatvirt",
-"tests/data/acpi/virt/SRAT.acpihmatvirt",
--
2.25.1
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