* [PATCH v5 00/11] Support disabling TCG on ARM (part 2)
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
Cover from Samuel Ortiz from (part 1) [1]:
This patchset allows for building and running ARM targets with TCG
disabled. [...]
The rationale behind this work comes from the NEMU project where we're
trying to only support x86 and ARM 64-bit architectures, without
including the TCG code base. We can only do so if we can build and run
ARM binaries with TCG disabled.
v5:
- addressed Paolo/Richard/Thomas review comments from v4 [5].
v4 almost 2 years later... [2]:
- Rebased on Meson
- Addressed Richard review comments
- Addressed Claudio review comments
v3 almost 18 months later [3]:
- Rebased
- Addressed Thomas review comments
- Added Travis-CI job to keep building --disable-tcg on ARM
v2 [4]:
- Addressed review comments from Richard and Thomas from v1 [1]
Regards,
Phil.
[1]: https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02451.html
[2]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689168.html
[3]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg641796.html
[4]: https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg05003.html
[5]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg746041.html
Philippe Mathieu-Daudé (9):
exec: Restrict TCG specific headers
default-configs: Remove unnecessary SEMIHOSTING selection
target/arm: Restrict ARMv4 cpus to TCG accel
target/arm: Restrict ARMv5 cpus to TCG accel
target/arm: Restrict ARMv6 cpus to TCG accel
target/arm: Restrict ARMv7 R-profile cpus to TCG accel
target/arm: Restrict ARMv7 M-profile cpus to TCG accel
target/arm: Reorder meson.build rules
.travis.yml: Add a KVM-only Aarch64 job
Samuel Ortiz (1):
target/arm: Do not build TCG objects when TCG is off
Thomas Huth (1):
target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
default-configs/devices/aarch64-softmmu.mak | 1 -
default-configs/devices/arm-softmmu.mak | 28 --------
include/exec/helper-proto.h | 2 +
target/arm/cpu.h | 12 ----
hw/arm/realview.c | 7 +-
target/arm/cpu_tcg.c | 4 +-
target/arm/helper.c | 7 --
target/arm/m_helper-stub.c | 73 +++++++++++++++++++++
.travis.yml | 32 +++++++++
hw/arm/Kconfig | 66 +++++++++++++++++--
target/arm/meson.build | 28 +++++---
11 files changed, 196 insertions(+), 64 deletions(-)
create mode 100644 target/arm/m_helper-stub.c
--
2.26.2
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 01/11] exec: Restrict TCG specific headers
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
Fixes when building with --disable-tcg:
In file included from target/arm/helper.c:16:
include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory
42 | #include "tcg-runtime.h"
| ^~~~~~~~~~~~~~~
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/exec/helper-proto.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index 659f9298e8f..740bff3bb4d 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
#include "helper.h"
#include "trace/generated-helpers.h"
+#ifdef CONFIG_TCG
#include "tcg-runtime.h"
#include "plugin-helpers.h"
+#endif /* CONFIG_TCG */
#undef IN_HELPER_PROTO
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 01/11] exec: Restrict TCG specific headers
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
Fixes when building with --disable-tcg:
In file included from target/arm/helper.c:16:
include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory
42 | #include "tcg-runtime.h"
| ^~~~~~~~~~~~~~~
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/exec/helper-proto.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index 659f9298e8f..740bff3bb4d 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
#include "helper.h"
#include "trace/generated-helpers.h"
+#ifdef CONFIG_TCG
#include "tcg-runtime.h"
#include "plugin-helpers.h"
+#endif /* CONFIG_TCG */
#undef IN_HELPER_PROTO
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 02/11] default-configs: Remove unnecessary SEMIHOSTING selection
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
Commit 56b5170c87e ("semihosting: Move ARM semihosting code to
shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which
already selects SEMIHOSTING. No need to select it again.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 1 -
1 file changed, 1 deletion(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 0500156a0c7..341d439de6f 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -41,6 +41,5 @@ CONFIG_MICROBIT=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 02/11] default-configs: Remove unnecessary SEMIHOSTING selection
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
Commit 56b5170c87e ("semihosting: Move ARM semihosting code to
shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which
already selects SEMIHOSTING. No need to select it again.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 1 -
1 file changed, 1 deletion(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 0500156a0c7..341d439de6f 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -41,6 +41,5 @@ CONFIG_MICROBIT=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
The following machines are no more built when TCG is disabled:
- cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310)
- sx1 Siemens SX1 (OMAP310) V2
- sx1-v1 Siemens SX1 (OMAP310) V1
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 2 --
hw/arm/Kconfig | 8 ++++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 341d439de6f..8a53e637d23 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 223016bb4e8..7126d82f6ce 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,3 +1,7 @@
+config ARM_V4
+ bool
+ depends on TCG
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -31,6 +35,8 @@ config ARM_VIRT
config CHEETAH
bool
+ default y if TCG
+ select ARM_V4
select OMAP
select TSC210X
@@ -249,6 +255,8 @@ config COLLIE
config SX1
bool
+ default y if TCG
+ select ARM_V4
select OMAP
config VERSATILE
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv4 CPUs when TCG is available:
- StrongARM (SA1100/1110)
- OMAP1510 (TI925T)
The following machines are no more built when TCG is disabled:
- cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310)
- sx1 Siemens SX1 (OMAP310) V2
- sx1-v1 Siemens SX1 (OMAP310) V1
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 2 --
hw/arm/Kconfig | 8 ++++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 341d439de6f..8a53e637d23 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 223016bb4e8..7126d82f6ce 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -1,3 +1,7 @@
+config ARM_V4
+ bool
+ depends on TCG
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -31,6 +35,8 @@ config ARM_VIRT
config CHEETAH
bool
+ default y if TCG
+ select ARM_V4
select OMAP
select TSC210X
@@ -249,6 +255,8 @@ config COLLIE
config SX1
bool
+ default y if TCG
+ select ARM_V4
select OMAP
config VERSATILE
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 14:48 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 14:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Richard Henderson, Claudio Fontana,
Alex Bennée, qemu-arm
On 1/30/21 2:52 AM, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
> - StrongARM (SA1100/1110)
> - OMAP1510 (TI925T)
>
> The following machines are no more built when TCG is disabled:
>
> - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310)
> - sx1 Siemens SX1 (OMAP310) V2
> - sx1-v1 Siemens SX1 (OMAP310) V1
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> default-configs/devices/arm-softmmu.mak | 2 --
> hw/arm/Kconfig | 8 ++++++++
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
> index 341d439de6f..8a53e637d23 100644
> --- a/default-configs/devices/arm-softmmu.mak
> +++ b/default-configs/devices/arm-softmmu.mak
> @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y
> CONFIG_FSL_IMX31=y
> CONFIG_MUSICPAL=y
> CONFIG_MUSCA=y
> -CONFIG_CHEETAH=y
> -CONFIG_SX1=y
> CONFIG_NSERIES=y
> CONFIG_STELLARIS=y
> CONFIG_REALVIEW=y
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 223016bb4e8..7126d82f6ce 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,3 +1,7 @@
> +config ARM_V4
> + bool
> + depends on TCG
> +
> config ARM_VIRT
> bool
> imply PCI_DEVICES
> @@ -31,6 +35,8 @@ config ARM_VIRT
>
> config CHEETAH
> bool
> + default y if TCG
This doesn't work as being added to all targets...
> + select ARM_V4
> select OMAP
> select TSC210X
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-30 14:48 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 14:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Richard Henderson,
qemu-arm, Claudio Fontana, Paolo Bonzini, Alex Bennée,
Richard Henderson
On 1/30/21 2:52 AM, Philippe Mathieu-Daudé wrote:
> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> Only enable the following ARMv4 CPUs when TCG is available:
>
> - StrongARM (SA1100/1110)
> - OMAP1510 (TI925T)
>
> The following machines are no more built when TCG is disabled:
>
> - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310)
> - sx1 Siemens SX1 (OMAP310) V2
> - sx1-v1 Siemens SX1 (OMAP310) V1
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> default-configs/devices/arm-softmmu.mak | 2 --
> hw/arm/Kconfig | 8 ++++++++
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
> index 341d439de6f..8a53e637d23 100644
> --- a/default-configs/devices/arm-softmmu.mak
> +++ b/default-configs/devices/arm-softmmu.mak
> @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y
> CONFIG_FSL_IMX31=y
> CONFIG_MUSICPAL=y
> CONFIG_MUSCA=y
> -CONFIG_CHEETAH=y
> -CONFIG_SX1=y
> CONFIG_NSERIES=y
> CONFIG_STELLARIS=y
> CONFIG_REALVIEW=y
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 223016bb4e8..7126d82f6ce 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -1,3 +1,7 @@
> +config ARM_V4
> + bool
> + depends on TCG
> +
> config ARM_VIRT
> bool
> imply PCI_DEVICES
> @@ -31,6 +35,8 @@ config ARM_VIRT
>
> config CHEETAH
> bool
> + default y if TCG
This doesn't work as being added to all targets...
> + select ARM_V4
> select OMAP
> select TSC210X
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 15:37 ` Peter Maydell
-1 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-30 15:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, Richard Henderson, kvm-devel, Fam Zheng,
Thomas Huth, Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> KVM requires a cpu based on (at least) the ARMv7 architecture.
These days it requires ARMv8, because we dropped 32-bit host
support, and all 64-bit host CPUs are v8.
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-30 15:37 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-30 15:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Alex Bennée,
Richard Henderson, QEMU Developers, qemu-arm, Claudio Fontana,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson
On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> KVM requires a cpu based on (at least) the ARMv7 architecture.
These days it requires ARMv8, because we dropped 32-bit host
support, and all 64-bit host CPUs are v8.
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 15:37 ` Peter Maydell
@ 2021-01-30 18:36 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 18:36 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Richard Henderson, kvm-devel, Fam Zheng,
Thomas Huth, Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
Hi Peter,
On 1/30/21 4:37 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> These days it requires ARMv8, because we dropped 32-bit host
> support, and all 64-bit host CPUs are v8.
Oh, this comment is about the target, to justify it is pointless to
include pre-v7 target cpus/machines in a KVM-only binary.
I'll update as:
"KVM requires the target cpu based on (at least) the ARMv7
architecture."
Is that OK?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-30 18:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 18:36 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Alex Bennée,
Richard Henderson, QEMU Developers, qemu-arm, Claudio Fontana,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson
Hi Peter,
On 1/30/21 4:37 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> KVM requires a cpu based on (at least) the ARMv7 architecture.
>
> These days it requires ARMv8, because we dropped 32-bit host
> support, and all 64-bit host CPUs are v8.
Oh, this comment is about the target, to justify it is pointless to
include pre-v7 target cpus/machines in a KVM-only binary.
I'll update as:
"KVM requires the target cpu based on (at least) the ARMv7
architecture."
Is that OK?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 18:36 ` Philippe Mathieu-Daudé
@ 2021-01-30 18:54 ` Peter Maydell
-1 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-30 18:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, Richard Henderson, kvm-devel, Fam Zheng,
Thomas Huth, Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Peter,
>
> On 1/30/21 4:37 PM, Peter Maydell wrote:
> > On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>
> >> KVM requires a cpu based on (at least) the ARMv7 architecture.
> >
> > These days it requires ARMv8, because we dropped 32-bit host
> > support, and all 64-bit host CPUs are v8.
>
> Oh, this comment is about the target, to justify it is pointless to
> include pre-v7 target cpus/machines in a KVM-only binary.
>
> I'll update as:
>
> "KVM requires the target cpu based on (at least) the ARMv7
> architecture."
KVM requires the target CPU to be at least ARMv8, because
we only support the "host" cpu type, and all KVM host CPUs
are v8, which means you can't pass a v7 CPU as the target CPU.
(This used to not be true when we still supported running
KVM on a v7 CPU like the Cortex-A15, in which case you could
pass it to the guest.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-30 18:54 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2021-01-30 18:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Fam Zheng, Thomas Huth, kvm-devel, Alex Bennée,
Richard Henderson, QEMU Developers, qemu-arm, Claudio Fontana,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson
On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Peter,
>
> On 1/30/21 4:37 PM, Peter Maydell wrote:
> > On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>
> >> KVM requires a cpu based on (at least) the ARMv7 architecture.
> >
> > These days it requires ARMv8, because we dropped 32-bit host
> > support, and all 64-bit host CPUs are v8.
>
> Oh, this comment is about the target, to justify it is pointless to
> include pre-v7 target cpus/machines in a KVM-only binary.
>
> I'll update as:
>
> "KVM requires the target cpu based on (at least) the ARMv7
> architecture."
KVM requires the target CPU to be at least ARMv8, because
we only support the "host" cpu type, and all KVM host CPUs
are v8, which means you can't pass a v7 CPU as the target CPU.
(This used to not be true when we still supported running
KVM on a v7 CPU like the Cortex-A15, in which case you could
pass it to the guest.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
2021-01-30 18:54 ` Peter Maydell
@ 2021-01-31 15:35 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-31 15:35 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Richard Henderson, kvm-devel, Fam Zheng,
Thomas Huth, Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
On 1/30/21 7:54 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> Hi Peter,
>>
>> On 1/30/21 4:37 PM, Peter Maydell wrote:
>>> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>>
>>>> KVM requires a cpu based on (at least) the ARMv7 architecture.
>>>
>>> These days it requires ARMv8, because we dropped 32-bit host
>>> support, and all 64-bit host CPUs are v8.
>>
>> Oh, this comment is about the target, to justify it is pointless to
>> include pre-v7 target cpus/machines in a KVM-only binary.
>>
>> I'll update as:
>>
>> "KVM requires the target cpu based on (at least) the ARMv7
>> architecture."
>
> KVM requires the target CPU to be at least ARMv8, because
> we only support the "host" cpu type, and all KVM host CPUs
> are v8, which means you can't pass a v7 CPU as the target CPU.
> (This used to not be true when we still supported running
> KVM on a v7 CPU like the Cortex-A15, in which case you could
> pass it to the guest.)
Indeed:
$ qemu-system-aarch64 -M xilinx-zynq-a9
qemu-system-aarch64: KVM is not supported for this guest CPU type
qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0):
Invalid argument
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel
@ 2021-01-31 15:35 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-31 15:35 UTC (permalink / raw)
To: Peter Maydell
Cc: Fam Zheng, Thomas Huth, kvm-devel, Alex Bennée,
Richard Henderson, QEMU Developers, qemu-arm, Claudio Fontana,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson
On 1/30/21 7:54 PM, Peter Maydell wrote:
> On Sat, 30 Jan 2021 at 18:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> Hi Peter,
>>
>> On 1/30/21 4:37 PM, Peter Maydell wrote:
>>> On Sat, 30 Jan 2021 at 01:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>>
>>>> KVM requires a cpu based on (at least) the ARMv7 architecture.
>>>
>>> These days it requires ARMv8, because we dropped 32-bit host
>>> support, and all 64-bit host CPUs are v8.
>>
>> Oh, this comment is about the target, to justify it is pointless to
>> include pre-v7 target cpus/machines in a KVM-only binary.
>>
>> I'll update as:
>>
>> "KVM requires the target cpu based on (at least) the ARMv7
>> architecture."
>
> KVM requires the target CPU to be at least ARMv8, because
> we only support the "host" cpu type, and all KVM host CPUs
> are v8, which means you can't pass a v7 CPU as the target CPU.
> (This used to not be true when we still supported running
> KVM on a v7 CPU like the Cortex-A15, in which case you could
> pass it to the guest.)
Indeed:
$ qemu-system-aarch64 -M xilinx-zynq-a9
qemu-system-aarch64: KVM is not supported for this guest CPU type
qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0):
Invalid argument
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v5 04/11] target/arm: Restrict ARMv5 cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv5 CPUs when TCG is available:
- ARM926
- ARM946
- ARM1026
- XScale (PXA250/255/260/261/262/270)
The following machines are no more built when TCG is disabled:
- akita Sharp SL-C1000 (Akita) PDA (PXA270)
- ast2500-evb Aspeed AST2500 EVB (ARM1176)
- ast2600-evb Aspeed AST2600 EVB (Cortex A7)
- borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270)
- canon-a1100 Canon PowerShot A1100 IS
- collie Sharp SL-5500 (Collie) PDA (SA-1110)
- connex Gumstix Connex (PXA255)
- g220a-bmc Bytedance G220A BMC (ARM1176)
- imx25-pdk ARM i.MX25 PDK board (ARM926)
- integratorcp ARM Integrator/CP (ARM926EJ-S)
- mainstone Mainstone II (PXA27x)
- musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S)
- palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S)
- realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S)
- romulus-bmc OpenPOWER Romulus BMC (ARM1176)
- sonorapass-bmc OCP SonoraPass BMC (ARM1176)
- spitz Sharp SL-C3000 (Spitz) PDA (PXA270)
- supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S)
- swift-bmc OpenPOWER Swift BMC (ARM1176)
- tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7)
- terrier Sharp SL-C3200 (Terrier) PDA (PXA270)
- tosa Sharp SL-6000 (Tosa) PDA (PXA255)
- verdex Gumstix Verdex (PXA270)
- versatileab ARM Versatile/AB (ARM926EJ-S)
- versatilepb ARM Versatile/PB (ARM926EJ-S)
- witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176)
- z2 Zipit Z2 (PXA27x)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 12 ------------
hw/arm/realview.c | 5 ++++-
hw/arm/Kconfig | 23 +++++++++++++++++++++++
3 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 8a53e637d23..5b25fafc9ab 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_MPS2=y
CONFIG_RASPI=y
-CONFIG_DIGIC=y
CONFIG_SABRELITE=y
CONFIG_EMCRAFT_SF2=y
CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 0831159d158..cd37b501287 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -18,6 +18,7 @@
#include "hw/pci/pci.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
#include "hw/boards.h"
#include "hw/i2c/i2c.h"
#include "exec/address-spaces.h"
@@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = {
static void realview_machine_init(void)
{
- type_register_static(&realview_eb_type);
+ if (tcg_enabled()) {
+ type_register_static(&realview_eb_type);
+ }
type_register_static(&realview_eb_mpcore_type);
type_register_static(&realview_pb_a8_type);
type_register_static(&realview_pbx_a9_type);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7126d82f6ce..bdb8c63af7b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -2,6 +2,10 @@ config ARM_V4
bool
depends on TCG
+config ARM_V5
+ bool
+ depends on TCG
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -46,6 +50,8 @@ config CUBIEBOARD
config DIGIC
bool
+ default y if TCG
+ select ARM_V5
select PTIMER
select PFLASH_CFI02
@@ -76,6 +82,8 @@ config HIGHBANK
config INTEGRATOR
bool
+ default y if TCG
+ select ARM_V5
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -88,6 +96,7 @@ config INTEGRATOR
config MAINSTONE
bool
+ default y if TCG
select PXA2XX
select PFLASH_CFI01
select SMC91C111
@@ -102,6 +111,8 @@ config MUSCA
config MUSICPAL
bool
+ default y if TCG
+ select ARM_V5
select OR_IRQ
select BITBANG_I2C
select MARVELL_88W8618
@@ -142,6 +153,7 @@ config OMAP
config PXA2XX
bool
+ select ARM_V5
select FRAMEBUFFER
select I2C
select SERIAL
@@ -151,12 +163,14 @@ config PXA2XX
config GUMSTIX
bool
+ default y if TCG
select PFLASH_CFI01
select SMC91C111
select PXA2XX
config TOSA
bool
+ default y if TCG
select ZAURUS # scoop
select MICRODRIVE
select PXA2XX
@@ -164,6 +178,7 @@ config TOSA
config SPITZ
bool
+ default y if TCG
select ADS7846 # touch-screen controller
select MAX111X # A/D converter
select WM8750 # audio codec
@@ -176,6 +191,7 @@ config SPITZ
config Z2
bool
+ default y if TCG
select PFLASH_CFI01
select WM8750
select PL011 # UART
@@ -249,6 +265,7 @@ config STRONGARM
config COLLIE
bool
+ default y if TCG
select PFLASH_CFI01
select ZAURUS # scoop
select STRONGARM
@@ -261,6 +278,8 @@ config SX1
config VERSATILE
bool
+ default y if TCG
+ select ARM_V5
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -382,6 +401,8 @@ config NPCM7XX
config FSL_IMX25
bool
+ default y if TCG
+ select ARM_V5
select IMX
select IMX_FEC
select IMX_I2C
@@ -408,6 +429,8 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ default y if TCG
+ select ARM_V5
select DS1338
select FTGMAC100
select I2C
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 04/11] target/arm: Restrict ARMv5 cpus to TCG accel
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv5 CPUs when TCG is available:
- ARM926
- ARM946
- ARM1026
- XScale (PXA250/255/260/261/262/270)
The following machines are no more built when TCG is disabled:
- akita Sharp SL-C1000 (Akita) PDA (PXA270)
- ast2500-evb Aspeed AST2500 EVB (ARM1176)
- ast2600-evb Aspeed AST2600 EVB (Cortex A7)
- borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270)
- canon-a1100 Canon PowerShot A1100 IS
- collie Sharp SL-5500 (Collie) PDA (SA-1110)
- connex Gumstix Connex (PXA255)
- g220a-bmc Bytedance G220A BMC (ARM1176)
- imx25-pdk ARM i.MX25 PDK board (ARM926)
- integratorcp ARM Integrator/CP (ARM926EJ-S)
- mainstone Mainstone II (PXA27x)
- musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S)
- palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S)
- realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S)
- romulus-bmc OpenPOWER Romulus BMC (ARM1176)
- sonorapass-bmc OCP SonoraPass BMC (ARM1176)
- spitz Sharp SL-C3000 (Spitz) PDA (PXA270)
- supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S)
- swift-bmc OpenPOWER Swift BMC (ARM1176)
- tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7)
- terrier Sharp SL-C3200 (Terrier) PDA (PXA270)
- tosa Sharp SL-6000 (Tosa) PDA (PXA255)
- verdex Gumstix Verdex (PXA270)
- versatileab ARM Versatile/AB (ARM926EJ-S)
- versatilepb ARM Versatile/PB (ARM926EJ-S)
- witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176)
- z2 Zipit Z2 (PXA27x)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 12 ------------
hw/arm/realview.c | 5 ++++-
hw/arm/Kconfig | 23 +++++++++++++++++++++++
3 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 8a53e637d23..5b25fafc9ab 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
CONFIG_MUSCA=y
CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_MPS2=y
CONFIG_RASPI=y
-CONFIG_DIGIC=y
CONFIG_SABRELITE=y
CONFIG_EMCRAFT_SF2=y
CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 0831159d158..cd37b501287 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -18,6 +18,7 @@
#include "hw/pci/pci.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
+#include "sysemu/tcg.h"
#include "hw/boards.h"
#include "hw/i2c/i2c.h"
#include "exec/address-spaces.h"
@@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = {
static void realview_machine_init(void)
{
- type_register_static(&realview_eb_type);
+ if (tcg_enabled()) {
+ type_register_static(&realview_eb_type);
+ }
type_register_static(&realview_eb_mpcore_type);
type_register_static(&realview_pb_a8_type);
type_register_static(&realview_pbx_a9_type);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7126d82f6ce..bdb8c63af7b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -2,6 +2,10 @@ config ARM_V4
bool
depends on TCG
+config ARM_V5
+ bool
+ depends on TCG
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -46,6 +50,8 @@ config CUBIEBOARD
config DIGIC
bool
+ default y if TCG
+ select ARM_V5
select PTIMER
select PFLASH_CFI02
@@ -76,6 +82,8 @@ config HIGHBANK
config INTEGRATOR
bool
+ default y if TCG
+ select ARM_V5
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -88,6 +96,7 @@ config INTEGRATOR
config MAINSTONE
bool
+ default y if TCG
select PXA2XX
select PFLASH_CFI01
select SMC91C111
@@ -102,6 +111,8 @@ config MUSCA
config MUSICPAL
bool
+ default y if TCG
+ select ARM_V5
select OR_IRQ
select BITBANG_I2C
select MARVELL_88W8618
@@ -142,6 +153,7 @@ config OMAP
config PXA2XX
bool
+ select ARM_V5
select FRAMEBUFFER
select I2C
select SERIAL
@@ -151,12 +163,14 @@ config PXA2XX
config GUMSTIX
bool
+ default y if TCG
select PFLASH_CFI01
select SMC91C111
select PXA2XX
config TOSA
bool
+ default y if TCG
select ZAURUS # scoop
select MICRODRIVE
select PXA2XX
@@ -164,6 +178,7 @@ config TOSA
config SPITZ
bool
+ default y if TCG
select ADS7846 # touch-screen controller
select MAX111X # A/D converter
select WM8750 # audio codec
@@ -176,6 +191,7 @@ config SPITZ
config Z2
bool
+ default y if TCG
select PFLASH_CFI01
select WM8750
select PL011 # UART
@@ -249,6 +265,7 @@ config STRONGARM
config COLLIE
bool
+ default y if TCG
select PFLASH_CFI01
select ZAURUS # scoop
select STRONGARM
@@ -261,6 +278,8 @@ config SX1
config VERSATILE
bool
+ default y if TCG
+ select ARM_V5
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -382,6 +401,8 @@ config NPCM7XX
config FSL_IMX25
bool
+ default y if TCG
+ select ARM_V5
select IMX
select IMX_FEC
select IMX_I2C
@@ -408,6 +429,8 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ default y if TCG
+ select ARM_V5
select DS1338
select FTGMAC100
select I2C
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 05/11] target/arm: Restrict ARMv6 cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
The following machines are no more built when TCG is disabled:
- kzm ARM KZM Emulation Baseboard (ARM1136)
- microbit BBC micro:bit (Cortex-M0)
- n800 Nokia N800 tablet aka. RX-34 (OMAP2420)
- n810 Nokia N810 tablet aka. RX-44 (OMAP2420)
- realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 2 --
hw/arm/realview.c | 2 +-
hw/arm/Kconfig | 11 +++++++++++
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 5b25fafc9ab..ee80bf15150 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_FSL_IMX31=y
CONFIG_MUSCA=y
-CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index cd37b501287..57a37608e39 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -463,8 +463,8 @@ static void realview_machine_init(void)
{
if (tcg_enabled()) {
type_register_static(&realview_eb_type);
+ type_register_static(&realview_eb_mpcore_type);
}
- type_register_static(&realview_eb_mpcore_type);
type_register_static(&realview_pb_a8_type);
type_register_static(&realview_pbx_a9_type);
}
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index bdb8c63af7b..daab7081994 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -6,6 +6,11 @@ config ARM_V5
bool
depends on TCG
+config ARM_V6
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -131,6 +136,8 @@ config NETDUINOPLUS2
config NSERIES
bool
+ default y if TCG
+ select ARM_V6
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -411,6 +418,8 @@ config FSL_IMX25
config FSL_IMX31
bool
+ default y if TCG
+ select ARM_V6
select SERIAL
select IMX
select IMX_I2C
@@ -488,11 +497,13 @@ config FSL_IMX6UL
config MICROBIT
bool
+ default y if TCG
select NRF51_SOC
config NRF51_SOC
bool
select I2C
+ select ARM_V6
select ARM_V7M
select UNIMP
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 05/11] target/arm: Restrict ARMv6 cpus to TCG accel
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
KVM requires a cpu based on (at least) the ARMv7 architecture.
Only enable the following ARMv6 CPUs when TCG is available:
- ARM1136
- ARM1176
- ARM11MPCore
- Cortex-M0
The following machines are no more built when TCG is disabled:
- kzm ARM KZM Emulation Baseboard (ARM1136)
- microbit BBC micro:bit (Cortex-M0)
- n800 Nokia N800 tablet aka. RX-34 (OMAP2420)
- n810 Nokia N810 tablet aka. RX-44 (OMAP2420)
- realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 2 --
hw/arm/realview.c | 2 +-
hw/arm/Kconfig | 11 +++++++++++
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index 5b25fafc9ab..ee80bf15150 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
CONFIG_HIGHBANK=y
-CONFIG_FSL_IMX31=y
CONFIG_MUSCA=y
-CONFIG_NSERIES=y
CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index cd37b501287..57a37608e39 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -463,8 +463,8 @@ static void realview_machine_init(void)
{
if (tcg_enabled()) {
type_register_static(&realview_eb_type);
+ type_register_static(&realview_eb_mpcore_type);
}
- type_register_static(&realview_eb_mpcore_type);
type_register_static(&realview_pb_a8_type);
type_register_static(&realview_pbx_a9_type);
}
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index bdb8c63af7b..daab7081994 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -6,6 +6,11 @@ config ARM_V5
bool
depends on TCG
+config ARM_V6
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -131,6 +136,8 @@ config NETDUINOPLUS2
config NSERIES
bool
+ default y if TCG
+ select ARM_V6
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -411,6 +418,8 @@ config FSL_IMX25
config FSL_IMX31
bool
+ default y if TCG
+ select ARM_V6
select SERIAL
select IMX
select IMX_I2C
@@ -488,11 +497,13 @@ config FSL_IMX6UL
config MICROBIT
bool
+ default y if TCG
select NRF51_SOC
config NRF51_SOC
bool
select I2C
+ select ARM_V6
select ARM_V7M
select UNIMP
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
A KVM-only build won't be able to run R-profile cpus.
Only enable the following ARMv7 R-Profile CPUs when TCG is available:
- Cortex-R5
- Cortex-R5F
The following machine is no more built when TCG is disabled:
- xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/aarch64-softmmu.mak | 1 -
hw/arm/Kconfig | 7 +++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak
index 958b1e08e40..a4202f56817 100644
--- a/default-configs/devices/aarch64-softmmu.mak
+++ b/default-configs/devices/aarch64-softmmu.mak
@@ -3,6 +3,5 @@
# We support all the 32 bit boards so need all their config
include arm-softmmu.mak
-CONFIG_XLNX_ZYNQMP_ARM=y
CONFIG_XLNX_VERSAL=y
CONFIG_SBSA_REF=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index daab7081994..320428bf97e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -11,6 +11,11 @@ config ARM_V6
depends on TCG
select ARM_COMPATIBLE_SEMIHOSTING
+config ARM_V7R
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -377,8 +382,10 @@ config STM32F405_SOC
config XLNX_ZYNQMP_ARM
bool
+ default y if TCG
select AHCI
select ARM_GIC
+ select ARM_V7R
select CADENCE
select DDC
select DPCD
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
A KVM-only build won't be able to run R-profile cpus.
Only enable the following ARMv7 R-Profile CPUs when TCG is available:
- Cortex-R5
- Cortex-R5F
The following machine is no more built when TCG is disabled:
- xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/aarch64-softmmu.mak | 1 -
hw/arm/Kconfig | 7 +++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak
index 958b1e08e40..a4202f56817 100644
--- a/default-configs/devices/aarch64-softmmu.mak
+++ b/default-configs/devices/aarch64-softmmu.mak
@@ -3,6 +3,5 @@
# We support all the 32 bit boards so need all their config
include arm-softmmu.mak
-CONFIG_XLNX_ZYNQMP_ARM=y
CONFIG_XLNX_VERSAL=y
CONFIG_SBSA_REF=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index daab7081994..320428bf97e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -11,6 +11,11 @@ config ARM_V6
depends on TCG
select ARM_COMPATIBLE_SEMIHOSTING
+config ARM_V7R
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -377,8 +382,10 @@ config STM32F405_SOC
config XLNX_ZYNQMP_ARM
bool
+ default y if TCG
select AHCI
select ARM_GIC
+ select ARM_V7R
select CADENCE
select DDC
select DPCD
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
A KVM-only build won't be able to run M-profile cpus.
Only enable the following ARMv7 M-Profile CPUs when TCG is available:
- Cortex-M0
- Cortex-M3
- Cortex-M4
- Cortex-M33
The following machines are no more built when TCG is disabled:
- emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010)
- highbank Calxeda Highbank (ECX-1000)
- lm3s6965evb Stellaris LM3S6965EVB
- lm3s811evb Stellaris LM3S811EVB
- midway Calxeda Midway (ECX-2000)
- mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3
- mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4
- mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7
- mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33
- mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3
- mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33
- musca-a ARM Musca-A board (dual Cortex-M33)
- musca-b1 ARM Musca-B1 board (dual Cortex-M33)
- netduino2 Netduino 2 Machine
- netduinoplus2 Netduino Plus 2 Machine
We don't need to enforce CONFIG_ARM_V7M in default-configs anymore.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 11 -----------
hw/arm/Kconfig | 17 +++++++++++++----
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index ee80bf15150..b72926b8fce 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -1,28 +1,17 @@
# Default configuration for arm-softmmu
-# TODO: ARM_V7M is currently always required - make this more flexible!
-CONFIG_ARM_V7M=y
-
# CONFIG_PCI_DEVICES=n
# CONFIG_TEST_DEVICES=n
CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
CONFIG_NPCM7XX=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 320428bf97e..f56c05c00a8 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -16,6 +16,12 @@ config ARM_V7R
depends on TCG
select ARM_COMPATIBLE_SEMIHOSTING
+config ARM_V7M
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+ select PTIMER
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -78,6 +84,7 @@ config EXYNOS4
config HIGHBANK
bool
+ default y if TCG
select A9MPCORE
select A15MPCORE
select AHCI
@@ -113,6 +120,7 @@ config MAINSTONE
config MUSCA
bool
+ default y if TCG
select ARMSSE
select PL011
select PL031
@@ -133,10 +141,12 @@ config MUSICPAL
config NETDUINO2
bool
+ default y if TCG
select STM32F205_SOC
config NETDUINOPLUS2
bool
+ default y if TCG
select STM32F405_SOC
config NSERIES
@@ -258,6 +268,7 @@ config SABRELITE
config STELLARIS
bool
+ default y if TCG
select ARM_V7M
select CMSDK_APB_WATCHDOG
select I2C
@@ -331,10 +342,6 @@ config ZYNQ
select XILINX_SPIPS
select ZYNQ_DEVCFG
-config ARM_V7M
- bool
- select PTIMER
-
config ALLWINNER_A10
bool
select AHCI
@@ -463,6 +470,7 @@ config ASPEED_SOC
config MPS2
bool
+ default y if TCG
select ARMSSE
select LAN9118
select MPS2_FPGAIO
@@ -516,6 +524,7 @@ config NRF51_SOC
config EMCRAFT_SF2
bool
+ default y if TCG
select MSF2
select SSI_M25P80
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
A KVM-only build won't be able to run M-profile cpus.
Only enable the following ARMv7 M-Profile CPUs when TCG is available:
- Cortex-M0
- Cortex-M3
- Cortex-M4
- Cortex-M33
The following machines are no more built when TCG is disabled:
- emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010)
- highbank Calxeda Highbank (ECX-1000)
- lm3s6965evb Stellaris LM3S6965EVB
- lm3s811evb Stellaris LM3S811EVB
- midway Calxeda Midway (ECX-2000)
- mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3
- mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4
- mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7
- mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33
- mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3
- mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33
- musca-a ARM Musca-A board (dual Cortex-M33)
- musca-b1 ARM Musca-B1 board (dual Cortex-M33)
- netduino2 Netduino 2 Machine
- netduinoplus2 Netduino Plus 2 Machine
We don't need to enforce CONFIG_ARM_V7M in default-configs anymore.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
default-configs/devices/arm-softmmu.mak | 11 -----------
hw/arm/Kconfig | 17 +++++++++++++----
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index ee80bf15150..b72926b8fce 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -1,28 +1,17 @@
# Default configuration for arm-softmmu
-# TODO: ARM_V7M is currently always required - make this more flexible!
-CONFIG_ARM_V7M=y
-
# CONFIG_PCI_DEVICES=n
# CONFIG_TEST_DEVICES=n
CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
CONFIG_NPCM7XX=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 320428bf97e..f56c05c00a8 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -16,6 +16,12 @@ config ARM_V7R
depends on TCG
select ARM_COMPATIBLE_SEMIHOSTING
+config ARM_V7M
+ bool
+ depends on TCG
+ select ARM_COMPATIBLE_SEMIHOSTING
+ select PTIMER
+
config ARM_VIRT
bool
imply PCI_DEVICES
@@ -78,6 +84,7 @@ config EXYNOS4
config HIGHBANK
bool
+ default y if TCG
select A9MPCORE
select A15MPCORE
select AHCI
@@ -113,6 +120,7 @@ config MAINSTONE
config MUSCA
bool
+ default y if TCG
select ARMSSE
select PL011
select PL031
@@ -133,10 +141,12 @@ config MUSICPAL
config NETDUINO2
bool
+ default y if TCG
select STM32F205_SOC
config NETDUINOPLUS2
bool
+ default y if TCG
select STM32F405_SOC
config NSERIES
@@ -258,6 +268,7 @@ config SABRELITE
config STELLARIS
bool
+ default y if TCG
select ARM_V7M
select CMSDK_APB_WATCHDOG
select I2C
@@ -331,10 +342,6 @@ config ZYNQ
select XILINX_SPIPS
select ZYNQ_DEVCFG
-config ARM_V7M
- bool
- select PTIMER
-
config ALLWINNER_A10
bool
select AHCI
@@ -463,6 +470,7 @@ config ASPEED_SOC
config MPS2
bool
+ default y if TCG
select ARMSSE
select LAN9118
select MPS2_FPGAIO
@@ -516,6 +524,7 @@ config NRF51_SOC
config EMCRAFT_SF2
bool
+ default y if TCG
select MSF2
select SSI_M25P80
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Philippe Mathieu-Daudé
From: Thomas Huth <thuth@redhat.com>
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other code without CONFIG_ARM_V7M.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190903154810.27365-4-thuth@redhat.com>
[PMD: Keep m_helper-stub.c but extend it, rewrite the rest]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Rewrite since v3, therefore removed Richard R-b tag.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.h | 12 -------
target/arm/cpu_tcg.c | 4 ++-
target/arm/helper.c | 7 ----
target/arm/m_helper-stub.c | 73 ++++++++++++++++++++++++++++++++++++++
target/arm/meson.build | 4 ++-
5 files changed, 79 insertions(+), 21 deletions(-)
create mode 100644 target/arm/m_helper-stub.c
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d080239863c..0bd0e51e498 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
/* Interface between CPU and Interrupt controller. */
#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_can_take_pending_exception(void *opaque);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
-{
- return true;
-}
-#endif
/**
* armv7m_nvic_set_pending: mark the specified exception as pending
* @opaque: the NVIC
@@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque);
* @secure: the security state to test
* This corresponds to the pseudocode IsReqExecPriNeg().
*/
-#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
-{
- return false;
-}
#endif
/* Interface for defining coprocessor registers.
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98544db2df3..3e1c9b40353 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifndef CONFIG_USER_ONLY
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
+#endif /* CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->info = data;
#ifndef CONFIG_USER_ONLY
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 47e266d7e64..fe3d0291f9c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
-#ifndef CONFIG_TCG
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
- g_assert_not_reached();
-}
-#endif
-
ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
{
ARMMMUIdx idx;
diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c
new file mode 100644
index 00000000000..6d751424e86
--- /dev/null
+++ b/target/arm/m_helper-stub.c
@@ -0,0 +1,73 @@
+/*
+ * ARM V7M related stubs.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "internals.h"
+
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+ g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+{
+ g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
+{
+ g_assert_not_reached();
+}
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
+{
+ g_assert_not_reached();
+}
+
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+ g_assert_not_reached();
+}
+
+#ifndef CONFIG_USER_ONLY
+
+bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ g_assert_not_reached();
+}
+
+void arm_v7m_cpu_do_interrupt(CPUState *cs)
+{
+ g_assert_not_reached();
+}
+
+#endif /* CONFIG_USER_ONLY */
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 15b936c1010..6c6081966cd 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -21,7 +21,6 @@
'gdbstub.c',
'helper.c',
'iwmmxt_helper.c',
- 'm_helper.c',
'neon_helper.c',
'op_helper.c',
'tlb_helper.c',
@@ -32,6 +31,9 @@
))
arm_ss.add(zlib)
+arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
+arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
+
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
From: Thomas Huth <thuth@redhat.com>
We've already got the CONFIG_ARM_V7M switch, but it currently can
not be disabled yet. The m_helper.c code should not be compiled
into the binary if the switch is not enabled. We also have to
provide some stubs in a separate file to make sure that we still
can link the other code without CONFIG_ARM_V7M.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190903154810.27365-4-thuth@redhat.com>
[PMD: Keep m_helper-stub.c but extend it, rewrite the rest]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Rewrite since v3, therefore removed Richard R-b tag.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.h | 12 -------
target/arm/cpu_tcg.c | 4 ++-
target/arm/helper.c | 7 ----
target/arm/m_helper-stub.c | 73 ++++++++++++++++++++++++++++++++++++++
target/arm/meson.build | 4 ++-
5 files changed, 79 insertions(+), 21 deletions(-)
create mode 100644 target/arm/m_helper-stub.c
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d080239863c..0bd0e51e498 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
/* Interface between CPU and Interrupt controller. */
#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_can_take_pending_exception(void *opaque);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
-{
- return true;
-}
-#endif
/**
* armv7m_nvic_set_pending: mark the specified exception as pending
* @opaque: the NVIC
@@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque);
* @secure: the security state to test
* This corresponds to the pseudocode IsReqExecPriNeg().
*/
-#ifndef CONFIG_USER_ONLY
bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
-{
- return false;
-}
#endif
/* Interface for defining coprocessor registers.
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 98544db2df3..3e1c9b40353 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifndef CONFIG_USER_ONLY
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
+#endif /* CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->info = data;
#ifndef CONFIG_USER_ONLY
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 47e266d7e64..fe3d0291f9c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
-#ifndef CONFIG_TCG
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
- g_assert_not_reached();
-}
-#endif
-
ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
{
ARMMMUIdx idx;
diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c
new file mode 100644
index 00000000000..6d751424e86
--- /dev/null
+++ b/target/arm/m_helper-stub.c
@@ -0,0 +1,73 @@
+/*
+ * ARM V7M related stubs.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "internals.h"
+
+void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
+{
+ g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+{
+ g_assert_not_reached();
+}
+
+uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_preserve_fp_state)(CPUARMState *env)
+{
+ g_assert_not_reached();
+}
+
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)
+{
+ g_assert_not_reached();
+}
+
+void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)
+{
+ g_assert_not_reached();
+}
+
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+ g_assert_not_reached();
+}
+
+#ifndef CONFIG_USER_ONLY
+
+bool armv7m_nvic_can_take_pending_exception(void *opaque)
+{
+ g_assert_not_reached();
+}
+
+void arm_v7m_cpu_do_interrupt(CPUState *cs)
+{
+ g_assert_not_reached();
+}
+
+#endif /* CONFIG_USER_ONLY */
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 15b936c1010..6c6081966cd 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -21,7 +21,6 @@
'gdbstub.c',
'helper.c',
'iwmmxt_helper.c',
- 'm_helper.c',
'neon_helper.c',
'op_helper.c',
'tlb_helper.c',
@@ -32,6 +31,9 @@
))
arm_ss.add(zlib)
+arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
+arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
+
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 09/11] target/arm: Reorder meson.build rules
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Reorder the rules to make this file easier to modify.
No logical change introduced in this commit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/meson.build | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6c6081966cd..aac9a383a61 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -14,31 +14,36 @@
arm_ss = ss.source_set()
arm_ss.add(gen)
+arm_ss.add(zlib)
arm_ss.add(files(
'cpu.c',
- 'crypto_helper.c',
- 'debug_helper.c',
'gdbstub.c',
'helper.c',
+ 'vfp_helper.c',
+))
+
+arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+ 'cpu64.c',
+ 'gdbstub64.c',
+))
+
+arm_ss.add(files(
+ 'crypto_helper.c',
+ 'debug_helper.c',
'iwmmxt_helper.c',
'neon_helper.c',
'op_helper.c',
'tlb_helper.c',
'translate.c',
'vec_helper.c',
- 'vfp_helper.c',
'cpu_tcg.c',
))
-arm_ss.add(zlib)
-
arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
- 'cpu64.c',
- 'gdbstub64.c',
'helper-a64.c',
'mte_helper.c',
'pauth_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 09/11] target/arm: Reorder meson.build rules
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Reorder the rules to make this file easier to modify.
No logical change introduced in this commit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/meson.build | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 6c6081966cd..aac9a383a61 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -14,31 +14,36 @@
arm_ss = ss.source_set()
arm_ss.add(gen)
+arm_ss.add(zlib)
arm_ss.add(files(
'cpu.c',
- 'crypto_helper.c',
- 'debug_helper.c',
'gdbstub.c',
'helper.c',
+ 'vfp_helper.c',
+))
+
+arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+ 'cpu64.c',
+ 'gdbstub64.c',
+))
+
+arm_ss.add(files(
+ 'crypto_helper.c',
+ 'debug_helper.c',
'iwmmxt_helper.c',
'neon_helper.c',
'op_helper.c',
'tlb_helper.c',
'translate.c',
'vec_helper.c',
- 'vfp_helper.c',
'cpu_tcg.c',
))
-arm_ss.add(zlib)
-
arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
- 'cpu64.c',
- 'gdbstub64.c',
'helper-a64.c',
'mte_helper.c',
'pauth_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 10/11] target/arm: Do not build TCG objects when TCG is off
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm,
Samuel Ortiz, Philippe Mathieu-Daudé
From: Samuel Ortiz <sameo@linux.intel.com>
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
[PMD: Heavily rebased during more than 2 years then finally rewritten]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/meson.build | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index aac9a383a61..11b7c0e18fe 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -27,7 +27,8 @@
'gdbstub64.c',
))
-arm_ss.add(files(
+arm_tcg_ss = ss.source_set()
+arm_tcg_ss.add(files(
'crypto_helper.c',
'debug_helper.c',
'iwmmxt_helper.c',
@@ -38,12 +39,12 @@
'vec_helper.c',
'cpu_tcg.c',
))
-arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
+arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
-arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files(
'helper-a64.c',
'mte_helper.c',
'pauth_helper.c',
@@ -52,14 +53,16 @@
'translate-sve.c',
))
+arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss)
+
arm_softmmu_ss = ss.source_set()
arm_softmmu_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'machine.c',
'monitor.c',
- 'psci.c',
))
+arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c'))
target_arch += {'arm': arm_ss}
target_softmmu_arch += {'arm': arm_softmmu_ss}
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 10/11] target/arm: Do not build TCG objects when TCG is off
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, Samuel Ortiz, kvm,
Alex Bennée, Richard Henderson, Philippe Mathieu-Daudé,
qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
From: Samuel Ortiz <sameo@linux.intel.com>
We can now safely turn all TCG dependent build off when CONFIG_TCG is
off. This allows building ARM binaries with --disable-tcg.
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
[PMD: Heavily rebased during more than 2 years then finally rewritten]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/meson.build | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index aac9a383a61..11b7c0e18fe 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -27,7 +27,8 @@
'gdbstub64.c',
))
-arm_ss.add(files(
+arm_tcg_ss = ss.source_set()
+arm_tcg_ss.add(files(
'crypto_helper.c',
'debug_helper.c',
'iwmmxt_helper.c',
@@ -38,12 +39,12 @@
'vec_helper.c',
'cpu_tcg.c',
))
-arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
+arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c'))
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
-arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files(
'helper-a64.c',
'mte_helper.c',
'pauth_helper.c',
@@ -52,14 +53,16 @@
'translate-sve.c',
))
+arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss)
+
arm_softmmu_ss = ss.source_set()
arm_softmmu_ss.add(files(
'arch_dump.c',
'arm-powerctl.c',
'machine.c',
'monitor.c',
- 'psci.c',
))
+arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c'))
target_arch += {'arm': arm_ss}
target_softmmu_arch += {'arm': arm_softmmu_ss}
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v5 11/11] .travis.yml: Add a KVM-only Aarch64 job
2021-01-30 1:52 ` Philippe Mathieu-Daudé
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Richard Henderson, kvm, Peter Maydell, Fam Zheng, Thomas Huth,
Paolo Bonzini, Philippe Mathieu-Daudé,
Richard Henderson, Claudio Fontana, Alex Bennée, qemu-arm
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
We explicitly modify default-configs/aarch64-softmmu.mak to
only select the 'virt' and 'SBSA-REF' machines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Job ran for 7 min 30 sec
https://travis-ci.org/github/philmd/qemu/jobs/731428859
---
.travis.yml | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 5f1dea873ec..4f1d662b5fc 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -264,6 +264,38 @@ jobs:
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
- UNRELIABLE=true
+ - name: "[aarch64] GCC (disable-tcg)"
+ arch: arm64
+ dist: focal
+ addons:
+ apt_packages:
+ - libaio-dev
+ - libattr1-dev
+ - libbrlapi-dev
+ - libcap-ng-dev
+ - libgcrypt20-dev
+ - libgnutls28-dev
+ - libgtk-3-dev
+ - libiscsi-dev
+ - liblttng-ust-dev
+ - libncurses5-dev
+ - libnfs-dev
+ - libnss3-dev
+ - libpixman-1-dev
+ - libpng-dev
+ - librados-dev
+ - libsdl2-dev
+ - libseccomp-dev
+ - liburcu-dev
+ - libusb-1.0-0-dev
+ - libvdeplug-dev
+ - libvte-2.91-dev
+ - ninja-build
+ env:
+ - CONFIG="--disable-containers --disable-tcg --enable-kvm --disable-xen --disable-tools --disable-docs"
+ - TEST_CMD="make check-unit"
+ - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64"
+
- name: "[ppc64] GCC check-tcg"
arch: ppc64le
dist: focal
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v5 11/11] .travis.yml: Add a KVM-only Aarch64 job
@ 2021-01-30 1:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-30 1:52 UTC (permalink / raw)
To: qemu-devel
Cc: Fam Zheng, Peter Maydell, Thomas Huth, kvm, Alex Bennée,
Richard Henderson, qemu-arm, Claudio Fontana, Paolo Bonzini,
Philippe Mathieu-Daudé,
Richard Henderson
From: Philippe Mathieu-Daudé <philmd@redhat.com>
Add a job to build QEMU on Aarch64 with TCG disabled, so
this configuration won't bitrot over time.
We explicitly modify default-configs/aarch64-softmmu.mak to
only select the 'virt' and 'SBSA-REF' machines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Job ran for 7 min 30 sec
https://travis-ci.org/github/philmd/qemu/jobs/731428859
---
.travis.yml | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/.travis.yml b/.travis.yml
index 5f1dea873ec..4f1d662b5fc 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -264,6 +264,38 @@ jobs:
- CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}"
- UNRELIABLE=true
+ - name: "[aarch64] GCC (disable-tcg)"
+ arch: arm64
+ dist: focal
+ addons:
+ apt_packages:
+ - libaio-dev
+ - libattr1-dev
+ - libbrlapi-dev
+ - libcap-ng-dev
+ - libgcrypt20-dev
+ - libgnutls28-dev
+ - libgtk-3-dev
+ - libiscsi-dev
+ - liblttng-ust-dev
+ - libncurses5-dev
+ - libnfs-dev
+ - libnss3-dev
+ - libpixman-1-dev
+ - libpng-dev
+ - librados-dev
+ - libsdl2-dev
+ - libseccomp-dev
+ - liburcu-dev
+ - libusb-1.0-0-dev
+ - libvdeplug-dev
+ - libvte-2.91-dev
+ - ninja-build
+ env:
+ - CONFIG="--disable-containers --disable-tcg --enable-kvm --disable-xen --disable-tools --disable-docs"
+ - TEST_CMD="make check-unit"
+ - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64"
+
- name: "[ppc64] GCC check-tcg"
arch: ppc64le
dist: focal
--
2.26.2
^ permalink raw reply related [flat|nested] 34+ messages in thread