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From: Matthias Brugger <matthias.bgg@gmail.com>
To: argus.lin@mediatek.com, Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>
Cc: Chenglin Xu <chenglin.xu@mediatek.com>,
	Sean Wang <sean.wang@mediatek.com>,
	wsd_upstream@mediatek.com, henryc.chen@mediatek.com,
	flora.fu@mediatek.com, Chen Zhong <chen.zhong@mediatek.com>,
	Christophe Jaillet <christophe.jaillet@wanadoo.fr>,
	"shailendra . v" <shailendra.v@samsung.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org
Subject: Re: [PATCH V4 2/8] soc: mediatek: pwrap: add caps flag for pwrap
Date: Wed, 2 May 2018 12:27:26 +0200	[thread overview]
Message-ID: <41027d71-a0b5-b78d-e9bf-aec4beb05a59@gmail.com> (raw)
In-Reply-To: <20180502092112.3991-3-argus.lin@mediatek.com>



On 05/02/2018 11:21 AM, argus.lin@mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> We use caps to describe pwrap's capability, used
> to replace has_bridge flag for single meaning.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index e9e054a15b7d..3a25ff6e6907 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -76,6 +76,12 @@
>  #define PWRAP_SLV_CAP_SECURITY	BIT(2)
>  #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
>  
> +/* Group of bits used for shown pwrap capability */
> +#define PWRAP_CAP_BRIDGE	BIT(0)
> +#define PWRAP_CAP_RESET		BIT(1)
> +#define PWRAP_CAP_DCM		BIT(2)
> +#define PWRAP_CAP_INT1_EN	BIT(3)
> +

You are missing the logic to handle the caps.
With out this logic, this patch is useless.

Regards,
Matthias

>  /* defines for slave device wrapper registers */
>  enum dew_regs {
>  	PWRAP_DEW_BASE,
> @@ -684,6 +690,8 @@ struct pmic_wrapper_type {
>  	u32 spi_w;
>  	u32 wdt_src;
>  	unsigned int has_bridge:1;
> +	/* Flags indicating the capability for the target pwrap */
> +	u8 caps;
>  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
>  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
>  };
> @@ -1394,6 +1402,7 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 0,
> +	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_mt2701_init_reg_clock,
>  	.init_soc_specific = pwrap_mt2701_init_soc_specific,
>  };
> @@ -1406,6 +1415,7 @@ static const struct pmic_wrapper_type pwrap_mt7622 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 0,
> +	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_common_init_reg_clock,
>  	.init_soc_specific = pwrap_mt7622_init_soc_specific,
>  };
> @@ -1418,6 +1428,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 1,
> +	.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_common_init_reg_clock,
>  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
>  };
> -- 
> 2.12.5
> 
> ************* Email Confidentiality Notice ********************
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> 

WARNING: multiple messages have this Message-ID (diff)
From: matthias.bgg@gmail.com (Matthias Brugger)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V4 2/8] soc: mediatek: pwrap: add caps flag for pwrap
Date: Wed, 2 May 2018 12:27:26 +0200	[thread overview]
Message-ID: <41027d71-a0b5-b78d-e9bf-aec4beb05a59@gmail.com> (raw)
In-Reply-To: <20180502092112.3991-3-argus.lin@mediatek.com>



On 05/02/2018 11:21 AM, argus.lin at mediatek.com wrote:
> From: Argus Lin <argus.lin@mediatek.com>
> 
> We use caps to describe pwrap's capability, used
> to replace has_bridge flag for single meaning.
> 
> Signed-off-by: Argus Lin <argus.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index e9e054a15b7d..3a25ff6e6907 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -76,6 +76,12 @@
>  #define PWRAP_SLV_CAP_SECURITY	BIT(2)
>  #define HAS_CAP(_c, _x)	(((_c) & (_x)) == (_x))
>  
> +/* Group of bits used for shown pwrap capability */
> +#define PWRAP_CAP_BRIDGE	BIT(0)
> +#define PWRAP_CAP_RESET		BIT(1)
> +#define PWRAP_CAP_DCM		BIT(2)
> +#define PWRAP_CAP_INT1_EN	BIT(3)
> +

You are missing the logic to handle the caps.
With out this logic, this patch is useless.

Regards,
Matthias

>  /* defines for slave device wrapper registers */
>  enum dew_regs {
>  	PWRAP_DEW_BASE,
> @@ -684,6 +690,8 @@ struct pmic_wrapper_type {
>  	u32 spi_w;
>  	u32 wdt_src;
>  	unsigned int has_bridge:1;
> +	/* Flags indicating the capability for the target pwrap */
> +	u8 caps;
>  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
>  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
>  };
> @@ -1394,6 +1402,7 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 0,
> +	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_mt2701_init_reg_clock,
>  	.init_soc_specific = pwrap_mt2701_init_soc_specific,
>  };
> @@ -1406,6 +1415,7 @@ static const struct pmic_wrapper_type pwrap_mt7622 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 0,
> +	.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_common_init_reg_clock,
>  	.init_soc_specific = pwrap_mt7622_init_soc_specific,
>  };
> @@ -1418,6 +1428,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
>  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
>  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
>  	.has_bridge = 1,
> +	.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
>  	.init_reg_clock = pwrap_common_init_reg_clock,
>  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
>  };
> -- 
> 2.12.5
> 
> ************* Email Confidentiality Notice ********************
> The information contained in this e-mail message (including any 
> attachments) may be confidential, proprietary, privileged, or otherwise
> exempt from disclosure under applicable laws. It is intended to be 
> conveyed only to the designated recipient(s). Any use, dissemination, 
> distribution, printing, retaining or copying of this e-mail (including its 
> attachments) by unintended recipient(s) is strictly prohibited and may 
> be unlawful. If you are not an intended recipient of this e-mail, or believe 
> that you have received this e-mail in error, please notify the sender 
> immediately (by replying to this e-mail), delete any and all copies of 
> this e-mail (including any attachments) from your system, and do not
> disclose the content of this e-mail to any other person. Thank you!
> 

  reply	other threads:[~2018-05-02 10:27 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-02  9:21 [PATCH V4 0/8] Pwrap: Mediatek pwrap driver for mt6797 argus.lin
2018-05-02  9:21 ` [PATCH V4 1/8] dt-bindings: pwrap: mediatek: add MT6351 PMIC support for MT6797 argus.lin
2018-05-03  2:01   ` Sean Wang
2018-05-03  2:01     ` Sean Wang
2018-05-03  2:01     ` Sean Wang
2018-05-02  9:21 ` [PATCH V4 2/8] soc: mediatek: pwrap: add caps flag for pwrap argus.lin
2018-05-02 10:27   ` Matthias Brugger [this message]
2018-05-02 10:27     ` Matthias Brugger
2018-05-02  9:21 ` [PATCH V4 3/8] soc: mediatek: pwrap: remove has_bridge flag argus.lin
2018-05-02 10:27   ` Matthias Brugger
2018-05-02 10:27     ` Matthias Brugger
2018-05-02  9:21 ` [PATCH V4 4/8] soc: mediatek: pwrap: add int1_en_all flag argus.lin
2018-05-02 10:29   ` Matthias Brugger
2018-05-02 10:29     ` Matthias Brugger
2018-05-02  9:21 ` [PATCH V4 5/8] soc: mediatek: pwrap: add pwrap for mt6797 SoCs argus.lin
2018-05-02 10:37   ` Matthias Brugger
2018-05-02 10:37     ` Matthias Brugger
2018-05-03  4:01   ` Sean Wang
2018-05-03  4:01     ` Sean Wang
2018-05-03  4:01     ` Sean Wang
2018-05-03  6:20     ` Argus Lin
2018-05-04  3:04       ` Sean Wang
2018-05-04  3:04         ` Sean Wang
2018-05-04  3:04         ` Sean Wang
2018-05-04  8:39         ` Matthias Brugger
2018-05-04  8:39           ` Matthias Brugger
2018-05-02  9:21 ` [PATCH V4 6/8] soc: mediatek: pwrap: fix cipher init argus.lin
2018-05-02  9:21 ` [PATCH V4 7/8] soc: mediatek: pwrap: add mt6351 for mt6797 SoCs argus.lin
2018-05-03  3:53   ` Sean Wang
2018-05-03  3:53     ` Sean Wang
2018-05-03  3:53     ` Sean Wang
2018-05-02  9:21 ` [PATCH V4 8/8] arm64: dts: mt6797: add pwrap support for mt6797 argus.lin
2018-05-03  2:22   ` Sean Wang
2018-05-03  2:22     ` Sean Wang
2018-05-03  2:22     ` Sean Wang

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