[PATCH 0/3] drm/amdgpu: implement raster configuration

[PATCH 0/3] drm/amdgpu: implement raster configuration

[Huang Rui]

Hi all,

This patch set is to introduce the raster configuration for all gfx
generations.

Thanks,
Rui

Huang Rui (3):
  drm/amdgpu: implement raster configuration for gfx v6
  drm/amdgpu: implement raster configuration for gfx v7
  drm/amdgpu: implement raster configuration for gfx v8

 drivers/gpu/drm/amd/amdgpu/cikd.h             |  36 ++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         | 133 +++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 160 +++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 168 +++++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vid.h              |  37 ++++++
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 ++++++
 6 files changed, 566 insertions(+), 3 deletions(-)

-- 
2.7.4

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[PATCH 1/3] drm/amdgpu: implement raster configuration for gfx v6

[Huang Rui]

This patch is to implement the raster configuration and harvested
configuration of gfx v6.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         | 133 +++++++++++++++++++++++++-
 drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 +++++++
 2 files changed, 167 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 17a560c..0905dd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -937,6 +937,123 @@ static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
 	return data & mask;
 }
 
+static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
+{
+	switch (adev->asic_type) {
+	case CHIP_TAHITI:
+	case CHIP_PITCAIRN:
+		*rconf |= RB_XSEL2(2) | RB_XSEL | PKR_MAP(2) | PKR_YSEL(1) |
+			  SE_MAP(2) | SE_XSEL(2) | SE_YSEL(2);
+		break;
+	case CHIP_VERDE:
+		*rconf |= RB_XSEL | PKR_MAP(2) | PKR_YSEL(1);
+		break;
+	case CHIP_OLAND:
+		*rconf |= RB_YSEL;
+		break;
+	case CHIP_HAINAN:
+		*rconf |= 0x0;
+		break;
+	default:
+		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
+		break;
+	}
+}
+
+static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
+						    u32 raster_config, unsigned rb_mask,
+						    unsigned num_rb)
+{
+	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
+	unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
+	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
+	unsigned rb_per_se = num_rb / num_se;
+	unsigned se_mask[4];
+	unsigned se;
+
+	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+	WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
+	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
+	WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
+
+	for (se = 0; se < num_se; se++) {
+		unsigned raster_config_se = raster_config;
+		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
+		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+		int idx = (se / 2) * 2;
+
+		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+			raster_config_se &= ~SE_MAP_MASK;
+
+			if (!se_mask[idx]) {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
+			} else {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
+			}
+		}
+
+		pkr0_mask &= rb_mask;
+		pkr1_mask &= rb_mask;
+		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+			raster_config_se &= ~PKR_MAP_MASK;
+
+			if (!pkr0_mask) {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
+			} else {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
+			}
+		}
+
+		if (rb_per_se >= 2) {
+			unsigned rb0_mask = 1 << (se * rb_per_se);
+			unsigned rb1_mask = rb0_mask << 1;
+
+			rb0_mask &= rb_mask;
+			rb1_mask &= rb_mask;
+			if (!rb0_mask || !rb1_mask) {
+				raster_config_se &= ~RB_MAP_PKR0_MASK;
+
+				if (!rb0_mask) {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
+				} else {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
+				}
+			}
+
+			if (rb_per_se > 2) {
+				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
+				rb1_mask = rb0_mask << 1;
+				rb0_mask &= rb_mask;
+				rb1_mask &= rb_mask;
+				if (!rb0_mask || !rb1_mask) {
+					raster_config_se &= ~RB_MAP_PKR1_MASK;
+
+					if (!rb0_mask) {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
+					} else {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
+					}
+				}
+			}
+		}
+
+		/* GRBM_GFX_INDEX has a different offset on SI */
+		gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
+		WREG32(PA_SC_RASTER_CONFIG, raster_config_se);
+	}
+
+	/* GRBM_GFX_INDEX has a different offset on SI */
+	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+}
+
 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 			      u32 se_num, u32 sh_per_se,
 			      u32 max_rb_num_per_se)
@@ -945,7 +1062,9 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 	u32 data, mask;
 	u32 disabled_rbs = 0;
 	u32 enabled_rbs = 0;
+	unsigned num_rb_pipes;
 
+	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < se_num; i++) {
 		for (j = 0; j < sh_per_se; j++) {
 			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -965,6 +1084,9 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 	adev->gfx.config.backend_enable_mask = enabled_rbs;
 	adev->gfx.config.num_rbs = hweight32(enabled_rbs);
 
+	num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
+			     adev->gfx.config.max_shader_engines, 16);
+
 	for (i = 0; i < se_num; i++) {
 		gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
 		data = 0;
@@ -983,9 +1105,18 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 			}
 			enabled_rbs >>= 2;
 		}
-		WREG32(PA_SC_RASTER_CONFIG, data);
+		gfx_v6_0_raster_config(adev, &data);
+
+		if (!adev->gfx.config.backend_enable_mask ||
+				adev->gfx.config.num_rbs >= num_rb_pipes)
+			WREG32(PA_SC_RASTER_CONFIG, data);
+		else
+			gfx_v6_0_write_harvested_raster_configs(adev, data,
+								adev->gfx.config.backend_enable_mask,
+								num_rb_pipes);
 	}
 	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 /*
 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
index 8c5608a..c57eff1 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/sid.h
@@ -1398,10 +1398,45 @@
 #define DB_DEPTH_INFO                                   0xA00F
 
 #define PA_SC_RASTER_CONFIG                             0xA0D4
+#	define RB_MAP_PKR0(x)				((x) << 0)
+#	define RB_MAP_PKR0_MASK				(0x3 << 0)
+#	define RB_MAP_PKR1(x)				((x) << 2)
+#	define RB_MAP_PKR1_MASK				(0x3 << 2)
 #       define RASTER_CONFIG_RB_MAP_0                   0
 #       define RASTER_CONFIG_RB_MAP_1                   1
 #       define RASTER_CONFIG_RB_MAP_2                   2
 #       define RASTER_CONFIG_RB_MAP_3                   3
+#	define RB_XSEL2(x)				((x) << 4)
+#	define RB_XSEL2_MASK				(0x3 << 4)
+#	define RB_XSEL					(1 << 6)
+#	define RB_YSEL					(1 << 7)
+#	define PKR_MAP(x)				((x) << 8)
+#	define PKR_MAP_MASK				(0x3 << 8)
+#       define RASTER_CONFIG_PKR_MAP_0			0
+#       define RASTER_CONFIG_PKR_MAP_1			1
+#       define RASTER_CONFIG_PKR_MAP_2			2
+#       define RASTER_CONFIG_PKR_MAP_3			3
+#	define PKR_XSEL(x)				((x) << 10)
+#	define PKR_XSEL_MASK				(0x3 << 10)
+#	define PKR_YSEL(x)				((x) << 12)
+#	define PKR_YSEL_MASK				(0x3 << 12)
+#	define SC_MAP(x)				((x) << 16)
+#	define SC_MAP_MASK				(0x3 << 16)
+#	define SC_XSEL(x)				((x) << 18)
+#	define SC_XSEL_MASK				(0x3 << 18)
+#	define SC_YSEL(x)				((x) << 20)
+#	define SC_YSEL_MASK				(0x3 << 20)
+#	define SE_MAP(x)				((x) << 24)
+#	define SE_MAP_MASK				(0x3 << 24)
+#       define RASTER_CONFIG_SE_MAP_0			0
+#       define RASTER_CONFIG_SE_MAP_1			1
+#       define RASTER_CONFIG_SE_MAP_2			2
+#       define RASTER_CONFIG_SE_MAP_3			3
+#	define SE_XSEL(x)				((x) << 26)
+#	define SE_XSEL_MASK				(0x3 << 26)
+#	define SE_YSEL(x)				((x) << 28)
+#	define SE_YSEL_MASK				(0x3 << 28)
+
 
 #define VGT_EVENT_INITIATOR                             0xA2A4
 #       define SAMPLE_STREAMOUTSTATS1                   (1 << 0)
-- 
2.7.4

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[PATCH 2/3] drm/amdgpu: implement raster configuration for gfx v7

[Huang Rui]

This patch is to implement the raster configuration and harvested
configuration of gfx v7.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cikd.h     |  36 ++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 160 +++++++++++++++++++++++++++++++++-
 2 files changed, 195 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index c4f6f00..8659852 100644
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -562,4 +562,40 @@ enum {
 	MTYPE_NONCACHED = 3
 };
 
+/* mmPA_SC_RASTER_CONFIG mask */
+#define RB_MAP_PKR0(x)				((x) << 0)
+#define RB_MAP_PKR0_MASK			(0x3 << 0)
+#define RB_MAP_PKR1(x)				((x) << 2)
+#define RB_MAP_PKR1_MASK			(0x3 << 2)
+#define RB_XSEL2(x)				((x) << 4)
+#define RB_XSEL2_MASK				(0x3 << 4)
+#define RB_XSEL					(1 << 6)
+#define RB_YSEL					(1 << 7)
+#define PKR_MAP(x)				((x) << 8)
+#define PKR_MAP_MASK				(0x3 << 8)
+#define PKR_XSEL(x)				((x) << 10)
+#define PKR_XSEL_MASK				(0x3 << 10)
+#define PKR_YSEL(x)				((x) << 12)
+#define PKR_YSEL_MASK				(0x3 << 12)
+#define SC_MAP(x)				((x) << 16)
+#define SC_MAP_MASK				(0x3 << 16)
+#define SC_XSEL(x)				((x) << 18)
+#define SC_XSEL_MASK				(0x3 << 18)
+#define SC_YSEL(x)				((x) << 20)
+#define SC_YSEL_MASK				(0x3 << 20)
+#define SE_MAP(x)				((x) << 24)
+#define SE_MAP_MASK				(0x3 << 24)
+#define SE_XSEL(x)				((x) << 26)
+#define SE_XSEL_MASK				(0x3 << 26)
+#define SE_YSEL(x)				((x) << 28)
+#define SE_YSEL_MASK				(0x3 << 28)
+
+/* mmPA_SC_RASTER_CONFIG_1 mask */
+#define SE_PAIR_MAP(x)				((x) << 0)
+#define SE_PAIR_MAP_MASK			(0x3 << 0)
+#define SE_PAIR_XSEL(x)				((x) << 2)
+#define SE_PAIR_XSEL_MASK			(0x3 << 2)
+#define SE_PAIR_YSEL(x)				((x) << 4)
+#define SE_PAIR_YSEL_MASK			(0x3 << 4)
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7fbdf08..b8065fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1645,6 +1645,147 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 	return (~data) & mask;
 }
 
+static void
+gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
+{
+	switch (adev->asic_type) {
+	case CHIP_BONAIRE:
+		*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
+			  SE_XSEL(1) | SE_YSEL(1);
+		*rconf1 |= 0x0;
+		break;
+	case CHIP_HAWAII:
+		*rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
+			  RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
+			  PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
+			  SE_YSEL(3);
+		*rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
+			   SE_PAIR_YSEL(2);
+		break;
+	case CHIP_KAVERI:
+		*rconf |= RB_MAP_PKR0(2);
+		*rconf1 |= 0x0;
+		break;
+	case CHIP_KABINI:
+	case CHIP_MULLINS:
+		*rconf |= 0x0;
+		*rconf1 |= 0x0;
+		break;
+	default:
+		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
+		break;
+	}
+}
+
+static void
+gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
+					u32 raster_config, u32 raster_config_1,
+					unsigned rb_mask, unsigned num_rb)
+{
+	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
+	unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
+	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
+	unsigned rb_per_se = num_rb / num_se;
+	unsigned se_mask[4];
+	unsigned se;
+
+	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+	WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
+	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
+	WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
+
+	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+			     (!se_mask[2] && !se_mask[3]))) {
+		raster_config_1 &= ~SE_PAIR_MAP_MASK;
+
+		if (!se_mask[0] && !se_mask[1]) {
+			raster_config_1 |=
+				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
+		} else {
+			raster_config_1 |=
+				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
+		}
+	}
+
+	for (se = 0; se < num_se; se++) {
+		unsigned raster_config_se = raster_config;
+		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
+		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+		int idx = (se / 2) * 2;
+
+		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+			raster_config_se &= ~SE_MAP_MASK;
+
+			if (!se_mask[idx]) {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
+			} else {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
+			}
+		}
+
+		pkr0_mask &= rb_mask;
+		pkr1_mask &= rb_mask;
+		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+			raster_config_se &= ~PKR_MAP_MASK;
+
+			if (!pkr0_mask) {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
+			} else {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
+			}
+		}
+
+		if (rb_per_se >= 2) {
+			unsigned rb0_mask = 1 << (se * rb_per_se);
+			unsigned rb1_mask = rb0_mask << 1;
+
+			rb0_mask &= rb_mask;
+			rb1_mask &= rb_mask;
+			if (!rb0_mask || !rb1_mask) {
+				raster_config_se &= ~RB_MAP_PKR0_MASK;
+
+				if (!rb0_mask) {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
+				} else {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
+				}
+			}
+
+			if (rb_per_se > 2) {
+				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
+				rb1_mask = rb0_mask << 1;
+				rb0_mask &= rb_mask;
+				rb1_mask &= rb_mask;
+				if (!rb0_mask || !rb1_mask) {
+					raster_config_se &= ~RB_MAP_PKR1_MASK;
+
+					if (!rb0_mask) {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
+					} else {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
+					}
+				}
+			}
+		}
+
+		/* GRBM_GFX_INDEX has a different offset on CI+ */
+		gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
+		WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
+		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
+	}
+
+	/* GRBM_GFX_INDEX has a different offset on CI+ */
+	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+}
+
 /**
  * gfx_v7_0_setup_rb - setup the RBs on the asic
  *
@@ -1658,9 +1799,11 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
 {
 	int i, j;
 	u32 data;
+	u32 raster_config = 0, raster_config_1 = 0;
 	u32 active_rbs = 0;
 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
 					adev->gfx.config.max_sh_per_se;
+	unsigned num_rb_pipes;
 
 	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
@@ -1672,10 +1815,25 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
 		}
 	}
 	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-	mutex_unlock(&adev->grbm_idx_mutex);
 
 	adev->gfx.config.backend_enable_mask = active_rbs;
 	adev->gfx.config.num_rbs = hweight32(active_rbs);
+
+	num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
+			     adev->gfx.config.max_shader_engines, 16);
+
+	gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
+
+	if (!adev->gfx.config.backend_enable_mask ||
+			adev->gfx.config.num_rbs >= num_rb_pipes) {
+		WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
+		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
+	} else {
+		gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
+							adev->gfx.config.backend_enable_mask,
+							num_rb_pipes);
+	}
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 /**
-- 
2.7.4

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[PATCH 3/3] drm/amdgpu: implement raster configuration for gfx v8

[Huang Rui]

This patch is to implement the raster configuration and harvested
configuration of gfx v8.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 168 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vid.h      |  37 ++++++++
 2 files changed, 204 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4bb0a39..8516331 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3493,13 +3493,163 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
 	return (~data) & mask;
 }
 
+static void
+gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
+{
+	switch (adev->asic_type) {
+	case CHIP_FIJI:
+		*rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
+			  RB_XSEL2(1) | PKR_MAP(2) |
+			  PKR_XSEL(1) | PKR_YSEL(1) |
+			  SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
+		*rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
+			   SE_PAIR_YSEL(2);
+		break;
+	case CHIP_TONGA:
+	case CHIP_POLARIS10:
+		*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
+			  SE_XSEL(1) | SE_YSEL(1);
+		*rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
+			   SE_PAIR_YSEL(2);
+		break;
+	case CHIP_TOPAZ:
+	case CHIP_CARRIZO:
+		*rconf |= RB_MAP_PKR0(2);
+		*rconf1 |= 0x0;
+		break;
+	case CHIP_POLARIS11:
+		*rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
+			  SE_XSEL(1) | SE_YSEL(1);
+		*rconf1 |= 0x0;
+		break;
+	case CHIP_STONEY:
+		*rconf |= 0x0;
+		*rconf1 |= 0x0;
+		break;
+	default:
+		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
+		break;
+	}
+}
+
+static void
+gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
+					u32 raster_config, u32 raster_config_1,
+					unsigned rb_mask, unsigned num_rb)
+{
+	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
+	unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
+	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
+	unsigned rb_per_se = num_rb / num_se;
+	unsigned se_mask[4];
+	unsigned se;
+
+	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+	WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
+	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
+	WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
+
+	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+			     (!se_mask[2] && !se_mask[3]))) {
+		raster_config_1 &= ~SE_PAIR_MAP_MASK;
+
+		if (!se_mask[0] && !se_mask[1]) {
+			raster_config_1 |=
+				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
+		} else {
+			raster_config_1 |=
+				SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
+		}
+	}
+
+	for (se = 0; se < num_se; se++) {
+		unsigned raster_config_se = raster_config;
+		unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
+		unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+		int idx = (se / 2) * 2;
+
+		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+			raster_config_se &= ~SE_MAP_MASK;
+
+			if (!se_mask[idx]) {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
+			} else {
+				raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
+			}
+		}
+
+		pkr0_mask &= rb_mask;
+		pkr1_mask &= rb_mask;
+		if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+			raster_config_se &= ~PKR_MAP_MASK;
+
+			if (!pkr0_mask) {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
+			} else {
+				raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
+			}
+		}
+
+		if (rb_per_se >= 2) {
+			unsigned rb0_mask = 1 << (se * rb_per_se);
+			unsigned rb1_mask = rb0_mask << 1;
+
+			rb0_mask &= rb_mask;
+			rb1_mask &= rb_mask;
+			if (!rb0_mask || !rb1_mask) {
+				raster_config_se &= ~RB_MAP_PKR0_MASK;
+
+				if (!rb0_mask) {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
+				} else {
+					raster_config_se |=
+						RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
+				}
+			}
+
+			if (rb_per_se > 2) {
+				rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
+				rb1_mask = rb0_mask << 1;
+				rb0_mask &= rb_mask;
+				rb1_mask &= rb_mask;
+				if (!rb0_mask || !rb1_mask) {
+					raster_config_se &= ~RB_MAP_PKR1_MASK;
+
+					if (!rb0_mask) {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
+					} else {
+						raster_config_se |=
+							RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
+					}
+				}
+			}
+		}
+
+		/* GRBM_GFX_INDEX has a different offset on VI */
+		gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
+		WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
+		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
+	}
+
+	/* GRBM_GFX_INDEX has a different offset on VI */
+	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+}
+
 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
 {
 	int i, j;
 	u32 data;
+	u32 raster_config = 0, raster_config_1 = 0;
 	u32 active_rbs = 0;
 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
 					adev->gfx.config.max_sh_per_se;
+	unsigned num_rb_pipes;
 
 	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
@@ -3511,10 +3661,26 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
 		}
 	}
 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-	mutex_unlock(&adev->grbm_idx_mutex);
 
 	adev->gfx.config.backend_enable_mask = active_rbs;
 	adev->gfx.config.num_rbs = hweight32(active_rbs);
+
+	num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
+			     adev->gfx.config.max_shader_engines, 16);
+
+	gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
+
+	if (!adev->gfx.config.backend_enable_mask ||
+			adev->gfx.config.num_rbs >= num_rb_pipes) {
+		WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
+		WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
+	} else {
+		gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
+							adev->gfx.config.backend_enable_mask,
+							num_rb_pipes);
+	}
+
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index f62b261..11746f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -373,4 +373,41 @@
 #define VCE_CMD_WAIT_GE         0x00000106
 #define VCE_CMD_UPDATE_PTB      0x00000107
 #define VCE_CMD_FLUSH_TLB       0x00000108
+
+/* mmPA_SC_RASTER_CONFIG mask */
+#define RB_MAP_PKR0(x)				((x) << 0)
+#define RB_MAP_PKR0_MASK			(0x3 << 0)
+#define RB_MAP_PKR1(x)				((x) << 2)
+#define RB_MAP_PKR1_MASK			(0x3 << 2)
+#define RB_XSEL2(x)				((x) << 4)
+#define RB_XSEL2_MASK				(0x3 << 4)
+#define RB_XSEL					(1 << 6)
+#define RB_YSEL					(1 << 7)
+#define PKR_MAP(x)				((x) << 8)
+#define PKR_MAP_MASK				(0x3 << 8)
+#define PKR_XSEL(x)				((x) << 10)
+#define PKR_XSEL_MASK				(0x3 << 10)
+#define PKR_YSEL(x)				((x) << 12)
+#define PKR_YSEL_MASK				(0x3 << 12)
+#define SC_MAP(x)				((x) << 16)
+#define SC_MAP_MASK				(0x3 << 16)
+#define SC_XSEL(x)				((x) << 18)
+#define SC_XSEL_MASK				(0x3 << 18)
+#define SC_YSEL(x)				((x) << 20)
+#define SC_YSEL_MASK				(0x3 << 20)
+#define SE_MAP(x)				((x) << 24)
+#define SE_MAP_MASK				(0x3 << 24)
+#define SE_XSEL(x)				((x) << 26)
+#define SE_XSEL_MASK				(0x3 << 26)
+#define SE_YSEL(x)				((x) << 28)
+#define SE_YSEL_MASK				(0x3 << 28)
+
+/* mmPA_SC_RASTER_CONFIG_1 mask */
+#define SE_PAIR_MAP(x)				((x) << 0)
+#define SE_PAIR_MAP_MASK			(0x3 << 0)
+#define SE_PAIR_XSEL(x)				((x) << 2)
+#define SE_PAIR_XSEL_MASK			(0x3 << 2)
+#define SE_PAIR_YSEL(x)				((x) << 4)
+#define SE_PAIR_YSEL_MASK			(0x3 << 4)
+
 #endif
-- 
2.7.4

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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Edward O'Callaghan]

[-- Attachment #1.1.1: Type: text/plain, Size: 962 bytes --]

This series is,
Acked-by: Edward O'Callaghan <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>

On 09/18/2016 12:36 PM, Huang Rui wrote:
> Hi all,
> 
> This patch set is to introduce the raster configuration for all gfx
> generations.
> 
> Thanks,
> Rui
> 
> Huang Rui (3):
>   drm/amdgpu: implement raster configuration for gfx v6
>   drm/amdgpu: implement raster configuration for gfx v7
>   drm/amdgpu: implement raster configuration for gfx v8
> 
>  drivers/gpu/drm/amd/amdgpu/cikd.h             |  36 ++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         | 133 +++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 160 +++++++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 168 +++++++++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/vid.h              |  37 ++++++
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 ++++++
>  6 files changed, 566 insertions(+), 3 deletions(-)
> 


[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Michel Dänzer]

On 18/09/16 11:36 AM, Huang Rui wrote:
> Hi all,
> 
> This patch set is to introduce the raster configuration for all gfx
> generations.

What's the motivation for doing this in the kernel? Mesa will write its
own values to these registers anyway.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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RE: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Deucher, Alexander]

> -----Original Message-----
> From: Michel Dänzer [mailto:michel@daenzer.net]
> Sent: Monday, September 19, 2016 10:37 PM
> To: Huang, Ray; Deucher, Alexander
> Cc: amd-gfx@lists.freedesktop.org; Wang, Ken; Huan, Alvin
> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
> 
> On 18/09/16 11:36 AM, Huang Rui wrote:
> > Hi all,
> >
> > This patch set is to introduce the raster configuration for all gfx
> > generations.
> 
> What's the motivation for doing this in the kernel? Mesa will write its
> own values to these registers anyway.

It's to fix the read register ioctl interface.  The raster config registers can be read back by the UMDs, but if the KMD hasn't programmed them, they may have bogus values.  It's mainly for the pro drivers which read the raster config registers to get the baseline before programming them.  Mesa hardcodes the default raster config settings before harvesting.  We arguably should have done it in the kernel as well for mesa (my bad).  At least this way both sides are doing the right thing.

Alex
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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Christian König]

Am 20.09.2016 um 06:05 schrieb Deucher, Alexander:
>> -----Original Message-----
>> From: Michel Dänzer [mailto:michel@daenzer.net]
>> Sent: Monday, September 19, 2016 10:37 PM
>> To: Huang, Ray; Deucher, Alexander
>> Cc: amd-gfx@lists.freedesktop.org; Wang, Ken; Huan, Alvin
>> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
>>
>> On 18/09/16 11:36 AM, Huang Rui wrote:
>>> Hi all,
>>>
>>> This patch set is to introduce the raster configuration for all gfx
>>> generations.
>> What's the motivation for doing this in the kernel? Mesa will write its
>> own values to these registers anyway.
> It's to fix the read register ioctl interface.  The raster config registers can be read back by the UMDs, but if the KMD hasn't programmed them, they may have bogus values.  It's mainly for the pro drivers which read the raster config registers to get the baseline before programming them.  Mesa hardcodes the default raster config settings before harvesting.  We arguably should have done it in the kernel as well for mesa (my bad).  At least this way both sides are doing the right thing.

Yeah, I wondered before as well why we don't do this in the kernel. What 
was the reason to move it into Mesa?

The patchset itself is Acked-by: Christian König <christian.koenig@amd.com>.

Regards,
Christian.

>
> Alex
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Alex Deucher]

On Tue, Sep 20, 2016 at 9:10 AM, Christian König
<deathsimple@vodafone.de> wrote:
> Am 20.09.2016 um 06:05 schrieb Deucher, Alexander:
>>>
>>> -----Original Message-----
>>> From: Michel Dänzer [mailto:michel@daenzer.net]
>>> Sent: Monday, September 19, 2016 10:37 PM
>>> To: Huang, Ray; Deucher, Alexander
>>> Cc: amd-gfx@lists.freedesktop.org; Wang, Ken; Huan, Alvin
>>> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
>>>
>>> On 18/09/16 11:36 AM, Huang Rui wrote:
>>>>
>>>> Hi all,
>>>>
>>>> This patch set is to introduce the raster configuration for all gfx
>>>> generations.
>>>
>>> What's the motivation for doing this in the kernel? Mesa will write its
>>> own values to these registers anyway.
>>
>> It's to fix the read register ioctl interface.  The raster config
>> registers can be read back by the UMDs, but if the KMD hasn't programmed
>> them, they may have bogus values.  It's mainly for the pro drivers which
>> read the raster config registers to get the baseline before programming
>> them.  Mesa hardcodes the default raster config settings before harvesting.
>> We arguably should have done it in the kernel as well for mesa (my bad).  At
>> least this way both sides are doing the right thing.
>
>
> Yeah, I wondered before as well why we don't do this in the kernel. What was
> the reason to move it into Mesa?

I just thought it made more sense to do it in mesa since it's part of
the 3D state and mesa needs to program it anyway (ideally we'd also
make adjustments to it to handle rendering to GTT and certain
crossfire configurations), but It makes more sense to put the base
harvest logic in the kernel driver.

Alex

>
> The patchset itself is Acked-by: Christian König <christian.koenig@amd.com>.
>
> Regards,
> Christian.
>
>
>>
>> Alex
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Marek Olšák]

The series is missing a DRM version bump, so Mesa can't really use it
even if it wanted.

Marek

On Sun, Sep 18, 2016 at 4:36 AM, Huang Rui <ray.huang@amd.com> wrote:
> Hi all,
>
> This patch set is to introduce the raster configuration for all gfx
> generations.
>
> Thanks,
> Rui
>
> Huang Rui (3):
>   drm/amdgpu: implement raster configuration for gfx v6
>   drm/amdgpu: implement raster configuration for gfx v7
>   drm/amdgpu: implement raster configuration for gfx v8
>
>  drivers/gpu/drm/amd/amdgpu/cikd.h             |  36 ++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         | 133 +++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 160 +++++++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 168 +++++++++++++++++++++++++-
>  drivers/gpu/drm/amd/amdgpu/vid.h              |  37 ++++++
>  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 ++++++
>  6 files changed, 566 insertions(+), 3 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Deucher, Alexander]

> -----Original Message-----
> From: Marek Olšák [mailto:maraeo@gmail.com]
> Sent: Monday, September 26, 2016 4:39 PM
> To: Huang, Ray
> Cc: amd-gfx mailing list; Deucher, Alexander; Wang, Ken; Huan, Alvin
> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
> 
> The series is missing a DRM version bump, so Mesa can't really use it
> even if it wanted.
> 

We bumped it already this cycle for several other things, but I can add a specific bump for this as well if that is preferred.

Alex

> Marek
> 
> On Sun, Sep 18, 2016 at 4:36 AM, Huang Rui <ray.huang@amd.com> wrote:
> > Hi all,
> >
> > This patch set is to introduce the raster configuration for all gfx
> > generations.
> >
> > Thanks,
> > Rui
> >
> > Huang Rui (3):
> >   drm/amdgpu: implement raster configuration for gfx v6
> >   drm/amdgpu: implement raster configuration for gfx v7
> >   drm/amdgpu: implement raster configuration for gfx v8
> >
> >  drivers/gpu/drm/amd/amdgpu/cikd.h             |  36 ++++++
> >  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c         | 133
> +++++++++++++++++++-
> >  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c         | 160
> +++++++++++++++++++++++-
> >  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 168
> +++++++++++++++++++++++++-
> >  drivers/gpu/drm/amd/amdgpu/vid.h              |  37 ++++++
> >  drivers/gpu/drm/amd/include/asic_reg/si/sid.h |  35 ++++++
> >  6 files changed, 566 insertions(+), 3 deletions(-)
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Marek Olšák]

On Mon, Sep 26, 2016 at 10:42 PM, Deucher, Alexander
<Alexander.Deucher@amd.com> wrote:
>> -----Original Message-----
>> From: Marek Olšák [mailto:maraeo@gmail.com]
>> Sent: Monday, September 26, 2016 4:39 PM
>> To: Huang, Ray
>> Cc: amd-gfx mailing list; Deucher, Alexander; Wang, Ken; Huan, Alvin
>> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
>>
>> The series is missing a DRM version bump, so Mesa can't really use it
>> even if it wanted.
>>
>
> We bumped it already this cycle for several other things, but I can add a specific bump for this as well if that is preferred.

Oh, that's not necessary. One bump per cycle is OK.

Marek
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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Christian König]

Am 27.09.2016 um 01:13 schrieb Marek Olšák:
> On Mon, Sep 26, 2016 at 10:42 PM, Deucher, Alexander
> <Alexander.Deucher@amd.com> wrote:
>>> -----Original Message-----
>>> From: Marek Olšák [mailto:maraeo@gmail.com]
>>> Sent: Monday, September 26, 2016 4:39 PM
>>> To: Huang, Ray
>>> Cc: amd-gfx mailing list; Deucher, Alexander; Wang, Ken; Huan, Alvin
>>> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
>>>
>>> The series is missing a DRM version bump, so Mesa can't really use it
>>> even if it wanted.
>>>
>> We bumped it already this cycle for several other things, but I can add a specific bump for this as well if that is preferred.
> Oh, that's not necessary. One bump per cycle is OK.

As I wrote in the other thread as well, bumping once per cycle sucks 
when you want to bisect something.

We are also not short on numbers, so I suggest that we establish that we 
always bump when we add a new interface to the kernel IOCTL.

Christian.

>
> Marek
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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Re: [PATCH 0/3] drm/amdgpu: implement raster configuration

[Michel Dänzer]

On 27/09/16 04:17 PM, Christian König wrote:
> Am 27.09.2016 um 01:13 schrieb Marek Olšák:
>> On Mon, Sep 26, 2016 at 10:42 PM, Deucher, Alexander
>> <Alexander.Deucher@amd.com> wrote:
>>>> -----Original Message-----
>>>> From: Marek Olšák [mailto:maraeo@gmail.com]
>>>> Sent: Monday, September 26, 2016 4:39 PM
>>>> To: Huang, Ray
>>>> Cc: amd-gfx mailing list; Deucher, Alexander; Wang, Ken; Huan, Alvin
>>>> Subject: Re: [PATCH 0/3] drm/amdgpu: implement raster configuration
>>>>
>>>> The series is missing a DRM version bump, so Mesa can't really use it
>>>> even if it wanted.
>>>>
>>> We bumped it already this cycle for several other things, but I can
>>> add a specific bump for this as well if that is preferred.
>> Oh, that's not necessary. One bump per cycle is OK.
> 
> As I wrote in the other thread as well, bumping once per cycle sucks
> when you want to bisect something.
> 
> We are also not short on numbers, so I suggest that we establish that we
> always bump when we add a new interface to the kernel IOCTL.

Seconded.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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