* [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins
@ 2016-11-11 20:30 Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 1/6] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Hi,
This series fixes two issues I encounter for bias handling in the PFC
while preparing my drive strength patch set.
I also attached a new patch 6/6 that adds the macro
SH_PFC_PIN_NAMED_CFG() and was previously part of the series 'pinctrl:
sh-pfc: r8a7795: Support none GPIO pins with configurable
drive-strength'.
The reason I moved this patch to this series are both 6/6 and the new
bias helper function introduced in 2/6 are dependencies for other PFC
patch series I wish to send out. So to simplify the dependencies between
series this looked like the best option, if not please let me know.
* Changes since v1
- Moved bias helper function from pfc-r8a7795.c to the sh-pfc core.
- Convert r8a7778 to use the new bias helper function.
- Fixed up spelling and attached Ack-tags.
- Attached a patch to add SH_PFC_PIN_NAMED_CFG() to simplify
dependencies for other series.
Niklas Söderlund (6):
pinctrl: sh-pfc: Do not unconditionally support
PIN_CONFIG_BIAS_DISABLE
pinctrl: sh-pfc: Add helper to handle bias lookup table
pinctrl: sh-pfc: r8a7795: Simplify get bias logic
pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
pinctrl: sh-pfc: r8a7778: Use lookup function for bias data
pinctrl: sh-pfc: Support named pins with custom configuration
drivers/pinctrl/sh-pfc/core.c | 16 ++
drivers/pinctrl/sh-pfc/core.h | 4 +
drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 340 ++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 352 +++++++++++++++++------------------
drivers/pinctrl/sh-pfc/pinctrl.c | 3 +-
drivers/pinctrl/sh-pfc/sh_pfc.h | 14 ++
6 files changed, 381 insertions(+), 348 deletions(-)
--
2.10.2
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCHv2 1/6] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table Niklas Söderlund
` (4 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.
Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it dose not know about.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index c577258..fcacfa7 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -570,7 +570,8 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- return true;
+ return pin->configs &
+ (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 1/6] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
2016-11-12 1:46 ` Laurent Pinchart
2016-11-11 20:30 ` [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic Niklas Söderlund
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.
Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/core.c | 16 ++++++++++++++++
drivers/pinctrl/sh-pfc/core.h | 4 ++++
drivers/pinctrl/sh-pfc/sh_pfc.h | 6 ++++++
3 files changed, 26 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index f3a8897..8e38df7 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -389,6 +389,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
+int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
+ unsigned int num, unsigned int pin,
+ struct sh_pfc_bias_info *info)
+{
+ unsigned int i;
+
+ for (i = 0; i < num; i++) {
+ if (pullups[i].pin == pin) {
+ *info = pullups[i];
+ return 0;
+ }
+ }
+
+ return WARN_ON_ONCE(-EINVAL);
+}
+
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 0bbdea58..d902cd2 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
+int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
+ unsigned int num, unsigned int pin,
+ struct sh_pfc_bias_info *info);
+
#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 2345421..fc82b6d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -189,6 +189,12 @@ struct sh_pfc_window {
unsigned long size;
};
+struct sh_pfc_bias_info {
+ unsigned int pin;
+ u16 reg : 11;
+ u16 bit : 5;
+};
+
struct sh_pfc_pin_range;
struct sh_pfc {
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 1/6] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
2016-11-11 22:42 ` Laurent Pinchart
2016-11-11 20:30 ` [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
The last else statement is missing braces and there indentation level
can be reduced.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 2e8cc2a..6c58563 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -5367,13 +5367,12 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
reg = pullups[pin].reg;
bit = BIT(pullups[pin].bit);
- if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
- if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
- return PIN_CONFIG_BIAS_PULL_UP;
- else
- return PIN_CONFIG_BIAS_PULL_DOWN;
- } else
+ if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
return PIN_CONFIG_BIAS_DISABLE;
+ else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
+ return PIN_CONFIG_BIAS_PULL_UP;
+ else
+ return PIN_CONFIG_BIAS_PULL_DOWN;
}
static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
` (2 preceding siblings ...)
2016-11-11 20:30 ` [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
2016-11-12 1:47 ` Laurent Pinchart
2016-11-11 20:30 ` [PATCHv2 5/6] pinctrl: sh-pfc: r8a7778: " Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 6/6] pinctrl: sh-pfc: Support named pins with custom configuration Niklas Söderlund
5 siblings, 1 reply; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0is accessed.
# cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
[..]
Call trace:
[<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
[<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
[<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
[<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
[<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
[<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
[<ffff0000081fe3bc>] seq_read+0x16c/0x420
[<ffff00000831a110>] full_proxy_read+0x58/0x88
[<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
[<ffff0000081d8874>] vfs_read+0x84/0x148
[<ffff0000081d9d64>] SyS_read+0x44/0xa0
[<ffff000008082f4c>] __sys_trace_return+0x0/0x4
This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.
Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 341 +++++++++++++++++------------------
1 file changed, 170 insertions(+), 171 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 6c58563..01ca592 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -5188,171 +5188,168 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
#define PU5 0x14
#define PU6 0x18
-static const struct {
- u16 reg : 11;
- u16 bit : 5;
-} pullups[] = {
- [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
- [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
- [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
-
- [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
- [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
- [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
- [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
- [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
- [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
- [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
- [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
- [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
- [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
- [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
- [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
- [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
- [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
- [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
- [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
- [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
- [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
- [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
- [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
- [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
- [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
- [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
- [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
- [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
- [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
- [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
- [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
- [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
- [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
- [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
- [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
-
- [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
- [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
- [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
- [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
- [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
- [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
- [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
- [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
- [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
- [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
- [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
- [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
- [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
- [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
- [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
- [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
- [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
- [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
- [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
- [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
- [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
- [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
- [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
- [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
- [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
- [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
- [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
- [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
-
- [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
- [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
- [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
- [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
- [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
- [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
- [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
- [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
- [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
- [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
- [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
- [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
- [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
- [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
- [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
- [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
- [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
- [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
- [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
- [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
- [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
- [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
-
- [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
- [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
- [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
- [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
- [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
- [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
- [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
- [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
- [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
- [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
- [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
- [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
- [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
- [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
- [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
- [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
- [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
- [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
- [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
- [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
- [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
- [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
- [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
- [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
- [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
- [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
- [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
- [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
- [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
- [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
- [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
- [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
-
- [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
- [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
- [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
- [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
- [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
- [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
- [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
- [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
- [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
- [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
- [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
- [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
- [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
- [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
- [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
- [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
- [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
- [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
- [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
- [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
- [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
- [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
- [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
- [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
- [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
- [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
- [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
- [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
- [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
- [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
- [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
-
- [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
- [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
- [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
- [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
- [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
- [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
- [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
+static const struct sh_pfc_bias_info pullups[] = {
+ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
+ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
+ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
+
+ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
+ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
+ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
+ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
+ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
+ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
+ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
+ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
+ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
+ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
+ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
+ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
+ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
+ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
+ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
+ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
+ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
+ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
+ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
+ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
+ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
+ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
+ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
+ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
+ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
+ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
+ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
+ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
+ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
+ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
+ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
+ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
+
+ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
+ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
+ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
+ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
+ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
+ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
+ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
+ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
+ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
+ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
+ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
+ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
+ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
+ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
+ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
+ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
+ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
+ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
+ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
+ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
+ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
+ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
+ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
+ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
+ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
+ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
+
+ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
+ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
+ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
+ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
+ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
+ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
+ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
+ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
+ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
+ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
+ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
+ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
+ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
+ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
+ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
+ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
+ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
+ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
+
+ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
+ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
+ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
+ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
+ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
+ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
+ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
+ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
+ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
+ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
+ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
+ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
+ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
+ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
+ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
+ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
+ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
+ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
+ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
+ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
+ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
+ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
+ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
+ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
+ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
+ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
+ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
+ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
+ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
+ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
+ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
+ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
+
+ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
+ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
+ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
+ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
+ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
+ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
+ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
+ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
+ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
+ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
+ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
+ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
+ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
+ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
+ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
+ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
+ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
+ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
+ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
+ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
+ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
+ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
+ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
+ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
+ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
+ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
+ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
+ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
+ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
+ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
+ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
+
+ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
+ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
+ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
+ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
+ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
+ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
+ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
};
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
@@ -5360,12 +5357,13 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
{
u32 reg;
u32 bit;
+ struct sh_pfc_bias_info info;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
return PIN_CONFIG_BIAS_DISABLE;
- reg = pullups[pin].reg;
- bit = BIT(pullups[pin].bit);
+ reg = info.reg;
+ bit = BIT(info.bit);
if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
return PIN_CONFIG_BIAS_DISABLE;
@@ -5381,12 +5379,13 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
u32 enable, updown;
u32 reg;
u32 bit;
+ struct sh_pfc_bias_info info;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
return;
- reg = pullups[pin].reg;
- bit = BIT(pullups[pin].bit);
+ reg = info.reg;
+ bit = BIT(info.bit);
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
if (bias != PIN_CONFIG_BIAS_DISABLE)
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 5/6] pinctrl: sh-pfc: r8a7778: Use lookup function for bias data
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
` (3 preceding siblings ...)
2016-11-11 20:30 ` [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 6/6] pinctrl: sh-pfc: Support named pins with custom configuration Niklas Söderlund
5 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 340 +++++++++++++++++------------------
1 file changed, 170 insertions(+), 170 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 18ef704..15824a6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -24,6 +24,7 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
@@ -2918,183 +2919,181 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PUPR4 0x110
#define PUPR5 0x114
-static const struct {
- u16 reg : 11;
- u16 bit : 5;
-} pullups[] = {
- [RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */
- [RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */
- [RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */
- [RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */
- [RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */
- [RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */
- [RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */
- [RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */
- [RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */
- [RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */
- [RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */
- [RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */
- [RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */
- [RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */
- [RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */
- [RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */
- [RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */
- [RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */
- [RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */
- [RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */
- [RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */
- [RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */
- [RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */
- [RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */
- [RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */
- [RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */
- [RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */
- [RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */
- [RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */
- [RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */
- [RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */
- [RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */
-
- [RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */
- [RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */
- [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */
- [RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */
- [RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */
- [RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */
- [RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */
- [RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */
- [RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */
- [RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */
-
- [RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */
- [RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */
- [RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */
- [RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */
- [RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */
- [RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */
- [RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */
- [RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */
- [RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */
- [RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */
- [RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */
- [RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */
- [RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */
- [RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */
- [RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */
- [RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */
- [RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */
- [RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */
- [RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */
- [RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */
- [RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */
- [RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */
- [RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */
- [RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */
- [RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */
- [RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
- [RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */
- [RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */
- [RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */
- [RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */
- [RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */
- [RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
-
- [RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */
- [RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */
- [RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */
- [RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */
- [RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */
- [RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */
- [RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */
- [RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */
- [RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */
- [RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */
- [RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */
- [RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */
- [RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */
- [RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */
- [RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */
- [RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */
- [RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */
- [RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */
- [RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */
- [RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */
- [RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */
- [RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */
- [RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */
- [RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */
- [RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */
- [RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */
- [RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */
- [RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */
- [RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */
- [RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */
- [RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */
- [RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */
-
- [RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */
- [RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */
- [RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */
- [RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */
- [RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */
- [RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */
- [RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */
- [RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */
- [RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */
- [RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */
- [RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */
- [RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */
- [RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */
- [RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */
- [RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */
- [RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */
- [RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */
- [RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */
- [RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */
- [RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */
- [RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */
- [RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */
- [RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */
- [RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */
- [RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */
- [RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */
- [RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */
- [RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */
- [RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */
- [RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */
- [RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */
- [RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */
-
- [RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */
- [RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */
- [RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */
- [RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */
- [RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */
- [RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */
- [RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */
- [RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */
- [RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */
- [RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */
- [RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */
- [RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */
- [RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */
- [RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */
- [RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */
- [RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */
- [RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */
+static const struct sh_pfc_bias_info pullups[] = {
+ { RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */
+ { RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */
+ { RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */
+ { RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */
+ { RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */
+ { RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */
+ { RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */
+ { RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */
+ { RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */
+ { RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */
+ { RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */
+ { RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */
+ { RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */
+ { RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */
+ { RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */
+ { RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */
+ { RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */
+ { RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */
+ { RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */
+ { RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */
+ { RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */
+ { RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */
+ { RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */
+ { RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */
+ { RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */
+ { RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */
+ { RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */
+ { RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */
+ { RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */
+ { RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */
+ { RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */
+ { RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */
+
+ { RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */
+ { RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */
+ { RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */
+ { RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */
+ { RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */
+ { RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */
+ { RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */
+ { RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */
+ { RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */
+ { RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */
+
+ { RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */
+ { RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */
+ { RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */
+ { RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */
+ { RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */
+ { RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */
+ { RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */
+ { RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */
+ { RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */
+ { RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */
+ { RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */
+ { RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */
+ { RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */
+ { RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */
+ { RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */
+ { RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */
+ { RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */
+ { RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */
+ { RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */
+ { RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */
+ { RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */
+ { RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */
+ { RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */
+ { RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */
+ { RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */
+ { RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
+ { RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */
+ { RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */
+ { RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */
+ { RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */
+ { RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */
+ { RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
+
+ { RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */
+ { RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */
+ { RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */
+ { RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */
+ { RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */
+ { RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */
+ { RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */
+ { RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */
+ { RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */
+ { RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */
+ { RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */
+ { RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */
+ { RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */
+ { RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */
+ { RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */
+ { RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */
+ { RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */
+ { RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */
+ { RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */
+ { RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */
+ { RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */
+ { RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */
+ { RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */
+ { RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */
+ { RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */
+ { RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */
+ { RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */
+ { RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */
+ { RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */
+ { RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */
+ { RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */
+ { RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */
+
+ { RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */
+ { RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */
+ { RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */
+ { RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */
+ { RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */
+ { RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */
+ { RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */
+ { RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */
+ { RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */
+ { RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */
+ { RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */
+ { RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */
+ { RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */
+ { RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */
+ { RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */
+ { RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */
+ { RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */
+ { RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */
+ { RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */
+ { RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */
+ { RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */
+ { RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */
+ { RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */
+ { RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */
+ { RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */
+ { RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */
+ { RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */
+ { RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */
+
+ { RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */
+ { RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */
+ { RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */
+ { RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */
+ { RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */
+ { RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */
+ { RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */
+ { RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */
+ { RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */
+ { RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */
+ { RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */
+ { RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */
+ { RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */
+ { RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */
+ { RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */
+ { RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */
+ { RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */
};
static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
{
+ struct sh_pfc_bias_info info;
void __iomem *addr;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
return PIN_CONFIG_BIAS_DISABLE;
- addr = pfc->windows->virt + pullups[pin].reg;
+ addr = pfc->windows->virt + info.reg;
- if (ioread32(addr) & BIT(pullups[pin].bit))
+ if (ioread32(addr) & BIT(info.bit))
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_DISABLE;
@@ -3103,15 +3102,16 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
+ struct sh_pfc_bias_info info;
void __iomem *addr;
u32 value;
u32 bit;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
return;
- addr = pfc->windows->virt + pullups[pin].reg;
- bit = BIT(pullups[pin].bit);
+ addr = pfc->windows->virt + info.reg;
+ bit = BIT(info.bit);
value = ioread32(addr) & ~bit;
if (bias == PIN_CONFIG_BIAS_PULL_UP)
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCHv2 6/6] pinctrl: sh-pfc: Support named pins with custom configuration
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
` (4 preceding siblings ...)
2016-11-11 20:30 ` [PATCHv2 5/6] pinctrl: sh-pfc: r8a7778: " Niklas Söderlund
@ 2016-11-11 20:30 ` Niklas Söderlund
5 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-11 20:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.
The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index fc82b6d..0be04f8 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -546,6 +546,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
+/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
+#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
+ { \
+ .pin = PIN_NUMBER(row, col), \
+ .name = __stringify(PIN_##_name), \
+ .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
+ }
+
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
--
2.10.2
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic
2016-11-11 20:30 ` [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic Niklas Söderlund
@ 2016-11-11 22:42 ` Laurent Pinchart
0 siblings, 0 replies; 14+ messages in thread
From: Laurent Pinchart @ 2016-11-11 22:42 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio,
Niklas Söderlund
Hi Niklas,
Thank you for the patch.
On Friday 11 Nov 2016 21:30:18 Niklas Söderlund wrote:
> From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> The last else statement is missing braces and there indentation level
> can be reduced.
>
> Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 2e8cc2a..6c58563 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> @@ -5367,13 +5367,12 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> sh_pfc *pfc, reg = pullups[pin].reg;
> bit = BIT(pullups[pin].bit);
>
> - if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> - if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> - return PIN_CONFIG_BIAS_PULL_UP;
> - else
> - return PIN_CONFIG_BIAS_PULL_DOWN;
> - } else
> + if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> return PIN_CONFIG_BIAS_DISABLE;
> + else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> + return PIN_CONFIG_BIAS_PULL_UP;
> + else
> + return PIN_CONFIG_BIAS_PULL_DOWN;
> }
>
> static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table
2016-11-11 20:30 ` [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table Niklas Söderlund
@ 2016-11-12 1:46 ` Laurent Pinchart
2016-11-12 13:41 ` Niklas Söderlund
0 siblings, 1 reply; 14+ messages in thread
From: Laurent Pinchart @ 2016-11-12 1:46 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio,
Niklas Söderlund
Hi Niklas,
Thank you for the patch.
On Friday 11 Nov 2016 21:30:17 Niklas Söderlund wrote:
> From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> On some SoC there are no simple mapping of pins to bias register bits
> and a lookup table is needed. This logic is already implemented in some
> SoC specific drivers that could benefit from a generic implementation.
>
> Add helpers to deal with the lookup which later can be used by the SoC
> specific drivers. The logic used to lookup are different from the one it
> aims to replace, this is intentional. This new method reduces the memory
> consumption at the cost of increased CPU usage and fix a bug where a
> WARN() would incorrectly be triggered if the register offset is 0.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/pinctrl/sh-pfc/core.c | 16 ++++++++++++++++
> drivers/pinctrl/sh-pfc/core.h | 4 ++++
> drivers/pinctrl/sh-pfc/sh_pfc.h | 6 ++++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
> index f3a8897..8e38df7 100644
> --- a/drivers/pinctrl/sh-pfc/core.c
> +++ b/drivers/pinctrl/sh-pfc/core.c
> @@ -389,6 +389,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned
> mark, int pinmux_type) return 0;
> }
>
> +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> + unsigned int num, unsigned int pin,
> + struct sh_pfc_bias_info *info)
How about returning a const struct sh_pfc_bias_info * instead ? This would
avoid copying the data into the *info argument. You could then rename pullups
to info (I don't really like the pullups name as the table can contain
pulldown information as well).
> +{
> + unsigned int i;
> +
> + for (i = 0; i < num; i++) {
> + if (pullups[i].pin == pin) {
> + *info = pullups[i];
> + return 0;
> + }
> + }
> +
> + return WARN_ON_ONCE(-EINVAL);
> +}
> +
> static int sh_pfc_init_ranges(struct sh_pfc *pfc)
> {
> struct sh_pfc_pin_range *range;
> diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
> index 0bbdea58..d902cd2 100644
> --- a/drivers/pinctrl/sh-pfc/core.h
> +++ b/drivers/pinctrl/sh-pfc/core.h
> @@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg,
> unsigned int width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned
> int pin);
> int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
>
> +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> + unsigned int num, unsigned int pin,
> + struct sh_pfc_bias_info *info);
> +
> #endif /* __SH_PFC_CORE_H__ */
> diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h
> b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2345421..fc82b6d 100644
> --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> @@ -189,6 +189,12 @@ struct sh_pfc_window {
> unsigned long size;
> };
>
> +struct sh_pfc_bias_info {
> + unsigned int pin;
You should make this a u16, otherwise the structure will be padded to 8 bytes
anyway, removing the benefit of storing reg and bit in 16 bits.
> + u16 reg : 11;
> + u16 bit : 5;
> +};
> +
> struct sh_pfc_pin_range;
>
> struct sh_pfc {
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-11 20:30 ` [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
@ 2016-11-12 1:47 ` Laurent Pinchart
2016-11-12 13:44 ` Niklas Söderlund
0 siblings, 1 reply; 14+ messages in thread
From: Laurent Pinchart @ 2016-11-12 1:47 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio,
Niklas Söderlund
Hi Niklas,
Thank you for the patch.
On Friday 11 Nov 2016 21:30:19 Niklas Söderlund wrote:
> From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> There is a bug in the r8a7795 bias code where a WARN() is trigged
> anytime a pin from PUEN0/PUD0is accessed.
>
> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
>
> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> Call trace:
> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> [<ffff0000081d8874>] vfs_read+0x84/0x148
> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
>
> This is due to the WARN() check if the reg field of the pullups struct
> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> registers since PU0 is defined as 0. Change the data structure and use
> the generic sh_pfc_pin_to_bias_info() function to get the register
> offset and bit information.
>
> Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> support")
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 341 ++++++++++++++------------------
> 1 file changed, 170 insertions(+), 171 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 6c58563..01ca592 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> @@ -5188,171 +5188,168 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> *pfc, unsigned int pin, u32 *poc #define PU5 0x14
> #define PU6 0x18
>
> -static const struct {
> - u16 reg : 11;
> - u16 bit : 5;
> -} pullups[] = {
> - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> -
> - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> -
> - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> -
> - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> -
> - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> -
> - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> -
> - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> +static const struct sh_pfc_bias_info pullups[] = {
I haven't reviewed this table, I trust your regexp skills.
> + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> +
> + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> +
> + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> +
> + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> +
> + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> +
> + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> +
> + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> };
>
> static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> @@ -5360,12 +5357,13 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> sh_pfc *pfc, {
> u32 reg;
> u32 bit;
> + struct sh_pfc_bias_info info;
Nitpicking, why am I the only one to find the code more readable when long
variable declarations come before short ones ? :-)
>
> - if (WARN_ON_ONCE(!pullups[pin].reg))
> + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> return PIN_CONFIG_BIAS_DISABLE;
The implementation will change slightly if you follow my advice regarding
patch 2/6.
The same comments apply to the set_bias function below too, and to patch 5/6
in this series (except for the variable declaration ordering that you got
right there :-)).
Apart from that, for 4/6 and 5/6,
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> - reg = pullups[pin].reg;
> - bit = BIT(pullups[pin].bit);
> + reg = info.reg;
> + bit = BIT(info.bit);
>
> if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> return PIN_CONFIG_BIAS_DISABLE;
> @@ -5381,12 +5379,13 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> *pfc, unsigned int pin, u32 enable, updown;
> u32 reg;
> u32 bit;
> + struct sh_pfc_bias_info info;
>
> - if (WARN_ON_ONCE(!pullups[pin].reg))
> + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> return;
>
> - reg = pullups[pin].reg;
> - bit = BIT(pullups[pin].bit);
> + reg = info.reg;
> + bit = BIT(info.bit);
>
> enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> if (bias != PIN_CONFIG_BIAS_DISABLE)
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table
2016-11-12 1:46 ` Laurent Pinchart
@ 2016-11-12 13:41 ` Niklas Söderlund
0 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-12 13:41 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
Thanks you for the feedback.
On 2016-11-12 03:46:11 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for the patch.
>
> On Friday 11 Nov 2016 21:30:17 Niklas Söderlund wrote:
> > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> >
> > On some SoC there are no simple mapping of pins to bias register bits
> > and a lookup table is needed. This logic is already implemented in some
> > SoC specific drivers that could benefit from a generic implementation.
> >
> > Add helpers to deal with the lookup which later can be used by the SoC
> > specific drivers. The logic used to lookup are different from the one it
> > aims to replace, this is intentional. This new method reduces the memory
> > consumption at the cost of increased CPU usage and fix a bug where a
> > WARN() would incorrectly be triggered if the register offset is 0.
> >
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/core.c | 16 ++++++++++++++++
> > drivers/pinctrl/sh-pfc/core.h | 4 ++++
> > drivers/pinctrl/sh-pfc/sh_pfc.h | 6 ++++++
> > 3 files changed, 26 insertions(+)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
> > index f3a8897..8e38df7 100644
> > --- a/drivers/pinctrl/sh-pfc/core.c
> > +++ b/drivers/pinctrl/sh-pfc/core.c
> > @@ -389,6 +389,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned
> > mark, int pinmux_type) return 0;
> > }
> >
> > +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> > + unsigned int num, unsigned int pin,
> > + struct sh_pfc_bias_info *info)
>
> How about returning a const struct sh_pfc_bias_info * instead ? This would
> avoid copying the data into the *info argument. You could then rename pullups
> to info (I don't really like the pullups name as the table can contain
> pulldown information as well).
Good idea, I will update the patch in this way.
>
> > +{
> > + unsigned int i;
> > +
> > + for (i = 0; i < num; i++) {
> > + if (pullups[i].pin == pin) {
> > + *info = pullups[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return WARN_ON_ONCE(-EINVAL);
> > +}
> > +
> > static int sh_pfc_init_ranges(struct sh_pfc *pfc)
> > {
> > struct sh_pfc_pin_range *range;
> > diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
> > index 0bbdea58..d902cd2 100644
> > --- a/drivers/pinctrl/sh-pfc/core.h
> > +++ b/drivers/pinctrl/sh-pfc/core.h
> > @@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg,
> > unsigned int width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned
> > int pin);
> > int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
> >
> > +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> > + unsigned int num, unsigned int pin,
> > + struct sh_pfc_bias_info *info);
> > +
> > #endif /* __SH_PFC_CORE_H__ */
> > diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h
> > b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2345421..fc82b6d 100644
> > --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> > +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> > @@ -189,6 +189,12 @@ struct sh_pfc_window {
> > unsigned long size;
> > };
> >
> > +struct sh_pfc_bias_info {
> > + unsigned int pin;
>
> You should make this a u16, otherwise the structure will be padded to 8 bytes
> anyway, removing the benefit of storing reg and bit in 16 bits.
Thanks I did not know that, will update.
>
> > + u16 reg : 11;
> > + u16 bit : 5;
> > +};
> > +
> > struct sh_pfc_pin_range;
> >
> > struct sh_pfc {
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table
@ 2016-11-12 13:41 ` Niklas Söderlund
0 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-12 13:41 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
Thanks you for the feedback.
On 2016-11-12 03:46:11 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for the patch.
>
> On Friday 11 Nov 2016 21:30:17 Niklas S�derlund wrote:
> > From: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> >
> > On some SoC there are no simple mapping of pins to bias register bits
> > and a lookup table is needed. This logic is already implemented in some
> > SoC specific drivers that could benefit from a generic implementation.
> >
> > Add helpers to deal with the lookup which later can be used by the SoC
> > specific drivers. The logic used to lookup are different from the one it
> > aims to replace, this is intentional. This new method reduces the memory
> > consumption at the cost of increased CPU usage and fix a bug where a
> > WARN() would incorrectly be triggered if the register offset is 0.
> >
> > Signed-off-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/core.c | 16 ++++++++++++++++
> > drivers/pinctrl/sh-pfc/core.h | 4 ++++
> > drivers/pinctrl/sh-pfc/sh_pfc.h | 6 ++++++
> > 3 files changed, 26 insertions(+)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
> > index f3a8897..8e38df7 100644
> > --- a/drivers/pinctrl/sh-pfc/core.c
> > +++ b/drivers/pinctrl/sh-pfc/core.c
> > @@ -389,6 +389,22 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned
> > mark, int pinmux_type) return 0;
> > }
> >
> > +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> > + unsigned int num, unsigned int pin,
> > + struct sh_pfc_bias_info *info)
>
> How about returning a const struct sh_pfc_bias_info * instead ? This would
> avoid copying the data into the *info argument. You could then rename pullups
> to info (I don't really like the pullups name as the table can contain
> pulldown information as well).
Good idea, I will update the patch in this way.
>
> > +{
> > + unsigned int i;
> > +
> > + for (i = 0; i < num; i++) {
> > + if (pullups[i].pin == pin) {
> > + *info = pullups[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return WARN_ON_ONCE(-EINVAL);
> > +}
> > +
> > static int sh_pfc_init_ranges(struct sh_pfc *pfc)
> > {
> > struct sh_pfc_pin_range *range;
> > diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
> > index 0bbdea58..d902cd2 100644
> > --- a/drivers/pinctrl/sh-pfc/core.h
> > +++ b/drivers/pinctrl/sh-pfc/core.h
> > @@ -33,4 +33,8 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg,
> > unsigned int width, int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned
> > int pin);
> > int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
> >
> > +int sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *pullups,
> > + unsigned int num, unsigned int pin,
> > + struct sh_pfc_bias_info *info);
> > +
> > #endif /* __SH_PFC_CORE_H__ */
> > diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h
> > b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2345421..fc82b6d 100644
> > --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> > +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> > @@ -189,6 +189,12 @@ struct sh_pfc_window {
> > unsigned long size;
> > };
> >
> > +struct sh_pfc_bias_info {
> > + unsigned int pin;
>
> You should make this a u16, otherwise the structure will be padded to 8 bytes
> anyway, removing the benefit of storing reg and bit in 16 bits.
Thanks I did not know that, will update.
>
> > + u16 reg : 11;
> > + u16 bit : 5;
> > +};
> > +
> > struct sh_pfc_pin_range;
> >
> > struct sh_pfc {
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-12 1:47 ` Laurent Pinchart
@ 2016-11-12 13:44 ` Niklas Söderlund
0 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-12 13:44 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
Thanks for your feedback!
On 2016-11-12 03:47:50 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for the patch.
>
> On Friday 11 Nov 2016 21:30:19 Niklas Söderlund wrote:
> > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> >
> > There is a bug in the r8a7795 bias code where a WARN() is trigged
> > anytime a pin from PUEN0/PUD0is accessed.
> >
> > # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >
> > WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> > r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> > Call trace:
> > [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> > [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> > [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> > [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> > [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> > [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> > [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> > [<ffff00000831a110>] full_proxy_read+0x58/0x88
> > [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> > [<ffff0000081d8874>] vfs_read+0x84/0x148
> > [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> > [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >
> > This is due to the WARN() check if the reg field of the pullups struct
> > is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> > registers since PU0 is defined as 0. Change the data structure and use
> > the generic sh_pfc_pin_to_bias_info() function to get the register
> > offset and bit information.
> >
> > Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> > support")
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 341 ++++++++++++++------------------
> > 1 file changed, 170 insertions(+), 171 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 6c58563..01ca592 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > @@ -5188,171 +5188,168 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> > *pfc, unsigned int pin, u32 *poc #define PU5 0x14
> > #define PU6 0x18
> >
> > -static const struct {
> > - u16 reg : 11;
> > - u16 bit : 5;
> > -} pullups[] = {
> > - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> > - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> > - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> > -
> > - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> > - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> > - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> > - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> > - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> > - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> > - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> > - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> > - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> > - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> > - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> > - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> > - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> > - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> > - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> > - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> > - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> > - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> > - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> > - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> > - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> > - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> > - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> > - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> > - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> > - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> > - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> > - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> > - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> > - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> > -
> > - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> > - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> > - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> > - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> > - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> > - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> > - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> > - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> > - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> > - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> > - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> > - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> > - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> > - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> > - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> > - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> > - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> > - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> > - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> > - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> > - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> > - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> > - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> > - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> > - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> > - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> > - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> > - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> > -
> > - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> > - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> > - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> > - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> > - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> > - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> > - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> > - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> > - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> > - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> > - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> > - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> > - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> > - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> > - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> > - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> > - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> > - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> > - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> > - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> > - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> > - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> > -
> > - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> > - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> > - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> > - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> > - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> > - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> > - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> > - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> > - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> > - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> > - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> > - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> > - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> > - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> > - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> > - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> > - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> > - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> > - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> > - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> > - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> > - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> > - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> > - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> > - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> > - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> > - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> > - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> > - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> > - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> > - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> > - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> > -
> > - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> > - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> > - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> > - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> > - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> > - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> > - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> > - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> > - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> > - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> > - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> > - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> > - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> > - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> > - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> > - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> > - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> > - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> > - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> > - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> > - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> > - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> > - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> > - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> > - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> > - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> > - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> > - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> > - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> > - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> > - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> > -
> > - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> > - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> > - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> > - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> > - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> > - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> > - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> > +static const struct sh_pfc_bias_info pullups[] = {
>
> I haven't reviewed this table, I trust your regexp skills.
Geert showed me a nice way to review changes like this:
git diff --color-words
>
> > + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> > + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> > + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> > +
> > + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> > + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> > + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> > + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> > + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> > + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> > + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> > + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> > + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> > + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> > + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> > + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> > + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> > + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> > + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> > + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> > + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> > + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> > + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> > + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> > + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> > + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> > + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> > + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> > + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> > + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> > + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> > + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> > + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> > + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> > +
> > + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> > + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> > + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> > + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> > + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> > + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> > + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> > + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> > + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> > + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> > + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> > + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> > + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> > + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> > + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> > + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> > + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> > + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> > + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> > + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> > + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> > + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> > + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> > + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> > + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> > + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> > + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> > + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> > +
> > + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> > + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> > + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> > + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> > + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> > + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> > + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> > + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> > + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> > + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> > + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> > + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> > + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> > + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> > + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> > + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> > + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> > + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> > + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> > + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> > + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> > + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> > +
> > + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> > + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> > + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> > + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> > + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> > + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> > + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> > + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> > + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> > + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> > + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> > + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> > + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> > + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> > + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> > + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> > + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> > + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> > + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> > + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> > + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> > + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> > + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> > + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> > + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> > + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> > + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> > + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> > + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> > + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> > + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> > + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> > +
> > + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> > + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> > + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> > + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> > + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> > + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> > + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> > + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> > + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> > + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> > + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> > + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> > + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> > + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> > + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> > + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> > + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> > + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> > + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> > + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> > + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> > + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> > + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> > + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> > + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> > + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> > + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> > + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> > + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> > + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> > + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> > +
> > + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> > + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> > + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> > + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> > + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> > + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> > + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> > };
> >
> > static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> > @@ -5360,12 +5357,13 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> > sh_pfc *pfc, {
> > u32 reg;
> > u32 bit;
> > + struct sh_pfc_bias_info info;
>
> Nitpicking, why am I the only one to find the code more readable when
> long variable declarations come before short ones ? :-)
I too find it more readable when longer variables come before short
ones, but in situations like this one where reg and bit are of the same
type but declared on two consecutive lines I get side tracked starring
at that trying to figure out why, also reg and bit are not declared in
alphabetical order... :-)
I will settle on the middle ground here and sort my line length as done
in 5/6 since a new iteration of this series are needed anyhow.
>
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> > return PIN_CONFIG_BIAS_DISABLE;
>
> The implementation will change slightly if you follow my advice regarding
> patch 2/6.
>
> The same comments apply to the set_bias function below too, and to patch 5/6
> in this series (except for the variable declaration ordering that you got
> right there :-)).
>
> Apart from that, for 4/6 and 5/6,
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Thank you, I will follow your advice in 2/6.
>
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > + reg = info.reg;
> > + bit = BIT(info.bit);
> >
> > if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> > return PIN_CONFIG_BIAS_DISABLE;
> > @@ -5381,12 +5379,13 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> > *pfc, unsigned int pin, u32 enable, updown;
> > u32 reg;
> > u32 bit;
> > + struct sh_pfc_bias_info info;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> > return;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > + reg = info.reg;
> > + bit = BIT(info.bit);
> >
> > enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> > if (bias != PIN_CONFIG_BIAS_DISABLE)
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
@ 2016-11-12 13:44 ` Niklas Söderlund
0 siblings, 0 replies; 14+ messages in thread
From: Niklas Söderlund @ 2016-11-12 13:44 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
Thanks for your feedback!
On 2016-11-12 03:47:50 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for the patch.
>
> On Friday 11 Nov 2016 21:30:19 Niklas S�derlund wrote:
> > From: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> >
> > There is a bug in the r8a7795 bias code where a WARN() is trigged
> > anytime a pin from PUEN0/PUD0is accessed.
> >
> > # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >
> > WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> > r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> > Call trace:
> > [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> > [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> > [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> > [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> > [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> > [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> > [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> > [<ffff00000831a110>] full_proxy_read+0x58/0x88
> > [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> > [<ffff0000081d8874>] vfs_read+0x84/0x148
> > [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> > [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >
> > This is due to the WARN() check if the reg field of the pullups struct
> > is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> > registers since PU0 is defined as 0. Change the data structure and use
> > the generic sh_pfc_pin_to_bias_info() function to get the register
> > offset and bit information.
> >
> > Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> > support")
> > Signed-off-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 341 ++++++++++++++------------------
> > 1 file changed, 170 insertions(+), 171 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 6c58563..01ca592 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > @@ -5188,171 +5188,168 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> > *pfc, unsigned int pin, u32 *poc #define PU5 0x14
> > #define PU6 0x18
> >
> > -static const struct {
> > - u16 reg : 11;
> > - u16 bit : 5;
> > -} pullups[] = {
> > - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> > - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> > - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> > -
> > - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> > - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> > - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> > - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> > - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> > - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> > - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> > - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> > - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> > - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> > - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> > - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> > - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> > - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> > - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> > - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> > - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> > - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> > - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> > - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> > - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> > - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> > - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> > - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> > - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> > - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> > - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> > - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> > - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> > - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> > -
> > - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> > - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> > - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> > - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> > - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> > - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> > - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> > - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> > - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> > - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> > - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> > - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> > - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> > - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> > - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> > - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> > - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> > - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> > - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> > - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> > - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> > - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> > - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> > - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> > - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> > - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> > - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> > - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> > -
> > - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> > - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> > - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> > - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> > - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> > - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> > - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> > - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> > - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> > - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> > - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> > - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> > - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> > - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> > - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> > - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> > - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> > - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> > - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> > - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> > - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> > - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> > -
> > - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> > - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> > - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> > - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> > - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> > - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> > - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> > - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> > - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> > - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> > - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> > - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> > - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> > - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> > - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> > - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> > - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> > - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> > - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> > - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> > - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> > - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> > - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> > - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> > - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> > - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> > - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> > - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> > - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> > - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> > - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> > - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> > -
> > - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> > - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> > - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> > - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> > - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> > - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> > - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> > - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> > - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> > - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> > - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> > - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> > - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> > - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> > - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> > - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> > - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> > - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> > - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> > - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> > - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> > - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> > - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> > - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> > - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> > - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> > - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> > - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> > - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> > - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> > - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> > -
> > - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> > - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> > - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> > - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> > - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> > - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> > - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> > +static const struct sh_pfc_bias_info pullups[] = {
>
> I haven't reviewed this table, I trust your regexp skills.
Geert showed me a nice way to review changes like this:
git diff --color-words
>
> > + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> > + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> > + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> > +
> > + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> > + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> > + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> > + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> > + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> > + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> > + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> > + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> > + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> > + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> > + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> > + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> > + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> > + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> > + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> > + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> > + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> > + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> > + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> > + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> > + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> > + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> > + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> > + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> > + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> > + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> > + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> > + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> > + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> > + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> > +
> > + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> > + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> > + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> > + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> > + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> > + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> > + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> > + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> > + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> > + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> > + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> > + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> > + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> > + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> > + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> > + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> > + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> > + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> > + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> > + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> > + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> > + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> > + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> > + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> > + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> > + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> > + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> > + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> > +
> > + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> > + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> > + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> > + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> > + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> > + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> > + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> > + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> > + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> > + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> > + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> > + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> > + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> > + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> > + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> > + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> > + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> > + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> > + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> > + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> > + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> > + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> > +
> > + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> > + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> > + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> > + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> > + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> > + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> > + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> > + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> > + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> > + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> > + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> > + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> > + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> > + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> > + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> > + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> > + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> > + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> > + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> > + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> > + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> > + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> > + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> > + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> > + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> > + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> > + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> > + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> > + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> > + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> > + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> > + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> > +
> > + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> > + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> > + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> > + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> > + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> > + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> > + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> > + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> > + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> > + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> > + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> > + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> > + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> > + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> > + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> > + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> > + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> > + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> > + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> > + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> > + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> > + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> > + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> > + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> > + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> > + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> > + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> > + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> > + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> > + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> > + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> > +
> > + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> > + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> > + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> > + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> > + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> > + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> > + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> > };
> >
> > static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> > @@ -5360,12 +5357,13 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> > sh_pfc *pfc, {
> > u32 reg;
> > u32 bit;
> > + struct sh_pfc_bias_info info;
>
> Nitpicking, why am I the only one to find the code more readable when
> long variable declarations come before short ones ? :-)
I too find it more readable when longer variables come before short
ones, but in situations like this one where reg and bit are of the same
type but declared on two consecutive lines I get side tracked starring
at that trying to figure out why, also reg and bit are not declared in
alphabetical order... :-)
I will settle on the middle ground here and sort my line length as done
in 5/6 since a new iteration of this series are needed anyhow.
>
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> > return PIN_CONFIG_BIAS_DISABLE;
>
> The implementation will change slightly if you follow my advice regarding
> patch 2/6.
>
> The same comments apply to the set_bias function below too, and to patch 5/6
> in this series (except for the variable declaration ordering that you got
> right there :-)).
>
> Apart from that, for 4/6 and 5/6,
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Thank you, I will follow your advice in 2/6.
>
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > + reg = info.reg;
> > + bit = BIT(info.bit);
> >
> > if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> > return PIN_CONFIG_BIAS_DISABLE;
> > @@ -5381,12 +5379,13 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> > *pfc, unsigned int pin, u32 enable, updown;
> > u32 reg;
> > u32 bit;
> > + struct sh_pfc_bias_info info;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (sh_pfc_pin_to_bias_info(pullups, ARRAY_SIZE(pullups), pin, &info))
> > return;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > + reg = info.reg;
> > + bit = BIT(info.bit);
> >
> > enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> > if (bias != PIN_CONFIG_BIAS_DISABLE)
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2016-11-12 13:44 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-11 20:30 [PATCHv2 0/6] pinctrl: sh-pfc: Fixups for bias handling and preparation for none GPIO pins Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 1/6] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 2/6] pinctrl: sh-pfc: Add helper to handle bias lookup table Niklas Söderlund
2016-11-12 1:46 ` Laurent Pinchart
2016-11-12 13:41 ` Niklas Söderlund
2016-11-12 13:41 ` Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 3/6] pinctrl: sh-pfc: r8a7795: Simplify get bias logic Niklas Söderlund
2016-11-11 22:42 ` Laurent Pinchart
2016-11-11 20:30 ` [PATCHv2 4/6] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
2016-11-12 1:47 ` Laurent Pinchart
2016-11-12 13:44 ` Niklas Söderlund
2016-11-12 13:44 ` Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 5/6] pinctrl: sh-pfc: r8a7778: " Niklas Söderlund
2016-11-11 20:30 ` [PATCHv2 6/6] pinctrl: sh-pfc: Support named pins with custom configuration Niklas Söderlund
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