[U-Boot] [PATCH v3 2/3] ids8313: add related support for IDS8313 boards

[U-Boot] [PATCH v3 2/3] ids8313: add related support for IDS8313 boards

[Sergej.Stepanov at ids.de]

The patch adds add related support for IDS8313 boards

Signed-off-by: Sergej Stepanov <ste@ids.de>
Signed-off-by: Rolf Riehle <rl@ids.de>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
---
Changes to v2:
	format issues are fixed
	split into the patchset
	using of I/O accessors
Changes to v3:
	recognition of CU73X / CC73X board types

 board/ids/ids8313/Makefile  |   52 +++++++++++
 board/ids/ids8313/ids8313.c |  196 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 248 insertions(+), 0 deletions(-)
 create mode 100644 board/ids/ids8313/Makefile
 create mode 100644 board/ids/ids8313/ids8313.c

diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile
new file mode 100644
index 0000000..b3e8f7d
--- /dev/null
+++ b/board/ids/ids8313/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2011 IDS GmbH, Germany
+#
+# Sergej Stepanov <ste@ids.de>
+# Based on board/freescale/mpc8313erdb/Makefile
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
new file mode 100644
index 0000000..cfcfe27
--- /dev/null
+++ b/board/ids/ids8313/ids8313.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <libfdt.h>
+
+/* CPLD contains the info about:
+ * - board type: *pCpld & 0xF0
+ * - hw-revision: *pCpld & 0x0F
+ * - cpld-revision: *pCpld+1
+ */
+int checkboard(void)
+{
+	char *pCpld = (char *)CONFIG_SYS_CPLD_BASE;
+	u8 u8Vers = readb(pCpld);
+	u8 u8Revs = readb(pCpld + 1);
+
+	printf("Board: ");
+	switch (u8Vers & 0xF0) {
+	case '\x40':
+		printf("CU73X");
+		break;
+	case '\x50':
+		printf("CC73X");
+		break;
+	default:
+		printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
+		return 0;
+	}
+	printf(", HW-Rev: %i, CPLD-Rev: %i\n",
+	       u8Vers & 0x0F, u8Revs & 0xFF);
+	return 0;
+}
+
+/*
+ *  fixed sdram init
+ */
+int fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#if (CONFIG_SYS_DDR_SIZE != 128)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+	sync();
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+
+	/* currently we use only one CS, so disable the other banks */
+	out_be32(&im->ddr.cs_config[1], 0);
+	out_be32(&im->ddr.cs_config[2], 0);
+	out_be32(&im->ddr.cs_config[3], 0);
+
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	sync();
+	udelay(300);
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	/* now check the real size */
+	disable_addr_trans();
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans();
+#endif
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	fsl_lbc_t *lbc = &im->im_lbc;
+	u32 msize = 0;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	msize = fixed_sdram();
+
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	sync();
+
+	return msize;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
+/* gpio mask for spi_cs */
+#define IDSCPLD_SPI_CS_MASK		0x00000001
+/* spi_cs multiplexed through cpld */
+#define IDSCPLD_SPI_CS_BASE		(CONFIG_SYS_CPLD_BASE + 0xf)
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* deactivate spi_cs channels */
+	out_8(spi_base, 0);
+	/* deactivate the spi_cs */
+	setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* select the spi_cs channel */
+	out_8(spi_base, 1 << slave->cs);
+	/* activate the spi_cs */
+	clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+	u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+	/* select the spi_cs channel */
+	out_8(spi_base, 1 << slave->cs);
+	/* deactivate the spi_cs */
+	setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+#endif /* CONFIG_HARD_SPI */
-- 
1.7.4.4