[igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation

[igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation

[Jason Ekstrand]

I'm trying to clean up some of our uAPI technical debt in i915.  One of the
biggest areas we have right now is context mutability.  There's no good
reason why things like the set of engines or the VM should be able to be
changed on the fly and no "real" userspace actually relies on this
functionality.  It does, however, make for a good excuse for tests and lots
of bug reports as things like swapping out the set of engines under load
break randomly.  The solution here is to stop allowing that behavior and
simplify the i915 internals.

In particular, we'd like to remove the following from the i915 API:

 1. I915_CONTEXT_CLONE_*.  These are only used by IGT and have never been
    used by any "real" userspace.

 2. Changing the VM or set of engines via SETPARAM after they've been
    "used" by an execbuf or similar.  This would effectively make those
    parameters create params rather than mutable state.  We can't drop
    setparam entirely for those because media does use it but we can
    enforce some rules.

 3. Unused (by non-IGT userspace) GETPARAM for things like engines.

As much as we'd love to do that, we have a bit of a problem in IGT.  The
way we handle multi-engine testing today relies heavily on this soon-to-be-
deprecated functionality.  In particular, the standard flow is usually
something like this:

    static void run_test1(int fd, uint32_t engine)
    {
        igt_spin_t *spin;

        ctx = = gem_context_clone_with_engines(fd, 0);
        __igt_spin_new(fd, ctx, .engine = engine);

        /* do some testing with ctx */

        igt_spin_free(fd, spin);
        gem_destroy_context(fd, ctx);
    }

    igt_main
    {
        struct intel_execution_engine2 *e;

        /* Usual fixture code */

        __for_each_physical_engine(fd, e)
            run_test1(fd, e->flags);

        __for_each_physical_engine(fd, e)
            run_test2(fd, e->flags);
    }

Let's walk through what this does:

 1. __for_each_physical_engine calls intel_init_engine_list() which resets
    the set of engines on ctx0 to the full set of engines available as per
    the engine query.  On older kernels/hardware where we don't have the
    engines query, it leaves the set alone.

 2. intel_init_engine_list() also returns a set of engines for iteration
    and __for_each_physical_engine() sets up a for loop to walk the set.

 3. gem_context_clone_with_engines() creates a new context using
    I915_CONTEXT_CONTEXT_CLONE_ENGINES (not used by anything other than
    IGT) to ask that the newly created context has the same set of engines
    as ctx0.  Remember we changed that at the start of loop iteration!

 4. When the context is passed to __igt_spin_new(), it calls
    gem_context_lookup_engine which does a GETPARAM to introspet the set of
    engines on the context and figure out the engine class.

If you've been keeping track, this trivial and extremely common example
uses every single one of these soon-to-be-deprecated APIs even though the
test author may be completely obvious to it.  It also means that getting
rid of IGT's use of them is going to require some fairly deep surgery.

The approach proposed and partially implemented here is to add a new
wrapper struct intel_ctx_t which wraps a GEM context handle as well as the
full set of parameters used to create it, represented by intel_ctx_cfg_t.
We can then use the context anywhere we would regularly use a context, we
just have to do ctx->id.  If we want to clone it, we can do so by re-using
the create parameters by calling intel_ctx_create(fd, &old_ctx->cfg);

Along with the above rework (which got long, sorry) I've got a few other
patches in here which delete tests which exist expressly to test APIs that
are on the chopping block.

--Jason


Cc: Daniel Vetter <daniel@ffwll.ch>

Jason Ekstrand (74):
  tests/i915: Drop gem_ctx_ringsize
  tests/i915/gem_exec_balancer: Drop the ringsize subtest
  tests/i915/gem_exec_endless: Stop setting the ring size
  tests/i915/gem_ctx_param: Drop the zeromap subtests
  tests/i915: Drop gem_ctx_clone
  lib/i915/gem_engine_topology: Expose the __query_engines helper
  lib/i915/gem_context: Add gem_context_create_ext helpers
  lib: Add an intel_ctx wrapper struct and helpers (v2)
  lib/i915/gem_engine_topology: Rework query_engine_list()
  lib/i915/gem_engine_topology: Factor out static engine listing
  lib/i915/gem_engine_topology: Add an iterator which doesn't munge
    contexts
  lib/i915/gem_engine_topology: Add an iterator for intel_ctx_t
  tests/i915/gem_exec_basic: Convert to intel_ctx_t
  lib/igt_spin: Rename igt_spin_factory::ctx to ctx_id
  lib/igt_spin: Support intel_ctx_t
  tests/i915/gem_exec_fence: Move the engine data into
    inter_engine_context
  tests/i915/gem_exec_fence: Convert to intel_ctx_t
  tests/i915/gem_exec_schedule: Convert to intel_ctx_t
  tests/i915/perf_pmu: Convert to intel_ctx_t
  tests/i915/gem_exec_nop: Convert to intel_ctx_t
  tests/i915/gem_exec_reloc: Convert to intel_ctx_t
  tests/i915/gem_busy: Convert to intel_ctx_t
  tests/i915/gem_ctx_isolation: Convert to intel_ctx_t
  tests/i915/gem_exec_async: Convert to intel_ctx_t
  tests/i915/sysfs_clients: Convert to intel_ctx_t
  tests/i915/gem_exec_fair: Convert to intel_ctx_t
  tests/i915/gem_spin_batch: Convert to intel_ctx_t
  tests/i915/gem_exec_store: Convert to intel_ctx_t
  tests/amdgpu/amd_prime: Convert to intel_ctx_t
  tests/i915/i915_hangman: Convert to intel_ctx_t
  tests/i915/gem_ringfill: Convert to intel_ctx_t
  tests/prime_busy: Convert to intel_ctx_t
  tests/prime_vgem: Convert to intel_ctx_t
  tests/gem_exec_whisper: Convert to intel_ctx_t
  tests/i915/gem_ctx_exec: Stop cloning contexts in close_race
  tests/i915/gem_ctx_exec: Convert to intel_ctx_t
  tests/i915/gem_exec_suspend: Convert to intel_ctx_t
  tests/i915/gem_sync: Convert to intel_ctx_t
  tests/i915/gem_userptr_blits: Convert to intel_ctx_t
  tests/i915/gem_wait: Convert to intel_ctx_t
  tests/i915/gem_request_retire: Convert to intel_ctx_t
  tests/i915/gem_ctx_shared: Convert to intel_ctx_t
  tests/i915/gem_ctx_shared: Stop cloning contexts
  tests/i915/gem_create: Convert to intel_ctx_t
  tests/i915/gem_ctx_switch: Convert to intel_ctx_t
  tests/i915/gem_exec_parallel: Convert to intel_ctx_t
  tests/i915/gem_exec_latency: Convert to intel_ctx_t
  tests/i915/gem_watchdog: Convert to intel_ctx_t
  tests/i915/gem_shrink: Convert to intel_ctx_t
  tests/i915/gem_exec_params: Convert to intel_ctx_t
  tests/i915/gem_exec_gttfill: Convert to intel_ctx_t
  tests/i915/gem_exec_capture: Convert to intel_ctx_t
  tests/i915/gem_exec_create: Convert to intel_ctx_t
  tests/i915/gem_exec_await: Convert to intel_ctx_t
  tests/i915/gem_ctx_persistence: Drop the clone subtest
  tests/i915/gem_ctx_persistence: Drop the engine replace subtests
  tests/i915/gem_ctx_persistence: Convert to intel_ctx_t
  tests/i915/module_load: Convert to intel_ctx_t
  tests/i915/pm_rc6_residency: Convert to intel_ctx_t
  tests/i915/gem_cs_tlb: Convert to intel_ctx_t
  tests/core_hotplug: Convert to intel_ctx_t
  tests/i915/gem_exec_balancer: Stop cloning engines
  tests/i915/gem_exec_balancer: Don't reset engines on a context
  tests/i915/gem_exec_balancer: Stop munging ctx0 engines
  tests/i915/gem_exec_endless: Stop munging ctx0 engines
  lib/i915: Use for_each_physical_ring for submission tests
  tests/i915/gem_ctx_engines: Rework execute-one*
  tests/i915/gem_ctx_engines: Use better engine iteration
  tests/i915/gem_ctx_engines: Drop the idempotent subtest
  tests/i915/gem_ctx_create: Convert benchmarks to intel_ctx_t
  lib/i915/gem_context: Delete all the context clone/copy stuff
  tests/i915/gem_ctx_engines: Delete the libapi subtest
  lib/igt_dummyload: Stop supporting ALL_ENGINES without an intel_ctx_t
  lib/i915/gem_engine_topology: Delete the old physical engine iterators

 lib/i915/gem_context.c             | 206 ++-----
 lib/i915/gem_context.h             |  19 +-
 lib/i915/gem_engine_topology.c     | 142 +++--
 lib/i915/gem_engine_topology.h     |  29 +-
 lib/i915/gem_submission.c          |  13 +-
 lib/igt_dummyload.c                |  13 +-
 lib/igt_dummyload.h                |   6 +-
 lib/igt_gt.c                       |   2 +-
 lib/intel_ctx.c                    | 177 ++++++
 lib/intel_ctx.h                    | 112 ++++
 lib/meson.build                    |   1 +
 tests/amdgpu/amd_prime.c           |  10 +-
 tests/core_hotunplug.c             |   6 +-
 tests/i915/gem_busy.c              |  77 +--
 tests/i915/gem_create.c            |  14 +-
 tests/i915/gem_cs_tlb.c            |  10 +-
 tests/i915/gem_ctx_clone.c         | 450 ---------------
 tests/i915/gem_ctx_create.c        |  76 +--
 tests/i915/gem_ctx_engines.c       | 239 ++------
 tests/i915/gem_ctx_exec.c          |  19 +-
 tests/i915/gem_ctx_isolation.c     | 112 ++--
 tests/i915/gem_ctx_param.c         |  33 --
 tests/i915/gem_ctx_persistence.c   | 435 ++++----------
 tests/i915/gem_ctx_ringsize.c      | 345 ------------
 tests/i915/gem_ctx_shared.c        | 335 ++++++-----
 tests/i915/gem_ctx_switch.c        | 115 ++--
 tests/i915/gem_eio.c               |   2 +-
 tests/i915/gem_exec_async.c        |  32 +-
 tests/i915/gem_exec_await.c        |  20 +-
 tests/i915/gem_exec_balancer.c     | 293 ++++------
 tests/i915/gem_exec_basic.c        |   7 +-
 tests/i915/gem_exec_capture.c      |  30 +-
 tests/i915/gem_exec_create.c       |   9 +-
 tests/i915/gem_exec_endless.c      |  14 +-
 tests/i915/gem_exec_fair.c         | 112 ++--
 tests/i915/gem_exec_fence.c        | 302 +++++-----
 tests/i915/gem_exec_gttfill.c      |  15 +-
 tests/i915/gem_exec_latency.c      | 118 ++--
 tests/i915/gem_exec_nop.c          | 156 ++---
 tests/i915/gem_exec_parallel.c     |  29 +-
 tests/i915/gem_exec_params.c       |   4 +-
 tests/i915/gem_exec_reloc.c        | 102 ++--
 tests/i915/gem_exec_schedule.c     | 876 +++++++++++++++--------------
 tests/i915/gem_exec_store.c        |  36 +-
 tests/i915/gem_exec_suspend.c      |  52 +-
 tests/i915/gem_exec_whisper.c      |  83 ++-
 tests/i915/gem_request_retire.c    |  17 +-
 tests/i915/gem_ringfill.c          |  48 +-
 tests/i915/gem_shrink.c            |  37 +-
 tests/i915/gem_spin_batch.c        |  79 +--
 tests/i915/gem_sync.c              | 159 +++---
 tests/i915/gem_userptr_blits.c     |  25 +-
 tests/i915/gem_vm_create.c         |   4 +-
 tests/i915/gem_wait.c              |  20 +-
 tests/i915/gem_watchdog.c          | 167 ++----
 tests/i915/gem_workarounds.c       |   2 +-
 tests/i915/i915_hangman.c          |  37 +-
 tests/i915/i915_module_load.c      |   7 +-
 tests/i915/i915_pm_rc6_residency.c |   7 +-
 tests/i915/perf_pmu.c              | 226 ++++----
 tests/i915/sysfs_clients.c         |  87 +--
 tests/meson.build                  |   2 -
 tests/prime_busy.c                 |  19 +-
 tests/prime_vgem.c                 |  35 +-
 64 files changed, 2785 insertions(+), 3481 deletions(-)
 create mode 100644 lib/intel_ctx.c
 create mode 100644 lib/intel_ctx.h
 delete mode 100644 tests/i915/gem_ctx_clone.c
 delete mode 100644 tests/i915/gem_ctx_ringsize.c

-- 
2.31.1

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[igt-dev] [PATCH i-g-t 01/74] tests/i915: Drop gem_ctx_ringsize

[Jason Ekstrand]

I915_CONTEXT_PARAM_RINGSIZE is being removed from upstream i915 because
it's never been used by any userspace other than IGT.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/i915/gem_ctx_ringsize.c | 345 ----------------------------------
 tests/meson.build             |   1 -
 2 files changed, 346 deletions(-)
 delete mode 100644 tests/i915/gem_ctx_ringsize.c

diff --git a/tests/i915/gem_ctx_ringsize.c b/tests/i915/gem_ctx_ringsize.c
deleted file mode 100644
index 60187b7c..00000000
--- a/tests/i915/gem_ctx_ringsize.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * Copyright © 2019 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <math.h>
-#include <signal.h>
-#include <sys/ioctl.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "drmtest.h"
-#include "i915/gem.h"
-#include "i915/gem_context.h"
-#include "i915/gem_engine_topology.h"
-#include "ioctl_wrappers.h" /* gem_wait()! */
-#include "sw_sync.h"
-
-static bool has_ringsize(int i915)
-{
-	struct drm_i915_gem_context_param p = {
-		.param = I915_CONTEXT_PARAM_RINGSIZE,
-	};
-
-	return __gem_context_get_param(i915, &p) == 0;
-}
-
-static void test_idempotent(int i915)
-{
-	struct drm_i915_gem_context_param p = {
-		.param = I915_CONTEXT_PARAM_RINGSIZE,
-	};
-	uint32_t saved;
-
-	/*
-	 * Simple test to verify that we are able to read back the same
-	 * value as we set.
-	 */
-
-	gem_context_get_param(i915, &p);
-	saved = p.value;
-
-	for (uint32_t x = 1 << 12; x <= 128 << 12; x <<= 1) {
-		p.value = x;
-		gem_context_set_param(i915, &p);
-		gem_context_get_param(i915, &p);
-		igt_assert_eq_u32(p.value, x);
-	}
-
-	p.value = saved;
-	gem_context_set_param(i915, &p);
-}
-
-static void test_invalid(int i915)
-{
-	struct drm_i915_gem_context_param p = {
-		.param = I915_CONTEXT_PARAM_RINGSIZE,
-	};
-	uint64_t invalid[] = {
-		0, 1, 4095, 4097, 8191, 8193,
-		/* upper limit may be HW dependent, atm it is 512KiB */
-		(512 << 10) - 1, (512 << 10) + 1,
-		-1, -1u
-	};
-	uint32_t saved;
-
-	/*
-	 * The HW only accepts certain aligned values and so we reject
-	 * any invalid sizes specified by the user.
-	 *
-	 * Currently, the HW only accepts 4KiB - 512KiB in 4K increments,
-	 * and is unlikely to ever accept smaller.
-	 */
-
-	gem_context_get_param(i915, &p);
-	saved = p.value;
-
-	for (int i = 0; i < ARRAY_SIZE(invalid); i++) {
-		p.value = invalid[i];
-		igt_assert_eq(__gem_context_set_param(i915, &p), -EINVAL);
-		gem_context_get_param(i915, &p);
-		igt_assert_eq_u64(p.value, saved);
-	}
-}
-
-static int create_ext_ioctl(int i915,
-			    struct drm_i915_gem_context_create_ext *arg)
-{
-	int err;
-
-	err = 0;
-	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
-		err = -errno;
-		igt_assume(err);
-	}
-
-	errno = 0;
-	return err;
-}
-
-static void test_create(int i915)
-{
-	struct drm_i915_gem_context_create_ext_setparam p = {
-		.base = {
-			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
-			.next_extension = 0, /* end of chain */
-		},
-		.param = {
-			.param = I915_CONTEXT_PARAM_RINGSIZE,
-			.value = 512 << 10,
-		}
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&p),
-	};
-
-	/*
-	 * Check that the ringsize parameter is used during context constuction.
-	 */
-
-	igt_assert_eq(create_ext_ioctl(i915, &create),  0);
-
-	p.param.ctx_id = create.ctx_id;
-	p.param.value = 0;
-	gem_context_get_param(i915, &p.param);
-	igt_assert_eq(p.param.value, 512 << 10);
-
-	gem_context_destroy(i915, create.ctx_id);
-}
-
-static void test_clone(int i915)
-{
-	struct drm_i915_gem_context_create_ext_setparam p = {
-		.base = {
-			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
-			.next_extension = 0, /* end of chain */
-		},
-		.param = {
-			.param = I915_CONTEXT_PARAM_RINGSIZE,
-			.value = 512 << 10,
-		}
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&p),
-	};
-
-	/*
-	 * Check that the ringsize is copied across during context cloning.
-	 */
-
-	igt_assert_eq(create_ext_ioctl(i915, &create),  0);
-
-	p.param.ctx_id = gem_context_clone(i915, create.ctx_id,
-					   I915_CONTEXT_CLONE_ENGINES, 0);
-	igt_assert_neq(p.param.ctx_id, create.ctx_id);
-	gem_context_destroy(i915, create.ctx_id);
-
-	p.param.value = 0;
-	gem_context_get_param(i915, &p.param);
-	igt_assert_eq(p.param.value, 512 << 10);
-
-	gem_context_destroy(i915, p.param.ctx_id);
-}
-
-static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
-{
-	int err;
-
-	err = 0;
-	if (ioctl(i915, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf)) {
-		err = -errno;
-		igt_assume(err);
-	}
-
-	errno = 0;
-	return err;
-}
-
-#define IDLE (1 << 0)
-#define PLUG (1 << 1)
-
-static void sighandler(int sig)
-{
-}
-
-static unsigned int
-measure_inflight(int i915, unsigned int engine, int timeout, unsigned int flags)
-{
-	IGT_CORK_FENCE(cork);
-	unsigned int count;
-	igt_spin_t *spin;
-	int fence;
-	int err;
-
-	fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) | O_NONBLOCK);
-	signal(SIGALRM, sighandler);
-	alarm(timeout);
-
-	fence = igt_cork_plug(&cork, i915);
-	spin = igt_spin_new(i915,
-			    .engine = engine,
-			    .fence = fence,
-			    .flags = (flags & PLUG) ? IGT_SPIN_FENCE_IN : 0);
-	for (count = 1; (err = __execbuf(i915, &spin->execbuf)) == 0; count++)
-		;
-	igt_debugfs_dump(i915, "i915_engine_info");
-	igt_assert_eq(err, -EWOULDBLOCK);
-	close(fence);
-
-	alarm(0);
-	signal(SIGALRM, SIG_DFL);
-	fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) & ~O_NONBLOCK);
-
-	igt_spin_free(i915, spin);
-	igt_cork_unplug(&cork);
-
-	return count;
-}
-
-static void test_resize(int i915,
-			const struct intel_execution_engine2 *e,
-			void *data)
-#define as_pointer(x) (void *)(uintptr_t)(x)
-{
-	struct drm_i915_gem_context_param p = {
-		.param = I915_CONTEXT_PARAM_RINGSIZE,
-	};
-	unsigned long flags = (uintptr_t)data;
-	unsigned int prev[2] = {};
-	uint64_t elapsed;
-	uint32_t saved;
-
-	/*
-	 * The ringsize directly affects the number of batches we can have
-	 * inflight -- when we run out of room in the ring, the client is
-	 * blocked (or if O_NONBLOCK is specified, -EWOULDBLOCK is reported).
-	 * The kernel throttles the client when they enter the last 4KiB page,
-	 * so as we double the size of the ring, we nearly double the number
-	 * of requests we can fit as 2^n-1: i.e 0, 1, 3, 7, 15, 31 pages.
-	 */
-
-	gem_context_get_param(i915, &p);
-	saved = p.value;
-
-	/* XXX disable hangchecking? */
-	elapsed = 0;
-	gem_quiescent_gpu(i915);
-	for (p.value = 1 << 12; p.value <= 128 << 12; p.value <<= 1) {
-		struct timespec tv = {};
-		unsigned int count;
-
-		gem_context_set_param(i915, &p);
-
-		igt_nsec_elapsed(&tv);
-		count = measure_inflight(i915,
-					 e->flags,
-					 1 + 4 * ceil(elapsed*1e-9),
-					 flags);
-		elapsed = igt_nsec_elapsed(&tv);
-
-		igt_info("%s: %6llx -> %'6d\n", e->name, p.value, count);
-		igt_assert(count > 3 * (prev[1] - prev[0]) / 4 + prev[1]);
-		if (flags & IDLE)
-			gem_quiescent_gpu(i915);
-
-		prev[0] = prev[1];
-		prev[1] = count;
-	}
-	gem_quiescent_gpu(i915);
-
-	p.value = saved;
-	gem_context_set_param(i915, &p);
-}
-
-static void gem_test_each_engine(int i915, const char *name,
-				 void (*fn)(int i915,
-					    const struct intel_execution_engine2 *e,
-					    void *data),
-				 void *data)
-{
-	const struct intel_execution_engine2 *e;
-
-	igt_subtest_with_dynamic(name) {
-		__for_each_physical_engine(i915, e) {
-			igt_dynamic_f("%s", e->name)
-				fn(i915, e, data);
-		}
-	}
-}
-
-igt_main
-{
-	int i915;
-
-	igt_fixture {
-		i915 = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(i915);
-
-		igt_require(has_ringsize(i915));
-	}
-
-	igt_subtest("idempotent")
-		test_idempotent(i915);
-
-	igt_subtest("invalid")
-		test_invalid(i915);
-
-	igt_subtest("create")
-		test_create(i915);
-	igt_subtest("clone")
-		test_clone(i915);
-
-	gem_test_each_engine(i915, "idle", test_resize, as_pointer(IDLE));
-	gem_test_each_engine(i915, "active", test_resize, 0);
-	gem_test_each_engine(i915, "plugged", test_resize, as_pointer(PLUG));
-
-	/* XXX ctx->engines[]? Clone (above) should be enough */
-
-	igt_fixture {
-		close(i915);
-	}
-}
diff --git a/tests/meson.build b/tests/meson.build
index 6ad34409..2c579d4c 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -133,7 +133,6 @@ i915_progs = [
 	'gem_ctx_isolation',
 	'gem_ctx_param',
 	'gem_ctx_persistence',
-	'gem_ctx_ringsize',
 	'gem_ctx_shared',
 	'gem_ctx_switch',
 	'gem_evict_alignment',
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 02/74] tests/i915/gem_exec_balancer: Drop the ringsize subtest

[Jason Ekstrand]

I915_CONTEXT_PARAM_RINGSIZE is being removed from upstream i915 because
it's never been used by any userspace other than IGT.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/i915/gem_exec_balancer.c | 81 ----------------------------------
 1 file changed, 81 deletions(-)

diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 01db0e11..bfd65b29 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -2551,84 +2551,6 @@ next:
 	gem_quiescent_gpu(i915);
 }
 
-static void sighandler(int sig)
-{
-}
-
-static unsigned int measure_inflight(int i915, uint32_t ctx, int timeout)
-{
-	igt_spin_t *spin = igt_spin_new(i915, ctx);
-	unsigned int count;
-	int err;
-
-	fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) | O_NONBLOCK);
-	signal(SIGALRM, sighandler);
-	alarm(timeout);
-
-	for (count = 1; (err = __execbuf(i915, &spin->execbuf)) == 0; count++)
-		;
-	igt_assert_eq(err, -EWOULDBLOCK);
-
-	alarm(0);
-	signal(SIGALRM, SIG_DFL);
-	fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) & ~O_NONBLOCK);
-
-	igt_spin_free(i915, spin);
-
-	return count;
-}
-
-static void __resize(int i915, uint32_t ctx)
-{
-	struct drm_i915_gem_context_param p = {
-		.ctx_id = ctx,
-		.param = I915_CONTEXT_PARAM_RINGSIZE,
-	};
-	unsigned int prev[2] = {};
-	uint64_t elapsed;
-
-	elapsed = 0;
-	gem_quiescent_gpu(i915);
-	for (p.value = 1 << 12; p.value <= 128 << 12; p.value <<= 1) {
-		struct timespec tv = {};
-		unsigned int count;
-
-		gem_context_set_param(i915, &p);
-
-		igt_nsec_elapsed(&tv);
-		count = measure_inflight(i915, ctx, 1 + 4 * ceil(elapsed*1e-9));
-		elapsed = igt_nsec_elapsed(&tv);
-
-		igt_info("%6llx -> %'6d\n", p.value, count);
-		igt_assert(count > 3 * (prev[1] - prev[0]) / 4 + prev[1]);
-
-		prev[0] = prev[1];
-		prev[1] = count;
-	}
-	gem_quiescent_gpu(i915);
-}
-
-static void ringsz(int i915)
-{
-	for (int class = 0; class < 32; class++) {
-		struct i915_engine_class_instance *ci;
-		unsigned int count;
-		uint32_t ctx;
-
-		ci = list_engines(i915, 1u << class, &count);
-		if (!ci || count < 2)
-			goto next;
-
-		ctx = load_balancer_create(i915, ci, count);
-		__resize(i915, ctx);
-		gem_context_destroy(i915, ctx);
-next:
-		free(ci);
-	}
-
-	gem_quiescent_gpu(i915);
-}
-
 static void ping(int i915, uint32_t ctx, unsigned int engine)
 {
 	struct drm_i915_gem_exec_object2 obj = {
@@ -3304,9 +3226,6 @@ igt_main
 	igt_subtest("fairslice")
 		fairslice(i915);
 
-	igt_subtest("ringsize")
-		ringsz(i915);
-
 	igt_subtest("nop")
 		nop(i915);
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 03/74] tests/i915/gem_exec_endless: Stop setting the ring size

[Jason Ekstrand]

I915_CONTEXT_PARAM_RINGSIZE is being removed from upstream i915 because
it's never been used by any userspace other than IGT.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/i915/gem_exec_endless.c | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/tests/i915/gem_exec_endless.c b/tests/i915/gem_exec_endless.c
index 1b320d4c..a3e2fa49 100644
--- a/tests/i915/gem_exec_endless.c
+++ b/tests/i915/gem_exec_endless.c
@@ -67,16 +67,6 @@ static unsigned int offset_in_page(void *addr)
 static uint32_t __supervisor_create_context(int i915,
 					    const struct intel_execution_engine2 *e)
 {
-	struct drm_i915_gem_context_create_ext_setparam p_ring = {
-		{
-			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
-			.next_extension = 0
-		},
-		{
-			.param = I915_CONTEXT_PARAM_RINGSIZE,
-			.value = 4096,
-		},
-	};
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
 		.engines = {
 			{ e->class, e->instance },
@@ -86,7 +76,7 @@ static uint32_t __supervisor_create_context(int i915,
 	struct drm_i915_gem_context_create_ext_setparam p_engines = {
 		{
 			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
-			.next_extension = to_user_pointer(&p_ring)
+			.next_extension = 0,
 		},
 		{
 			.param = I915_CONTEXT_PARAM_ENGINES,
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 04/74] tests/i915/gem_ctx_param: Drop the zeromap subtests

[Jason Ekstrand]

The idea behind this param is to support OpenCL drivers with relocations
because OpenCL reserves 0x0 for NULL and, if we placed memory there, it
would confuse CL kernels.  It was originally sent out as part of a patch
series including libdrm [1] and Beignet [2] support.  However, the
libdrm and Beignet patches never landed in their respective upstream
projects so this API has never been used.  It's never been used in Mesa
or any other driver, either.

This means that these IGT tests are the only userspace for NO_ZEROMAP
which has ever really existed.  Let's drop them and drop support from
i915 as well.

[1]: https://lists.freedesktop.org/archives/intel-gfx/2015-May/067030.html
[2]: https://lists.freedesktop.org/archives/intel-gfx/2015-May/067031.html

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/i915/gem_ctx_param.c | 33 ---------------------------------
 1 file changed, 33 deletions(-)

diff --git a/tests/i915/gem_ctx_param.c b/tests/i915/gem_ctx_param.c
index ab0e3007..47fea06d 100644
--- a/tests/i915/gem_ctx_param.c
+++ b/tests/i915/gem_ctx_param.c
@@ -335,39 +335,6 @@ igt_main
 		gem_context_set_param(fd, &arg);
 	}
 
-	arg.param = I915_CONTEXT_PARAM_NO_ZEROMAP;
-
-	igt_describe("Validates context set param ioctl in non root mode with param "
-	       "set to no zeromap");
-	igt_subtest("non-root-set-no-zeromap") {
-		igt_fork(child, 1) {
-			igt_drop_root();
-
-			arg.ctx_id = ctx;
-			gem_context_get_param(fd, &arg);
-			arg.value--;
-			gem_context_set_param(fd, &arg);
-		}
-
-		igt_waitchildren();
-	}
-
-	igt_describe("Tests the context set param ioctl with no zeromap enabled in root mode");
-	igt_subtest("root-set-no-zeromap-enabled") {
-		arg.ctx_id = ctx;
-		gem_context_get_param(fd, &arg);
-		arg.value = 1;
-		gem_context_set_param(fd, &arg);
-	}
-
-	igt_describe("Tests the context set param ioctl with no zeromap disabled in root mode");
-	igt_subtest("root-set-no-zeromap-disabled") {
-		arg.ctx_id = ctx;
-		gem_context_get_param(fd, &arg);
-		arg.value = 0;
-		gem_context_set_param(fd, &arg);
-	}
-
 	igt_describe("Tests that multiple contexts can share the same VMA");
 	igt_subtest("vm")
 		test_vm(fd);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 05/74] tests/i915: Drop gem_ctx_clone

[Jason Ekstrand]

We're going to be deleting the CONTEXT_CLONE API since IGT is the only
userspace to ever use it.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/i915/gem_ctx_clone.c | 450 -------------------------------------
 tests/meson.build          |   1 -
 2 files changed, 451 deletions(-)
 delete mode 100644 tests/i915/gem_ctx_clone.c

diff --git a/tests/i915/gem_ctx_clone.c b/tests/i915/gem_ctx_clone.c
deleted file mode 100644
index b72269bc..00000000
--- a/tests/i915/gem_ctx_clone.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * Copyright © 2019 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "i915/gem.h"
-#include "i915/gem_vm.h"
-#include "i915_drm.h"
-#include "igt.h"
-#include "igt_gt.h"
-
-static int ctx_create_ioctl(int i915, struct drm_i915_gem_context_create_ext *arg)
-{
-	int err;
-
-	err = 0;
-	if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, arg)) {
-		err = -errno;
-		igt_assume(err);
-	}
-
-	errno = 0;
-	return err;
-}
-
-static void invalid_clone(int i915)
-{
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-
-	igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-	gem_context_destroy(i915, create.ctx_id);
-
-	ext.flags = -1; /* Hopefully we won't run out of flags */
-	igt_assert_eq(ctx_create_ioctl(i915, &create), -EINVAL);
-	ext.flags = 0;
-
-	ext.base.next_extension = -1;
-	igt_assert_eq(ctx_create_ioctl(i915, &create), -EFAULT);
-	ext.base.next_extension = to_user_pointer(&ext);
-	igt_assert_eq(ctx_create_ioctl(i915, &create), -E2BIG);
-	ext.base.next_extension = 0;
-
-	ext.clone_id = -1;
-	igt_assert_eq(ctx_create_ioctl(i915, &create), -ENOENT);
-	ext.clone_id = 0;
-}
-
-static void clone_flags(int i915)
-{
-	struct drm_i915_gem_context_create_ext_setparam set = {
-		{ .name = I915_CONTEXT_CREATE_EXT_SETPARAM },
-		{ .param = I915_CONTEXT_PARAM_RECOVERABLE },
-	};
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.flags = I915_CONTEXT_CLONE_FLAGS,
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-	int expected;
-
-	set.param.value = 1; /* default is recoverable */
-	igt_require(__gem_context_set_param(i915, &set.param) == 0);
-
-	for (int pass = 0; pass < 2; pass++) { /* cloning default, then child */
-		igt_debug("Cloning %d\n", ext.clone_id);
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		set.param.ctx_id = ext.clone_id;
-		gem_context_get_param(i915, &set.param);
-		expected = set.param.value;
-
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.param,
-				  I915_CONTEXT_PARAM_RECOVERABLE);
-		igt_assert_eq((int)set.param.value, expected);
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		expected = set.param.value = 0;
-		set.param.ctx_id = ext.clone_id;
-		gem_context_set_param(i915, &set.param);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.param,
-				  I915_CONTEXT_PARAM_RECOVERABLE);
-		igt_assert_eq((int)set.param.value, expected);
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		/* clone but then reset priority to default... */
-		set.param.ctx_id = 0;
-		set.param.value = 1;
-		ext.base.next_extension = to_user_pointer(&set);
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		ext.base.next_extension = 0;
-
-		/* then new context should have updated priority... */
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.value, 1);
-
-		/* but original context should have default priority */
-		set.param.ctx_id = ext.clone_id;
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.value, 0);
-
-		gem_context_destroy(i915, create.ctx_id);
-		ext.clone_id = gem_context_create(i915);
-	}
-
-	gem_context_destroy(i915, ext.clone_id);
-}
-
-static void clone_engines(int i915)
-{
-	struct drm_i915_gem_context_create_ext_setparam set = {
-		{ .name = I915_CONTEXT_CREATE_EXT_SETPARAM },
-		{ .param = I915_CONTEXT_PARAM_ENGINES },
-	};
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.flags = I915_CONTEXT_CLONE_ENGINES,
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(expected, 64);
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 64);
-	uint64_t ex_size;
-
-	memset(&expected, 0, sizeof(expected));
-	memset(&engines, 0, sizeof(engines));
-
-	igt_require(__gem_context_set_param(i915, &set.param) == 0);
-
-	for (int pass = 0; pass < 2; pass++) { /* cloning default, then child */
-		igt_debug("Cloning %d\n", ext.clone_id);
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		/* Check that we cloned the engine map */
-		set.param.ctx_id = ext.clone_id;
-		set.param.size = sizeof(expected);
-		set.param.value = to_user_pointer(&expected);
-		gem_context_get_param(i915, &set.param);
-		ex_size = set.param.size;
-
-		set.param.ctx_id = create.ctx_id;
-		set.param.size = sizeof(engines);
-		set.param.value = to_user_pointer(&engines);
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.param, I915_CONTEXT_PARAM_ENGINES);
-		igt_assert_eq_u64(set.param.size, ex_size);
-		igt_assert(!memcmp(&engines, &expected, ex_size));
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		/* Check that the clone will replace an earlier set */
-		expected.engines[0].engine_class =
-			I915_ENGINE_CLASS_INVALID;
-		expected.engines[0].engine_instance =
-			I915_ENGINE_CLASS_INVALID_NONE;
-		ex_size = (sizeof(struct i915_context_param_engines) +
-			   sizeof(expected.engines[0]));
-
-		set.param.ctx_id = ext.clone_id;
-		set.param.size = ex_size;
-		set.param.value = to_user_pointer(&expected);
-		gem_context_set_param(i915, &set.param);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		set.param.ctx_id = create.ctx_id;
-		set.param.size = sizeof(engines);
-		set.param.value = to_user_pointer(&engines);
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.size, ex_size);
-		igt_assert(!memcmp(&engines, &expected, ex_size));
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		/* clone but then reset engines to default */
-		set.param.ctx_id = 0;
-		set.param.size = 0;
-		set.param.value = 0;
-		ext.base.next_extension = to_user_pointer(&set);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		ext.base.next_extension = 0;
-
-		set.param.ctx_id = create.ctx_id;
-		set.param.size = sizeof(engines);
-		set.param.value = to_user_pointer(&engines);
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.size, 0);
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		/* And check we ignore the flag */
-		ext.flags = 0;
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		ext.flags = I915_CONTEXT_CLONE_ENGINES;
-
-		set.param.ctx_id = create.ctx_id;
-		set.param.size = sizeof(engines);
-		set.param.value = to_user_pointer(&engines);
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.size, 0);
-
-		ext.clone_id = gem_context_create(i915);
-	}
-
-	gem_context_destroy(i915, ext.clone_id);
-}
-
-static void clone_scheduler(int i915)
-{
-	struct drm_i915_gem_context_create_ext_setparam set = {
-		{ .name = I915_CONTEXT_CREATE_EXT_SETPARAM },
-		{ .param = I915_CONTEXT_PARAM_PRIORITY },
-	};
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.flags = I915_CONTEXT_CLONE_SCHEDATTR,
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-	int expected;
-
-	igt_require(__gem_context_set_param(i915, &set.param) == 0);
-
-	for (int pass = 0; pass < 2; pass++) { /* cloning default, then child */
-		igt_debug("Cloning %d\n", ext.clone_id);
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		set.param.ctx_id = ext.clone_id;
-		gem_context_get_param(i915, &set.param);
-		expected = set.param.value;
-
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.param, I915_CONTEXT_PARAM_PRIORITY);
-		igt_assert_eq((int)set.param.value, expected);
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		expected = set.param.value = 1;
-		set.param.ctx_id = ext.clone_id;
-		gem_context_set_param(i915, &set.param);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-
-		igt_assert_eq_u64(set.param.param, I915_CONTEXT_PARAM_PRIORITY);
-		igt_assert_eq((int)set.param.value, expected);
-
-		gem_context_destroy(i915, create.ctx_id);
-
-		/* clone but then reset priority to default */
-		set.param.ctx_id = 0;
-		set.param.value = 0;
-		ext.base.next_extension = to_user_pointer(&set);
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		ext.base.next_extension = 0;
-
-		set.param.ctx_id = create.ctx_id;
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.value, 0);
-
-		set.param.ctx_id = ext.clone_id;
-		gem_context_get_param(i915, &set.param);
-		igt_assert_eq_u64(set.param.value, 1);
-
-		gem_context_destroy(i915, create.ctx_id);
-		ext.clone_id = gem_context_create(i915);
-	}
-
-	gem_context_destroy(i915, ext.clone_id);
-}
-
-static uint32_t __batch_create(int i915, uint32_t offset)
-{
-	const uint32_t bbe = MI_BATCH_BUFFER_END;
-	uint32_t handle;
-
-	handle = gem_create(i915, ALIGN(offset + 4, 4096));
-	gem_write(i915, handle, offset, &bbe, sizeof(bbe));
-
-	return handle;
-}
-
-static uint32_t batch_create(int i915)
-{
-	return __batch_create(i915, 0);
-}
-
-static void check_same_vm(int i915, uint32_t ctx_a, uint32_t ctx_b)
-{
-	struct drm_i915_gem_exec_object2 batch = {
-		.handle = batch_create(i915),
-	};
-	struct drm_i915_gem_execbuffer2 eb = {
-		.buffers_ptr = to_user_pointer(&batch),
-		.buffer_count = 1,
-	};
-
-	/* First verify that we try to use "softpinning" by default */
-	batch.offset = 48 << 20;
-	eb.rsvd1 = ctx_a;
-	gem_execbuf(i915, &eb);
-	igt_assert_eq_u64(batch.offset, 48 << 20);
-
-	/* An already active VMA will try to keep its offset */
-	batch.offset = 0;
-	eb.rsvd1 = ctx_b;
-	gem_execbuf(i915, &eb);
-	igt_assert_eq_u64(batch.offset, 48 << 20);
-
-	gem_sync(i915, batch.handle);
-	gem_close(i915, batch.handle);
-
-	gem_quiescent_gpu(i915); /* evict the vma */
-}
-
-static void clone_vm(int i915)
-{
-	struct drm_i915_gem_context_param set = {
-		.param = I915_CONTEXT_PARAM_VM,
-	};
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.flags = I915_CONTEXT_CLONE_VM,
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-	uint32_t vm_id[2];
-
-	igt_require(__gem_context_set_param(i915, &set) == -ENOENT);
-
-	/* Scrub the VM for our tests */
-	i915 = gem_reopen_driver(i915);
-
-	set.ctx_id = gem_context_create(i915);
-	gem_context_get_param(i915, &set);
-	vm_id[0] = set.value;
-	gem_context_destroy(i915, set.ctx_id);
-
-	vm_id[1] = gem_vm_create(i915);
-
-	for (int pass = 0; pass < 2; pass++) { /* cloning default, then child */
-		igt_debug("Cloning %d\n", ext.clone_id);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		check_same_vm(i915, ext.clone_id, create.ctx_id);
-		gem_context_destroy(i915, create.ctx_id);
-
-		set.value = vm_id[pass];
-		set.ctx_id = ext.clone_id;
-		gem_context_set_param(i915, &set);
-
-		igt_assert_eq(ctx_create_ioctl(i915, &create), 0);
-		check_same_vm(i915, ext.clone_id, create.ctx_id);
-		gem_context_destroy(i915, create.ctx_id);
-
-		ext.clone_id = gem_context_create(i915);
-	}
-
-	gem_context_destroy(i915, ext.clone_id);
-
-	for (int i = 0; i < ARRAY_SIZE(vm_id); i++)
-		gem_vm_destroy(i915, vm_id[i]);
-
-	close(i915);
-}
-
-igt_main
-{
-	int i915 = -1;
-
-	igt_fixture {
-		i915 = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(i915);
-		gem_require_contexts(i915);
-
-		igt_require(gem_has_context_clone(i915));
-		igt_fork_hang_detector(i915);
-	}
-
-	igt_subtest("invalid")
-		invalid_clone(i915);
-
-	igt_subtest("engines")
-		clone_engines(i915);
-
-	igt_subtest("flags")
-		clone_flags(i915);
-
-	igt_subtest("scheduler")
-		clone_scheduler(i915);
-
-	igt_subtest("vm")
-		clone_vm(i915);
-
-	igt_fixture {
-		igt_stop_hang_detector();
-		close(i915);
-	}
-}
diff --git a/tests/meson.build b/tests/meson.build
index 2c579d4c..f8f0beb2 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -126,7 +126,6 @@ i915_progs = [
 	'gem_concurrent_blit',
 	'gem_cs_tlb',
 	'gem_ctx_bad_destroy',
-	'gem_ctx_clone',
 	'gem_ctx_create',
 	'gem_ctx_engines',
 	'gem_ctx_exec',
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 06/74] lib/i915/gem_engine_topology: Expose the __query_engines helper

[Jason Ekstrand]

---
 lib/i915/gem_engine_topology.c | 20 +++++++++++---------
 lib/i915/gem_engine_topology.h |  4 ++++
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index c12cd920..5d196f59 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -62,14 +62,9 @@ static int __gem_query(int fd, struct drm_i915_query *q)
 	return err;
 }
 
-static void gem_query(int fd, struct drm_i915_query *q)
-{
-	igt_assert_eq(__gem_query(fd, q), 0);
-}
-
-static void query_engines(int fd,
-			  struct drm_i915_query_engine_info *query_engines,
-			  int length)
+int __gem_query_engines(int fd,
+			struct drm_i915_query_engine_info *query_engines,
+			int length)
 {
 	struct drm_i915_query_item item = { };
 	struct drm_i915_query query = { };
@@ -81,7 +76,14 @@ static void query_engines(int fd,
 
 	item.data_ptr = to_user_pointer(query_engines);
 
-	gem_query(fd, &query);
+	return __gem_query(fd, &query);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines,
+			  int length)
+{
+	igt_assert_eq(__gem_query_engines(fd, query_engines, length), 0);
 }
 
 static void ctx_map_engines(int fd, struct intel_engine_data *ed,
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index f5edcb5d..76b7cd4d 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -29,6 +29,10 @@
 
 #define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
 
+int __gem_query_engines(int fd,
+			struct drm_i915_query_engine_info *query_engines,
+			int length);
+
 struct intel_engine_data {
 	uint32_t nengines;
 	uint32_t n;
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 07/74] lib/i915/gem_context: Add gem_context_create_ext helpers

[Jason Ekstrand]

---
 lib/i915/gem_context.c | 57 ++++++++++++++++++++++++++++++++++++++++++
 lib/i915/gem_context.h |  3 +++
 2 files changed, 60 insertions(+)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 79411e10..49ed7120 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -107,6 +107,40 @@ int __gem_context_create(int fd, uint32_t *ctx_id)
        return err;
 }
 
+/**
+ * __gem_context_create_config:
+ * @fd: open i915 drm file descriptor
+ * @flags: context create flags
+ * @extensions: first extension struct, or 0 for no extensions
+ * @ctx_id: on success, the context ID is written here
+ *
+ * Creates a new GEM context with flags and extensions.  If no flags or
+ * extensions are required, it's the same as __gem_context_create and works
+ * on older kernels.
+ */
+int __gem_context_create_ext(int fd, uint32_t flags, uint64_t extensions,
+			     uint32_t *ctx_id)
+{
+	struct drm_i915_gem_context_create_ext ctx_create;
+	int err = 0;
+
+	if (!flags && !extensions)
+		return __gem_context_create(fd, ctx_id);
+
+	memset(&ctx_create, 0, sizeof(ctx_create));
+	ctx_create.flags = flags;
+	if (extensions) {
+		ctx_create.flags |= I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS;
+		ctx_create.extensions = extensions;
+	}
+
+	err = create_ext_ioctl(fd, &ctx_create);
+	if (!err)
+		*ctx_id = ctx_create.ctx_id;
+
+	return err;
+}
+
 /**
  * gem_context_create:
  * @fd: open i915 drm file descriptor
@@ -127,6 +161,29 @@ uint32_t gem_context_create(int fd)
 	return ctx_id;
 }
 
+/**
+ * __gem_context_create_config:
+ * @fd: open i915 drm file descriptor
+ * @flags: context create flags
+ * @extensions: first extension struct, or 0 for no extensions
+ * @ctx_id: on success, the context ID is written here
+ *
+ * Creates a new GEM context with flags and extensions.  If no flags or
+ * extensions are required, it's the same as gem_context_create and works
+ * on older kernels.
+ *
+ * Returns: The id of the allocated context.
+ */
+uint32_t gem_context_create_ext(int fd, uint32_t flags, uint64_t extensions)
+{
+	uint32_t ctx_id;
+
+	igt_assert_eq(__gem_context_create_ext(fd, flags, extensions, &ctx_id), 0);
+	igt_assert(ctx_id != 0);
+
+	return ctx_id;
+}
+
 int __gem_context_destroy(int fd, uint32_t ctx_id)
 {
 	struct drm_i915_gem_context_destroy destroy = { ctx_id };
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index c2c2b827..91bb9e7f 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -30,7 +30,10 @@
 struct drm_i915_gem_context_param;
 
 uint32_t gem_context_create(int fd);
+uint32_t gem_context_create_ext(int fd, uint32_t flags, uint64_t extensions);
 int __gem_context_create(int fd, uint32_t *ctx_id);
+int __gem_context_create_ext(int fd, uint32_t flags, uint64_t extensions,
+			     uint32_t *ctx_id);
 void gem_context_destroy(int fd, uint32_t ctx_id);
 int __gem_context_destroy(int fd, uint32_t ctx_id);
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 08/74] lib: Add an intel_ctx wrapper struct and helpers (v2)

[Jason Ekstrand]

We're trying to clean up some of our technical debt in the i915 API.  In
particular, context mutability and unnecessary getparam().  There's
quite a bit of the introspection stuff that's not used by any userspace
other than IGT.  Most drivers don't care about fetching the set of
engines, for instance, because they don't forget about what set of
engines they asked for int the first place.

Unfortunately, IGT relies heavily on context introspection for just
about everything when it comes to multi-engine testing.  It also likes
to use ctx0 as temporary storage for whatever the current test config
is.  While effective at keeping IGC simple in some ways, this means
we're making heavy use of context mutability.  Also, passing data around
with in tests isn't really what contexts are for.

This patch adds a new intel_ctx_t struct which wraps a context and
remembers the full context configuration.  This will provide similar
ease-of-use without having use ctx0 as temporary storage.

v2 (Jason Ekstrand):
 - Make all intel_ctx_t's const
---
 lib/intel_ctx.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/intel_ctx.h | 110 ++++++++++++++++++++++++++++++++
 lib/meson.build |   1 +
 3 files changed, 275 insertions(+)
 create mode 100644 lib/intel_ctx.c
 create mode 100644 lib/intel_ctx.h

diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
new file mode 100644
index 00000000..75c77fbd
--- /dev/null
+++ b/lib/intel_ctx.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <stddef.h>
+
+#include "intel_ctx.h"
+#include "ioctl_wrappers.h"
+#include "i915/gem_engine_topology.h"
+
+static void
+add_user_ext(uint64_t *root_ext_u64, struct i915_user_extension *ext)
+{
+	ext->next_extension = *root_ext_u64;
+	*root_ext_u64 = to_user_pointer(ext);
+}
+
+static size_t sizeof_param_engines(int count)
+{
+	return offsetof(struct i915_context_param_engines, engines[count]);
+}
+
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					 engines[GEM_MAX_ENGINES])
+
+intel_ctx_cfg_t intel_ctx_cfg_all_physical(int fd)
+{
+	uint8_t buff[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *qei = (void *) buff;
+	intel_ctx_cfg_t cfg = {};
+	int i;
+
+	if (__gem_query_engines(fd, qei, SIZEOF_QUERY) == 0) {
+		cfg.num_engines = qei->num_engines;
+		for (i = 0; i < qei->num_engines; i++)
+			cfg.engines[i] = qei->engines[i].engine;
+	}
+
+	return cfg;
+}
+
+static int
+__context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
+{
+	uint64_t ext_root = 0;
+	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
+	struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
+	uint32_t i;
+
+	if (cfg->vm) {
+		vm_param = (struct drm_i915_gem_context_create_ext_setparam) {
+			.base = {
+				.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			},
+			.param = {
+				.param = I915_CONTEXT_PARAM_VM,
+				.value = cfg->vm,
+			},
+		};
+		add_user_ext(&ext_root, &vm_param.base);
+	}
+
+	if (cfg->num_engines) {
+		memset(&engines, 0, sizeof(engines));
+		for (i = 0; i < cfg->num_engines; i++)
+			engines.engines[i] = cfg->engines[i];
+
+		engines_param = (struct drm_i915_gem_context_create_ext_setparam) {
+			.base = {
+				.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			},
+			.param = {
+				.param = I915_CONTEXT_PARAM_ENGINES,
+				.size = sizeof_param_engines(cfg->num_engines),
+				.value = to_user_pointer(&engines),
+			},
+		};
+		add_user_ext(&ext_root, &engines_param.base);
+	}
+
+	return __gem_context_create_ext(fd, cfg->flags, ext_root, ctx_id);
+}
+
+int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg,
+		       const intel_ctx_t **out_ctx)
+{
+	uint32_t ctx_id;
+	intel_ctx_t *ctx;
+	int err;
+
+	if (cfg)
+		err = __context_create_cfg(fd, cfg, &ctx_id);
+	else
+		err = __gem_context_create(fd, &ctx_id);
+	if (err)
+		return err;
+
+	ctx = calloc(1, sizeof(*ctx));
+	igt_assert(ctx);
+
+	ctx->id = ctx_id;
+	ctx->cfg = *cfg;
+
+	*out_ctx = ctx;
+	return 0;
+}
+
+const intel_ctx_t *intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg)
+{
+	const intel_ctx_t *ctx;
+	int err;
+
+	err = __intel_ctx_create(fd, cfg, &ctx);
+	igt_assert_eq(err, 0);
+
+	return ctx;
+}
+
+static const intel_ctx_t __intel_ctx_0 = {};
+
+const intel_ctx_t *intel_ctx_0(int fd)
+{
+	(void)fd;
+	return &__intel_ctx_0;
+}
+
+const intel_ctx_t *intel_ctx_create_all_physical(int fd)
+{
+	intel_ctx_cfg_t cfg;
+
+	if (!gem_has_contexts(fd))
+		return intel_ctx_0(fd);
+
+	cfg = intel_ctx_cfg_all_physical(fd);
+	return intel_ctx_create(fd, &cfg);
+}
+
+void intel_ctx_destroy(int fd, const intel_ctx_t *ctx)
+{
+	if (!ctx || ctx->id == 0)
+		return;
+
+	gem_context_destroy(fd, ctx->id);
+	free((void *)ctx);
+}
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
new file mode 100644
index 00000000..e61d6c91
--- /dev/null
+++ b/lib/intel_ctx.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef INTEL_CTX_H
+#define INTEL_CTX_H
+
+#include "igt_core.h"
+
+#include "i915_drm.h"
+
+#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
+
+/**
+ * intel_ctx_cfg_t:
+ * @flags: Context create flags
+ * @vm: VM to inherit or 0 for using a per-context VM
+ * @num_engines: Number of client-specified engines or 0 for legacy mode
+ * @engines: Client-specified engines
+ *
+ * Represents the full configuration of an intel_ctx.
+ */
+typedef struct intel_ctx_cfg {
+	uint32_t flags;
+	uint32_t vm;
+	unsigned int num_engines;
+	struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
+} intel_ctx_cfg_t;
+
+intel_ctx_cfg_t intel_ctx_cfg_all_physical(int fd);
+
+/**
+ * intel_ctx_t:
+ * @id: the context id/handle
+ * @cfg: the config used to create this context
+ *
+ * Represents the full configuration of an intel_ctx.
+ */
+typedef struct intel_ctx {
+	uint32_t id;
+	intel_ctx_cfg_t cfg;
+} intel_ctx_t;
+
+/**
+ * __intel_ctx_create:
+ * @fd: open i915 drm file descriptor
+ * @cfg: configuration for the created context
+ * @out_ctx: on success, the new intel_ctx_t pointer is written here
+ *
+ * Like intel_ctx_create but returns an error instead of asserting.
+ */
+int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg,
+		       const intel_ctx_t **out_ctx);
+
+/**
+ * intel_ctx_create:
+ * @fd: open i915 drm file descriptor
+ * @cfg: configuration for the created context
+ *
+ * Creates a new intel_ctx_t with the given config
+ */
+const intel_ctx_t *intel_ctx_create(int i915, const intel_ctx_cfg_t *cfg);
+
+/**
+ * intel_ctx_0:
+ * @fd: open i915 drm file descriptor
+ *
+ * Returns an intel_ctx_t representing the default context.
+ */
+const intel_ctx_t *intel_ctx_0(int fd);
+
+/**
+ * intel_ctx_create_all_physical:
+ * @fd: open i915 drm file descriptor
+ *
+ * Creates an intel_ctx_t containing all physical engines.  On kernels
+ * without the engines API, the created context will be the same as
+ * intel_ctx_0() except that it will be a new GEM context.
+ */
+const intel_ctx_t *intel_ctx_create_all_physical(int fd);
+
+/**
+ * intel_ctx_destroy:
+ * @fd: open i915 drm file descriptor
+ * @ctx: context to destroy, or NULL
+ *
+ * Destroys an intel_ctx_t.
+ */
+void intel_ctx_destroy(int fd, const intel_ctx_t *ctx);
+
+#endif
diff --git a/lib/meson.build b/lib/meson.build
index 9929520e..d66748ad 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -42,6 +42,7 @@ lib_sources = [
 	'intel_batchbuffer.c',
 	'intel_bufops.c',
 	'intel_chipset.c',
+	'intel_ctx.c',
 	'intel_device_info.c',
 	'intel_os.c',
 	'intel_mmio.c',
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 09/74] lib/i915/gem_engine_topology: Rework query_engine_list()

[Jason Ekstrand]

This gives us a no-assert version.
---
 lib/i915/gem_engine_topology.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 5d196f59..833b3abe 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -79,13 +79,6 @@ int __gem_query_engines(int fd,
 	return __gem_query(fd, &query);
 }
 
-static void query_engines(int fd,
-			  struct drm_i915_query_engine_info *query_engines,
-			  int length)
-{
-	igt_assert_eq(__gem_query_engines(fd, query_engines, length), 0);
-}
-
 static void ctx_map_engines(int fd, struct intel_engine_data *ed,
 			    struct drm_i915_gem_context_param *param)
 {
@@ -144,14 +137,16 @@ static void init_engine(struct intel_execution_engine2 *e2,
 	igt_assert(ret < sizeof(e2->name));
 }
 
-static void query_engine_list(int fd, struct intel_engine_data *ed)
+static int __query_engine_list(int fd, struct intel_engine_data *ed)
 {
 	uint8_t buff[SIZEOF_QUERY] = { };
 	struct drm_i915_query_engine_info *query_engine =
 			(struct drm_i915_query_engine_info *) buff;
-	int i;
+	int i, err;
 
-	query_engines(fd, query_engine, SIZEOF_QUERY);
+	err = __gem_query_engines(fd, query_engine, SIZEOF_QUERY);
+	if (err)
+		return err;
 
 	for (i = 0; i < query_engine->num_engines; i++)
 		init_engine(&ed->engines[i],
@@ -159,6 +154,13 @@ static void query_engine_list(int fd, struct intel_engine_data *ed)
 			    query_engine->engines[i].engine.engine_instance, i);
 
 	ed->nengines = query_engine->num_engines;
+
+	return 0;
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+	igt_assert_eq(__query_engine_list(fd, ed), 0);
 }
 
 struct intel_execution_engine2 *
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 10/74] lib/i915/gem_engine_topology: Factor out static engine listing

[Jason Ekstrand]

---
 lib/i915/gem_engine_topology.c | 51 +++++++++++++++++++---------------
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 833b3abe..606d3c1d 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -196,6 +196,34 @@ intel_get_current_physical_engine(struct intel_engine_data *ed)
 	return e;
 }
 
+static struct intel_engine_data intel_engine_list_for_static(int fd)
+{
+	const struct intel_execution_engine2 *e2;
+	struct intel_engine_data engine_data = { };
+
+	igt_debug("using pre-allocated engine list\n");
+
+	__for_each_static_engine(e2) {
+		if (igt_only_list_subtests() ||
+		    (fd < 0) ||
+		    gem_has_ring(fd, e2->flags)) {
+			struct intel_execution_engine2 *__e2 =
+				&engine_data.engines[
+				engine_data.nengines];
+
+			strcpy(__e2->name, e2->name);
+			__e2->instance   = e2->instance;
+			__e2->class      = e2->class;
+			__e2->flags      = e2->flags;
+			__e2->is_virtual = false;
+
+			engine_data.nengines++;
+                }
+	}
+
+	return engine_data;
+}
+
 static int gem_topology_get_param(int fd,
 				  struct drm_i915_gem_context_param *p)
 {
@@ -216,28 +244,7 @@ struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
 
 	if (gem_topology_get_param(fd, &param)) {
 		/* if kernel does not support engine/context mapping */
-		const struct intel_execution_engine2 *e2;
-
-		igt_debug("using pre-allocated engine list\n");
-
-		__for_each_static_engine(e2) {
-			if (igt_only_list_subtests() ||
-			    (fd < 0) ||
-			    gem_has_ring(fd, e2->flags)) {
-				struct intel_execution_engine2 *__e2 =
-					&engine_data.engines[
-					engine_data.nengines];
-
-				strcpy(__e2->name, e2->name);
-				__e2->instance   = e2->instance;
-				__e2->class      = e2->class;
-				__e2->flags      = e2->flags;
-				__e2->is_virtual = false;
-
-				engine_data.nengines++;
-                        }
-		}
-		return engine_data;
+		return intel_engine_list_for_static(fd);
 	}
 
 	if (!param.size) {
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 11/74] lib/i915/gem_engine_topology: Add an iterator which doesn't munge contexts

[Jason Ekstrand]

the current for_each_physical_engine iterators smash the set of engines
on the context (or ctx0 for the __ version).  This new one just gets the
list of engines from i915 and iterates over them.
---
 lib/i915/gem_engine_topology.c | 10 ++++++++++
 lib/i915/gem_engine_topology.h |  6 ++++++
 2 files changed, 16 insertions(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 606d3c1d..4319895f 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -224,6 +224,16 @@ static struct intel_engine_data intel_engine_list_for_static(int fd)
 	return engine_data;
 }
 
+struct intel_engine_data intel_engine_list_of_physical(int fd)
+{
+	struct intel_engine_data engine_data = { };
+
+	if (__query_engine_list(fd, &engine_data) == 0)
+		return engine_data;
+
+	return intel_engine_list_for_static(fd);
+}
+
 static int gem_topology_get_param(int fd,
 				  struct drm_i915_gem_context_param *p)
 {
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 76b7cd4d..69565240 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -41,6 +41,7 @@ struct intel_engine_data {
 };
 
 bool gem_has_engine_topology(int fd);
+struct intel_engine_data intel_engine_list_of_physical(int fd);
 struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
 
 /* iteration functions */
@@ -70,6 +71,11 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
 	     ((e__) = intel_get_current_engine(&i__)); \
 	     intel_next_engine(&i__))
 
+#define for_each_physical_engine(fd__, e__) \
+	for (struct intel_engine_data i__##e__ = intel_engine_list_of_physical(fd__); \
+	     ((e__) = intel_get_current_physical_engine(&i__##e__)); \
+	     intel_next_engine(&i__##e__))
+
 /* needs to replace "for_each_physical_engine" when conflicts are fixed */
 #define ____for_each_physical_engine(fd__, ctx__, e__) \
 	for (struct intel_engine_data i__##e__ = intel_init_engine_list(fd__, ctx__); \
-- 
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[igt-dev] [PATCH i-g-t 12/74] lib/i915/gem_engine_topology: Add an iterator for intel_ctx_t

[Jason Ekstrand]

---
 lib/i915/gem_engine_topology.c | 21 +++++++++++++++++++++
 lib/i915/gem_engine_topology.h | 14 ++++++++++++--
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index 4319895f..ec891dab 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -234,6 +234,27 @@ struct intel_engine_data intel_engine_list_of_physical(int fd)
 	return intel_engine_list_for_static(fd);
 }
 
+struct intel_engine_data
+intel_engine_list_for_ctx_cfg(int fd, const intel_ctx_cfg_t *cfg)
+{
+	if (fd >= 0 && cfg->num_engines) {
+		struct intel_engine_data engine_data = { };
+		int i;
+
+		engine_data.nengines = cfg->num_engines;
+		for (i = 0; i < cfg->num_engines; i++)
+			init_engine(&engine_data.engines[i],
+				    cfg->engines[i].engine_class,
+				    cfg->engines[i].engine_instance,
+				    i);
+
+		return engine_data;
+	} else {
+		/* This is a legacy context */
+		return intel_engine_list_for_static(fd);
+	}
+}
+
 static int gem_topology_get_param(int fd,
 				  struct drm_i915_gem_context_param *p)
 {
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index 69565240..b2e15c1e 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -26,8 +26,7 @@
 
 #include "igt_gt.h"
 #include "i915_drm.h"
-
-#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
+#include "intel_ctx.h"
 
 int __gem_query_engines(int fd,
 			struct drm_i915_query_engine_info *query_engines,
@@ -42,6 +41,8 @@ struct intel_engine_data {
 
 bool gem_has_engine_topology(int fd);
 struct intel_engine_data intel_engine_list_of_physical(int fd);
+struct intel_engine_data
+intel_engine_list_for_ctx_cfg(int fd, const intel_ctx_cfg_t *cfg);
 struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
 
 /* iteration functions */
@@ -66,6 +67,15 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
 #define __for_each_static_engine(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name[0]; (e__)++)
 
+#define for_each_ctx_cfg_engine(fd__, ctx_cfg__, e__) \
+	for (struct intel_engine_data i__##e__ = \
+			intel_engine_list_for_ctx_cfg(fd__, ctx_cfg__); \
+	     ((e__) = intel_get_current_engine(&i__##e__)); \
+	     intel_next_engine(&i__##e__))
+
+#define for_each_ctx_engine(fd__, ctx__, e__) \
+	for_each_ctx_cfg_engine(fd__, &(ctx__)->cfg, e__)
+
 #define for_each_context_engine(fd__, ctx__, e__) \
 	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
 	     ((e__) = intel_get_current_engine(&i__)); \
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 13/74] tests/i915/gem_exec_basic: Convert to intel_ctx_t

[Jason Ekstrand]

This acts as a template for the rest of this patch series.  The rough
idea is that we create a new context if the HW supports contexts and
otherwise we use intel_ctx_0().  Once we have an intel_ctx_t, we can
iterate over all of the engines in it in a consistent way.
---
 tests/i915/gem_exec_basic.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 31f6a234..e21f9ff1 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -41,10 +41,13 @@ static uint32_t batch_create(int fd)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
+		ctx = intel_ctx_create_all_physical(fd);
+
 		/* igt_require_gem(fd); // test is mandatory */
 		igt_fork_hang_detector(fd);
 	}
@@ -54,12 +57,13 @@ igt_main
 			.handle = batch_create(fd),
 		};
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name) {
 				struct drm_i915_gem_execbuffer2 execbuf = {
 					.buffers_ptr = to_user_pointer(&exec),
 					.buffer_count = 1,
 					.flags = e->flags,
+					.rsvd1 = ctx->id,
 				};
 
 				gem_execbuf(fd, &execbuf);
@@ -72,6 +76,7 @@ igt_main
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 14/74] lib/igt_spin: Rename igt_spin_factory::ctx to ctx_id

[Jason Ekstrand]

---
 lib/igt_dummyload.c            |  6 +++---
 lib/igt_dummyload.h            |  2 +-
 lib/igt_gt.c                   |  2 +-
 tests/i915/gem_ctx_engines.c   |  6 +++---
 tests/i915/gem_ctx_exec.c      |  2 +-
 tests/i915/gem_ctx_isolation.c | 18 +++++++++---------
 tests/i915/gem_ctx_shared.c    | 16 ++++++++--------
 tests/i915/gem_eio.c           |  2 +-
 tests/i915/gem_exec_balancer.c | 26 +++++++++++++-------------
 tests/i915/gem_exec_latency.c  |  2 +-
 tests/i915/gem_exec_nop.c      |  2 +-
 tests/i915/gem_exec_schedule.c | 26 +++++++++++++-------------
 tests/i915/gem_spin_batch.c    |  2 +-
 tests/i915/gem_sync.c          |  2 +-
 tests/i915/gem_vm_create.c     |  4 ++--
 tests/i915/gem_watchdog.c      |  2 +-
 tests/i915/gem_workarounds.c   |  2 +-
 tests/i915/perf_pmu.c          |  4 ++--
 18 files changed, 63 insertions(+), 63 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 34ad9221..5a11ec4e 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -127,7 +127,7 @@ emit_recursive_batch(igt_spin_t *spin,
 	if (opts->engine == ALL_ENGINES) {
 		struct intel_execution_engine2 *engine;
 
-		for_each_context_engine(fd, opts->ctx, engine) {
+		for_each_context_engine(fd, opts->ctx_id, engine) {
 			if (opts->flags & IGT_SPIN_POLL_RUN &&
 			    !gem_class_can_store_dword(fd, engine->class))
 				continue;
@@ -325,7 +325,7 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	execbuf->buffers_ptr =
 	       	to_user_pointer(obj + (2 - execbuf->buffer_count));
-	execbuf->rsvd1 = opts->ctx;
+	execbuf->rsvd1 = opts->ctx_id;
 
 	if (opts->flags & IGT_SPIN_FENCE_OUT)
 		execbuf->flags |= I915_EXEC_FENCE_OUT;
@@ -423,7 +423,7 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 		int class;
 
 		if (!gem_context_lookup_engine(fd, opts->engine,
-					       opts->ctx, &e)) {
+					       opts->ctx_id, &e)) {
 			class = e.class;
 		} else {
 			gem_require_ring(fd, opts->engine);
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index a75fcdeb..aee72da8 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -60,7 +60,7 @@ typedef struct igt_spin {
 } igt_spin_t;
 
 struct igt_spin_factory {
-	uint32_t ctx;
+	uint32_t ctx_id;
 	uint32_t dependency;
 	unsigned int engine;
 	unsigned int flags;
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index f601d726..4981ef26 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -298,7 +298,7 @@ igt_hang_t igt_hang_ctx(int fd, uint32_t ctx, int ring, unsigned flags)
 		context_set_ban(fd, ctx, 0);
 
 	spin = __igt_spin_new(fd,
-			      .ctx = ctx,
+			      .ctx_id = ctx,
 			      .engine = ring,
 			      .flags = IGT_SPIN_NO_PREEMPTION);
 
diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index 643a0b2f..058b2cc2 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -336,7 +336,7 @@ static void execute_one(int i915)
 	igt_spin_t *spin;
 
 	/* Prewarm the spinner */
-	spin = igt_spin_new(i915, .ctx = param.ctx_id,
+	spin = igt_spin_new(i915, .ctx_id = param.ctx_id,
 			    .flags = (IGT_SPIN_NO_PREEMPTION |
 				      IGT_SPIN_POLL_RUN));
 
@@ -439,7 +439,7 @@ static void execute_oneforall(int i915)
 			igt_spin_t *spin;
 
 			spin = __igt_spin_new(i915,
-					      .ctx = param.ctx_id,
+					      .ctx_id = param.ctx_id,
 					      .engine = i);
 
 			busy.handle = spin->handle;
@@ -480,7 +480,7 @@ static void execute_allforone(int i915)
 		igt_spin_t *spin;
 
 		spin = __igt_spin_new(i915,
-				      .ctx = param.ctx_id,
+				      .ctx_id = param.ctx_id,
 				      .engine = i++);
 
 		busy.handle = spin->handle;
diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index 89776185..03c66bf7 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -184,7 +184,7 @@ static void norecovery(int i915)
 		igt_assert_eq(param.value, pass);
 
 		spin = __igt_spin_new(i915,
-				      .ctx = param.ctx_id,
+				      .ctx_id = param.ctx_id,
 				      .flags = IGT_SPIN_POLL_RUN);
 		igt_spin_busywait_until_started(spin);
 
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 4f174268..a57a6637 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -629,7 +629,7 @@ static void nonpriv(int fd,
 
 		tmpl_regs(fd, ctx, e, tmpl, values[v]);
 
-		spin = igt_spin_new(fd, .ctx = ctx, .engine = e->flags);
+		spin = igt_spin_new(fd, .ctx_id = ctx, .engine = e->flags);
 
 		igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
 			  __func__, v, values[v]);
@@ -641,12 +641,12 @@ static void nonpriv(int fd,
 
 			/* Explicit sync to keep the switch between write/read */
 			syncpt = igt_spin_new(fd,
-					      .ctx = ctx,
+					      .ctx_id = ctx,
 					      .engine = e->flags,
 					      .flags = IGT_SPIN_FENCE_OUT);
 
 			dirt = igt_spin_new(fd,
-					    .ctx = sw,
+					    .ctx_id = sw,
 					    .engine = e->flags,
 					    .fence = syncpt->out_fence,
 					    .flags = (IGT_SPIN_FENCE_IN |
@@ -654,7 +654,7 @@ static void nonpriv(int fd,
 			igt_spin_free(fd, syncpt);
 
 			syncpt = igt_spin_new(fd,
-					      .ctx = ctx,
+					      .ctx_id = ctx,
 					      .engine = e->flags,
 					      .fence = dirt->out_fence,
 					      .flags = IGT_SPIN_FENCE_IN);
@@ -708,7 +708,7 @@ static void isolation(int fd,
 		ctx[0] = gem_context_clone_with_engines(fd, 0);
 		regs[0] = read_regs(fd, ctx[0], e, flags);
 
-		spin = igt_spin_new(fd, .ctx = ctx[0], .engine = e->flags);
+		spin = igt_spin_new(fd, .ctx_id = ctx[0], .engine = e->flags);
 
 		if (flags & DIRTY1) {
 			igt_debug("%s[%d]: Setting all registers of ctx 0 to 0x%08x\n",
@@ -776,7 +776,7 @@ static uint32_t create_reset_context(int i915)
 static void inject_reset_context(int fd, const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
-		.ctx = create_reset_context(fd),
+		.ctx_id = create_reset_context(fd),
 		.engine = e->flags,
 		.flags = IGT_SPIN_FAST,
 	};
@@ -801,7 +801,7 @@ static void inject_reset_context(int fd, const struct intel_execution_engine2 *e
 	igt_force_gpu_reset(fd);
 
 	igt_spin_free(fd, spin);
-	gem_context_destroy(fd, opts.ctx);
+	gem_context_destroy(fd, opts.ctx_id);
 }
 
 static void preservation(int fd,
@@ -825,7 +825,7 @@ static void preservation(int fd,
 	gem_quiescent_gpu(fd);
 
 	ctx[num_values] = gem_context_clone_with_engines(fd, 0);
-	spin = igt_spin_new(fd, .ctx = ctx[num_values], .engine = e->flags);
+	spin = igt_spin_new(fd, .ctx_id = ctx[num_values], .engine = e->flags);
 	regs[num_values][0] = read_regs(fd, ctx[num_values], e, flags);
 	for (int v = 0; v < num_values; v++) {
 		ctx[v] = gem_context_clone_with_engines(fd, 0);
@@ -865,7 +865,7 @@ static void preservation(int fd,
 		break;
 	}
 
-	spin = igt_spin_new(fd, .ctx = ctx[num_values], .engine = e->flags);
+	spin = igt_spin_new(fd, .ctx_id = ctx[num_values], .engine = e->flags);
 	for (int v = 0; v < num_values; v++)
 		regs[v][1] = read_regs(fd, ctx[v], e, flags);
 	regs[num_values][1] = read_regs(fd, ctx[num_values], e, flags);
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index 6b21994d..e3e8a9be 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -124,8 +124,8 @@ static void disjoint_timelines(int i915)
 	child = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0);
 	plug = igt_cork_plug(&cork, i915);
 
-	spin[0] = __igt_spin_new(i915, .ctx = 0, .dependency = plug);
-	spin[1] = __igt_spin_new(i915, .ctx = child);
+	spin[0] = __igt_spin_new(i915, .ctx_id = 0, .dependency = plug);
+	spin[1] = __igt_spin_new(i915, .ctx_id = child);
 
 	/* Wait for the second spinner, will hang if stuck behind the first */
 	igt_spin_end(spin[1]);
@@ -388,7 +388,7 @@ static void exec_single_timeline(int i915, unsigned int engine)
 			continue;
 
 		if (spin == NULL) {
-			spin = __igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
+			spin = __igt_spin_new(i915, .ctx_id = ctx, .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 execbuf = {
 				.buffers_ptr = spin->execbuf.buffers_ptr,
@@ -416,7 +416,7 @@ static void exec_single_timeline(int i915, unsigned int engine)
 			continue;
 
 		if (spin == NULL) {
-			spin = __igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
+			spin = __igt_spin_new(i915, .ctx_id = ctx, .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 execbuf = {
 				.buffers_ptr = spin->execbuf.buffers_ptr,
@@ -510,11 +510,11 @@ static void unplug_show_queue(int i915, struct igt_cork *c, unsigned int engine)
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
 		const struct igt_spin_factory opts = {
-			.ctx = create_highest_priority(i915),
+			.ctx_id = create_highest_priority(i915),
 			.engine = engine,
 		};
 		spin[n] = __igt_spin_factory(i915, &opts);
-		gem_context_destroy(i915, opts.ctx);
+		gem_context_destroy(i915, opts.ctx_id);
 	}
 
 	igt_cork_unplug(c); /* batches will now be queued on the engine */
@@ -592,11 +592,11 @@ static void independent(int i915,
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
 		const struct igt_spin_factory opts = {
-			.ctx = create_highest_priority(i915),
+			.ctx_id = create_highest_priority(i915),
 			.engine = e->flags,
 		};
 		spin[n] = __igt_spin_factory(i915, &opts);
-		gem_context_destroy(i915, opts.ctx);
+		gem_context_destroy(i915, opts.ctx_id);
 	}
 
 	fence = igt_cork_plug(&cork, i915);
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index d86ccf2b..0036c4aa 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -176,7 +176,7 @@ static int __gem_wait(int fd, uint32_t handle, int64_t timeout)
 static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
 {
 	struct igt_spin_factory opts = {
-		.ctx = ctx,
+		.ctx_id = ctx,
 		.engine = flags,
 		.flags = IGT_SPIN_NO_PREEMPTION | IGT_SPIN_FENCE_OUT,
 	};
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index bfd65b29..c1b64578 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -530,7 +530,7 @@ static void check_individual_engine(int i915,
 			     I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
 						  ci[idx].engine_instance));
 
-	spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
+	spin = igt_spin_new(i915, .ctx_id = ctx, .engine = idx + 1);
 	load = measure_load(pmu, 10000);
 	igt_spin_free(i915, spin);
 
@@ -659,13 +659,13 @@ static void bonded(int i915, unsigned int flags)
 			plug = NULL;
 			if (flags & CORK) {
 				plug = __igt_spin_new(i915,
-						      .ctx = master,
+						      .ctx_id = master,
 						      .engine = bond,
 						      .dependency = igt_cork_plug(&cork, i915));
 			}
 
 			spin = __igt_spin_new(i915,
-					      .ctx = master,
+					      .ctx_id = master,
 					      .engine = bond,
 					      .flags = IGT_SPIN_FENCE_OUT);
 
@@ -806,7 +806,7 @@ static void bonded_slice(int i915)
 		set_load_balancer(i915, ctx, siblings, count, NULL);
 
 		spin = __igt_spin_new(i915,
-				      .ctx = ctx,
+				      .ctx_id = ctx,
 				      .flags = (IGT_SPIN_NO_PREEMPTION |
 						IGT_SPIN_POLL_RUN));
 		igt_spin_end(spin); /* we just want its address for later */
@@ -831,7 +831,7 @@ static void bonded_slice(int i915)
 
 			while (!READ_ONCE(*stop)) {
 				spin = igt_spin_new(i915,
-						    .ctx = ctx,
+						    .ctx_id = ctx,
 						    .engine = (1 + rand() % count),
 						    .flags = IGT_SPIN_POLL_RUN);
 				igt_spin_busywait_until_started(spin);
@@ -892,7 +892,7 @@ static void __bonded_chain(int i915, uint32_t ctx,
 		if (priorities[i] < 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
 		spin = igt_spin_new(i915,
-				    .ctx = ctx,
+				    .ctx_id = ctx,
 				    .engine = 1,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_FENCE_OUT));
@@ -971,7 +971,7 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 		if (priorities[i] < 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
 		spin = igt_spin_new(i915,
-				    .ctx = ctx,
+				    .ctx_id = ctx,
 				    .engine = 1,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_FENCE_OUT));
@@ -1838,7 +1838,7 @@ static void __bonded_early(int i915, uint32_t ctx,
 
 	/* A: spin forever on engine 1 */
 	spin = igt_spin_new(i915,
-			    .ctx = ctx,
+			    .ctx_id = ctx,
 			    .engine = (flags & VIRTUAL_ENGINE) ? 0 : 1,
 			    .flags = IGT_SPIN_NO_PREEMPTION);
 
@@ -1953,10 +1953,10 @@ static void busy(int i915)
 		free(ci);
 
 		spin[0] = __igt_spin_new(i915,
-					 .ctx = ctx,
+					 .ctx_id = ctx,
 					 .flags = IGT_SPIN_POLL_RUN);
 		spin[1] = __igt_spin_new(i915,
-					 .ctx = ctx,
+					 .ctx_id = ctx,
 					 .dependency = scratch);
 
 		igt_spin_busywait_until_started(spin[0]);
@@ -2055,7 +2055,7 @@ static void full(int i915, unsigned int flags)
 			ctx = load_balancer_create(i915, ci, count);
 
 			if (spin == NULL) {
-				spin = __igt_spin_new(i915, .ctx = ctx);
+				spin = __igt_spin_new(i915, .ctx_id = ctx);
 			} else {
 				struct drm_i915_gem_execbuffer2 eb = {
 					.buffers_ptr = spin->execbuf.buffers_ptr,
@@ -2602,7 +2602,7 @@ static void semaphore(int i915)
 		for (int i = 0; i < count; i++) {
 			set_load_balancer(i915, block[i], ci, count, NULL);
 			spin[i] = __igt_spin_new(i915,
-						 .ctx = block[i],
+						 .ctx_id = block[i],
 						 .dependency = scratch);
 		}
 
@@ -2919,7 +2919,7 @@ static void __fairslice(int i915,
 	for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
 		ctx[i] = load_balancer_create(i915, ci, count);
 		if (spin == NULL) {
-			spin = __igt_spin_new(i915, .ctx = ctx[i]);
+			spin = __igt_spin_new(i915, .ctx_id = ctx[i]);
 		} else {
 			struct drm_i915_gem_execbuffer2 eb = {
 				.buffer_count = 1,
diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
index 8ba924b8..e6466965 100644
--- a/tests/i915/gem_exec_latency.c
+++ b/tests/i915/gem_exec_latency.c
@@ -318,7 +318,7 @@ static void latency_from_ring(int fd,
 
 		if (flags & PREEMPT)
 			spin = __igt_spin_new(fd,
-					      .ctx = ctx[0],
+					      .ctx_id = ctx[0],
 					      .engine = e->flags);
 
 		if (flags & CORK) {
diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c
index 62554ecb..f24ff88f 100644
--- a/tests/i915/gem_exec_nop.c
+++ b/tests/i915/gem_exec_nop.c
@@ -917,7 +917,7 @@ static void preempt(int fd, uint32_t handle,
 	intel_detect_and_clear_missed_interrupts(fd);
 
 	count = 0;
-	spin = __igt_spin_new(fd, .ctx = ctx[0], .engine = e->flags);
+	spin = __igt_spin_new(fd, .ctx_id = ctx[0], .engine = e->flags);
 	clock_gettime(CLOCK_MONOTONIC, &start);
 	do {
 		gem_execbuf(fd, &execbuf);
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 9585059d..f84967c7 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -205,11 +205,11 @@ static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
 
 	for (int n = 0; n < max; n++) {
 		const struct igt_spin_factory opts = {
-			.ctx = create_highest_priority(fd),
+			.ctx_id = create_highest_priority(fd),
 			.engine = engine,
 		};
 		spin[n] = __igt_spin_factory(fd, &opts);
-		gem_context_destroy(fd, opts.ctx);
+		gem_context_destroy(fd, opts.ctx_id);
 	}
 
 	igt_cork_unplug(c); /* batches will now be queued on the engine */
@@ -639,7 +639,7 @@ static void lateslice(int i915, unsigned int engine, unsigned long flags)
 	igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
 	ctx = gem_context_create(i915);
-	spin[0] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
+	spin[0] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
 			       .flags = (IGT_SPIN_POLL_RUN |
 					 IGT_SPIN_FENCE_OUT |
 					 flags));
@@ -648,7 +648,7 @@ static void lateslice(int i915, unsigned int engine, unsigned long flags)
 	igt_spin_busywait_until_started(spin[0]);
 
 	ctx = gem_context_create(i915);
-	spin[1] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
+	spin[1] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
 			       .fence = spin[0]->out_fence,
 			       .flags = (IGT_SPIN_POLL_RUN |
 					 IGT_SPIN_FENCE_IN |
@@ -665,7 +665,7 @@ static void lateslice(int i915, unsigned int engine, unsigned long flags)
 	 */
 
 	ctx = gem_context_create(i915);
-	spin[2] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
+	spin[2] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
 			       .flags = IGT_SPIN_POLL_RUN | flags);
 	gem_context_destroy(i915, ctx);
 
@@ -765,7 +765,7 @@ static void submit_slice(int i915,
 		engines.engines[0].engine_class = e->class;
 		engines.engines[0].engine_instance = e->instance;
 		gem_context_set_param(i915, &param);
-		spin = igt_spin_new(i915, .ctx = param.ctx_id,
+		spin = igt_spin_new(i915, .ctx_id = param.ctx_id,
 				    .fence = fence,
 				    .flags =
 				    IGT_SPIN_POLL_RUN |
@@ -909,7 +909,7 @@ static void semaphore_codependency(int i915, unsigned long flags)
 
 		task[i].xcs =
 			__igt_spin_new(i915,
-				       .ctx = ctx,
+				       .ctx_id = ctx,
 				       .engine = e->flags,
 				       .flags = IGT_SPIN_POLL_RUN | flags);
 		igt_spin_busywait_until_started(task[i].xcs);
@@ -917,7 +917,7 @@ static void semaphore_codependency(int i915, unsigned long flags)
 		/* Common rcs tasks will be queued in FIFO */
 		task[i].rcs =
 			__igt_spin_new(i915,
-				       .ctx = ctx,
+				       .ctx_id = ctx,
 				       .engine = 0,
 				       .dependency = task[i].xcs->handle);
 
@@ -1403,7 +1403,7 @@ static void preempt(int fd, const struct intel_execution_engine2 *e, unsigned fl
 			gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
 		}
 		spin[n] = __igt_spin_new(fd,
-					 .ctx = ctx[LO],
+					 .ctx_id = ctx[LO],
 					 .engine = e->flags,
 					 .flags = flags & USERPTR ? IGT_SPIN_USERPTR : 0);
 		igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle);
@@ -1439,7 +1439,7 @@ static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
 	__for_each_physical_engine(fd, e) {
 		if (spin == NULL) {
 			spin = __igt_spin_new(fd,
-					      .ctx = ctx,
+					      .ctx_id = ctx,
 					      .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 eb = {
@@ -1718,7 +1718,7 @@ static void preempt_self(int fd, unsigned ring)
 	gem_context_set_priority(fd, ctx[HI], MIN_PRIO);
 	__for_each_physical_engine(fd, e) {
 		spin[n] = __igt_spin_new(fd,
-					 .ctx = ctx[NOISE],
+					 .ctx_id = ctx[NOISE],
 					 .engine = e->flags);
 		store_dword(fd, ctx[HI], e->flags,
 			    result, (n + 1)*sizeof(uint32_t), n + 1,
@@ -1766,7 +1766,7 @@ static void preemptive_hang(int fd, const struct intel_execution_engine2 *e)
 		gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
 
 		spin[n] = __igt_spin_new(fd,
-					 .ctx = ctx[LO],
+					 .ctx_id = ctx[LO],
 					 .engine = e->flags);
 
 		gem_context_destroy(fd, ctx[LO]);
@@ -2751,7 +2751,7 @@ static void fairslice(int i915,
 		ctx[i] = gem_context_clone_with_engines(i915, 0);
 		if (spin == NULL) {
 			spin = __igt_spin_new(i915,
-					      .ctx = ctx[i],
+					      .ctx_id = ctx[i],
 					      .engine = e->flags,
 					      .flags = flags);
 		} else {
diff --git a/tests/i915/gem_spin_batch.c b/tests/i915/gem_spin_batch.c
index 2ed601a6..db0af018 100644
--- a/tests/i915/gem_spin_batch.c
+++ b/tests/i915/gem_spin_batch.c
@@ -145,7 +145,7 @@ static void spin_all(int i915, unsigned int flags)
 
 		/* Prevent preemption so only one is allowed on each engine */
 		spin = igt_spin_new(i915,
-				    .ctx = ctx,
+				    .ctx_id = ctx,
 				    .engine = e->flags,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_NO_PREEMPTION));
diff --git a/tests/i915/gem_sync.c b/tests/i915/gem_sync.c
index 6ad31517..58781a5e 100644
--- a/tests/i915/gem_sync.c
+++ b/tests/i915/gem_sync.c
@@ -1109,7 +1109,7 @@ preempt(int fd, unsigned ring, int num_children, int timeout)
 		do {
 			igt_spin_t *spin =
 				__igt_spin_new(fd,
-					       .ctx = ctx[0],
+					       .ctx_id = ctx[0],
 					       .engine = execbuf.flags);
 
 			do {
diff --git a/tests/i915/gem_vm_create.c b/tests/i915/gem_vm_create.c
index 6d93c98a..954ba13e 100644
--- a/tests/i915/gem_vm_create.c
+++ b/tests/i915/gem_vm_create.c
@@ -363,7 +363,7 @@ static void async_destroy(int i915)
 	int err;
 
 	spin[0] = igt_spin_new(i915,
-			       .ctx = arg.ctx_id,
+			       .ctx_id = arg.ctx_id,
 			       .flags = IGT_SPIN_POLL_RUN);
 	igt_spin_busywait_until_started(spin[0]);
 
@@ -372,7 +372,7 @@ static void async_destroy(int i915)
 		err = 0;
 	igt_assert_eq(err, 0);
 
-	spin[1] = __igt_spin_new(i915, .ctx = arg.ctx_id);
+	spin[1] = __igt_spin_new(i915, .ctx_id = arg.ctx_id);
 
 	igt_spin_end(spin[0]);
 	gem_sync(i915, spin[0]->handle);
diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
index 8f9fb177..22acf15c 100644
--- a/tests/i915/gem_watchdog.c
+++ b/tests/i915/gem_watchdog.c
@@ -305,7 +305,7 @@ static void virtual(int i915)
 			set_load_balancer(i915, ctx[i], ci, count, NULL);
 
 			spin[i] = igt_spin_new(i915,
-					       .ctx = ctx[i],
+					       .ctx_id = ctx[i],
 					       .flags = spin_flags());
 			i++;
 		}
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 00b475c2..0daf0cd6 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -135,7 +135,7 @@ static int workaround_fail_count(int i915, uint32_t ctx)
 
 	gem_set_domain(i915, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
 
-	spin = igt_spin_new(i915, .ctx = ctx, .flags = IGT_SPIN_POLL_RUN);
+	spin = igt_spin_new(i915, .ctx_id = ctx, .flags = IGT_SPIN_POLL_RUN);
 	igt_spin_busywait_until_started(spin);
 
 	fw = igt_open_forcewake_handle(i915);
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 50b5c82b..c7ddac85 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -175,7 +175,7 @@ static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
 				const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
-		.ctx = ctx,
+		.ctx_id = ctx,
 		.engine = e->flags,
 	};
 
@@ -381,7 +381,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	spin[0] = __spin_sync(gem_fd, 0, e);
 	usleep(500e3);
 	spin[1] = __igt_spin_new(gem_fd,
-				 .ctx = ctx,
+				 .ctx_id = ctx,
 				 .engine = e->flags);
 
 	/*
-- 
2.31.1

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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 15/74] lib/igt_spin: Support intel_ctx_t

[Jason Ekstrand]

---
 lib/igt_dummyload.c | 30 ++++++++++++++++++++++--------
 lib/igt_dummyload.h |  4 ++++
 2 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 5a11ec4e..ac83b331 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -123,16 +123,28 @@ emit_recursive_batch(igt_spin_t *spin,
 	addr += random() % addr / 2;
 	addr &= -4096;
 
+	assert(!(opts->ctx && opts->ctx_id));
+
 	nengine = 0;
 	if (opts->engine == ALL_ENGINES) {
 		struct intel_execution_engine2 *engine;
 
-		for_each_context_engine(fd, opts->ctx_id, engine) {
-			if (opts->flags & IGT_SPIN_POLL_RUN &&
-			    !gem_class_can_store_dword(fd, engine->class))
-				continue;
+		if (opts->ctx) {
+			for_each_ctx_engine(fd, opts->ctx, engine) {
+				if (opts->flags & IGT_SPIN_POLL_RUN &&
+				    !gem_class_can_store_dword(fd, engine->class))
+					continue;
 
-			flags[nengine++] = engine->flags;
+				flags[nengine++] = engine->flags;
+			}
+		} else {
+			for_each_context_engine(fd, opts->ctx_id, engine) {
+				if (opts->flags & IGT_SPIN_POLL_RUN &&
+				    !gem_class_can_store_dword(fd, engine->class))
+					continue;
+
+				flags[nengine++] = engine->flags;
+			}
 		}
 	} else {
 		flags[nengine++] = opts->engine;
@@ -325,7 +337,7 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	execbuf->buffers_ptr =
 	       	to_user_pointer(obj + (2 - execbuf->buffer_count));
-	execbuf->rsvd1 = opts->ctx_id;
+	execbuf->rsvd1 = opts->ctx ? opts->ctx->id : opts->ctx_id;
 
 	if (opts->flags & IGT_SPIN_FENCE_OUT)
 		execbuf->flags |= I915_EXEC_FENCE_OUT;
@@ -422,8 +434,10 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
 		struct intel_execution_engine2 e;
 		int class;
 
-		if (!gem_context_lookup_engine(fd, opts->engine,
-					       opts->ctx_id, &e)) {
+		if (opts->ctx) {
+			class = opts->ctx->cfg.engines[opts->engine].engine_class;
+		} else if (!gem_context_lookup_engine(fd, opts->engine,
+						      opts->ctx_id, &e)) {
 			class = e.class;
 		} else {
 			gem_require_ring(fd, opts->engine);
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index aee72da8..b26a7b7d 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -32,9 +32,12 @@
 #include "igt_list.h"
 #include "i915_drm.h"
 
+struct intel_ctx;
+
 typedef struct igt_spin {
 	struct igt_list_head link;
 
+
 	uint32_t handle;
 	uint32_t poll_handle;
 
@@ -61,6 +64,7 @@ typedef struct igt_spin {
 
 struct igt_spin_factory {
 	uint32_t ctx_id;
+	const struct intel_ctx *ctx;
 	uint32_t dependency;
 	unsigned int engine;
 	unsigned int flags;
-- 
2.31.1

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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 16/74] tests/i915/gem_exec_fence: Move the engine data into inter_engine_context

[Jason Ekstrand]

This will make iteration easier when we switch to intel_ctx_t.
---
 tests/i915/gem_exec_fence.c | 79 +++++++++++++++++++------------------
 1 file changed, 40 insertions(+), 39 deletions(-)

diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index b7b3f8e3..7377c7e7 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -2346,7 +2346,7 @@ struct inter_engine_context {
 		uint32_t context;
 	} iterations[9];
 
-	struct intel_engine_data *engines;
+	struct intel_engine_data engines;
 
 	struct inter_engine_batches {
 		void *increment_bb;
@@ -2414,7 +2414,7 @@ static void submit_timeline_execbuf(struct inter_engine_context *context,
 		execbuf->cliprects_ptr = to_user_pointer(&fence_list);
 	}
 
-	execbuf->flags |= context->engines->engines[run_engine_idx].flags;
+	execbuf->flags |= context->engines.engines[run_engine_idx].flags;
 
 	gem_execbuf(context->fd, execbuf);
 }
@@ -2659,12 +2659,12 @@ get_cs_timestamp_frequency(int fd)
 	igt_skip("Kernel with PARAM_CS_TIMESTAMP_FREQUENCY support required\n");
 }
 
-static void setup_timeline_chain_engines(struct inter_engine_context *context, int fd, struct intel_engine_data *engines)
+static void setup_timeline_chain_engines(struct inter_engine_context *context, int fd)
 {
 	memset(context, 0, sizeof(*context));
 
 	context->fd = fd;
-	context->engines = engines;
+	context->engines = intel_init_engine_list(fd, 0);
 
 	context->wait_context = gem_context_clone_with_engines(fd, 0);
 	context->wait_timeline = syncobj_create(fd, 0);
@@ -2684,15 +2684,16 @@ static void setup_timeline_chain_engines(struct inter_engine_context *context, i
 	gem_write(fd, context->wait_bb_handle, 0,
 		  context->wait_bb, context->wait_bb_len);
 
-	context->batches = calloc(engines->nengines, sizeof(*context->batches));
-	for (uint32_t e = 0; e < engines->nengines; e++) {
+	context->batches = calloc(context->engines.nengines,
+				  sizeof(*context->batches));
+	for (uint32_t e = 0; e < context->engines.nengines; e++) {
 		struct inter_engine_batches *batches = &context->batches[e];
 
 		batches->timeline = syncobj_create(fd, 0);
 
 		build_increment_engine_bb(
 			batches,
-			gem_engine_mmio_base(fd, engines->engines[e].name));
+			gem_engine_mmio_base(fd, context->engines.engines[e].name));
 		batches->increment_bb_handle = gem_create(fd, 4096);
 		gem_write(fd, batches->increment_bb_handle, 0,
 			  batches->increment_bb, batches->increment_bb_len);
@@ -2705,7 +2706,7 @@ static void setup_timeline_chain_engines(struct inter_engine_context *context, i
 	{
 		uint64_t dword = 1;
 		gem_write(fd, context->engine_counter_object.handle,
-			  sizeof(dword) * (context->engines->nengines - 1),
+			  sizeof(dword) * (context->engines.nengines - 1),
 			  &dword, sizeof(dword));
 	}
 }
@@ -2723,7 +2724,7 @@ static void teardown_timeline_chain_engines(struct inter_engine_context *context
 	gem_close(context->fd, context->wait_bb_handle);
 	free(context->wait_bb);
 
-	for (uint32_t e = 0; e < context->engines->nengines; e++) {
+	for (uint32_t e = 0; e < context->engines.nengines; e++) {
 		struct inter_engine_batches *batches = &context->batches[e];
 
 		syncobj_destroy(context->fd, batches->timeline);
@@ -2733,12 +2734,12 @@ static void teardown_timeline_chain_engines(struct inter_engine_context *context
 	free(context->batches);
 }
 
-static void test_syncobj_timeline_chain_engines(int fd, struct intel_engine_data *engines)
+static void test_syncobj_timeline_chain_engines(int fd)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd, engines);
+	setup_timeline_chain_engines(&ctx, fd);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2747,11 +2748,11 @@ static void test_syncobj_timeline_chain_engines(int fd, struct intel_engine_data
 	wait_engine(&ctx, 0, ctx.wait_timeline, 1);
 
 	for (uint32_t iter = 0; iter < ARRAY_SIZE(ctx.iterations); iter++) {
-		for (uint32_t engine = 0; engine < engines->nengines; engine++) {
+		for (uint32_t engine = 0; engine < ctx.engines.nengines; engine++) {
 			uint32_t prev_prev_engine =
-				(engines->nengines + engine - 2) % engines->nengines;
+				(ctx.engines.nengines + engine - 2) % ctx.engines.nengines;
 			uint32_t prev_engine =
-				(engines->nengines + engine - 1) % engines->nengines;
+				(ctx.engines.nengines + engine - 1) % ctx.engines.nengines;
 			/*
 			 * Pick up the wait engine semaphore for the
 			 * first increment, then pick up the previous
@@ -2777,28 +2778,28 @@ static void test_syncobj_timeline_chain_engines(int fd, struct intel_engine_data
 
 	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
-	for (uint32_t i = 0; i < ctx.engines->nengines; i++)
+	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
-			  ctx.engines->engines[i].name, counter_output[i]);
+			  ctx.engines.engines[i].name, counter_output[i]);
 
 	/*
 	 * Verify that we get the fibonacci number expected (we start
 	 * at the sequence on the second number : 1).
 	 */
-	igt_assert_eq(counter_output[engines->nengines - 1],
-		      fib(ARRAY_SIZE(ctx.iterations) * engines->nengines + 1));
+	igt_assert_eq(counter_output[ctx.engines.nengines - 1],
+		      fib(ARRAY_SIZE(ctx.iterations) * ctx.engines.nengines + 1));
 
 	munmap(counter_output, 4096);
 
 	teardown_timeline_chain_engines(&ctx);
 }
 
-static void test_syncobj_stationary_timeline_chain_engines(int fd, struct intel_engine_data *engines)
+static void test_syncobj_stationary_timeline_chain_engines(int fd)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd, engines);
+	setup_timeline_chain_engines(&ctx, fd);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2807,11 +2808,11 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd, struct intel_
 	wait_engine(&ctx, 0, ctx.wait_timeline, 1);
 
 	for (uint32_t iter = 0; iter < ARRAY_SIZE(ctx.iterations); iter++) {
-		for (uint32_t engine = 0; engine < engines->nengines; engine++) {
+		for (uint32_t engine = 0; engine < ctx.engines.nengines; engine++) {
 			uint32_t prev_prev_engine =
-				(engines->nengines + engine - 2) % engines->nengines;
+				(ctx.engines.nengines + engine - 2) % ctx.engines.nengines;
 			uint32_t prev_engine =
-				(engines->nengines + engine - 1) % engines->nengines;
+				(ctx.engines.nengines + engine - 1) % ctx.engines.nengines;
 			/*
 			 * Pick up the wait engine semaphore for the
 			 * first increment, then pick up the previous
@@ -2843,23 +2844,23 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd, struct intel_
 
 	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
-	for (uint32_t i = 0; i < ctx.engines->nengines; i++)
+	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
-			  ctx.engines->engines[i].name, counter_output[i]);
-	igt_assert_eq(counter_output[engines->nengines - 1],
-		      fib(ARRAY_SIZE(ctx.iterations) * engines->nengines + 1));
+			  ctx.engines.engines[i].name, counter_output[i]);
+	igt_assert_eq(counter_output[ctx.engines.nengines - 1],
+		      fib(ARRAY_SIZE(ctx.iterations) * ctx.engines.nengines + 1));
 
 	munmap(counter_output, 4096);
 
 	teardown_timeline_chain_engines(&ctx);
 }
 
-static void test_syncobj_backward_timeline_chain_engines(int fd, struct intel_engine_data *engines)
+static void test_syncobj_backward_timeline_chain_engines(int fd)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd, engines);
+	setup_timeline_chain_engines(&ctx, fd);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2868,11 +2869,11 @@ static void test_syncobj_backward_timeline_chain_engines(int fd, struct intel_en
 	wait_engine(&ctx, 0, ctx.wait_timeline, 1);
 
 	for (uint32_t iter = 0; iter < ARRAY_SIZE(ctx.iterations); iter++) {
-		for (uint32_t engine = 0; engine < engines->nengines; engine++) {
+		for (uint32_t engine = 0; engine < ctx.engines.nengines; engine++) {
 			uint32_t prev_prev_engine =
-				(engines->nengines + engine - 2) % engines->nengines;
+				(ctx.engines.nengines + engine - 2) % ctx.engines.nengines;
 			uint32_t prev_engine =
-				(engines->nengines + engine - 1) % engines->nengines;
+				(ctx.engines.nengines + engine - 1) % ctx.engines.nengines;
 			/*
 			 * Pick up the wait engine semaphore for the
 			 * first increment, then pick up the previous
@@ -2904,11 +2905,11 @@ static void test_syncobj_backward_timeline_chain_engines(int fd, struct intel_en
 
 	counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
-	for (uint32_t i = 0; i < ctx.engines->nengines; i++)
+	for (uint32_t i = 0; i < ctx.engines.nengines; i++)
 		igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
-			  ctx.engines->engines[i].name, counter_output[i]);
-	igt_assert_eq(counter_output[engines->nengines - 1],
-		      fib(ARRAY_SIZE(ctx.iterations) * engines->nengines + 1));
+			  ctx.engines.engines[i].name, counter_output[i]);
+	igt_assert_eq(counter_output[ctx.engines.nengines - 1],
+		      fib(ARRAY_SIZE(ctx.iterations) * ctx.engines.nengines + 1));
 
 	munmap(counter_output, 4096);
 
@@ -3216,13 +3217,13 @@ igt_main
 			}
 
 			igt_subtest("syncobj-timeline-chain-engines")
-				test_syncobj_timeline_chain_engines(i915, &engines);
+				test_syncobj_timeline_chain_engines(i915);
 
 			igt_subtest("syncobj-stationary-timeline-chain-engines")
-				test_syncobj_stationary_timeline_chain_engines(i915, &engines);
+				test_syncobj_stationary_timeline_chain_engines(i915);
 
 			igt_subtest("syncobj-backward-timeline-chain-engines")
-				test_syncobj_backward_timeline_chain_engines(i915, &engines);
+				test_syncobj_backward_timeline_chain_engines(i915);
 		}
 
 		igt_fixture {
-- 
2.31.1

_______________________________________________
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igt-dev@lists.freedesktop.org
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[igt-dev] [PATCH i-g-t 17/74] tests/i915/gem_exec_fence: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_fence.c | 245 ++++++++++++++++++++----------------
 1 file changed, 139 insertions(+), 106 deletions(-)

diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 7377c7e7..fc7bacce 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -30,6 +30,7 @@
 #include "igt_syncobj.h"
 #include "igt_sysfs.h"
 #include "igt_vgem.h"
+#include "intel_ctx.h"
 #include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Check that execbuf waits for explicit fences");
@@ -55,7 +56,8 @@ struct sync_merge_data {
 #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
 #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
 
-static void store(int fd, const struct intel_execution_engine2 *e,
+static void store(int fd, const intel_ctx_t *ctx,
+		  const struct intel_execution_engine2 *e,
 		  int fence, uint32_t target, unsigned offset_value)
 {
 	const int SCRATCH = 0;
@@ -71,6 +73,7 @@ static void store(int fd, const struct intel_execution_engine2 *e,
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
 	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
+	execbuf.rsvd1 = ctx->id;
 	execbuf.rsvd2 = fence;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
@@ -118,7 +121,8 @@ static bool fence_busy(int fence)
 #define NONBLOCK 0x2
 #define WAIT 0x4
 
-static void test_fence_busy(int fd, const struct intel_execution_engine2 *e,
+static void test_fence_busy(int fd, const intel_ctx_t *ctx,
+			    const struct intel_execution_engine2 *e,
 			    unsigned flags)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -138,6 +142,7 @@ static void test_fence_busy(int fd, const struct intel_execution_engine2 *e,
 	execbuf.buffers_ptr = to_user_pointer(&obj);
 	execbuf.buffer_count = 1;
 	execbuf.flags = e->flags | I915_EXEC_FENCE_OUT;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = gem_create(fd, 4096);
@@ -214,7 +219,7 @@ static void test_fence_busy(int fd, const struct intel_execution_engine2 *e,
 	gem_quiescent_gpu(fd);
 }
 
-static void test_fence_busy_all(int fd, unsigned flags)
+static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags)
 {
 	const struct intel_execution_engine2 *e;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -272,7 +277,7 @@ static void test_fence_busy_all(int fd, unsigned flags)
 	i++;
 
 	all = -1;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		int fence, new;
 
 		if ((flags & HANG) == 0 &&
@@ -280,6 +285,7 @@ static void test_fence_busy_all(int fd, unsigned flags)
 			continue;
 
 		execbuf.flags = e->flags | I915_EXEC_FENCE_OUT;
+		execbuf.rsvd1 = ctx->id;
 		execbuf.rsvd2 = -1;
 		gem_execbuf_wr(fd, &execbuf);
 		fence = execbuf.rsvd2 >> 32;
@@ -336,7 +342,8 @@ static unsigned int spin_hang(unsigned int flags)
 	return IGT_SPIN_NO_PREEMPTION | IGT_SPIN_INVALID_CS;
 }
 
-static void test_fence_await(int fd, const struct intel_execution_engine2 *e,
+static void test_fence_await(int fd, const intel_ctx_t *ctx,
+			     const struct intel_execution_engine2 *e,
 			     unsigned flags)
 {
 	const struct intel_execution_engine2 *e2;
@@ -350,20 +357,21 @@ static void test_fence_await(int fd, const struct intel_execution_engine2 *e,
 			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
 	spin = igt_spin_new(fd,
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .flags = IGT_SPIN_FENCE_OUT | spin_hang(flags));
 	igt_assert(spin->out_fence != -1);
 
 	i = 0;
-	__for_each_physical_engine(fd, e2) {
+	for_each_ctx_engine(fd, ctx, e2) {
 		if (!gem_class_can_store_dword(fd, e->class))
 			continue;
 
 		if (flags & NONBLOCK) {
-			store(fd, e2, spin->out_fence, scratch, i);
+			store(fd, ctx, e2, spin->out_fence, scratch, i);
 		} else {
 			igt_fork(child, 1)
-				store(fd, e2, spin->out_fence, scratch, i);
+				store(fd, ctx, e2, spin->out_fence, scratch, i);
 		}
 
 		i++;
@@ -439,9 +447,10 @@ static uint32_t timeslicing_batches(int i915, uint32_t *offset)
         return handle;
 }
 
-static void test_submit_fence(int i915, unsigned int engine)
+static void test_submit_fence(int i915, const intel_ctx_t *ctx,
+			      const struct intel_execution_engine2 *e)
 {
-	const struct intel_execution_engine2 *e;
+	const struct intel_execution_engine2 *e2;
 
 	/*
 	 * Create a pair of interlocking batches, that ping pong
@@ -450,8 +459,9 @@ static void test_submit_fence(int i915, unsigned int engine)
 	 * switch to the other batch in order to advance.
 	 */
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e2) {
 		unsigned int offset = 24 << 20;
+		const intel_ctx_t *tmp_ctx;
 		struct drm_i915_gem_exec_object2 obj = {
 			.offset = offset,
 			.flags = EXEC_OBJECT_PINNED,
@@ -467,17 +477,19 @@ static void test_submit_fence(int i915, unsigned int engine)
 		result = gem_mmap__device_coherent(i915, obj.handle,
 						   0, 4096, PROT_READ);
 
-		execbuf.flags = engine | I915_EXEC_FENCE_OUT;
+		execbuf.flags = e->flags | I915_EXEC_FENCE_OUT;
 		execbuf.batch_start_offset = 0;
+		execbuf.rsvd1 = ctx->id;
 		gem_execbuf_wr(i915, &execbuf);
 
-		execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+		tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
 		execbuf.rsvd2 >>= 32;
-		execbuf.flags = e->flags;
+		execbuf.flags = e2->flags;
 		execbuf.flags |= I915_EXEC_FENCE_SUBMIT | I915_EXEC_FENCE_OUT;
 		execbuf.batch_start_offset = offset;
 		gem_execbuf_wr(i915, &execbuf);
-		gem_context_destroy(i915, execbuf.rsvd1);
+		intel_ctx_destroy(i915, tmp_ctx);
 
 		gem_sync(i915, obj.handle);
 		gem_close(i915, obj.handle);
@@ -532,7 +544,9 @@ static uint32_t submitN_batches(int i915, uint32_t offset, int count)
         return handle;
 }
 
-static void test_submitN(int i915, unsigned int engine, int count)
+static void test_submitN(int i915, const intel_ctx_t *ctx,
+			 const struct intel_execution_engine2 *e,
+			 int count)
 {
 	unsigned int offset = 24 << 20;
 	unsigned int sz = ALIGN((count + 1) * 1024, 4096);
@@ -544,7 +558,8 @@ static void test_submitN(int i915, unsigned int engine, int count)
 	struct drm_i915_gem_execbuffer2 execbuf  = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.flags = engine | I915_EXEC_FENCE_OUT,
+		.flags = e->flags | I915_EXEC_FENCE_OUT,
+		.rsvd1 = ctx->id,
 	};
 	uint32_t *result =
 		gem_mmap__device_coherent(i915, obj.handle, 0, sz, PROT_READ);
@@ -555,10 +570,11 @@ static void test_submitN(int i915, unsigned int engine, int count)
 	igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
 	for (int i = 0; i < count; i++) {
-		execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+		const intel_ctx_t *tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
 		execbuf.batch_start_offset = (i + 1) * 1024;
 		gem_execbuf_wr(i915, &execbuf);
-		gem_context_destroy(i915, execbuf.rsvd1);
+		intel_ctx_destroy(i915, tmp_ctx);
 
 		execbuf.flags |= I915_EXEC_FENCE_SUBMIT;
 		execbuf.rsvd2 >>= 32;
@@ -594,7 +610,8 @@ static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
 	return err;
 }
 
-static void test_parallel(int i915, const struct intel_execution_engine2 *e)
+static void test_parallel(int i915, const intel_ctx_t *ctx,
+			  const struct intel_execution_engine2 *e)
 {
 	const struct intel_execution_engine2 *e2;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
@@ -608,6 +625,7 @@ static void test_parallel(int i915, const struct intel_execution_engine2 *e)
 
 	fence = igt_cork_plug(&cork, i915),
 	spin = igt_spin_new(i915,
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .fence = fence,
 			    .flags = (IGT_SPIN_FENCE_OUT |
@@ -615,7 +633,7 @@ static void test_parallel(int i915, const struct intel_execution_engine2 *e)
 	close(fence);
 
 	/* Queue all secondaries */
-	__for_each_physical_engine(i915, e2) {
+	for_each_ctx_engine(i915, ctx, e2) {
 		struct drm_i915_gem_relocation_entry reloc = {
 			.target_handle = scratch,
 			.offset = sizeof(uint32_t),
@@ -632,6 +650,7 @@ static void test_parallel(int i915, const struct intel_execution_engine2 *e)
 			.buffers_ptr = to_user_pointer(obj),
 			.buffer_count = ARRAY_SIZE(obj),
 			.flags = e2->flags | I915_EXEC_FENCE_SUBMIT,
+			.rsvd1 = ctx->id,
 			.rsvd2 = spin->out_fence,
 		};
 		uint32_t batch[16];
@@ -701,7 +720,8 @@ static void test_parallel(int i915, const struct intel_execution_engine2 *e)
 	igt_spin_free(i915, spin);
 }
 
-static void test_concurrent(int i915, const struct intel_execution_engine2 *e)
+static void test_concurrent(int i915, const intel_ctx_t *ctx,
+			    const struct intel_execution_engine2 *e)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	struct drm_i915_gem_relocation_entry reloc = {
@@ -721,10 +741,12 @@ static void test_concurrent(int i915, const struct intel_execution_engine2 *e)
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = e->flags | I915_EXEC_FENCE_SUBMIT,
+		.rsvd1 = ctx->id,
 	};
 	IGT_CORK_FENCE(cork);
 	uint32_t batch[16];
 	igt_spin_t *spin;
+	const intel_ctx_t *tmp_ctx;
 	uint32_t result;
 	int fence;
 	int i;
@@ -737,6 +759,7 @@ static void test_concurrent(int i915, const struct intel_execution_engine2 *e)
 
 	fence = igt_cork_plug(&cork, i915),
 	      spin = igt_spin_new(i915,
+				  .ctx = ctx,
 				  .engine = e->flags,
 				  .fence = fence,
 				  .flags = (IGT_SPIN_FENCE_OUT |
@@ -760,13 +783,14 @@ static void test_concurrent(int i915, const struct intel_execution_engine2 *e)
 	batch[++i] = MI_BATCH_BUFFER_END;
 	gem_write(i915, obj[1].handle, 0, batch, sizeof(batch));
 
-	execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+	tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
+	execbuf.rsvd1 = tmp_ctx->id;
 	execbuf.rsvd2 = spin->out_fence;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
 	gem_execbuf(i915, &execbuf);
-	gem_context_destroy(i915, execbuf.rsvd1);
+	intel_ctx_destroy(i915, tmp_ctx);
 	gem_close(i915, obj[1].handle);
 
 	/*
@@ -795,7 +819,7 @@ static void test_concurrent(int i915, const struct intel_execution_engine2 *e)
 	igt_spin_free(i915, spin);
 }
 
-static void test_submit_chain(int i915)
+static void test_submit_chain(int i915, const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
 	igt_spin_t *spin, *sn;
@@ -806,8 +830,9 @@ static void test_submit_chain(int i915)
 	/* Check that we can simultaneously launch spinners on each engine */
 
 	fence = igt_cork_plug(&cork, i915);
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		spin = igt_spin_new(i915,
+				    .ctx = ctx,
 				    .engine = e->flags,
 				    .fence = fence,
 				    .flags = (IGT_SPIN_POLL_RUN |
@@ -847,7 +872,8 @@ static uint32_t batch_create(int fd)
 	return handle;
 }
 
-static void test_keep_in_fence(int fd, const struct intel_execution_engine2 *e)
+static void test_keep_in_fence(int fd, const intel_ctx_t *ctx,
+			       const struct intel_execution_engine2 *e)
 {
 	struct sigaction sa = { .sa_handler = alarm_handler };
 	struct drm_i915_gem_exec_object2 obj = {
@@ -857,13 +883,14 @@ static void test_keep_in_fence(int fd, const struct intel_execution_engine2 *e)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = e->flags | I915_EXEC_FENCE_OUT,
+		.rsvd1 = ctx->id,
 	};
 	unsigned long count, last;
 	struct itimerval itv;
 	igt_spin_t *spin;
 	int fence;
 
-	spin = igt_spin_new(fd, .engine = e->flags);
+	spin = igt_spin_new(fd, .ctx = ctx, .engine = e->flags);
 
 	gem_execbuf_wr(fd, &execbuf);
 	fence = upper_32_bits(execbuf.rsvd2);
@@ -915,7 +942,8 @@ static void test_keep_in_fence(int fd, const struct intel_execution_engine2 *e)
 }
 
 #define EXPIRED 0x10000
-static void test_long_history(int fd, long ring_size, unsigned flags)
+static void test_long_history(int fd, const intel_ctx_t *ctx,
+			      long ring_size, unsigned flags)
 {
 	const uint32_t sz = 1 << 20;
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -932,7 +960,7 @@ static void test_long_history(int fd, long ring_size, unsigned flags)
 		limit = ring_size / 3;
 
 	nengine = 0;
-	__for_each_physical_engine(fd, e)
+	for_each_ctx_engine(fd, ctx, e)
 		engines[nengine++] = e->flags;
 	igt_require(nengine);
 
@@ -946,6 +974,7 @@ static void test_long_history(int fd, long ring_size, unsigned flags)
 	execbuf.buffers_ptr = to_user_pointer(&obj[1]);
 	execbuf.buffer_count = 1;
 	execbuf.flags = I915_EXEC_FENCE_OUT;
+	execbuf.rsvd1 = ctx->id;
 
 	gem_execbuf_wr(fd, &execbuf);
 	all_fences = execbuf.rsvd2 >> 32;
@@ -956,7 +985,8 @@ static void test_long_history(int fd, long ring_size, unsigned flags)
 	obj[0].handle = igt_cork_plug(&c, fd);
 
 	igt_until_timeout(5) {
-		execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
+		const intel_ctx_t *tmp_ctx = intel_ctx_create(fd, &ctx->cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
 
 		for (n = 0; n < nengine; n++) {
 			struct sync_merge_data merge;
@@ -977,7 +1007,7 @@ static void test_long_history(int fd, long ring_size, unsigned flags)
 			all_fences = merge.fence;
 		}
 
-		gem_context_destroy(fd, execbuf.rsvd1);
+		intel_ctx_destroy(fd, tmp_ctx);
 		if (!--limit)
 			break;
 	}
@@ -991,7 +1021,7 @@ static void test_long_history(int fd, long ring_size, unsigned flags)
 	execbuf.buffers_ptr = to_user_pointer(&obj[1]);
 	execbuf.buffer_count = 1;
 	execbuf.rsvd2 = all_fences;
-	execbuf.rsvd1 = 0;
+	execbuf.rsvd1 = ctx->id;
 
 	for (s = 0; s < ring_size; s++) {
 		for (n = 0; n < nengine; n++) {
@@ -1257,7 +1287,7 @@ static void test_syncobj_signal(int fd)
 	syncobj_destroy(fd, fence.handle);
 }
 
-static void test_syncobj_wait(int fd)
+static void test_syncobj_wait(int fd, const intel_ctx_t *ctx)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_exec_object2 obj;
@@ -1299,12 +1329,13 @@ static void test_syncobj_wait(int fd)
 	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
 
 	n = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		obj.handle = gem_create(fd, 4096);
 		gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
 
 		/* Now wait upon the blocked engine */
 		execbuf.flags = I915_EXEC_FENCE_ARRAY | e->flags;
+		execbuf.rsvd1 = ctx->id;
 		execbuf.cliprects_ptr = to_user_pointer(&fence);
 		execbuf.num_cliprects = 1;
 		fence.flags = I915_EXEC_FENCE_WAIT;
@@ -1997,7 +2028,7 @@ static void test_syncobj_timeline_signal(int fd)
 static const char *test_syncobj_timeline_wait_desc =
 	"Verifies that waiting on a timeline syncobj point between engines"
 	" works";
-static void test_syncobj_timeline_wait(int fd)
+static void test_syncobj_timeline_wait(int fd, const intel_ctx_t *ctx)
 {
 	const uint32_t bbe[2] = {
 		MI_BATCH_BUFFER_END,
@@ -2024,7 +2055,7 @@ static void test_syncobj_timeline_wait(int fd)
 
 	gem_quiescent_gpu(fd);
 
-	spin = igt_spin_new(fd, .engine = ALL_ENGINES);
+	spin = igt_spin_new(fd, .ctx = ctx, .engine = ALL_ENGINES);
 
 	memset(&timeline_fences, 0, sizeof(timeline_fences));
 	timeline_fences.base.name = DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES;
@@ -2046,12 +2077,13 @@ static void test_syncobj_timeline_wait(int fd)
 	gem_close(fd, obj.handle);
 
 	n = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		obj.handle = gem_create(fd, 4096);
 		gem_write(fd, obj.handle, 0, bbe, sizeof(bbe));
 
 		/* Now wait upon the blocked engine */
 		execbuf.flags = I915_EXEC_USE_EXTENSIONS | e->flags;
+		execbuf.rsvd1 = ctx->id,
 		execbuf.cliprects_ptr = to_user_pointer(&timeline_fences);
 		execbuf.num_cliprects = 0;
 		fence.flags = I915_EXEC_FENCE_WAIT;
@@ -2341,9 +2373,10 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
 
 struct inter_engine_context {
 	int fd;
+	const intel_ctx_cfg_t *cfg;
 
 	struct {
-		uint32_t context;
+		const intel_ctx_t *ctx;
 	} iterations[9];
 
 	struct intel_engine_data engines;
@@ -2367,7 +2400,7 @@ struct inter_engine_context {
 	void *jump_ptr;
 	void *timestamp2_ptr;
 
-	uint32_t wait_context;
+	const intel_ctx_t *wait_ctx;
 	uint32_t wait_timeline;
 
 	struct drm_i915_gem_exec_object2 engine_counter_object;
@@ -2495,7 +2528,7 @@ static void wait_engine(struct inter_engine_context *context,
 		.buffers_ptr = to_user_pointer(&objects[0]),
 		.buffer_count = 2,
 		.flags = I915_EXEC_HANDLE_LUT,
-		.rsvd1 = context->wait_context,
+		.rsvd1 = context->wait_ctx->id,
 		.batch_len = context->wait_bb_len,
 	};
 
@@ -2562,7 +2595,7 @@ static void build_increment_engine_bb(struct inter_engine_batches *batch,
 }
 
 static void increment_engine(struct inter_engine_context *context,
-			     uint32_t gem_context,
+			     const intel_ctx_t *ctx,
 			     uint32_t read0_engine_idx,
 			     uint32_t read1_engine_idx,
 			     uint32_t write_engine_idx,
@@ -2585,7 +2618,7 @@ static void increment_engine(struct inter_engine_context *context,
 		.buffers_ptr = to_user_pointer(&objects[0]),
 		.buffer_count = ARRAY_SIZE(objects),
 		.flags = I915_EXEC_HANDLE_LUT,
-		.rsvd1 = gem_context,
+		.rsvd1 = ctx->id,
 		.batch_len = batch->increment_bb_len,
 	};
 
@@ -2659,23 +2692,25 @@ get_cs_timestamp_frequency(int fd)
 	igt_skip("Kernel with PARAM_CS_TIMESTAMP_FREQUENCY support required\n");
 }
 
-static void setup_timeline_chain_engines(struct inter_engine_context *context, int fd)
+static void setup_timeline_chain_engines(struct inter_engine_context *context, int fd,
+					 const intel_ctx_cfg_t *cfg)
 {
 	memset(context, 0, sizeof(*context));
 
 	context->fd = fd;
-	context->engines = intel_init_engine_list(fd, 0);
+	context->cfg = cfg;
+	context->engines = intel_engine_list_for_ctx_cfg(fd, cfg);
 
-	context->wait_context = gem_context_clone_with_engines(fd, 0);
+	context->wait_ctx = intel_ctx_create(fd, cfg);
 	context->wait_timeline = syncobj_create(fd, 0);
 
 	context->engine_counter_object.handle = gem_create(fd, 4096);
 
 	for (uint32_t i = 0; i < ARRAY_SIZE(context->iterations); i++) {
-		context->iterations[i].context = gem_context_clone_with_engines(fd, 0);
+		context->iterations[i].ctx = intel_ctx_create(fd, context->cfg);
 
 		/* Give a different priority to all contexts. */
-		gem_context_set_priority(fd, context->iterations[i].context,
+		gem_context_set_priority(fd, context->iterations[i].ctx->id,
 					 I915_CONTEXT_MAX_USER_PRIORITY - ARRAY_SIZE(context->iterations) + i);
 	}
 
@@ -2716,10 +2751,10 @@ static void teardown_timeline_chain_engines(struct inter_engine_context *context
 	gem_close(context->fd, context->engine_counter_object.handle);
 
 	for (uint32_t i = 0; i < ARRAY_SIZE(context->iterations); i++) {
-		gem_context_destroy(context->fd, context->iterations[i].context);
+		intel_ctx_destroy(context->fd, context->iterations[i].ctx);
 	}
 
-	gem_context_destroy(context->fd, context->wait_context);
+	intel_ctx_destroy(context->fd, context->wait_ctx);
 	syncobj_destroy(context->fd, context->wait_timeline);
 	gem_close(context->fd, context->wait_bb_handle);
 	free(context->wait_bb);
@@ -2734,12 +2769,12 @@ static void teardown_timeline_chain_engines(struct inter_engine_context *context
 	free(context->batches);
 }
 
-static void test_syncobj_timeline_chain_engines(int fd)
+static void test_syncobj_timeline_chain_engines(int fd, const intel_ctx_cfg_t *cfg)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd);
+	setup_timeline_chain_engines(&ctx, fd, cfg);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2765,7 +2800,7 @@ static void test_syncobj_timeline_chain_engines(int fd)
 				iter == 0 && engine == 0 ?
 				1 : (engine == 0 ? iter : (iter + 1));
 
-			increment_engine(&ctx, ctx.iterations[iter].context,
+			increment_engine(&ctx, ctx.iterations[iter].ctx,
 					 prev_prev_engine /* read0 engine */,
 					 prev_engine /* read1 engine */,
 					 engine /* write engine */,
@@ -2794,12 +2829,12 @@ static void test_syncobj_timeline_chain_engines(int fd)
 	teardown_timeline_chain_engines(&ctx);
 }
 
-static void test_syncobj_stationary_timeline_chain_engines(int fd)
+static void test_syncobj_stationary_timeline_chain_engines(int fd, const intel_ctx_cfg_t *cfg)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd);
+	setup_timeline_chain_engines(&ctx, fd, cfg);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2831,7 +2866,7 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd)
 				iter == 0 && engine == 0 ?
 				1 : 10;
 
-			increment_engine(&ctx, ctx.iterations[iter].context,
+			increment_engine(&ctx, ctx.iterations[iter].ctx,
 					 prev_prev_engine /* read0 engine */,
 					 prev_engine /* read1 engine */,
 					 engine /* write engine */,
@@ -2855,12 +2890,12 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd)
 	teardown_timeline_chain_engines(&ctx);
 }
 
-static void test_syncobj_backward_timeline_chain_engines(int fd)
+static void test_syncobj_backward_timeline_chain_engines(int fd, const intel_ctx_cfg_t *cfg)
 {
 	struct inter_engine_context ctx;
 	uint64_t *counter_output;
 
-	setup_timeline_chain_engines(&ctx, fd);
+	setup_timeline_chain_engines(&ctx, fd, cfg);
 
 	/*
 	 * Delay all the other operations by making them depend on an
@@ -2892,7 +2927,7 @@ static void test_syncobj_backward_timeline_chain_engines(int fd)
 				iter == 0 && engine == 0 ?
 				1 : 1;
 
-			increment_engine(&ctx, ctx.iterations[iter].context,
+			increment_engine(&ctx, ctx.iterations[iter].ctx,
 					 prev_prev_engine /* read0 engine */,
 					 prev_engine /* read1 engine */,
 					 engine /* write engine */,
@@ -2919,6 +2954,7 @@ static void test_syncobj_backward_timeline_chain_engines(int fd)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int i915 = -1;
 
 	igt_fixture {
@@ -2926,6 +2962,7 @@ igt_main
 		igt_require_gem(i915);
 		igt_require(gem_has_exec_fence(i915));
 		gem_require_mmap_wc(i915);
+		ctx = intel_ctx_create_all_physical(i915);
 
 		gem_submission_print_method(i915);
 	}
@@ -2938,19 +2975,19 @@ igt_main
 		}
 
 		igt_subtest("basic-busy-all")
-			test_fence_busy_all(i915, 0);
+			test_fence_busy_all(i915, ctx, 0);
 		igt_subtest("basic-wait-all")
-			test_fence_busy_all(i915, WAIT);
+			test_fence_busy_all(i915, ctx, WAIT);
 
 		igt_fixture {
 			igt_stop_hang_detector();
-			hang = igt_allow_hang(i915, 0, 0);
+			hang = igt_allow_hang(i915, ctx->id, 0);
 		}
 
 		igt_subtest("busy-hang-all")
-			test_fence_busy_all(i915, HANG);
+			test_fence_busy_all(i915, ctx, HANG);
 		igt_subtest("wait-hang-all")
-			test_fence_busy_all(i915, WAIT | HANG);
+			test_fence_busy_all(i915, ctx, WAIT | HANG);
 
 		igt_fixture {
 			igt_disallow_hang(i915, hang);
@@ -2958,7 +2995,7 @@ igt_main
 	}
 
 	igt_subtest_group {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			igt_fixture {
 				igt_require(gem_class_can_store_dword(i915, e->class));
 			}
@@ -2969,42 +3006,42 @@ igt_main
 			}
 
 			igt_subtest_with_dynamic("basic-busy") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_busy(i915, e, 0);
+						test_fence_busy(i915, ctx, e, 0);
 				}
 			}
 			igt_subtest_with_dynamic("basic-wait") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_busy(i915, e, WAIT);
+						test_fence_busy(i915, ctx, e, WAIT);
 				}
 			}
 			igt_subtest_with_dynamic("basic-await") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_await(i915, e, 0);
+						test_fence_await(i915, ctx, e, 0);
 				}
 			}
 			igt_subtest_with_dynamic("nb-await") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_await(i915,
-								 e, NONBLOCK);
+						test_fence_await(i915, ctx, e,
+								 NONBLOCK);
 				}
 			}
 			igt_subtest_with_dynamic("keep-in-fence") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_keep_in_fence(i915, e);
+						test_keep_in_fence(i915, ctx, e);
 				}
 			}
 			igt_subtest_with_dynamic("parallel") {
 				igt_require(has_submit_fence(i915));
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name) {
 						igt_until_timeout(2)
-							test_parallel(i915, e);
+							test_parallel(i915, ctx, e);
 					}
 				}
 			}
@@ -3013,9 +3050,9 @@ igt_main
 				igt_require(has_submit_fence(i915));
 				igt_require(gem_scheduler_has_semaphores(i915));
 				igt_require(gem_scheduler_has_preemption(i915));
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_concurrent(i915, e);
+						test_concurrent(i915, ctx, e);
 				}
 			}
 
@@ -3024,9 +3061,9 @@ igt_main
 				igt_require(gem_scheduler_has_preemption(i915));
 				igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_submit_fence(i915, e->flags);
+						test_submit_fence(i915, ctx, e);
 				}
 			}
 
@@ -3035,9 +3072,9 @@ igt_main
 				igt_require(gem_scheduler_has_preemption(i915));
 				igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_submitN(i915, e->flags, 3);
+						test_submitN(i915, ctx, e, 3);
 				}
 			}
 
@@ -3046,15 +3083,15 @@ igt_main
 				igt_require(gem_scheduler_has_preemption(i915));
 				igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_submitN(i915, e->flags, 67);
+						test_submitN(i915, ctx, e, 67);
 				}
 			}
 
 			igt_subtest("submit-chain") {
 				igt_require(has_submit_fence(i915));
-				test_submit_chain(i915);
+				test_submit_chain(i915, ctx);
 			}
 
 			igt_fixture {
@@ -3070,27 +3107,27 @@ igt_main
 			}
 
 			igt_subtest_with_dynamic("busy-hang") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_busy(i915, e, HANG);
+						test_fence_busy(i915, ctx, e, HANG);
 				}
 			}
 			igt_subtest_with_dynamic("wait-hang") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_busy(i915, e, HANG | WAIT);
+						test_fence_busy(i915, ctx, e, HANG | WAIT);
 				}
 			}
 			igt_subtest_with_dynamic("await-hang") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_await(i915, e, HANG);
+						test_fence_await(i915, ctx, e, HANG);
 				}
 			}
 			igt_subtest_with_dynamic("nb-await-hang") {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						test_fence_await(i915, e, NONBLOCK | HANG);
+						test_fence_await(i915, ctx, e, NONBLOCK | HANG);
 				}
 			}
 			igt_fixture {
@@ -3111,10 +3148,10 @@ igt_main
 		}
 
 		igt_subtest("long-history")
-			test_long_history(i915, ring_size, 0);
+			test_long_history(i915, ctx, ring_size, 0);
 
 		igt_subtest("expired-history")
-			test_long_history(i915, ring_size, EXPIRED);
+			test_long_history(i915, ctx, ring_size, EXPIRED);
 	}
 
 	igt_subtest_group { /* syncobj */
@@ -3140,7 +3177,7 @@ igt_main
 			test_syncobj_signal(i915);
 
 		igt_subtest("syncobj-wait")
-			test_syncobj_wait(i915);
+			test_syncobj_wait(i915, ctx);
 
 		igt_subtest("syncobj-export")
 			test_syncobj_export(i915);
@@ -3188,7 +3225,7 @@ igt_main
 
 		igt_describe(test_syncobj_timeline_wait_desc);
 		igt_subtest("syncobj-timeline-wait")
-			test_syncobj_timeline_wait(i915);
+			test_syncobj_timeline_wait(i915, ctx);
 
 		igt_describe(test_syncobj_timeline_export_desc);
 		igt_subtest("syncobj-timeline-export")
@@ -3203,8 +3240,6 @@ igt_main
 			test_syncobj_timeline_multiple_ext_nodes(i915);
 
 		igt_subtest_group { /* syncobj timeline engine chaining */
-			struct intel_engine_data engines;
-
 			igt_fixture {
 				/*
 				 * We need support for MI_ALU on all
@@ -3212,18 +3247,16 @@ igt_main
 				 * only on Gen8+
 				 */
 				igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
-				engines = intel_init_engine_list(i915, 0);
-				igt_require(engines.nengines > 1);
 			}
 
 			igt_subtest("syncobj-timeline-chain-engines")
-				test_syncobj_timeline_chain_engines(i915);
+				test_syncobj_timeline_chain_engines(i915, &ctx->cfg);
 
 			igt_subtest("syncobj-stationary-timeline-chain-engines")
-				test_syncobj_stationary_timeline_chain_engines(i915);
+				test_syncobj_stationary_timeline_chain_engines(i915, &ctx->cfg);
 
 			igt_subtest("syncobj-backward-timeline-chain-engines")
-				test_syncobj_backward_timeline_chain_engines(i915);
+				test_syncobj_backward_timeline_chain_engines(i915, &ctx->cfg);
 		}
 
 		igt_fixture {
-- 
2.31.1

_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 18/74] tests/i915/gem_exec_schedule: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_schedule.c | 892 +++++++++++++++++----------------
 1 file changed, 471 insertions(+), 421 deletions(-)

diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index f84967c7..fdb719fb 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -35,11 +35,13 @@
 #include <unistd.h>
 
 #include "i915/gem.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 #include "igt_rand.h"
 #include "igt_rapl.h"
 #include "igt_sysfs.h"
 #include "igt_vgem.h"
+#include "intel_ctx.h"
 #include "sw_sync.h"
 
 #define LO 0
@@ -51,7 +53,6 @@
 
 #define MAX_CONTEXTS 1024
 #define MAX_ELSP_QLEN 16
-#define MAX_ENGINES (I915_EXEC_RING_MASK + 1)
 
 #define MI_SEMAPHORE_WAIT		(0x1c << 23)
 #define   MI_SEMAPHORE_POLL             (1 << 15)
@@ -89,7 +90,7 @@ void __sync_read_u32_count(int fd, uint32_t handle, uint32_t *dst, uint64_t size
 	gem_read(fd, handle, 0, dst, size);
 }
 
-static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
+static uint32_t __store_dword(int fd, const intel_ctx_t *ctx, unsigned ring,
 			      uint32_t target, uint32_t offset, uint32_t value,
 			      uint32_t cork, int fence, unsigned write_domain)
 {
@@ -106,7 +107,7 @@ static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
 	execbuf.flags = ring;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ctx->id;
 
 	if (fence != -1) {
 		execbuf.flags |= I915_EXEC_FENCE_IN;
@@ -153,7 +154,7 @@ static uint32_t __store_dword(int fd, uint32_t ctx, unsigned ring,
 	return obj[2].handle;
 }
 
-static void store_dword(int fd, uint32_t ctx, unsigned ring,
+static void store_dword(int fd, const intel_ctx_t *ctx, unsigned ring,
 			uint32_t target, uint32_t offset, uint32_t value,
 			unsigned write_domain)
 {
@@ -162,7 +163,7 @@ static void store_dword(int fd, uint32_t ctx, unsigned ring,
 				    0, -1, write_domain));
 }
 
-static void store_dword_plug(int fd, uint32_t ctx, unsigned ring,
+static void store_dword_plug(int fd, const intel_ctx_t *ctx, unsigned ring,
 			     uint32_t target, uint32_t offset, uint32_t value,
 			     uint32_t cork, unsigned write_domain)
 {
@@ -171,7 +172,7 @@ static void store_dword_plug(int fd, uint32_t ctx, unsigned ring,
 				    cork, -1, write_domain));
 }
 
-static void store_dword_fenced(int fd, uint32_t ctx, unsigned ring,
+static void store_dword_fenced(int fd, const intel_ctx_t *ctx, unsigned ring,
 			       uint32_t target, uint32_t offset, uint32_t value,
 			       int fence, unsigned write_domain)
 {
@@ -180,21 +181,24 @@ static void store_dword_fenced(int fd, uint32_t ctx, unsigned ring,
 				    0, fence, write_domain));
 }
 
-static uint32_t create_highest_priority(int fd)
+static const intel_ctx_t *
+create_highest_priority(int fd, const intel_ctx_cfg_t *cfg)
 {
-	uint32_t ctx = gem_context_clone_with_engines(fd, 0);
+	const intel_ctx_t *ctx = intel_ctx_create(fd, cfg);
 
 	/*
 	 * If there is no priority support, all contexts will have equal
 	 * priority (and therefore the max user priority), so no context
 	 * can overtake us, and we effectively can form a plug.
 	 */
-	__gem_context_set_priority(fd, ctx, MAX_PRIO);
+	__gem_context_set_priority(fd, ctx->id, MAX_PRIO);
 
 	return ctx;
 }
 
-static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
+static void unplug_show_queue(int fd, struct igt_cork *c,
+			      const intel_ctx_cfg_t *cfg,
+			      unsigned int engine)
 {
 	igt_spin_t *spin[MAX_ELSP_QLEN];
 	int max = MAX_ELSP_QLEN;
@@ -204,12 +208,9 @@ static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
 		max = 1;
 
 	for (int n = 0; n < max; n++) {
-		const struct igt_spin_factory opts = {
-			.ctx_id = create_highest_priority(fd),
-			.engine = engine,
-		};
-		spin[n] = __igt_spin_factory(fd, &opts);
-		gem_context_destroy(fd, opts.ctx_id);
+		const intel_ctx_t *ctx = create_highest_priority(fd, cfg);
+		spin[n] = __igt_spin_new(fd, .ctx = ctx, .engine = engine);
+		intel_ctx_destroy(fd, ctx);
 	}
 
 	igt_cork_unplug(c); /* batches will now be queued on the engine */
@@ -220,7 +221,7 @@ static void unplug_show_queue(int fd, struct igt_cork *c, unsigned int engine)
 
 }
 
-static void fifo(int fd, unsigned ring)
+static void fifo(int fd, const intel_ctx_t *ctx, unsigned ring)
 {
 	IGT_CORK_FENCE(cork);
 	uint32_t scratch;
@@ -232,10 +233,10 @@ static void fifo(int fd, unsigned ring)
 	fence = igt_cork_plug(&cork, fd);
 
 	/* Same priority, same timeline, final result will be the second eb */
-	store_dword_fenced(fd, 0, ring, scratch, 0, 1, fence, 0);
-	store_dword_fenced(fd, 0, ring, scratch, 0, 2, fence, 0);
+	store_dword_fenced(fd, ctx, ring, scratch, 0, 1, fence, 0);
+	store_dword_fenced(fd, ctx, ring, scratch, 0, 2, fence, 0);
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, &ctx->cfg, ring);
 	close(fence);
 
 	result =  __sync_read_u32(fd, scratch, 0);
@@ -249,7 +250,8 @@ enum implicit_dir {
 	WRITE_READ = 0x2,
 };
 
-static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
+static void implicit_rw(int i915, const intel_ctx_t *ctx, unsigned int ring,
+			enum implicit_dir dir)
 {
 	const struct intel_execution_engine2 *e;
 	IGT_CORK_FENCE(cork);
@@ -259,7 +261,7 @@ static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
 	int fence;
 
 	count = 0;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (e->flags == ring)
 			continue;
 
@@ -274,28 +276,28 @@ static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
 	fence = igt_cork_plug(&cork, i915);
 
 	if (dir & WRITE_READ)
-		store_dword_fenced(i915, 0,
+		store_dword_fenced(i915, ctx,
 				   ring, scratch, 0, ~ring,
 				   fence, I915_GEM_DOMAIN_RENDER);
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (e->flags == ring)
 			continue;
 
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
-		store_dword_fenced(i915, 0,
+		store_dword_fenced(i915, ctx,
 				   e->flags, scratch, 0, e->flags,
 				   fence, 0);
 	}
 
 	if (dir & READ_WRITE)
-		store_dword_fenced(i915, 0,
+		store_dword_fenced(i915, ctx,
 				   ring, scratch, 0, ring,
 				   fence, I915_GEM_DOMAIN_RENDER);
 
-	unplug_show_queue(i915, &cork, ring);
+	unplug_show_queue(i915, &cork, &ctx->cfg, ring);
 	close(fence);
 
 	result =  __sync_read_u32(i915, scratch, 0);
@@ -307,7 +309,8 @@ static void implicit_rw(int i915, unsigned ring, enum implicit_dir dir)
 		igt_assert_eq_u32(result, ring);
 }
 
-static void independent(int fd, unsigned int engine, unsigned long flags)
+static void independent(int fd, const intel_ctx_t *ctx, unsigned int engine,
+			unsigned long flags)
 {
 	const struct intel_execution_engine2 *e;
 	IGT_CORK_FENCE(cork);
@@ -323,7 +326,7 @@ static void independent(int fd, unsigned int engine, unsigned long flags)
 	fence = igt_cork_plug(&cork, fd);
 
 	/* Check that we can submit to engine while all others are blocked */
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		if (e->flags == engine)
 			continue;
 
@@ -332,6 +335,7 @@ static void independent(int fd, unsigned int engine, unsigned long flags)
 
 		if (spin == NULL) {
 			spin = __igt_spin_new(fd,
+					      .ctx = ctx,
 					      .engine = e->flags,
 					      .flags = flags);
 		} else {
@@ -343,14 +347,14 @@ static void independent(int fd, unsigned int engine, unsigned long flags)
 			gem_execbuf(fd, &eb);
 		}
 
-		store_dword_fenced(fd, 0, e->flags, scratch, 0, e->flags, fence, 0);
+		store_dword_fenced(fd, ctx, e->flags, scratch, 0, e->flags, fence, 0);
 	}
 	igt_require(spin);
 
 	/* Same priority, but different timeline (as different engine) */
-	batch = __store_dword(fd, 0, engine, scratch, 0, engine, 0, fence, 0);
+	batch = __store_dword(fd, ctx, engine, scratch, 0, engine, 0, fence, 0);
 
-	unplug_show_queue(fd, &cork, engine);
+	unplug_show_queue(fd, &cork, &ctx->cfg, engine);
 	close(fence);
 
 	gem_sync(fd, batch);
@@ -373,11 +377,12 @@ static void independent(int fd, unsigned int engine, unsigned long flags)
 	gem_close(fd, scratch);
 }
 
-static void smoketest(int fd, unsigned ring, unsigned timeout)
+static void smoketest(int fd, const intel_ctx_cfg_t *cfg,
+		      unsigned ring, unsigned timeout)
 {
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	const struct intel_execution_engine2 *e;
-	unsigned engines[MAX_ENGINES];
+	unsigned engines[GEM_MAX_ENGINES];
 	unsigned nengine;
 	unsigned engine;
 	uint32_t scratch;
@@ -385,7 +390,7 @@ static void smoketest(int fd, unsigned ring, unsigned timeout)
 
 	nengine = 0;
 	if (ring == ALL_ENGINES) {
-		__for_each_physical_engine(fd, e)
+		for_each_ctx_cfg_engine(fd, cfg, e)
 			if (gem_class_can_store_dword(fd, e->class))
 				engines[nengine++] = e->flags;
 	} else {
@@ -396,16 +401,16 @@ static void smoketest(int fd, unsigned ring, unsigned timeout)
 	scratch = gem_create(fd, 4096);
 	igt_fork(child, ncpus) {
 		unsigned long count = 0;
-		uint32_t ctx;
+		const intel_ctx_t *ctx;
 
 		hars_petruska_f54_1_random_perturb(child);
 
-		ctx = gem_context_clone_with_engines(fd, 0);
+		ctx = intel_ctx_create(fd, cfg);
 		igt_until_timeout(timeout) {
 			int prio;
 
 			prio = hars_petruska_f54_1_random_unsafe_max(MAX_PRIO - MIN_PRIO) + MIN_PRIO;
-			gem_context_set_priority(fd, ctx, prio);
+			gem_context_set_priority(fd, ctx->id, prio);
 
 			engine = engines[hars_petruska_f54_1_random_unsafe_max(nengine)];
 			store_dword(fd, ctx, engine, scratch,
@@ -416,7 +421,7 @@ static void smoketest(int fd, unsigned ring, unsigned timeout)
 					    8*child + 4, count++,
 					    0);
 		}
-		gem_context_destroy(fd, ctx);
+		intel_ctx_destroy(fd, ctx);
 	}
 	igt_waitchildren();
 
@@ -483,7 +488,8 @@ static uint32_t timeslicing_batches(int i915, uint32_t *offset)
         return handle;
 }
 
-static void timeslice(int i915, unsigned int engine)
+static void timeslice(int i915, const intel_ctx_cfg_t *cfg,
+		      unsigned int engine)
 {
 	unsigned int offset = 24 << 20;
 	struct drm_i915_gem_exec_object2 obj = {
@@ -494,6 +500,7 @@ static void timeslice(int i915, unsigned int engine)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 	};
+	const intel_ctx_t *ctx;
 	uint32_t *result;
 	int out;
 
@@ -517,12 +524,13 @@ static void timeslice(int i915, unsigned int engine)
 
 	/* No coupling between requests; free to timeslice */
 
-	execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+	ctx = intel_ctx_create(i915, cfg);
+	execbuf.rsvd1 = ctx->id;
 	execbuf.rsvd2 >>= 32;
 	execbuf.flags = engine | I915_EXEC_FENCE_OUT;
 	execbuf.batch_start_offset = offset;
 	gem_execbuf_wr(i915, &execbuf);
-	gem_context_destroy(i915, execbuf.rsvd1);
+	intel_ctx_destroy(i915, ctx);
 
 	gem_sync(i915, obj.handle);
 	gem_close(i915, obj.handle);
@@ -576,7 +584,8 @@ static uint32_t timesliceN_batches(int i915, uint32_t offset, int count)
         return handle;
 }
 
-static void timesliceN(int i915, unsigned int engine, int count)
+static void timesliceN(int i915, const intel_ctx_cfg_t *cfg,
+		       unsigned int engine, int count)
 {
 	const unsigned int sz = ALIGN((count + 1) * 1024, 4096);
 	unsigned int offset = 24 << 20;
@@ -592,6 +601,7 @@ static void timesliceN(int i915, unsigned int engine, int count)
 	};
 	uint32_t *result =
 		gem_mmap__device_coherent(i915, obj.handle, 0, sz, PROT_READ);
+	const intel_ctx_t *ctx;
 	int fence[count];
 
 	/*
@@ -608,10 +618,11 @@ static void timesliceN(int i915, unsigned int engine, int count)
 	/* No coupling between requests; free to timeslice */
 
 	for (int i = 0; i < count; i++) {
-		execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+		ctx = intel_ctx_create(i915, cfg);
+		execbuf.rsvd1 = ctx->id;
 		execbuf.batch_start_offset = (i + 1) * 1024;;
 		gem_execbuf_wr(i915, &execbuf);
-		gem_context_destroy(i915, execbuf.rsvd1);
+		intel_ctx_destroy(i915, ctx);
 
 		fence[i] = execbuf.rsvd2 >> 32;
 	}
@@ -629,31 +640,32 @@ static void timesliceN(int i915, unsigned int engine, int count)
 	munmap(result, sz);
 }
 
-static void lateslice(int i915, unsigned int engine, unsigned long flags)
+static void lateslice(int i915, const intel_ctx_cfg_t *cfg,
+		      unsigned int engine, unsigned long flags)
 {
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin[3];
-	uint32_t ctx;
 
 	igt_require(gem_scheduler_has_semaphores(i915));
 	igt_require(gem_scheduler_has_preemption(i915));
 	igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
-	ctx = gem_context_create(i915);
-	spin[0] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
+	ctx = intel_ctx_create(i915, cfg);
+	spin[0] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
 			       .flags = (IGT_SPIN_POLL_RUN |
 					 IGT_SPIN_FENCE_OUT |
 					 flags));
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_spin_busywait_until_started(spin[0]);
 
-	ctx = gem_context_create(i915);
-	spin[1] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
+	ctx = intel_ctx_create(i915, cfg);
+	spin[1] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
 			       .fence = spin[0]->out_fence,
 			       .flags = (IGT_SPIN_POLL_RUN |
 					 IGT_SPIN_FENCE_IN |
 					 flags));
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	usleep(5000); /* give some time for the new spinner to be scheduled */
 
@@ -664,10 +676,10 @@ static void lateslice(int i915, unsigned int engine, unsigned long flags)
 	 * third spinner we then expect timeslicing to be real enabled.
 	 */
 
-	ctx = gem_context_create(i915);
-	spin[2] = igt_spin_new(i915, .ctx_id = ctx, .engine = engine,
+	ctx = intel_ctx_create(i915, cfg);
+	spin[2] = igt_spin_new(i915, .ctx = ctx, .engine = engine,
 			       .flags = IGT_SPIN_POLL_RUN | flags);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_spin_busywait_until_started(spin[2]);
 
@@ -689,7 +701,7 @@ static void lateslice(int i915, unsigned int engine, unsigned long flags)
 }
 
 static void cancel_spinner(int i915,
-			   uint32_t ctx, unsigned int engine,
+			   const intel_ctx_t *ctx, unsigned int engine,
 			   igt_spin_t *spin)
 {
 	struct drm_i915_gem_exec_object2 obj = {
@@ -699,7 +711,7 @@ static void cancel_spinner(int i915,
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = engine | I915_EXEC_FENCE_SUBMIT,
-		.rsvd1 = ctx, /* same vm */
+		.rsvd1 = ctx->id, /* same vm */
 		.rsvd2 = spin->out_fence,
 	};
 	uint32_t *map, *cs;
@@ -720,21 +732,18 @@ static void cancel_spinner(int i915,
 	gem_close(i915, obj.handle);
 }
 
-static void submit_slice(int i915,
+static void submit_slice(int i915, const intel_ctx_cfg_t *cfg,
 			 const struct intel_execution_engine2 *e,
 			 unsigned int flags)
 #define EARLY_SUBMIT 0x1
 #define LATE_SUBMIT 0x2
 #define USERPTR 0x4
 {
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , 1) = {};
 	const struct intel_execution_engine2 *cancel;
-	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
+	intel_ctx_cfg_t engine_cfg = {
+		.num_engines = 1,
 	};
+	const intel_ctx_t *ctx;
 
 	/*
 	 * When using a submit fence, we do not want to block concurrent work,
@@ -745,7 +754,7 @@ static void submit_slice(int i915,
 	igt_require(gem_scheduler_has_preemption(i915));
 	igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
 
-	__for_each_physical_engine(i915, cancel) {
+	for_each_ctx_cfg_engine(i915, cfg, cancel) {
 		igt_spin_t *bg, *spin;
 		int timeline = -1;
 		int fence = -1;
@@ -762,10 +771,10 @@ static void submit_slice(int i915,
 			fence = sw_sync_timeline_create_fence(timeline, 1);
 		}
 
-		engines.engines[0].engine_class = e->class;
-		engines.engines[0].engine_instance = e->instance;
-		gem_context_set_param(i915, &param);
-		spin = igt_spin_new(i915, .ctx_id = param.ctx_id,
+		engine_cfg.engines[0].engine_class = e->class;
+		engine_cfg.engines[0].engine_instance = e->instance;
+		ctx = intel_ctx_create(i915, &engine_cfg);
+		spin = igt_spin_new(i915, .ctx = ctx,
 				    .fence = fence,
 				    .flags =
 				    IGT_SPIN_POLL_RUN |
@@ -778,10 +787,13 @@ static void submit_slice(int i915,
 		if (flags & EARLY_SUBMIT)
 			igt_spin_busywait_until_started(spin);
 
-		engines.engines[0].engine_class = cancel->class;
-		engines.engines[0].engine_instance = cancel->instance;
-		gem_context_set_param(i915, &param);
-		cancel_spinner(i915, param.ctx_id, 0, spin);
+		intel_ctx_destroy(i915, ctx);
+
+		engine_cfg.engines[0].engine_class = cancel->class;
+		engine_cfg.engines[0].engine_instance = cancel->instance;
+		ctx = intel_ctx_create(i915, &engine_cfg);
+
+		cancel_spinner(i915, ctx, 0, spin);
 
 		if (timeline != -1)
 			close(timeline);
@@ -789,9 +801,9 @@ static void submit_slice(int i915,
 		gem_sync(i915, spin->handle);
 		igt_spin_free(i915, spin);
 		igt_spin_free(i915, bg);
-	}
 
-	gem_context_destroy(i915, param.ctx_id);
+		intel_ctx_destroy(i915, ctx);
+	}
 }
 
 static uint32_t __batch_create(int i915, uint32_t offset)
@@ -810,7 +822,8 @@ static uint32_t batch_create(int i915)
 	return __batch_create(i915, 0);
 }
 
-static void semaphore_userlock(int i915, unsigned long flags)
+static void semaphore_userlock(int i915, const intel_ctx_t *ctx,
+			       unsigned long flags)
 {
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_exec_object2 obj = {
@@ -818,6 +831,7 @@ static void semaphore_userlock(int i915, unsigned long flags)
 	};
 	igt_spin_t *spin = NULL;
 	uint32_t scratch;
+	const intel_ctx_t *tmp_ctx;
 
 	igt_require(gem_scheduler_has_semaphores(i915));
 
@@ -829,9 +843,10 @@ static void semaphore_userlock(int i915, unsigned long flags)
 	 */
 
 	scratch = gem_create(i915, 4096);
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (!spin) {
 			spin = igt_spin_new(i915,
+					    .ctx = ctx,
 					    .dependency = scratch,
 					    .engine = e->flags,
 					    .flags = flags);
@@ -854,13 +869,13 @@ static void semaphore_userlock(int i915, unsigned long flags)
 	 * on a HW semaphore) but it should not prevent any real work from
 	 * taking precedence.
 	 */
-	scratch = gem_context_clone_with_engines(i915, 0);
-	__for_each_physical_engine(i915, e) {
+	tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
+	for_each_ctx_engine(i915, ctx, e) {
 		struct drm_i915_gem_execbuffer2 execbuf = {
 			.buffers_ptr = to_user_pointer(&obj),
 			.buffer_count = 1,
 			.flags = e->flags,
-			.rsvd1 = scratch,
+			.rsvd1 = tmp_ctx->id,
 		};
 
 		if (e->flags == (spin->execbuf.flags & I915_EXEC_RING_MASK))
@@ -868,14 +883,15 @@ static void semaphore_userlock(int i915, unsigned long flags)
 
 		gem_execbuf(i915, &execbuf);
 	}
-	gem_context_destroy(i915, scratch);
+	intel_ctx_destroy(i915, tmp_ctx);
 	gem_sync(i915, obj.handle); /* to hang unless we can preempt */
 	gem_close(i915, obj.handle);
 
 	igt_spin_free(i915, spin);
 }
 
-static void semaphore_codependency(int i915, unsigned long flags)
+static void semaphore_codependency(int i915, const intel_ctx_t *ctx,
+				   unsigned long flags)
 {
 	const struct intel_execution_engine2 *e;
 	struct {
@@ -894,8 +910,8 @@ static void semaphore_codependency(int i915, unsigned long flags)
 	 */
 
 	i = 0;
-	__for_each_physical_engine(i915, e) {
-		uint32_t ctx;
+	for_each_ctx_engine(i915, ctx, e) {
+		const intel_ctx_t *tmp_ctx;
 
 		if (!e->flags) {
 			igt_require(gem_class_can_store_dword(i915, e->class));
@@ -905,11 +921,11 @@ static void semaphore_codependency(int i915, unsigned long flags)
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
-		ctx = gem_context_clone_with_engines(i915, 0);
+		tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
 
 		task[i].xcs =
 			__igt_spin_new(i915,
-				       .ctx_id = ctx,
+				       .ctx = tmp_ctx,
 				       .engine = e->flags,
 				       .flags = IGT_SPIN_POLL_RUN | flags);
 		igt_spin_busywait_until_started(task[i].xcs);
@@ -917,11 +933,11 @@ static void semaphore_codependency(int i915, unsigned long flags)
 		/* Common rcs tasks will be queued in FIFO */
 		task[i].rcs =
 			__igt_spin_new(i915,
-				       .ctx_id = ctx,
+				       .ctx = tmp_ctx,
 				       .engine = 0,
 				       .dependency = task[i].xcs->handle);
 
-		gem_context_destroy(i915, ctx);
+		intel_ctx_destroy(i915, tmp_ctx);
 
 		if (++i == ARRAY_SIZE(task))
 			break;
@@ -944,11 +960,13 @@ static void semaphore_codependency(int i915, unsigned long flags)
 	}
 }
 
-static void semaphore_resolve(int i915, unsigned long flags)
+static void semaphore_resolve(int i915, const intel_ctx_cfg_t *cfg,
+			      unsigned long flags)
 {
 	const struct intel_execution_engine2 *e;
 	const uint32_t SEMAPHORE_ADDR = 64 << 10;
-	uint32_t semaphore, outer, inner, *sema;
+	uint32_t semaphore, *sema;
+	const intel_ctx_t *outer, *inner;
 
 	/*
 	 * Userspace may submit batches that wait upon unresolved
@@ -962,13 +980,13 @@ static void semaphore_resolve(int i915, unsigned long flags)
 	igt_require(gem_scheduler_has_preemption(i915));
 	igt_require(intel_get_drm_devid(i915) >= 8); /* for MI_SEMAPHORE_WAIT */
 
-	outer = gem_context_clone_with_engines(i915, 0);
-	inner = gem_context_clone_with_engines(i915, 0);
+	outer = intel_ctx_create(i915, cfg);
+	inner = intel_ctx_create(i915, cfg);
 
 	semaphore = gem_create(i915, 4096);
 	sema = gem_mmap__wc(i915, semaphore, 0, 4096, PROT_WRITE);
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		struct drm_i915_gem_exec_object2 obj[3];
 		struct drm_i915_gem_execbuffer2 eb;
 		uint32_t handle, cancel;
@@ -1023,7 +1041,7 @@ static void semaphore_resolve(int i915, unsigned long flags)
 		obj[2].handle = handle;
 		eb.buffer_count = 3;
 		eb.buffers_ptr = to_user_pointer(obj);
-		eb.rsvd1 = outer;
+		eb.rsvd1 = outer->id;
 		gem_execbuf(i915, &eb);
 
 		/* Then add the GPU hang intermediatory */
@@ -1054,7 +1072,7 @@ static void semaphore_resolve(int i915, unsigned long flags)
 		obj[0].flags = EXEC_OBJECT_PINNED;
 		obj[1].handle = cancel;
 		eb.buffer_count = 2;
-		eb.rsvd1 = inner;
+		eb.rsvd1 = inner->id;
 		gem_execbuf(i915, &eb);
 		gem_wait(i915, cancel, &poke); /* match sync's WAIT_PRIORITY */
 		gem_close(i915, cancel);
@@ -1069,22 +1087,23 @@ static void semaphore_resolve(int i915, unsigned long flags)
 	munmap(sema, 4096);
 	gem_close(i915, semaphore);
 
-	gem_context_destroy(i915, inner);
-	gem_context_destroy(i915, outer);
+	intel_ctx_destroy(i915, inner);
+	intel_ctx_destroy(i915, outer);
 }
 
-static void semaphore_noskip(int i915, unsigned long flags)
+static void semaphore_noskip(int i915, const intel_ctx_cfg_t *cfg,
+			     unsigned long flags)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	const struct intel_execution_engine2 *outer, *inner;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	igt_require(gen >= 6); /* MI_STORE_DWORD_IMM convenience */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
+	ctx = intel_ctx_create(i915, cfg);
 
-	__for_each_physical_engine(i915, outer) {
-	__for_each_physical_engine(i915, inner) {
+	for_each_ctx_engine(i915, ctx, outer) {
+	for_each_ctx_engine(i915, ctx, inner) {
 		struct drm_i915_gem_exec_object2 obj[3];
 		struct drm_i915_gem_execbuffer2 eb;
 		uint32_t handle, *cs, *map;
@@ -1094,9 +1113,11 @@ static void semaphore_noskip(int i915, unsigned long flags)
 		    !gem_class_can_store_dword(i915, inner->class))
 			continue;
 
-		chain = __igt_spin_new(i915, .engine = outer->flags, .flags = flags);
+		chain = __igt_spin_new(i915, .ctx = ctx,
+				       .engine = outer->flags, .flags = flags);
 
-		spin = __igt_spin_new(i915, .engine = inner->flags, .flags = flags);
+		spin = __igt_spin_new(i915, .ctx = ctx,
+				      .engine = inner->flags, .flags = flags);
 		igt_spin_end(spin); /* we just want its address for later */
 		gem_sync(i915, spin->handle);
 		igt_spin_reset(spin);
@@ -1129,7 +1150,7 @@ static void semaphore_noskip(int i915, unsigned long flags)
 		memset(&eb, 0, sizeof(eb));
 		eb.buffer_count = 3;
 		eb.buffers_ptr = to_user_pointer(obj);
-		eb.rsvd1 = ctx;
+		eb.rsvd1 = ctx->id;
 		eb.flags = inner->flags;
 		gem_execbuf(i915, &eb);
 
@@ -1153,11 +1174,12 @@ static void semaphore_noskip(int i915, unsigned long flags)
 	}
 	}
 
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 }
 
 static void
-noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
+noreorder(int i915, const intel_ctx_cfg_t *cfg,
+	  unsigned int engine, int prio, unsigned int flags)
 #define CORKED 0x1
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
@@ -1169,24 +1191,24 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = engine,
-		.rsvd1 = gem_context_clone_with_engines(i915, 0),
 	};
+	intel_ctx_cfg_t vm_cfg = *cfg;
+	const intel_ctx_t *ctx;
 	IGT_CORK_FENCE(cork);
 	uint32_t *map, *cs;
 	igt_spin_t *slice;
 	igt_spin_t *spin;
 	int fence = -1;
 	uint64_t addr;
-	uint32_t ctx;
 
 	if (flags & CORKED)
 		fence = igt_cork_plug(&cork, i915);
 
-	ctx = gem_context_clone(i915, execbuf.rsvd1,
-			      I915_CONTEXT_CLONE_ENGINES |
-			      I915_CONTEXT_CLONE_VM,
-			      0);
-	spin = igt_spin_new(i915, ctx,
+	vm_cfg.vm = gem_vm_create(i915);
+
+	ctx = intel_ctx_create(i915, &vm_cfg);
+
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .fence = fence,
 			    .flags = IGT_SPIN_FENCE_OUT | IGT_SPIN_FENCE_IN);
@@ -1195,7 +1217,7 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 	/* Loop around the engines, creating a chain of fences */
 	spin->execbuf.rsvd2 = (uint64_t)dup(spin->out_fence) << 32;
 	spin->execbuf.rsvd2 |= 0xffffffff;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (e->flags == engine)
 			continue;
 
@@ -1208,7 +1230,7 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 	}
 	close(spin->execbuf.rsvd2);
 	spin->execbuf.rsvd2 >>= 32;
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	/*
 	 * Wait upon the fence chain, and try to terminate the spinner.
@@ -1241,11 +1263,13 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 	execbuf.rsvd2 = spin->execbuf.rsvd2;
 	execbuf.flags |= I915_EXEC_FENCE_IN;
 
-	gem_context_set_priority(i915, execbuf.rsvd1, prio);
+	ctx = intel_ctx_create(i915, &vm_cfg);
+	gem_context_set_priority(i915, ctx->id, prio);
+	execbuf.rsvd1 = ctx->id;
 
 	gem_execbuf(i915, &execbuf);
 	gem_close(i915, obj.handle);
-	gem_context_destroy(i915, execbuf.rsvd1);
+	intel_ctx_destroy(i915, ctx);
 	if (cork.fd != -1)
 		igt_cork_unplug(&cork);
 
@@ -1258,7 +1282,9 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 	 *
 	 * Without timeslices, fallback to waiting a second.
 	 */
+	ctx = intel_ctx_create(i915, &vm_cfg);
 	slice = igt_spin_new(i915,
+			    .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_POLL_RUN);
 	igt_until_timeout(1) {
@@ -1266,6 +1292,7 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 			break;
 	}
 	igt_spin_free(i915, slice);
+	intel_ctx_destroy(i915, ctx);
 
 	/* Check the store did not run before the spinner */
 	igt_assert_eq(sync_fence_status(spin->out_fence), 0);
@@ -1273,20 +1300,21 @@ noreorder(int i915, unsigned int engine, int prio, unsigned int flags)
 	gem_quiescent_gpu(i915);
 }
 
-static void reorder(int fd, unsigned ring, unsigned flags)
+static void reorder(int fd, const intel_ctx_cfg_t *cfg,
+		    unsigned ring, unsigned flags)
 #define EQUAL 1
 {
 	IGT_CORK_FENCE(cork);
 	uint32_t scratch;
 	uint32_t result;
-	uint32_t ctx[2];
+	const intel_ctx_t *ctx[2];
 	int fence;
 
-	ctx[LO] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[HI], flags & EQUAL ? MIN_PRIO : 0);
+	ctx[HI] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[HI]->id, flags & EQUAL ? MIN_PRIO : 0);
 
 	scratch = gem_create(fd, 4096);
 	fence = igt_cork_plug(&cork, fd);
@@ -1294,40 +1322,40 @@ static void reorder(int fd, unsigned ring, unsigned flags)
 	/* We expect the high priority context to be executed first, and
 	 * so the final result will be value from the low priority context.
 	 */
-	store_dword_fenced(fd, ctx[LO], ring, scratch, 0, ctx[LO], fence, 0);
-	store_dword_fenced(fd, ctx[HI], ring, scratch, 0, ctx[HI], fence, 0);
+	store_dword_fenced(fd, ctx[LO], ring, scratch, 0, ctx[LO]->id, fence, 0);
+	store_dword_fenced(fd, ctx[HI], ring, scratch, 0, ctx[HI]->id, fence, 0);
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, cfg, ring);
 	close(fence);
 
-	gem_context_destroy(fd, ctx[LO]);
-	gem_context_destroy(fd, ctx[HI]);
-
 	result =  __sync_read_u32(fd, scratch, 0);
 	gem_close(fd, scratch);
 
 	if (flags & EQUAL) /* equal priority, result will be fifo */
-		igt_assert_eq_u32(result, ctx[HI]);
+		igt_assert_eq_u32(result, ctx[HI]->id);
 	else
-		igt_assert_eq_u32(result, ctx[LO]);
+		igt_assert_eq_u32(result, ctx[LO]->id);
+
+	intel_ctx_destroy(fd, ctx[LO]);
+	intel_ctx_destroy(fd, ctx[HI]);
 }
 
-static void promotion(int fd, unsigned ring)
+static void promotion(int fd, const intel_ctx_cfg_t *cfg, unsigned ring)
 {
 	IGT_CORK_FENCE(cork);
 	uint32_t result, dep;
 	uint32_t result_read, dep_read;
-	uint32_t ctx[3];
+	const intel_ctx_t *ctx[3];
 	int fence;
 
-	ctx[LO] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[HI], 0);
+	ctx[HI] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[HI]->id, 0);
 
-	ctx[NOISE] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[NOISE], MIN_PRIO/2);
+	ctx[NOISE] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[NOISE]->id, MIN_PRIO/2);
 
 	result = gem_create(fd, 4096);
 	dep = gem_create(fd, 4096);
@@ -1339,30 +1367,30 @@ static void promotion(int fd, unsigned ring)
 	 * fifo would be NOISE, LO, HI.
 	 * strict priority would be  HI, NOISE, LO
 	 */
-	store_dword_fenced(fd, ctx[NOISE], ring, result, 0, ctx[NOISE], fence, 0);
-	store_dword_fenced(fd, ctx[LO], ring, result, 0, ctx[LO], fence, 0);
+	store_dword_fenced(fd, ctx[NOISE], ring, result, 0, ctx[NOISE]->id, fence, 0);
+	store_dword_fenced(fd, ctx[LO], ring, result, 0, ctx[LO]->id, fence, 0);
 
 	/* link LO <-> HI via a dependency on another buffer */
-	store_dword(fd, ctx[LO], ring, dep, 0, ctx[LO], I915_GEM_DOMAIN_INSTRUCTION);
-	store_dword(fd, ctx[HI], ring, dep, 0, ctx[HI], 0);
+	store_dword(fd, ctx[LO], ring, dep, 0, ctx[LO]->id, I915_GEM_DOMAIN_INSTRUCTION);
+	store_dword(fd, ctx[HI], ring, dep, 0, ctx[HI]->id, 0);
 
-	store_dword(fd, ctx[HI], ring, result, 0, ctx[HI], 0);
+	store_dword(fd, ctx[HI], ring, result, 0, ctx[HI]->id, 0);
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, cfg, ring);
 	close(fence);
 
-	gem_context_destroy(fd, ctx[NOISE]);
-	gem_context_destroy(fd, ctx[LO]);
-	gem_context_destroy(fd, ctx[HI]);
-
 	dep_read = __sync_read_u32(fd, dep, 0);
 	gem_close(fd, dep);
 
 	result_read = __sync_read_u32(fd, result, 0);
 	gem_close(fd, result);
 
-	igt_assert_eq_u32(dep_read, ctx[HI]);
-	igt_assert_eq_u32(result_read, ctx[NOISE]);
+	igt_assert_eq_u32(dep_read, ctx[HI]->id);
+	igt_assert_eq_u32(result_read, ctx[NOISE]->id);
+
+	intel_ctx_destroy(fd, ctx[NOISE]);
+	intel_ctx_destroy(fd, ctx[LO]);
+	intel_ctx_destroy(fd, ctx[HI]);
 }
 
 static bool set_preempt_timeout(int i915,
@@ -1376,34 +1404,35 @@ static bool set_preempt_timeout(int i915,
 
 #define NEW_CTX (0x1 << 0)
 #define HANG_LP (0x1 << 1)
-static void preempt(int fd, const struct intel_execution_engine2 *e, unsigned flags)
+static void preempt(int fd, const intel_ctx_cfg_t *cfg,
+		    const struct intel_execution_engine2 *e, unsigned flags)
 {
 	uint32_t result = gem_create(fd, 4096);
 	uint32_t result_read;
 	igt_spin_t *spin[MAX_ELSP_QLEN];
-	uint32_t ctx[2];
+	const intel_ctx_t *ctx[2];
 	igt_hang_t hang;
 
 	/* Set a fast timeout to speed the test up (if available) */
 	set_preempt_timeout(fd, e, 150);
 
-	ctx[LO] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+	ctx[HI] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
 
 	if (flags & HANG_LP)
-		hang = igt_hang_ctx(fd, ctx[LO], e->flags, 0);
+		hang = igt_hang_ctx(fd, ctx[LO]->id, e->flags, 0);
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
 		if (flags & NEW_CTX) {
-			gem_context_destroy(fd, ctx[LO]);
-			ctx[LO] = gem_context_clone_with_engines(fd, 0);
-			gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+			intel_ctx_destroy(fd, ctx[LO]);
+			ctx[LO] = intel_ctx_create(fd, cfg);
+			gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 		}
 		spin[n] = __igt_spin_new(fd,
-					 .ctx_id = ctx[LO],
+					 .ctx = ctx[LO],
 					 .engine = e->flags,
 					 .flags = flags & USERPTR ? IGT_SPIN_USERPTR : 0);
 		igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle);
@@ -1421,8 +1450,8 @@ static void preempt(int fd, const struct intel_execution_engine2 *e, unsigned fl
 	if (flags & HANG_LP)
 		igt_post_hang_ring(fd, hang);
 
-	gem_context_destroy(fd, ctx[LO]);
-	gem_context_destroy(fd, ctx[HI]);
+	intel_ctx_destroy(fd, ctx[LO]);
+	intel_ctx_destroy(fd, ctx[HI]);
 
 	gem_close(fd, result);
 }
@@ -1430,22 +1459,23 @@ static void preempt(int fd, const struct intel_execution_engine2 *e, unsigned fl
 #define CHAIN 0x1
 #define CONTEXTS 0x2
 
-static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
+static igt_spin_t *__noise(int fd, const intel_ctx_t *ctx,
+			   int prio, igt_spin_t *spin)
 {
 	const struct intel_execution_engine2 *e;
 
-	gem_context_set_priority(fd, ctx, prio);
+	gem_context_set_priority(fd, ctx->id, prio);
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		if (spin == NULL) {
 			spin = __igt_spin_new(fd,
-					      .ctx_id = ctx,
+					      .ctx = ctx,
 					      .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 eb = {
 				.buffer_count = 1,
 				.buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
-				.rsvd1 = ctx,
+				.rsvd1 = ctx->id,
 				.flags = e->flags,
 			};
 			gem_execbuf(fd, &eb);
@@ -1456,7 +1486,7 @@ static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
 }
 
 static void __preempt_other(int fd,
-			    uint32_t *ctx,
+			    const intel_ctx_t **ctx,
 			    unsigned int target, unsigned int primary,
 			    unsigned flags)
 {
@@ -1472,7 +1502,7 @@ static void __preempt_other(int fd,
 	n++;
 
 	if (flags & CHAIN) {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx[LO], e) {
 			store_dword(fd, ctx[LO], e->flags,
 				    result, (n + 1)*sizeof(uint32_t), n + 1,
 				    I915_GEM_DOMAIN_RENDER);
@@ -1496,11 +1526,12 @@ static void __preempt_other(int fd,
 	gem_close(fd, result);
 }
 
-static void preempt_other(int fd, unsigned ring, unsigned int flags)
+static void preempt_other(int fd, const intel_ctx_cfg_t *cfg,
+			  unsigned ring, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e;
 	igt_spin_t *spin = NULL;
-	uint32_t ctx[3];
+	const intel_ctx_t *ctx[3];
 
 	/* On each engine, insert
 	 * [NOISE] spinner,
@@ -1512,16 +1543,16 @@ static void preempt_other(int fd, unsigned ring, unsigned int flags)
 	 * can cross engines.
 	 */
 
-	ctx[LO] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 
-	ctx[NOISE] = gem_context_clone_with_engines(fd, 0);
+	ctx[NOISE] = intel_ctx_create(fd, cfg);
 	spin = __noise(fd, ctx[NOISE], 0, NULL);
 
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+	ctx[HI] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_cfg_engine(fd, cfg, e) {
 		igt_debug("Primary engine: %s\n", e->name);
 		__preempt_other(fd, ctx, ring, e->flags, flags);
 
@@ -1530,12 +1561,12 @@ static void preempt_other(int fd, unsigned ring, unsigned int flags)
 	igt_assert(gem_bo_busy(fd, spin->handle));
 	igt_spin_free(fd, spin);
 
-	gem_context_destroy(fd, ctx[LO]);
-	gem_context_destroy(fd, ctx[NOISE]);
-	gem_context_destroy(fd, ctx[HI]);
+	intel_ctx_destroy(fd, ctx[LO]);
+	intel_ctx_destroy(fd, ctx[NOISE]);
+	intel_ctx_destroy(fd, ctx[HI]);
 }
 
-static void __preempt_queue(int fd,
+static void __preempt_queue(int fd, const intel_ctx_cfg_t *cfg,
 			    unsigned target, unsigned primary,
 			    unsigned depth, unsigned flags)
 {
@@ -1543,33 +1574,33 @@ static void __preempt_queue(int fd,
 	uint32_t result = gem_create(fd, 4096);
 	uint32_t result_read[4096 / sizeof(uint32_t)];
 	igt_spin_t *above = NULL, *below = NULL;
-	uint32_t ctx[3] = {
-		gem_context_clone_with_engines(fd, 0),
-		gem_context_clone_with_engines(fd, 0),
-		gem_context_clone_with_engines(fd, 0),
+	const intel_ctx_t *ctx[3] = {
+		intel_ctx_create(fd, cfg),
+		intel_ctx_create(fd, cfg),
+		intel_ctx_create(fd, cfg),
 	};
 	int prio = MAX_PRIO;
 	unsigned int n, i;
 
 	for (n = 0; n < depth; n++) {
 		if (flags & CONTEXTS) {
-			gem_context_destroy(fd, ctx[NOISE]);
-			ctx[NOISE] = gem_context_clone_with_engines(fd, 0);
+			intel_ctx_destroy(fd, ctx[NOISE]);
+			ctx[NOISE] = intel_ctx_create(fd, cfg);
 		}
 		above = __noise(fd, ctx[NOISE], prio--, above);
 	}
 
-	gem_context_set_priority(fd, ctx[HI], prio--);
+	gem_context_set_priority(fd, ctx[HI]->id, prio--);
 
 	for (; n < MAX_ELSP_QLEN; n++) {
 		if (flags & CONTEXTS) {
-			gem_context_destroy(fd, ctx[NOISE]);
-			ctx[NOISE] = gem_context_clone_with_engines(fd, 0);
+			intel_ctx_destroy(fd, ctx[NOISE]);
+			ctx[NOISE] = intel_ctx_create(fd, cfg);
 		}
 		below = __noise(fd, ctx[NOISE], prio--, below);
 	}
 
-	gem_context_set_priority(fd, ctx[LO], prio--);
+	gem_context_set_priority(fd, ctx[LO]->id, prio--);
 
 	n = 0;
 	store_dword(fd, ctx[LO], primary,
@@ -1578,7 +1609,7 @@ static void __preempt_queue(int fd,
 	n++;
 
 	if (flags & CHAIN) {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx[LO], e) {
 			store_dword(fd, ctx[LO], e->flags,
 				    result, (n + 1)*sizeof(uint32_t), n + 1,
 				    I915_GEM_DOMAIN_RENDER);
@@ -1610,25 +1641,26 @@ static void __preempt_queue(int fd,
 		igt_spin_free(fd, below);
 	}
 
-	gem_context_destroy(fd, ctx[LO]);
-	gem_context_destroy(fd, ctx[NOISE]);
-	gem_context_destroy(fd, ctx[HI]);
+	intel_ctx_destroy(fd, ctx[LO]);
+	intel_ctx_destroy(fd, ctx[NOISE]);
+	intel_ctx_destroy(fd, ctx[HI]);
 
 	gem_close(fd, result);
 }
 
-static void preempt_queue(int fd, unsigned ring, unsigned int flags)
+static void preempt_queue(int fd, const intel_ctx_cfg_t *cfg,
+			  unsigned ring, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e;
 
 	for (unsigned depth = 1; depth <= MAX_ELSP_QLEN; depth *= 4)
-		__preempt_queue(fd, ring, ring, depth, flags);
+		__preempt_queue(fd, cfg, ring, ring, depth, flags);
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_cfg_engine(fd, cfg, e) {
 		if (ring == e->flags)
 			continue;
 
-		__preempt_queue(fd, ring, e->flags, MAX_ELSP_QLEN, flags);
+		__preempt_queue(fd, cfg, ring, e->flags, MAX_ELSP_QLEN, flags);
 	}
 }
 
@@ -1645,19 +1677,16 @@ static void preempt_engines(int i915,
 			    const struct intel_execution_engine2 *e,
 			    unsigned int flags)
 {
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , I915_EXEC_RING_MASK + 1);
-	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
-	};
 	struct pnode {
 		struct igt_list_head spinners;
 		struct igt_list_head link;
-	} pnode[I915_EXEC_RING_MASK + 1], *p;
+	} pnode[GEM_MAX_ENGINES], *p;
+	struct intel_ctx_cfg cfg = {
+		.num_engines = GEM_MAX_ENGINES,
+	};
 	IGT_LIST_HEAD(plist);
 	igt_spin_t *spin, *sn;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * A quick test that each engine within a context is an independent
@@ -1666,19 +1695,19 @@ static void preempt_engines(int i915,
 
 	igt_require(has_context_engines(i915));
 
-	for (int n = 0; n <= I915_EXEC_RING_MASK; n++) {
-		engines.engines[n].engine_class = e->class;
-		engines.engines[n].engine_instance = e->instance;
+	for (int n = 0; n < GEM_MAX_ENGINES; n++) {
+		cfg.engines[n].engine_class = e->class;
+		cfg.engines[n].engine_instance = e->instance;
 		IGT_INIT_LIST_HEAD(&pnode[n].spinners);
 		igt_list_add(&pnode[n].link, &plist);
 	}
-	gem_context_set_param(i915, &param);
+	ctx = intel_ctx_create(i915, &cfg);
 
-	for (int n = -I915_EXEC_RING_MASK; n <= I915_EXEC_RING_MASK; n++) {
+	for (int n = -(GEM_MAX_ENGINES - 1); n < GEM_MAX_ENGINES; n++) {
 		unsigned int engine = n & I915_EXEC_RING_MASK;
 
-		gem_context_set_priority(i915, param.ctx_id, n);
-		spin = igt_spin_new(i915, param.ctx_id, .engine = engine);
+		gem_context_set_priority(i915, ctx->id, n);
+		spin = igt_spin_new(i915, .ctx = ctx, .engine = engine);
 
 		igt_list_move_tail(&spin->link, &pnode[engine].spinners);
 		igt_list_move(&pnode[engine].link, &plist);
@@ -1691,17 +1720,18 @@ static void preempt_engines(int i915,
 			igt_spin_free(i915, spin);
 		}
 	}
-	gem_context_destroy(i915, param.ctx_id);
+	intel_ctx_destroy(i915, ctx);
 }
 
-static void preempt_self(int fd, unsigned ring)
+static void preempt_self(int fd, const intel_ctx_cfg_t *cfg,
+			 unsigned ring)
 {
 	const struct intel_execution_engine2 *e;
 	uint32_t result = gem_create(fd, 4096);
 	uint32_t result_read[4096 / sizeof(uint32_t)];
 	igt_spin_t *spin[MAX_ELSP_QLEN];
 	unsigned int n, i;
-	uint32_t ctx[3];
+	const intel_ctx_t *ctx[3];
 
 	/* On each engine, insert
 	 * [NOISE] spinner,
@@ -1711,21 +1741,21 @@ static void preempt_self(int fd, unsigned ring)
 	 * preempt its own lower priority task on any engine.
 	 */
 
-	ctx[NOISE] = gem_context_clone_with_engines(fd, 0);
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
+	ctx[NOISE] = intel_ctx_create(fd, cfg);
+	ctx[HI] = intel_ctx_create(fd, cfg);
 
 	n = 0;
-	gem_context_set_priority(fd, ctx[HI], MIN_PRIO);
-	__for_each_physical_engine(fd, e) {
+	gem_context_set_priority(fd, ctx[HI]->id, MIN_PRIO);
+	for_each_ctx_cfg_engine(fd, cfg, e) {
 		spin[n] = __igt_spin_new(fd,
-					 .ctx_id = ctx[NOISE],
+					 .ctx = ctx[NOISE],
 					 .engine = e->flags);
 		store_dword(fd, ctx[HI], e->flags,
 			    result, (n + 1)*sizeof(uint32_t), n + 1,
 			    I915_GEM_DOMAIN_RENDER);
 		n++;
 	}
-	gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+	gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
 	store_dword(fd, ctx[HI], ring,
 		    result, (n + 1)*sizeof(uint32_t), n + 1,
 		    I915_GEM_DOMAIN_RENDER);
@@ -1743,36 +1773,37 @@ static void preempt_self(int fd, unsigned ring)
 	for (i = 0; i <= n; i++)
 		igt_assert_eq_u32(result_read[i], i);
 
-	gem_context_destroy(fd, ctx[NOISE]);
-	gem_context_destroy(fd, ctx[HI]);
+	intel_ctx_destroy(fd, ctx[NOISE]);
+	intel_ctx_destroy(fd, ctx[HI]);
 
 	gem_close(fd, result);
 }
 
-static void preemptive_hang(int fd, const struct intel_execution_engine2 *e)
+static void preemptive_hang(int fd, const intel_ctx_cfg_t *cfg,
+			    const struct intel_execution_engine2 *e)
 {
 	igt_spin_t *spin[MAX_ELSP_QLEN];
 	igt_hang_t hang;
-	uint32_t ctx[2];
+	const intel_ctx_t *ctx[2];
 
 	/* Set a fast timeout to speed the test up (if available) */
 	set_preempt_timeout(fd, e, 150);
 
-	ctx[HI] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+	ctx[HI] = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx[HI]->id, MAX_PRIO);
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
-		ctx[LO] = gem_context_clone_with_engines(fd, 0);
-		gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
+		ctx[LO] = intel_ctx_create(fd, cfg);
+		gem_context_set_priority(fd, ctx[LO]->id, MIN_PRIO);
 
 		spin[n] = __igt_spin_new(fd,
-					 .ctx_id = ctx[LO],
+					 .ctx = ctx[LO],
 					 .engine = e->flags);
 
-		gem_context_destroy(fd, ctx[LO]);
+		intel_ctx_destroy(fd, ctx[LO]);
 	}
 
-	hang = igt_hang_ctx(fd, ctx[HI], e->flags, 0);
+	hang = igt_hang_ctx(fd, ctx[HI]->id, e->flags, 0);
 	igt_post_hang_ring(fd, hang);
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
@@ -1784,10 +1815,11 @@ static void preemptive_hang(int fd, const struct intel_execution_engine2 *e)
 		igt_spin_free(fd, spin[n]);
 	}
 
-	gem_context_destroy(fd, ctx[HI]);
+	intel_ctx_destroy(fd, ctx[HI]);
 }
 
-static void deep(int fd, unsigned ring)
+static void deep(int fd, const intel_ctx_cfg_t *cfg,
+		 unsigned ring)
 {
 #define XS 8
 	const unsigned int max_req = MAX_PRIO - MIN_PRIO;
@@ -1799,13 +1831,13 @@ static void deep(int fd, unsigned ring)
 	uint32_t result, dep[XS];
 	uint32_t read_buf[size / sizeof(uint32_t)];
 	uint32_t expected = 0;
-	uint32_t *ctx;
+	const intel_ctx_t **ctx;
 	int dep_nreq;
 	int n;
 
 	ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
 	for (n = 0; n < MAX_CONTEXTS; n++) {
-		ctx[n] = gem_context_clone_with_engines(fd, 0);
+		ctx[n] = intel_ctx_create(fd, cfg);
 	}
 
 	nreq = gem_submission_measure(fd, ring) / (3 * XS) * MAX_CONTEXTS;
@@ -1835,7 +1867,7 @@ static void deep(int fd, unsigned ring)
 		execbuf.buffer_count = XS + 2;
 		execbuf.flags = ring;
 		for (n = 0; n < MAX_CONTEXTS; n++) {
-			execbuf.rsvd1 = ctx[n];
+			execbuf.rsvd1 = ctx[n]->id;
 			gem_execbuf(fd, &execbuf);
 		}
 		gem_close(fd, obj[XS+1].handle);
@@ -1853,7 +1885,7 @@ static void deep(int fd, unsigned ring)
 			.buffers_ptr = to_user_pointer(obj),
 			.buffer_count = 3,
 			.flags = ring | (gen < 6 ? I915_EXEC_SECURE : 0),
-			.rsvd1 = ctx[n % MAX_CONTEXTS],
+			.rsvd1 = ctx[n % MAX_CONTEXTS]->id,
 		};
 		uint32_t batch[16];
 		int i;
@@ -1901,33 +1933,33 @@ static void deep(int fd, unsigned ring)
 	dep_nreq = n;
 
 	for (n = 0; n < nreq && igt_seconds_elapsed(&tv) < 4; n++) {
-		uint32_t context = ctx[n % MAX_CONTEXTS];
-		gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+		const intel_ctx_t *context = ctx[n % MAX_CONTEXTS];
+		gem_context_set_priority(fd, context->id, MAX_PRIO - nreq + n);
 
+		expected = context->id;
 		for (int m = 0; m < XS; m++) {
-			store_dword_plug(fd, context, ring, result, 4*n, context, dep[m], 0);
-			store_dword(fd, context, ring, result, 4*m, context, I915_GEM_DOMAIN_INSTRUCTION);
+			store_dword_plug(fd, context, ring, result, 4*n, expected, dep[m], 0);
+			store_dword(fd, context, ring, result, 4*m, expected, I915_GEM_DOMAIN_INSTRUCTION);
 		}
-		expected = context;
 	}
 	igt_info("Second deptree: %d requests [%.3fs]\n",
 		 n * XS, 1e-9*igt_nsec_elapsed(&tv));
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, cfg, ring);
 	gem_close(fd, plug);
 	igt_require(expected); /* too slow */
 
-	for (n = 0; n < MAX_CONTEXTS; n++)
-		gem_context_destroy(fd, ctx[n]);
-
 	for (int m = 0; m < XS; m++) {
 		__sync_read_u32_count(fd, dep[m], read_buf, sizeof(read_buf));
 		gem_close(fd, dep[m]);
 
 		for (n = 0; n < dep_nreq; n++)
-			igt_assert_eq_u32(read_buf[n], ctx[n % MAX_CONTEXTS]);
+			igt_assert_eq_u32(read_buf[n], ctx[n % MAX_CONTEXTS]->id);
 	}
 
+	for (n = 0; n < MAX_CONTEXTS; n++)
+		intel_ctx_destroy(fd, ctx[n]);
+
 	__sync_read_u32_count(fd, result, read_buf, sizeof(read_buf));
 	gem_close(fd, result);
 
@@ -1951,20 +1983,20 @@ static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
 	return err;
 }
 
-static void wide(int fd, unsigned ring)
+static void wide(int fd, const intel_ctx_cfg_t *cfg, unsigned ring)
 {
 	const unsigned int ring_size = gem_submission_measure(fd, ring);
 	struct timespec tv = {};
 	IGT_CORK_FENCE(cork);
 	uint32_t result;
 	uint32_t result_read[MAX_CONTEXTS];
-	uint32_t *ctx;
+	const intel_ctx_t **ctx;
 	unsigned int count;
 	int fence;
 
 	ctx = malloc(sizeof(*ctx)*MAX_CONTEXTS);
 	for (int n = 0; n < MAX_CONTEXTS; n++)
-		ctx[n] = gem_context_clone_with_engines(fd, 0);
+		ctx[n] = intel_ctx_create(fd, cfg);
 
 	result = gem_create(fd, 4*MAX_CONTEXTS);
 
@@ -1975,28 +2007,28 @@ static void wide(int fd, unsigned ring)
 	     igt_seconds_elapsed(&tv) < 5 && count < ring_size;
 	     count++) {
 		for (int n = 0; n < MAX_CONTEXTS; n++) {
-			store_dword_fenced(fd, ctx[n], ring, result, 4*n, ctx[n],
+			store_dword_fenced(fd, ctx[n], ring, result, 4*n, ctx[n]->id,
 					   fence, I915_GEM_DOMAIN_INSTRUCTION);
 		}
 	}
 	igt_info("Submitted %d requests over %d contexts in %.1fms\n",
 		 count, MAX_CONTEXTS, igt_nsec_elapsed(&tv) * 1e-6);
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, cfg, ring);
 	close(fence);
 
+	__sync_read_u32_count(fd, result, result_read, sizeof(result_read));
 	for (int n = 0; n < MAX_CONTEXTS; n++)
-		gem_context_destroy(fd, ctx[n]);
+		igt_assert_eq_u32(result_read[n], ctx[n]->id);
 
-	__sync_read_u32_count(fd, result, result_read, sizeof(result_read));
 	for (int n = 0; n < MAX_CONTEXTS; n++)
-		igt_assert_eq_u32(result_read[n], ctx[n]);
+		intel_ctx_destroy(fd, ctx[n]);
 
 	gem_close(fd, result);
 	free(ctx);
 }
 
-static void reorder_wide(int fd, unsigned ring)
+static void reorder_wide(int fd, const intel_ctx_cfg_t *cfg, unsigned ring)
 {
 	const unsigned int ring_size = gem_submission_measure(fd, ring);
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -2040,9 +2072,11 @@ static void reorder_wide(int fd, unsigned ring)
 	for (int n = 0, x = 1; n < ARRAY_SIZE(priorities); n++, x++) {
 		unsigned int sz = ALIGN(ring_size * 64, 4096);
 		uint32_t *batch;
+		const intel_ctx_t *tmp_ctx;
 
-		execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
-		gem_context_set_priority(fd, execbuf.rsvd1, priorities[n]);
+		tmp_ctx = intel_ctx_create(fd, cfg);
+		gem_context_set_priority(fd, tmp_ctx->id, priorities[n]);
+		execbuf.rsvd1 = tmp_ctx->id;
 
 		obj[1].handle = gem_create(fd, sz);
 		batch = gem_mmap__device_coherent(fd, obj[1].handle, 0, sz, PROT_WRITE);
@@ -2082,10 +2116,10 @@ static void reorder_wide(int fd, unsigned ring)
 
 		munmap(batch, sz);
 		gem_close(fd, obj[1].handle);
-		gem_context_destroy(fd, execbuf.rsvd1);
+		intel_ctx_destroy(fd, tmp_ctx);
 	}
 
-	unplug_show_queue(fd, &cork, ring);
+	unplug_show_queue(fd, &cork, cfg, ring);
 	close(fence);
 
 	__sync_read_u32_count(fd, result, result_read, sizeof(result_read));
@@ -2111,17 +2145,18 @@ static void bind_to_cpu(int cpu)
 	igt_assert(sched_setaffinity(getpid(), sizeof(cpu_set_t), &allowed) == 0);
 }
 
-static void test_pi_ringfull(int fd, unsigned int engine, unsigned int flags)
+static void test_pi_ringfull(int fd, const intel_ctx_cfg_t *cfg,
+			     unsigned int engine, unsigned int flags)
 #define SHARED BIT(0)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct sigaction sa = { .sa_handler = alarm_handler };
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj[2];
+	const intel_ctx_t *ctx, *vip;
 	unsigned int last, count;
 	struct itimerval itv;
 	IGT_CORK_HANDLE(c);
-	uint32_t vip;
 	bool *result;
 
 	/*
@@ -2153,17 +2188,18 @@ static void test_pi_ringfull(int fd, unsigned int engine, unsigned int flags)
 
 	execbuf.buffers_ptr = to_user_pointer(&obj[1]);
 	execbuf.buffer_count = 1;
-	execbuf.flags = engine;
 
 	/* Warm up both (hi/lo) contexts */
-	execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, execbuf.rsvd1, MAX_PRIO);
+	ctx = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx->id, MAX_PRIO);
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_sync(fd, obj[1].handle);
-	vip = execbuf.rsvd1;
+	vip = ctx;
 
-	execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, execbuf.rsvd1, MIN_PRIO);
+	ctx = intel_ctx_create(fd, cfg);
+	gem_context_set_priority(fd, ctx->id, MIN_PRIO);
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_sync(fd, obj[1].handle);
 
@@ -2213,7 +2249,7 @@ static void test_pi_ringfull(int fd, unsigned int engine, unsigned int flags)
 			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
 		}
 
-		result[0] = vip != execbuf.rsvd1;
+		result[0] = vip->id != execbuf.rsvd1;
 
 		igt_debug("Waking parent\n");
 		kill(getppid(), SIGALRM);
@@ -2230,7 +2266,7 @@ static void test_pi_ringfull(int fd, unsigned int engine, unsigned int flags)
 		 * able to add ourselves to *our* ring without interruption.
 		 */
 		igt_debug("HP child executing\n");
-		execbuf.rsvd1 = vip;
+		execbuf.rsvd1 = vip->id;
 		err = __execbuf(fd, &execbuf);
 		igt_debug("HP execbuf returned %d\n", err);
 
@@ -2261,8 +2297,8 @@ static void test_pi_ringfull(int fd, unsigned int engine, unsigned int flags)
 	igt_cork_unplug(&c);
 	igt_waitchildren();
 
-	gem_context_destroy(fd, execbuf.rsvd1);
-	gem_context_destroy(fd, vip);
+	intel_ctx_destroy(fd, ctx);
+	intel_ctx_destroy(fd, vip);
 	gem_close(fd, obj[1].handle);
 	gem_close(fd, obj[0].handle);
 	munmap(result, 4096);
@@ -2277,8 +2313,8 @@ struct ufd_thread {
 	uint32_t batch;
 	uint32_t scratch;
 	uint32_t *page;
+	const intel_ctx_cfg_t *cfg;
 	unsigned int engine;
-	unsigned int flags;
 	int i915;
 
 	pthread_mutex_t mutex;
@@ -2301,11 +2337,12 @@ static void *ufd_thread(void *arg)
 		{ .handle = create_userptr(t->i915, t->page) },
 		{ .handle = t->batch },
 	};
+	const intel_ctx_t *ctx = intel_ctx_create(t->i915, t->cfg);
 	struct drm_i915_gem_execbuffer2 eb = {
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = t->engine,
-		.rsvd1 = gem_context_clone_with_engines(t->i915, 0),
+		.rsvd1 = ctx->id,
 	};
 	gem_context_set_priority(t->i915, eb.rsvd1, MIN_PRIO);
 
@@ -2314,13 +2351,15 @@ static void *ufd_thread(void *arg)
 	gem_sync(t->i915, obj[0].handle);
 	gem_close(t->i915, obj[0].handle);
 
-	gem_context_destroy(t->i915, eb.rsvd1);
+	intel_ctx_destroy(t->i915, ctx);
 
 	t->i915 = -1;
 	return NULL;
 }
 
-static void test_pi_userfault(int i915, unsigned int engine)
+static void test_pi_userfault(int i915,
+			      const intel_ctx_cfg_t *cfg,
+			      unsigned int engine)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct uffdio_api api = { .api = UFFD_API };
@@ -2353,6 +2392,7 @@ static void test_pi_userfault(int i915, unsigned int engine)
 		      "userfaultfd API v%lld:%lld\n", UFFD_API, api.api);
 
 	t.i915 = i915;
+	t.cfg = cfg;
 	t.engine = engine;
 
 	t.page = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, 0, 0);
@@ -2383,11 +2423,12 @@ static void test_pi_userfault(int i915, unsigned int engine)
 			.handle = gem_create(i915, 4096),
 		};
 		struct pollfd pfd;
+		const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
 		struct drm_i915_gem_execbuffer2 eb = {
 			.buffers_ptr = to_user_pointer(&obj),
 			.buffer_count = 1,
 			.flags = engine | I915_EXEC_FENCE_OUT,
-			.rsvd1 = gem_context_clone_with_engines(i915, 0),
+			.rsvd1 = ctx->id,
 		};
 		gem_context_set_priority(i915, eb.rsvd1, MAX_PRIO);
 		gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
@@ -2401,7 +2442,7 @@ static void test_pi_userfault(int i915, unsigned int engine)
 		igt_assert_eq(sync_fence_status(pfd.fd), 1);
 		close(pfd.fd);
 
-		gem_context_destroy(i915, eb.rsvd1);
+		intel_ctx_destroy(i915, ctx);
 	}
 
 	/* Confirm the low priority context is still waiting */
@@ -2425,15 +2466,10 @@ static void test_pi_userfault(int i915, unsigned int engine)
 
 static void *iova_thread(struct ufd_thread *t, int prio)
 {
-	unsigned int clone;
-	uint32_t ctx;
-
-	clone = I915_CONTEXT_CLONE_ENGINES;
-	if (t->flags & SHARED)
-		clone |= I915_CONTEXT_CLONE_VM;
+	const intel_ctx_t *ctx;
 
-	ctx = gem_context_clone(t->i915, 0, clone, 0);
-	gem_context_set_priority(t->i915, ctx, prio);
+	ctx = intel_ctx_create(t->i915, t->cfg);
+	gem_context_set_priority(t->i915, ctx->id, prio);
 
 	store_dword_plug(t->i915, ctx, t->engine,
 			 t->scratch, 0, prio,
@@ -2444,7 +2480,7 @@ static void *iova_thread(struct ufd_thread *t, int prio)
 		pthread_cond_signal(&t->cond);
 	pthread_mutex_unlock(&t->mutex);
 
-	gem_context_destroy(t->i915, ctx);
+	intel_ctx_destroy(t->i915, ctx);
 	return NULL;
 }
 
@@ -2458,8 +2494,10 @@ static void *iova_high(void *arg)
 	return iova_thread(arg, MAX_PRIO);
 }
 
-static void test_pi_iova(int i915, unsigned int engine, unsigned int flags)
+static void test_pi_iova(int i915, const intel_ctx_cfg_t *cfg,
+			 unsigned int engine, unsigned int flags)
 {
+	intel_ctx_cfg_t ufd_cfg = *cfg;
 	struct uffdio_api api = { .api = UFFD_API };
 	struct uffdio_register reg;
 	struct uffdio_copy copy;
@@ -2493,9 +2531,12 @@ static void test_pi_iova(int i915, unsigned int engine, unsigned int flags)
 	igt_require_f(ioctl(ufd, UFFDIO_API, &api) == 0 && api.api == UFFD_API,
 		      "userfaultfd API v%lld:%lld\n", UFFD_API, api.api);
 
+	if (flags & SHARED)
+		ufd_cfg.vm = gem_vm_create(i915);
+
 	t.i915 = i915;
+	t.cfg = &ufd_cfg;
 	t.engine = engine;
-	t.flags = flags;
 
 	t.count = 2;
 	pthread_cond_init(&t.cond, NULL);
@@ -2534,9 +2575,10 @@ static void test_pi_iova(int i915, unsigned int engine, unsigned int flags)
 	 */
 	spin = igt_spin_new(i915, .engine = engine);
 	for (int i = 0; i < MAX_ELSP_QLEN; i++) {
-		spin->execbuf.rsvd1 = create_highest_priority(i915);
+		const intel_ctx_t *ctx = create_highest_priority(i915, cfg);
+		spin->execbuf.rsvd1 = ctx->id;
 		gem_execbuf(i915, &spin->execbuf);
-		gem_context_destroy(i915, spin->execbuf.rsvd1);
+		intel_ctx_destroy(i915, ctx);
 	}
 
 	/* Kick off the submission threads */
@@ -2573,10 +2615,14 @@ static void test_pi_iova(int i915, unsigned int engine, unsigned int flags)
 	gem_close(i915, t.scratch);
 
 	munmap(t.page, 4096);
+
+	if (flags & SHARED)
+		gem_vm_destroy(i915, ufd_cfg.vm);
+
 	close(ufd);
 }
 
-static void measure_semaphore_power(int i915)
+static void measure_semaphore_power(int i915, const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *signaler, *e;
 	struct rapl gpu, pkg;
@@ -2584,7 +2630,7 @@ static void measure_semaphore_power(int i915)
 	igt_require(gpu_power_open(&gpu) == 0);
 	pkg_power_open(&pkg);
 
-	__for_each_physical_engine(i915, signaler) {
+	for_each_ctx_engine(i915, ctx, signaler) {
 		struct {
 			struct power_sample pkg, gpu;
 		} s_spin[2], s_sema[2];
@@ -2596,6 +2642,7 @@ static void measure_semaphore_power(int i915)
 			continue;
 
 		spin = __igt_spin_new(i915,
+				      .ctx = ctx,
 				      .engine = signaler->flags,
 				      .flags = IGT_SPIN_POLL_RUN);
 		gem_wait(i915, spin->handle, &jiffie); /* waitboost */
@@ -2608,13 +2655,14 @@ static void measure_semaphore_power(int i915)
 		rapl_read(&pkg, &s_spin[1].pkg);
 
 		/* Add a waiter to each engine */
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			igt_spin_t *sema;
 
 			if (e->flags == signaler->flags)
 				continue;
 
 			sema = __igt_spin_new(i915,
+					      .ctx = ctx,
 					      .engine = e->flags,
 					      .dependency = spin->handle);
 
@@ -2686,8 +2734,7 @@ static int cmp_u32(const void *A, const void *B)
 		return 0;
 }
 
-static uint32_t read_ctx_timestamp(int i915,
-				   uint32_t ctx,
+static uint32_t read_ctx_timestamp(int i915, const intel_ctx_t *ctx,
 				   const struct intel_execution_engine2 *e)
 {
 	const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
@@ -2703,7 +2750,7 @@ static uint32_t read_ctx_timestamp(int i915,
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = e->flags,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 	};
 #define RUNTIME (base + 0x3a8)
 	uint32_t *map, *cs;
@@ -2736,7 +2783,7 @@ static uint32_t read_ctx_timestamp(int i915,
 	return ts;
 }
 
-static void fairslice(int i915,
+static void fairslice(int i915, const intel_ctx_cfg_t *cfg,
 		      const struct intel_execution_engine2 *e,
 		      unsigned long flags,
 		      int duration)
@@ -2744,14 +2791,14 @@ static void fairslice(int i915,
 	const double timeslice_duration_ns = 1e6;
 	igt_spin_t *spin = NULL;
 	double threshold;
-	uint32_t ctx[3];
+	const intel_ctx_t *ctx[3];
 	uint32_t ts[3];
 
 	for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
-		ctx[i] = gem_context_clone_with_engines(i915, 0);
+		ctx[i] = intel_ctx_create(i915, cfg);
 		if (spin == NULL) {
 			spin = __igt_spin_new(i915,
-					      .ctx_id = ctx[i],
+					      .ctx = ctx[i],
 					      .engine = e->flags,
 					      .flags = flags);
 		} else {
@@ -2759,7 +2806,7 @@ static void fairslice(int i915,
 				.buffer_count = 1,
 				.buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
 				.flags = e->flags,
-				.rsvd1 = ctx[i],
+				.rsvd1 = ctx[i]->id,
 			};
 			gem_execbuf(i915, &eb);
 		}
@@ -2773,7 +2820,7 @@ static void fairslice(int i915,
 		ts[i] = read_ctx_timestamp(i915, ctx[i], e);
 
 	for (int i = 0; i < ARRAY_SIZE(ctx); i++)
-		gem_context_destroy(i915, ctx[i]);
+		intel_ctx_destroy(i915, ctx[i]);
 	igt_spin_free(i915, spin);
 
 	/*
@@ -2800,18 +2847,19 @@ static void fairslice(int i915,
 		     1e-6 * threshold * 2);
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		igt_dynamic_f("%s", e->name)
 
-#define test_each_engine_store(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine_store(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if(gem_class_can_store_dword(fd, e->class)) \
 		igt_dynamic_f("%s", e->name)
 
 igt_main
 {
 	int fd = -1;
+	const intel_ctx_t *ctx = NULL;
 
 	igt_fixture {
 		igt_require_sw_sync();
@@ -2823,6 +2871,7 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_mmap_wc(fd);
 		gem_require_contexts(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
@@ -2830,22 +2879,22 @@ igt_main
 	igt_subtest_group {
 		const struct intel_execution_engine2 *e;
 
-		test_each_engine_store("fifo", fd, e)
-			fifo(fd, e->flags);
+		test_each_engine_store("fifo", fd, ctx, e)
+			fifo(fd, ctx, e->flags);
 
-		test_each_engine_store("implicit-read-write", fd, e)
-			implicit_rw(fd, e->flags, READ_WRITE);
+		test_each_engine_store("implicit-read-write", fd, ctx, e)
+			implicit_rw(fd, ctx, e->flags, READ_WRITE);
 
-		test_each_engine_store("implicit-write-read", fd, e)
-			implicit_rw(fd, e->flags, WRITE_READ);
+		test_each_engine_store("implicit-write-read", fd, ctx, e)
+			implicit_rw(fd, ctx, e->flags, WRITE_READ);
 
-		test_each_engine_store("implicit-boths", fd, e)
-			implicit_rw(fd, e->flags, READ_WRITE | WRITE_READ);
+		test_each_engine_store("implicit-boths", fd, ctx, e)
+			implicit_rw(fd, ctx, e->flags, READ_WRITE | WRITE_READ);
 
-		test_each_engine_store("independent", fd, e)
-			independent(fd, e->flags, 0);
-		test_each_engine_store("u-independent", fd, e)
-			independent(fd, e->flags, IGT_SPIN_USERPTR);
+		test_each_engine_store("independent", fd, ctx, e)
+			independent(fd, ctx, e->flags, 0);
+		test_each_engine_store("u-independent", fd, ctx, e)
+			independent(fd, ctx, e->flags, IGT_SPIN_USERPTR);
 	}
 
 	igt_subtest_group {
@@ -2856,19 +2905,19 @@ igt_main
 			igt_require(gem_scheduler_has_ctx_priority(fd));
 		}
 
-		test_each_engine("timeslicing", fd, e)
-			timeslice(fd, e->flags);
+		test_each_engine("timeslicing", fd, ctx, e)
+			timeslice(fd, &ctx->cfg, e->flags);
 
-		test_each_engine("thriceslice", fd, e)
-			timesliceN(fd, e->flags, 3);
+		test_each_engine("thriceslice", fd, ctx, e)
+			timesliceN(fd, &ctx->cfg, e->flags, 3);
 
-		test_each_engine("manyslice", fd, e)
-			timesliceN(fd, e->flags, 67);
+		test_each_engine("manyslice", fd, ctx, e)
+			timesliceN(fd, &ctx->cfg, e->flags, 67);
 
-		test_each_engine("lateslice", fd, e)
-			lateslice(fd, e->flags, 0);
-		test_each_engine("u-lateslice", fd, e)
-			lateslice(fd, e->flags, IGT_SPIN_USERPTR);
+		test_each_engine("lateslice", fd, ctx, e)
+			lateslice(fd, &ctx->cfg, e->flags, 0);
+		test_each_engine("u-lateslice", fd, ctx, e)
+			lateslice(fd, &ctx->cfg, e->flags, IGT_SPIN_USERPTR);
 
 		igt_subtest_group {
 			igt_fixture {
@@ -2877,23 +2926,23 @@ igt_main
 				igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
 			}
 
-			test_each_engine("fairslice", fd, e)
-				fairslice(fd, e, 0, 2);
+			test_each_engine("fairslice", fd, ctx, e)
+				fairslice(fd, &ctx->cfg, e, 0, 2);
 
-			test_each_engine("u-fairslice", fd, e)
-				fairslice(fd, e, IGT_SPIN_USERPTR, 2);
+			test_each_engine("u-fairslice", fd, ctx, e)
+				fairslice(fd, &ctx->cfg, e, IGT_SPIN_USERPTR, 2);
 
 			igt_subtest("fairslice-all")  {
-				__for_each_physical_engine(fd, e) {
+				for_each_ctx_engine(fd, ctx, e) {
 					igt_fork(child, 1)
-						fairslice(fd, e, 0, 2);
+						fairslice(fd, &ctx->cfg, e, 0, 2);
 				}
 				igt_waitchildren();
 			}
 			igt_subtest("u-fairslice-all")  {
-				__for_each_physical_engine(fd, e) {
+				for_each_ctx_engine(fd, ctx, e) {
 					igt_fork(child, 1)
-						fairslice(fd, e,
+						fairslice(fd, &ctx->cfg, e,
 							  IGT_SPIN_USERPTR,
 							  2);
 				}
@@ -2901,84 +2950,84 @@ igt_main
 			}
 		}
 
-		test_each_engine("submit-early-slice", fd, e)
-			submit_slice(fd, e, EARLY_SUBMIT);
-		test_each_engine("u-submit-early-slice", fd, e)
-			submit_slice(fd, e, EARLY_SUBMIT | USERPTR);
-		test_each_engine("submit-golden-slice", fd, e)
-			submit_slice(fd, e, 0);
-		test_each_engine("u-submit-golden-slice", fd, e)
-			submit_slice(fd, e, USERPTR);
-		test_each_engine("submit-late-slice", fd, e)
-			submit_slice(fd, e, LATE_SUBMIT);
-		test_each_engine("u-submit-late-slice", fd, e)
-			submit_slice(fd, e, LATE_SUBMIT | USERPTR);
+		test_each_engine("submit-early-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, EARLY_SUBMIT);
+		test_each_engine("u-submit-early-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, EARLY_SUBMIT | USERPTR);
+		test_each_engine("submit-golden-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, 0);
+		test_each_engine("u-submit-golden-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, USERPTR);
+		test_each_engine("submit-late-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, LATE_SUBMIT);
+		test_each_engine("u-submit-late-slice", fd, ctx, e)
+			submit_slice(fd, &ctx->cfg, e, LATE_SUBMIT | USERPTR);
 
 		igt_subtest("semaphore-user")
-			semaphore_userlock(fd, 0);
+			semaphore_userlock(fd, ctx, 0);
 		igt_subtest("semaphore-codependency")
-			semaphore_codependency(fd, 0);
+			semaphore_codependency(fd, ctx, 0);
 		igt_subtest("semaphore-resolve")
-			semaphore_resolve(fd, 0);
+			semaphore_resolve(fd, &ctx->cfg, 0);
 		igt_subtest("semaphore-noskip")
-			semaphore_noskip(fd, 0);
+			semaphore_noskip(fd, &ctx->cfg, 0);
 
 		igt_subtest("u-semaphore-user")
-			semaphore_userlock(fd, IGT_SPIN_USERPTR);
+			semaphore_userlock(fd, ctx, IGT_SPIN_USERPTR);
 		igt_subtest("u-semaphore-codependency")
-			semaphore_codependency(fd, IGT_SPIN_USERPTR);
+			semaphore_codependency(fd, ctx, IGT_SPIN_USERPTR);
 		igt_subtest("u-semaphore-resolve")
-			semaphore_resolve(fd, IGT_SPIN_USERPTR);
+			semaphore_resolve(fd, &ctx->cfg, IGT_SPIN_USERPTR);
 		igt_subtest("u-semaphore-noskip")
-			semaphore_noskip(fd, IGT_SPIN_USERPTR);
+			semaphore_noskip(fd, &ctx->cfg, IGT_SPIN_USERPTR);
 
 		igt_subtest("smoketest-all")
-			smoketest(fd, ALL_ENGINES, 30);
+			smoketest(fd, &ctx->cfg, ALL_ENGINES, 30);
 
-		test_each_engine_store("in-order", fd, e)
-			reorder(fd, e->flags, EQUAL);
+		test_each_engine_store("in-order", fd, ctx, e)
+			reorder(fd, &ctx->cfg, e->flags, EQUAL);
 
-		test_each_engine_store("out-order", fd, e)
-			reorder(fd, e->flags, 0);
+		test_each_engine_store("out-order", fd, ctx, e)
+			reorder(fd, &ctx->cfg, e->flags, 0);
 
-		test_each_engine_store("promotion", fd, e)
-			promotion(fd, e->flags);
+		test_each_engine_store("promotion", fd, ctx, e)
+			promotion(fd, &ctx->cfg, e->flags);
 
 		igt_subtest_group {
 			igt_fixture {
 				igt_require(gem_scheduler_has_preemption(fd));
 			}
 
-			test_each_engine_store("preempt", fd, e)
-				preempt(fd, e, 0);
+			test_each_engine_store("preempt", fd, ctx, e)
+				preempt(fd, &ctx->cfg, e, 0);
 
-			test_each_engine_store("preempt-contexts", fd, e)
-				preempt(fd, e, NEW_CTX);
+			test_each_engine_store("preempt-contexts", fd, ctx, e)
+				preempt(fd, &ctx->cfg, e, NEW_CTX);
 
-			test_each_engine_store("preempt-user", fd, e)
-				preempt(fd, e, USERPTR);
+			test_each_engine_store("preempt-user", fd, ctx, e)
+				preempt(fd, &ctx->cfg, e, USERPTR);
 
-			test_each_engine_store("preempt-self", fd, e)
-				preempt_self(fd, e->flags);
+			test_each_engine_store("preempt-self", fd, ctx, e)
+				preempt_self(fd, &ctx->cfg, e->flags);
 
-			test_each_engine_store("preempt-other", fd, e)
-				preempt_other(fd, e->flags, 0);
+			test_each_engine_store("preempt-other", fd, ctx, e)
+				preempt_other(fd, &ctx->cfg, e->flags, 0);
 
-			test_each_engine_store("preempt-other-chain", fd, e)
-				preempt_other(fd, e->flags, CHAIN);
+			test_each_engine_store("preempt-other-chain", fd, ctx, e)
+				preempt_other(fd, &ctx->cfg, e->flags, CHAIN);
 
-			test_each_engine_store("preempt-queue", fd, e)
-				preempt_queue(fd, e->flags, 0);
+			test_each_engine_store("preempt-queue", fd, ctx, e)
+				preempt_queue(fd, &ctx->cfg, e->flags, 0);
 
-			test_each_engine_store("preempt-queue-chain", fd, e)
-				preempt_queue(fd, e->flags, CHAIN);
-			test_each_engine_store("preempt-queue-contexts", fd, e)
-				preempt_queue(fd, e->flags, CONTEXTS);
+			test_each_engine_store("preempt-queue-chain", fd, ctx, e)
+				preempt_queue(fd, &ctx->cfg, e->flags, CHAIN);
+			test_each_engine_store("preempt-queue-contexts", fd, ctx, e)
+				preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS);
 
-			test_each_engine_store("preempt-queue-contexts-chain", fd, e)
-				preempt_queue(fd, e->flags, CONTEXTS | CHAIN);
+			test_each_engine_store("preempt-queue-contexts-chain", fd, ctx, e)
+				preempt_queue(fd, &ctx->cfg, e->flags, CONTEXTS | CHAIN);
 
-			test_each_engine_store("preempt-engines", fd, e)
+			test_each_engine_store("preempt-engines", fd, ctx, e)
 				preempt_engines(fd, e, 0);
 
 			igt_subtest_group {
@@ -2989,11 +3038,11 @@ igt_main
 					hang = igt_allow_hang(fd, 0, 0);
 				}
 
-				test_each_engine_store("preempt-hang", fd, e)
-					preempt(fd, e, NEW_CTX | HANG_LP);
+				test_each_engine_store("preempt-hang", fd, ctx, e)
+					preempt(fd, &ctx->cfg, e, NEW_CTX | HANG_LP);
 
-				test_each_engine_store("preemptive-hang", fd, e)
-					preemptive_hang(fd, e);
+				test_each_engine_store("preemptive-hang", fd, ctx, e)
+					preemptive_hang(fd, &ctx->cfg, e);
 
 				igt_fixture {
 					igt_disallow_hang(fd, hang);
@@ -3002,30 +3051,30 @@ igt_main
 			}
 		}
 
-		test_each_engine_store("noreorder", fd, e)
-			noreorder(fd, e->flags, 0, 0);
+		test_each_engine_store("noreorder", fd, ctx, e)
+			noreorder(fd, &ctx->cfg, e->flags, 0, 0);
 
-		test_each_engine_store("noreorder-priority", fd, e) {
+		test_each_engine_store("noreorder-priority", fd, ctx, e) {
 			igt_require(gem_scheduler_enabled(fd));
-			noreorder(fd, e->flags, MAX_PRIO, 0);
+			noreorder(fd, &ctx->cfg, e->flags, MAX_PRIO, 0);
 		}
 
-		test_each_engine_store("noreorder-corked", fd, e) {
+		test_each_engine_store("noreorder-corked", fd, ctx, e) {
 			igt_require(gem_scheduler_enabled(fd));
-			noreorder(fd, e->flags, MAX_PRIO, CORKED);
+			noreorder(fd, &ctx->cfg, e->flags, MAX_PRIO, CORKED);
 		}
 
-		test_each_engine_store("deep", fd, e)
-			deep(fd, e->flags);
+		test_each_engine_store("deep", fd, ctx, e)
+			deep(fd, &ctx->cfg, e->flags);
 
-		test_each_engine_store("wide", fd, e)
-			wide(fd, e->flags);
+		test_each_engine_store("wide", fd, ctx, e)
+			wide(fd, &ctx->cfg, e->flags);
 
-		test_each_engine_store("reorder-wide", fd, e)
-			reorder_wide(fd, e->flags);
+		test_each_engine_store("reorder-wide", fd, ctx, e)
+			reorder_wide(fd, &ctx->cfg, e->flags);
 
-		test_each_engine_store("smoketest", fd, e)
-			smoketest(fd, e->flags, 5);
+		test_each_engine_store("smoketest", fd, ctx, e)
+			smoketest(fd, &ctx->cfg, e->flags, 5);
 	}
 
 	igt_subtest_group {
@@ -3037,20 +3086,20 @@ igt_main
 			igt_require(gem_scheduler_has_preemption(fd));
 		}
 
-		test_each_engine("pi-ringfull", fd, e)
-			test_pi_ringfull(fd, e->flags, 0);
+		test_each_engine("pi-ringfull", fd, ctx, e)
+			test_pi_ringfull(fd, &ctx->cfg, e->flags, 0);
 
-		test_each_engine("pi-common", fd, e)
-			test_pi_ringfull(fd, e->flags, SHARED);
+		test_each_engine("pi-common", fd, ctx, e)
+			test_pi_ringfull(fd, &ctx->cfg, e->flags, SHARED);
 
-		test_each_engine("pi-userfault", fd, e)
-			test_pi_userfault(fd, e->flags);
+		test_each_engine("pi-userfault", fd, ctx, e)
+			test_pi_userfault(fd, &ctx->cfg, e->flags);
 
-		test_each_engine("pi-distinct-iova", fd, e)
-			test_pi_iova(fd, e->flags, 0);
+		test_each_engine("pi-distinct-iova", fd, ctx, e)
+			test_pi_iova(fd, &ctx->cfg, e->flags, 0);
 
-		test_each_engine("pi-shared-iova", fd, e)
-			test_pi_iova(fd, e->flags, SHARED);
+		test_each_engine("pi-shared-iova", fd, ctx, e)
+			test_pi_iova(fd, &ctx->cfg, e->flags, SHARED);
 	}
 
 	igt_subtest_group {
@@ -3060,11 +3109,12 @@ igt_main
 		}
 
 		igt_subtest("semaphore-power")
-			measure_semaphore_power(fd);
+			measure_semaphore_power(fd, ctx);
 	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 19/74] tests/i915/perf_pmu: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/perf_pmu.c | 228 ++++++++++++++++++++++++------------------
 1 file changed, 128 insertions(+), 100 deletions(-)

diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index c7ddac85..7f2c1664 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -46,6 +46,7 @@
 #include "igt_perf.h"
 #include "igt_sysfs.h"
 #include "igt_pm.h"
+#include "intel_ctx.h"
 #include "sw_sync.h"
 
 IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
@@ -171,11 +172,11 @@ static unsigned int measured_usleep(unsigned int usec)
 #define FLAG_HANG (32)
 #define TEST_S3 (64)
 
-static igt_spin_t * __spin_poll(int fd, uint32_t ctx,
+static igt_spin_t * __spin_poll(int fd, const intel_ctx_t *ctx,
 				const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
-		.ctx_id = ctx,
+		.ctx = ctx,
 		.engine = e->flags,
 	};
 
@@ -214,7 +215,7 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
 	return igt_nsec_elapsed(&start);
 }
 
-static igt_spin_t * __spin_sync(int fd, uint32_t ctx,
+static igt_spin_t * __spin_sync(int fd, const intel_ctx_t *ctx,
 				const struct intel_execution_engine2 *e)
 {
 	igt_spin_t *spin = __spin_poll(fd, ctx, e);
@@ -224,7 +225,7 @@ static igt_spin_t * __spin_sync(int fd, uint32_t ctx,
 	return spin;
 }
 
-static igt_spin_t * spin_sync(int fd, uint32_t ctx,
+static igt_spin_t * spin_sync(int fd, const intel_ctx_t *ctx,
 			      const struct intel_execution_engine2 *e)
 {
 	igt_require_gem(fd);
@@ -232,7 +233,7 @@ static igt_spin_t * spin_sync(int fd, uint32_t ctx,
 	return __spin_sync(fd, ctx, e);
 }
 
-static igt_spin_t * spin_sync_flags(int fd, uint32_t ctx, unsigned int flags)
+static igt_spin_t * spin_sync_flags(int fd, const intel_ctx_t *ctx, unsigned int flags)
 {
 	struct intel_execution_engine2 e = { };
 
@@ -276,7 +277,8 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
 }
 
 static void
-single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
+single(int gem_fd, const intel_ctx_t *ctx,
+       const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	unsigned long slept;
 	igt_spin_t *spin;
@@ -286,7 +288,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e);
+		spin = spin_sync(gem_fd, ctx, e);
 	else
 		spin = NULL;
 
@@ -322,7 +324,8 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 }
 
 static void
-busy_start(int gem_fd, const struct intel_execution_engine2 *e)
+busy_start(int gem_fd, const intel_ctx_t *ctx,
+	   const struct intel_execution_engine2 *e)
 {
 	unsigned long slept;
 	uint64_t val, ts[2];
@@ -335,7 +338,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	sleep(2);
 
-	spin = __spin_sync(gem_fd, 0, e);
+	spin = __spin_sync(gem_fd, ctx, e);
 
 	fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
@@ -357,15 +360,16 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
  * will depend on the CI systems running it a lot to detect issues.
  */
 static void
-busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
+busy_double_start(int gem_fd, const intel_ctx_t *ctx,
+		  const struct intel_execution_engine2 *e)
 {
 	unsigned long slept;
 	uint64_t val, val2, ts[2];
 	igt_spin_t *spin[2];
-	uint32_t ctx;
+	const intel_ctx_t *tmp_ctx;
 	int fd;
 
-	ctx = gem_context_clone_with_engines(gem_fd, 0);
+	tmp_ctx = intel_ctx_create(gem_fd, &ctx->cfg);
 
 	/*
 	 * Defeat the busy stats delayed disable, we need to guarantee we are
@@ -378,10 +382,10 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 * re-submission in execlists mode. Make sure busyness is correctly
 	 * reported with the engine busy, and after the engine went idle.
 	 */
-	spin[0] = __spin_sync(gem_fd, 0, e);
+	spin[0] = __spin_sync(gem_fd, ctx, e);
 	usleep(500e3);
 	spin[1] = __igt_spin_new(gem_fd,
-				 .ctx_id = ctx,
+				 .ctx = tmp_ctx,
 				 .engine = e->flags);
 
 	/*
@@ -412,7 +416,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 
 	close(fd);
 
-	gem_context_destroy(gem_fd, ctx);
+	intel_ctx_destroy(gem_fd, tmp_ctx);
 
 	assert_within_epsilon(val, ts[1] - ts[0], tolerance);
 	igt_assert_eq(val2, 0);
@@ -440,7 +444,8 @@ static void log_busy(unsigned int num_engines, uint64_t *val)
 }
 
 static void
-busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
+busy_check_all(int gem_fd, const intel_ctx_t *ctx,
+	       const struct intel_execution_engine2 *e,
 	       const unsigned int num_engines, unsigned int flags)
 {
 	struct intel_execution_engine2 *e_;
@@ -453,7 +458,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	__for_each_physical_engine(gem_fd, e_) {
+	for_each_ctx_engine(gem_fd, ctx, e_) {
 		if (e->class == e_->class && e->instance == e_->instance)
 			busy_idx = i;
 
@@ -465,7 +470,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	igt_assert_eq(i, num_engines);
 
-	spin = spin_sync(gem_fd, 0, e);
+	spin = spin_sync(gem_fd, ctx, e);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
@@ -506,7 +511,8 @@ __submit_spin(int gem_fd, igt_spin_t *spin,
 }
 
 static void
-most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
+most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
+		    const struct intel_execution_engine2 *e,
 		    const unsigned int num_engines, unsigned int flags)
 {
 	struct intel_execution_engine2 *e_;
@@ -518,13 +524,13 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	__for_each_physical_engine(gem_fd, e_) {
+	for_each_ctx_engine(gem_fd, ctx, e_) {
 		if (e->class == e_->class && e->instance == e_->instance)
 			idle_idx = i;
 		else if (spin)
 			__submit_spin(gem_fd, spin, e_, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e_);
+			spin = __spin_poll(gem_fd, ctx, e_);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
 	}
@@ -564,7 +570,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 }
 
 static void
-all_busy_check_all(int gem_fd, const unsigned int num_engines,
+all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
+		   const unsigned int num_engines,
 		   unsigned int flags)
 {
 	struct intel_execution_engine2 *e;
@@ -576,11 +583,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	__for_each_physical_engine(gem_fd, e) {
+	for_each_ctx_engine(gem_fd, ctx, e) {
 		if (spin)
 			__submit_spin(gem_fd, spin, e, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e);
+			spin = __spin_poll(gem_fd, ctx, e);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	}
@@ -615,7 +622,9 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 }
 
 static void
-no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
+no_sema(int gem_fd, const intel_ctx_t *ctx,
+	const struct intel_execution_engine2 *e,
+	unsigned int flags)
 {
 	igt_spin_t *spin;
 	uint64_t val[2][2];
@@ -627,7 +636,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 			   fd[0]);
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e);
+		spin = spin_sync(gem_fd, ctx, e);
 	else
 		spin = NULL;
 
@@ -658,7 +667,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
 
 static void
-sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
+sema_wait(int gem_fd, const intel_ctx_t *ctx,
+	  const struct intel_execution_engine2 *e,
 	  unsigned int flags)
 {
 	struct drm_i915_gem_relocation_entry reloc[2] = {};
@@ -717,6 +727,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
 	eb.buffer_count = 2;
 	eb.buffers_ptr = to_user_pointer(obj);
 	eb.flags = e->flags;
+	eb.rsvd1 = ctx->id;
 
 	/**
 	 * Start the semaphore wait PMU and after some known time let the above
@@ -788,7 +799,7 @@ create_sema(int gem_fd, struct drm_i915_gem_relocation_entry *reloc)
 }
 
 static void
-__sema_busy(int gem_fd, int pmu,
+__sema_busy(int gem_fd, int pmu, const intel_ctx_t *ctx,
 	    const struct intel_execution_engine2 *e,
 	    int sema_pct,
 	    int busy_pct)
@@ -810,6 +821,7 @@ __sema_busy(int gem_fd, int pmu,
 		.buffer_count = 1,
 		.buffers_ptr = to_user_pointer(&obj),
 		.flags = e->flags,
+		.rsvd1 = ctx->id,
 	};
 	igt_spin_t *spin;
 	uint32_t *map;
@@ -821,7 +833,7 @@ __sema_busy(int gem_fd, int pmu,
 
 	map = gem_mmap__wc(gem_fd, obj.handle, 0, 4096, PROT_WRITE);
 	gem_execbuf(gem_fd, &eb);
-	spin = igt_spin_new(gem_fd, .engine = e->flags);
+	spin = igt_spin_new(gem_fd, .ctx = ctx, .engine = e->flags);
 
 	/* Wait until the batch is executed and the semaphore is busy-waiting */
 	while (!READ_ONCE(*map) && gem_bo_busy(gem_fd, obj.handle))
@@ -861,7 +873,7 @@ __sema_busy(int gem_fd, int pmu,
 }
 
 static void
-sema_busy(int gem_fd,
+sema_busy(int gem_fd, const intel_ctx_t *ctx,
 	  const struct intel_execution_engine2 *e,
 	  unsigned int flags)
 {
@@ -874,15 +886,15 @@ sema_busy(int gem_fd,
 	fd[1] = open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance),
 			   fd[0]);
 
-	__sema_busy(gem_fd, fd[0], e, 50, 100);
-	__sema_busy(gem_fd, fd[0], e, 25, 50);
-	__sema_busy(gem_fd, fd[0], e, 75, 75);
+	__sema_busy(gem_fd, fd[0], ctx, e, 50, 100);
+	__sema_busy(gem_fd, fd[0], ctx, e, 25, 50);
+	__sema_busy(gem_fd, fd[0], ctx, e, 75, 75);
 
 	close(fd[0]);
 	close(fd[1]);
 }
 
-static void test_awake(int i915)
+static void test_awake(int i915, const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
 	unsigned long slept;
@@ -893,8 +905,8 @@ static void test_awake(int i915)
 	igt_skip_on(fd < 0);
 
 	/* Check that each engine is captured by the GT wakeref */
-	__for_each_physical_engine(i915, e) {
-		igt_spin_new(i915, .engine = e->flags);
+	for_each_ctx_engine(i915, ctx, e) {
+		igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
 
 		val = pmu_read_single(fd);
 		slept = measured_usleep(batch_duration_ns / 1000);
@@ -905,8 +917,8 @@ static void test_awake(int i915)
 	}
 
 	/* And that the total GT wakeref matches walltime not summation */
-	__for_each_physical_engine(i915, e)
-		igt_spin_new(i915, .engine = e->flags);
+	for_each_ctx_engine(i915, ctx, e)
+		igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
 
 	val = pmu_read_single(fd);
 	slept = measured_usleep(batch_duration_ns / 1000);
@@ -995,7 +1007,8 @@ static int has_secure_batches(const int fd)
 }
 
 static void
-event_wait(int gem_fd, const struct intel_execution_engine2 *e)
+event_wait(int gem_fd, const intel_ctx_t *ctx,
+	   const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_exec_object2 obj = { };
 	struct drm_i915_gem_execbuffer2 eb = { };
@@ -1051,6 +1064,7 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
 	eb.flags = e->flags | I915_EXEC_SECURE;
+	eb.rsvd1 = ctx->id;
 
 	for_each_pipe_with_valid_output(&data.display, p, output) {
 		struct igt_helper_process waiter = { };
@@ -1123,7 +1137,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 }
 
 static void
-multi_client(int gem_fd, const struct intel_execution_engine2 *e)
+multi_client(int gem_fd, const intel_ctx_t *ctx,
+	     const struct intel_execution_engine2 *e)
 {
 	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	unsigned long slept[2];
@@ -1142,7 +1157,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	fd[1] = open_pmu(gem_fd, config);
 
-	spin = spin_sync(gem_fd, 0, e);
+	spin = spin_sync(gem_fd, ctx, e);
 
 	val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
 	slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1705,7 +1720,8 @@ test_rc6(int gem_fd, unsigned int flags)
 }
 
 static void
-test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
+test_enable_race(int gem_fd, const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e)
 {
 	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	struct igt_helper_process engine_load = { };
@@ -1723,6 +1739,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
 	eb.flags = e->flags;
+	eb.rsvd1 = ctx->id;
 
 	/*
 	 * This test is probabilistic so run in a few times to increase the
@@ -1769,7 +1786,8 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
 	__assert_within(x, ref, tolerance, tolerance)
 
 static void
-accuracy(int gem_fd, const struct intel_execution_engine2 *e,
+accuracy(int gem_fd, const intel_ctx_t *ctx,
+	 const struct intel_execution_engine2 *e,
 	 unsigned long target_busy_pct,
 	 unsigned long target_iters)
 {
@@ -1819,7 +1837,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 		igt_spin_t *spin;
 
 		/* Allocate our spin batch and idle it. */
-		spin = igt_spin_new(gem_fd, .engine = e->flags);
+		spin = igt_spin_new(gem_fd, .ctx = ctx, .engine = e->flags);
 		igt_spin_end(spin);
 		gem_sync(gem_fd, spin->handle);
 
@@ -1978,6 +1996,7 @@ static int unload_i915(void)
 static void test_unload(unsigned int num_engines)
 {
 	igt_fork(child, 1) {
+		intel_ctx_cfg_t cfg;
 		const struct intel_execution_engine2 *e;
 		int fd[4 + num_engines * 3], i;
 		uint64_t *buf;
@@ -2003,7 +2022,8 @@ static void test_unload(unsigned int num_engines)
 		if (fd[count] != -1)
 			count++;
 
-		__for_each_physical_engine(i915, e) {
+		cfg = intel_ctx_cfg_all_physical(i915);
+		for_each_ctx_cfg_engine(i915, &cfg, e) {
 			fd[count] = perf_i915_open_group(i915,
 							 I915_PMU_ENGINE_BUSY(e->class, e->instance),
 							 fd[count - 1]);
@@ -2051,12 +2071,12 @@ static void test_unload(unsigned int num_engines)
 	igt_assert_eq(unload_i915(), 0);
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		igt_dynamic_f("%s", e->name)
 
-#define test_each_rcs(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_rcs(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if((e)->class == I915_ENGINE_CLASS_RENDER) \
 			igt_dynamic_f("%s", e->name)
 
@@ -2064,6 +2084,7 @@ igt_main
 {
 	const struct intel_execution_engine2 *e;
 	unsigned int num_engines = 0;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	/**
@@ -2078,7 +2099,9 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_perf_type_id(fd) > 0);
 
-		__for_each_physical_engine(fd, e)
+		ctx = intel_ctx_create_all_physical(fd);
+
+		for_each_ctx_engine(fd, ctx, e)
 			num_engines++;
 		igt_require(num_engines);
 	}
@@ -2106,48 +2129,48 @@ igt_main
 	 * Test that a single engine metric can be initialized or it
 	 * is correctly rejected.
 	 */
-	test_each_engine("init-busy", fd, e)
+	test_each_engine("init-busy", fd, ctx, e)
 		init(fd, e, I915_SAMPLE_BUSY);
 
-	test_each_engine("init-wait", fd, e)
+	test_each_engine("init-wait", fd, ctx, e)
 		init(fd, e, I915_SAMPLE_WAIT);
 
-	test_each_engine("init-sema", fd, e)
+	test_each_engine("init-sema", fd, ctx, e)
 		init(fd, e, I915_SAMPLE_SEMA);
 
 	/**
 	 * Test that engines show no load when idle.
 	 */
-	test_each_engine("idle", fd, e)
-		single(fd, e, 0);
+	test_each_engine("idle", fd, ctx, e)
+		single(fd, ctx, e, 0);
 
 	/**
 	 * Test that a single engine reports load correctly.
 	 */
-	test_each_engine("busy", fd, e)
-		single(fd, e, TEST_BUSY);
-	test_each_engine("busy-idle", fd, e)
-		single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+	test_each_engine("busy", fd, ctx, e)
+		single(fd, ctx, e, TEST_BUSY);
+	test_each_engine("busy-idle", fd, ctx, e)
+		single(fd, ctx, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
 	 * Test that when one engine is loaded other report no
 	 * load.
 	 */
-	test_each_engine("busy-check-all", fd, e)
-		busy_check_all(fd, e, num_engines, TEST_BUSY);
-	test_each_engine("busy-idle-check-all", fd, e)
-		busy_check_all(fd, e, num_engines,
+	test_each_engine("busy-check-all", fd, ctx, e)
+		busy_check_all(fd, ctx, e, num_engines, TEST_BUSY);
+	test_each_engine("busy-idle-check-all", fd, ctx, e)
+		busy_check_all(fd, ctx, e, num_engines,
 			       TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
 	 * Test that when all except one engine are loaded all
 	 * loads are correctly reported.
 	 */
-	test_each_engine("most-busy-check-all", fd, e)
-		most_busy_check_all(fd, e, num_engines,
+	test_each_engine("most-busy-check-all", fd, ctx, e)
+		most_busy_check_all(fd, ctx, e, num_engines,
 				    TEST_BUSY);
-	test_each_engine("most-busy-idle-check-all", fd, e)
-		most_busy_check_all(fd, e, num_engines,
+	test_each_engine("most-busy-idle-check-all", fd, ctx, e)
+		most_busy_check_all(fd, ctx, e, num_engines,
 				    TEST_BUSY |
 				    TEST_TRAILING_IDLE);
 
@@ -2155,40 +2178,40 @@ igt_main
 	 * Test that semphore counters report no activity on
 	 * idle or busy engines.
 	 */
-	test_each_engine("idle-no-semaphores", fd, e)
-		no_sema(fd, e, 0);
+	test_each_engine("idle-no-semaphores", fd, ctx, e)
+		no_sema(fd, ctx, e, 0);
 
-	test_each_engine("busy-no-semaphores", fd, e)
-		no_sema(fd, e, TEST_BUSY);
+	test_each_engine("busy-no-semaphores", fd, ctx, e)
+		no_sema(fd, ctx, e, TEST_BUSY);
 
-	test_each_engine("busy-idle-no-semaphores", fd, e)
-		no_sema(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+	test_each_engine("busy-idle-no-semaphores", fd, ctx, e)
+		no_sema(fd, ctx, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
 	 * Test that semaphore waits are correctly reported.
 	 */
-	test_each_engine("semaphore-wait", fd, e)
-		sema_wait(fd, e, TEST_BUSY);
+	test_each_engine("semaphore-wait", fd, ctx, e)
+		sema_wait(fd, ctx, e, TEST_BUSY);
 
-	test_each_engine("semaphore-wait-idle", fd, e)
-		sema_wait(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+	test_each_engine("semaphore-wait-idle", fd, ctx, e)
+		sema_wait(fd, ctx, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
-	test_each_engine("semaphore-busy", fd, e)
-		sema_busy(fd, e, 0);
+	test_each_engine("semaphore-busy", fd, ctx, e)
+		sema_busy(fd, ctx, e, 0);
 
 	/**
 	 * Check that two perf clients do not influence each
 	 * others observations.
 	 */
-	test_each_engine("multi-client", fd, e)
-		multi_client(fd, e);
+	test_each_engine("multi-client", fd, ctx, e)
+		multi_client(fd, ctx, e);
 
 	/**
 	 * Check that reported usage is correct when PMU is
 	 * enabled after the batch is running.
 	 */
-	test_each_engine("busy-start", fd, e)
-		busy_start(fd, e);
+	test_each_engine("busy-start", fd, ctx, e)
+		busy_start(fd, ctx, e);
 
 	/**
 	 * Check that reported usage is correct when PMU is
@@ -2197,16 +2220,16 @@ igt_main
 	igt_subtest_group {
 		igt_fixture gem_require_contexts(fd);
 
-		test_each_engine("busy-double-start", fd, e)
-			busy_double_start(fd, e);
+		test_each_engine("busy-double-start", fd, ctx, e)
+			busy_double_start(fd, ctx, e);
 	}
 
 	/**
 	 * Check that the PMU can be safely enabled in face of
 	 * interrupt-heavy engine load.
 	 */
-	test_each_engine("enable-race", fd, e)
-		test_enable_race(fd, e);
+	test_each_engine("enable-race", fd, ctx, e)
+		test_enable_race(fd, ctx, e);
 
 	igt_subtest_group {
 		const unsigned int pct[] = { 2, 50, 98 };
@@ -2216,18 +2239,18 @@ igt_main
 		 */
 		for (unsigned int i = 0; i < ARRAY_SIZE(pct); i++) {
 			igt_subtest_with_dynamic_f("busy-accuracy-%u", pct[i]) {
-				__for_each_physical_engine(fd, e) {
+				for_each_ctx_engine(fd, ctx, e) {
 					igt_dynamic_f("%s", e->name)
-						accuracy(fd, e, pct[i], 10);
+						accuracy(fd, ctx, e, pct[i], 10);
 				}
 			}
 		}
 	}
 
-	test_each_engine("busy-hang", fd, e) {
+	test_each_engine("busy-hang", fd, ctx, e) {
 		igt_hang_t hang = igt_allow_hang(fd, 0, 0);
 
-		single(fd, e, TEST_BUSY | FLAG_HANG);
+		single(fd, ctx, e, TEST_BUSY | FLAG_HANG);
 
 		igt_disallow_hang(fd, hang);
 	}
@@ -2235,17 +2258,18 @@ igt_main
 	/**
 	 * Test that event waits are correctly reported.
 	 */
-	test_each_rcs("event-wait", fd, e)
-		event_wait(fd, e);
+	test_each_rcs("event-wait", fd, ctx, e)
+		event_wait(fd, ctx, e);
 
 	/**
 	 * Test that when all engines are loaded all loads are
 	 * correctly reported.
 	 */
 	igt_subtest("all-busy-check-all")
-		all_busy_check_all(fd, num_engines, TEST_BUSY);
+		all_busy_check_all(fd, ctx, num_engines,
+				   TEST_BUSY);
 	igt_subtest("all-busy-idle-check-all")
-		all_busy_check_all(fd, num_engines,
+		all_busy_check_all(fd, ctx, num_engines,
 				   TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
@@ -2290,32 +2314,36 @@ igt_main
 	 * Test GT wakeref tracking (similar to RC0, opposite of RC6)
 	 */
 	igt_subtest("gt-awake")
-		test_awake(fd);
+		test_awake(fd, ctx);
 
 	/**
 	 * Check render nodes are counted.
 	 */
 	igt_subtest_group {
 		int render_fd = -1;
+		const intel_ctx_t *render_ctx = NULL;
 
 		igt_fixture {
 			render_fd = __drm_open_driver_render(DRIVER_INTEL);
 			igt_require_gem(render_fd);
+			render_ctx = intel_ctx_create_all_physical(render_fd);
 
 			gem_quiescent_gpu(fd);
 		}
 
-		test_each_engine("render-node-busy", render_fd, e)
-			single(render_fd, e, TEST_BUSY);
-		test_each_engine("render-node-busy-idle", render_fd, e)
-			single(render_fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+		test_each_engine("render-node-busy", render_fd, ctx, e)
+			single(render_fd, render_ctx, e, TEST_BUSY);
+		test_each_engine("render-node-busy-idle", render_fd, ctx, e)
+			single(render_fd, render_ctx, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 		igt_fixture {
+			intel_ctx_destroy(render_fd, render_ctx);
 			close(render_fd);
 		}
 	}
 
 	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 
-- 
2.31.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 20/74] tests/i915/gem_exec_nop: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_nop.c | 156 ++++++++++++++++++++++----------------
 1 file changed, 92 insertions(+), 64 deletions(-)

diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c
index f24ff88f..98c308d7 100644
--- a/tests/i915/gem_exec_nop.c
+++ b/tests/i915/gem_exec_nop.c
@@ -45,6 +45,7 @@
 #include "igt_device.h"
 #include "igt_rand.h"
 #include "igt_sysfs.h"
+#include "intel_ctx.h"
 
 
 #define ENGINE_FLAGS  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
@@ -62,7 +63,7 @@ static double elapsed(const struct timespec *start, const struct timespec *end)
 		(end->tv_nsec - start->tv_nsec)*1e-9);
 }
 
-static double nop_on_ring(int fd, uint32_t handle,
+static double nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx,
 			  const struct intel_execution_engine2 *e,
 			  int timeout_ms,
 			  unsigned long *out)
@@ -81,6 +82,7 @@ static double nop_on_ring(int fd, uint32_t handle,
 	execbuf.flags = e->flags;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = e->flags;
 		gem_execbuf(fd, &execbuf);
@@ -101,7 +103,8 @@ static double nop_on_ring(int fd, uint32_t handle,
 	return elapsed(&start, &now);
 }
 
-static void poll_ring(int fd, const struct intel_execution_engine2 *e,
+static void poll_ring(int fd, const intel_ctx_t *ctx,
+		      const struct intel_execution_engine2 *e,
 		      int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -185,6 +188,7 @@ static void poll_ring(int fd, const struct intel_execution_engine2 *e,
 	execbuf.buffers_ptr = to_user_pointer(&obj);
 	execbuf.buffer_count = 1;
 	execbuf.flags = e->flags | flags;
+	execbuf.rsvd1 = ctx->id;
 
 	cycles = 0;
 	do {
@@ -212,7 +216,8 @@ static void poll_ring(int fd, const struct intel_execution_engine2 *e,
 	gem_close(fd, obj.handle);
 }
 
-static void poll_sequential(int fd, const char *name, int timeout)
+static void poll_sequential(int fd, const intel_ctx_t *ctx,
+			    const char *name, int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	const struct intel_execution_engine2 *e;
@@ -232,7 +237,7 @@ static void poll_sequential(int fd, const char *name, int timeout)
 		flags |= I915_EXEC_SECURE;
 
 	nengine = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		if (!gem_class_can_store_dword(fd, e->class) ||
 		    !gem_class_has_mutable_submission(fd, e->class))
 			continue;
@@ -312,6 +317,7 @@ static void poll_sequential(int fd, const char *name, int timeout)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = ARRAY_SIZE(obj);
+	execbuf.rsvd1 = ctx->id;
 
 	cycles = 0;
 	do {
@@ -342,19 +348,19 @@ static void poll_sequential(int fd, const char *name, int timeout)
 	gem_close(fd, obj[0].handle);
 }
 
-static void single(int fd, uint32_t handle,
+static void single(int fd, uint32_t handle, const intel_ctx_t *ctx,
 		   const struct intel_execution_engine2 *e)
 {
 	double time;
 	unsigned long count;
 
-	time = nop_on_ring(fd, handle, e, 20000, &count);
+	time = nop_on_ring(fd, handle, ctx, e, 20000, &count);
 	igt_info("%s: %'lu cycles: %.3fus\n",
 		  e->name, count, time*1e6 / count);
 }
 
 static double
-stable_nop_on_ring(int fd, uint32_t handle,
+stable_nop_on_ring(int fd, uint32_t handle, const intel_ctx_t *ctx,
 		   const struct intel_execution_engine2 *e,
 		   int timeout_ms,
 		   int reps)
@@ -371,7 +377,7 @@ stable_nop_on_ring(int fd, uint32_t handle,
 		unsigned long count;
 		double time;
 
-		time = nop_on_ring(fd, handle, e, timeout_ms, &count);
+		time = nop_on_ring(fd, handle, ctx, e, timeout_ms, &count);
 		igt_stats_push_float(&s, time / count);
 	}
 
@@ -387,7 +393,7 @@ stable_nop_on_ring(int fd, uint32_t handle,
                      "'%s' != '%s' (%f not within %f%% tolerance of %f)\n",\
                      #x, #ref, x, tolerance * 100.0, ref)
 
-static void headless(int fd, uint32_t handle,
+static void headless(int fd, uint32_t handle, const intel_ctx_t *ctx,
 		     const struct intel_execution_engine2 *e)
 {
 	unsigned int nr_connected = 0;
@@ -411,11 +417,11 @@ static void headless(int fd, uint32_t handle,
 	/* set graphics mode to prevent blanking */
 	kmstest_set_vt_graphics_mode();
 
-	nop_on_ring(fd, handle, e, 10, &count);
+	nop_on_ring(fd, handle, ctx, e, 10, &count);
 	igt_require_f(count > 100, "submillisecond precision required\n");
 
 	/* benchmark nops */
-	n_display = stable_nop_on_ring(fd, handle, e, 500, 5);
+	n_display = stable_nop_on_ring(fd, handle, ctx, e, 500, 5);
 	igt_info("With one display connected: %.2fus\n",
 		 n_display * 1e6);
 
@@ -423,7 +429,7 @@ static void headless(int fd, uint32_t handle,
 	kmstest_unset_all_crtcs(fd, res);
 
 	/* benchmark nops again */
-	n_headless = stable_nop_on_ring(fd, handle, e, 500, 5);
+	n_headless = stable_nop_on_ring(fd, handle, ctx, e, 500, 5);
 	igt_info("Without a display connected (headless): %.2fus\n",
 		 n_headless * 1e6);
 
@@ -431,7 +437,8 @@ static void headless(int fd, uint32_t handle,
 	assert_within_epsilon(n_headless, n_display, 0.1f);
 }
 
-static void parallel(int fd, uint32_t handle, int timeout)
+static void parallel(int fd, uint32_t handle,
+		     const intel_ctx_t *ctx, int timeout)
 {
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -445,11 +452,11 @@ static void parallel(int fd, uint32_t handle, int timeout)
 	sum = 0;
 	nengine = 0;
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		engines[nengine] = e->flags;
 		names[nengine++] = strdup(e->name);
 
-		time = nop_on_ring(fd, handle, e, 250, &count) / count;
+		time = nop_on_ring(fd, handle, ctx, e, 250, &count) / count;
 		sum += time;
 		igt_debug("%s: %.3fus\n", e->name, 1e6*time);
 	}
@@ -464,6 +471,7 @@ static void parallel(int fd, uint32_t handle, int timeout)
 	execbuf.buffer_count = 1;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = 0;
 		gem_execbuf(fd, &execbuf);
@@ -494,7 +502,8 @@ static void parallel(int fd, uint32_t handle, int timeout)
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
-static void independent(int fd, uint32_t handle, int timeout)
+static void independent(int fd, uint32_t handle,
+			const intel_ctx_t *ctx, int timeout)
 {
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -507,11 +516,11 @@ static void independent(int fd, uint32_t handle, int timeout)
 
 	sum = 0;
 	nengine = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		engines[nengine] = e->flags;
 		names[nengine++] = strdup(e->name);
 
-		time = nop_on_ring(fd, handle, e, 250, &count) / count;
+		time = nop_on_ring(fd, handle, ctx, e, 250, &count) / count;
 		sum += time;
 		igt_debug("%s: %.3fus\n", e->name, 1e6*time);
 	}
@@ -526,6 +535,7 @@ static void independent(int fd, uint32_t handle, int timeout)
 	execbuf.buffer_count = 1;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = 0;
 		gem_execbuf(fd, &execbuf);
@@ -562,7 +572,7 @@ static void independent(int fd, uint32_t handle, int timeout)
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
-static void multiple(int fd,
+static void multiple(int fd, const intel_ctx_t *ctx,
 		     const struct intel_execution_engine2 *e,
 		     int timeout)
 {
@@ -581,6 +591,7 @@ static void multiple(int fd,
 	execbuf.flags = e->flags;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = e->flags;
 		gem_execbuf(fd, &execbuf);
@@ -592,9 +603,11 @@ static void multiple(int fd,
 		unsigned long count;
 		double time;
 		int i915;
+		const intel_ctx_t *child_ctx;
 
 		i915 = gem_reopen_driver(fd);
-		gem_context_copy_engines(fd, 0, i915, 0);
+		child_ctx = intel_ctx_create(i915, &ctx->cfg);
+		execbuf.rsvd1 = child_ctx->id;
 
 		obj.handle = gem_create(i915, 4096);
 		gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
@@ -609,6 +622,7 @@ static void multiple(int fd,
 		} while (elapsed(&start, &now) < timeout);
 		time = elapsed(&start, &now) / count;
 		igt_info("%d: %ld cycles, %.3fus\n", child, count, 1e6*time);
+		intel_ctx_destroy(i915, child_ctx);
 	}
 
 	igt_waitchildren();
@@ -617,7 +631,8 @@ static void multiple(int fd,
 	gem_close(fd, obj.handle);
 }
 
-static void series(int fd, uint32_t handle, int timeout)
+static void series(int fd, uint32_t handle,
+		   const intel_ctx_t *ctx, int timeout)
 {
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -630,8 +645,8 @@ static void series(int fd, uint32_t handle, int timeout)
 	const char *name;
 
 	nengine = 0;
-	__for_each_physical_engine(fd, e) {
-		time = nop_on_ring(fd, handle, e, 250, &count) / count;
+	for_each_ctx_engine(fd, ctx, e) {
+		time = nop_on_ring(fd, handle, ctx, e, 250, &count) / count;
 		if (time > max) {
 			name = e->name;
 			max = time;
@@ -653,6 +668,7 @@ static void series(int fd, uint32_t handle, int timeout)
 	execbuf.buffer_count = 1;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = 0;
 		gem_execbuf(fd, &execbuf);
@@ -688,9 +704,11 @@ static void xchg(void *array, unsigned i, unsigned j)
 	u[j] = tmp;
 }
 
-static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
+static void sequential(int fd, uint32_t handle,
+		       const intel_ctx_t *ctx, unsigned flags, int timeout)
 {
 	const int ncpus = flags & FORKED ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
+	const intel_ctx_t *tmp_ctx = NULL, *child_ctx = NULL;
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -707,10 +725,10 @@ static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
 
 	nengine = 0;
 	sum = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		unsigned long count;
 
-		time = nop_on_ring(fd, handle, e, 250, &count) / count;
+		time = nop_on_ring(fd, handle, ctx, e, 250, &count) / count;
 		sum += time;
 		igt_debug("%s: %.3fus\n", e->name, 1e6*time);
 
@@ -734,7 +752,8 @@ static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
 
 	if (flags & CONTEXT) {
 		gem_require_contexts(fd);
-		execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
+		tmp_ctx = intel_ctx_create(fd, &ctx->cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
 	}
 
 	for (n = 0; n < nengine; n++) {
@@ -754,7 +773,8 @@ static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
 
 		if (flags & CONTEXT) {
 			gem_require_contexts(fd);
-			execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
+			child_ctx = intel_ctx_create(fd, &ctx->cfg);
+			execbuf.rsvd1 = child_ctx->id;
 		}
 
 		hars_petruska_f54_1_random_perturb(child);
@@ -777,7 +797,7 @@ static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
 		results[child] = elapsed(&start, &now) / count;
 
 		if (flags & CONTEXT)
-			gem_context_destroy(fd, execbuf.rsvd1);
+			intel_ctx_destroy(fd, child_ctx);
 
 		gem_close(fd, obj[0].handle);
 	}
@@ -793,7 +813,7 @@ static void sequential(int fd, uint32_t handle, unsigned flags, int timeout)
 		 nengine, ncpus, 1e6*results[ncpus], 1e6*sum*ncpus);
 
 	if (flags & CONTEXT)
-		gem_context_destroy(fd, execbuf.rsvd1);
+		intel_ctx_destroy(fd, tmp_ctx);
 
 	gem_close(fd, obj[0].handle);
 	munmap(results, 4096);
@@ -810,6 +830,7 @@ static bool fence_wait(int fence)
 }
 
 static void fence_signal(int fd, uint32_t handle,
+			 const intel_ctx_t *ctx,
 			 const struct intel_execution_engine2 *ring_id,
 			 const char *ring_name, int timeout)
 {
@@ -827,7 +848,7 @@ static void fence_signal(int fd, uint32_t handle,
 
 	nengine = 0;
 	if (!ring_id) {
-		__for_each_physical_engine(fd, __e)
+		for_each_ctx_engine(fd, ctx, __e)
 			engines[nengine++] = __e->flags;
 	} else {
 		engines[nengine++] = ring_id->flags;
@@ -845,6 +866,7 @@ static void fence_signal(int fd, uint32_t handle,
 	execbuf.buffers_ptr = to_user_pointer(&obj);
 	execbuf.buffer_count = 1;
 	execbuf.flags = I915_EXEC_FENCE_OUT;
+	execbuf.rsvd1 = ctx->id;
 
 	n = 0;
 	count = 0;
@@ -885,20 +907,21 @@ static void fence_signal(int fd, uint32_t handle,
 }
 
 static void preempt(int fd, uint32_t handle,
+		    const intel_ctx_t *ctx,
 		    const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj;
 	struct timespec start, now;
 	unsigned long count;
-	uint32_t ctx[2];
+	const intel_ctx_t *tmp_ctx[2];
 	igt_spin_t *spin;
 
-	ctx[0] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[0], MIN_PRIO);
+	tmp_ctx[0] = intel_ctx_create(fd, &ctx->cfg);
+	gem_context_set_priority(fd, tmp_ctx[0]->id, MIN_PRIO);
 
-	ctx[1] = gem_context_clone_with_engines(fd, 0);
-	gem_context_set_priority(fd, ctx[1], MAX_PRIO);
+	tmp_ctx[1] = intel_ctx_create(fd, &ctx->cfg);
+	gem_context_set_priority(fd, tmp_ctx[1]->id, MAX_PRIO);
 
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = handle;
@@ -909,15 +932,16 @@ static void preempt(int fd, uint32_t handle,
 	execbuf.flags = e->flags;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = e->flags;
 		gem_execbuf(fd, &execbuf);
 	}
-	execbuf.rsvd1 = ctx[1];
+	execbuf.rsvd1 = tmp_ctx[1]->id;
 	intel_detect_and_clear_missed_interrupts(fd);
 
 	count = 0;
-	spin = __igt_spin_new(fd, .ctx_id = ctx[0], .engine = e->flags);
+	spin = __igt_spin_new(fd, .ctx = tmp_ctx[0], .engine = e->flags);
 	clock_gettime(CLOCK_MONOTONIC, &start);
 	do {
 		gem_execbuf(fd, &execbuf);
@@ -927,8 +951,8 @@ static void preempt(int fd, uint32_t handle,
 	igt_spin_free(fd, spin);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 
-	gem_context_destroy(fd, ctx[1]);
-	gem_context_destroy(fd, ctx[0]);
+	intel_ctx_destroy(fd, tmp_ctx[1]);
+	intel_ctx_destroy(fd, tmp_ctx[0]);
 
 	igt_info("%s: %'lu cycles: %.3fus\n",
 		 e->name, count, elapsed(&start, &now)*1e6 / count);
@@ -937,6 +961,7 @@ static void preempt(int fd, uint32_t handle,
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	uint32_t handle = 0;
 	int device = -1;
 
@@ -948,6 +973,8 @@ igt_main
 		gem_submission_print_method(device);
 		gem_scheduler_print_capability(device);
 
+		ctx = intel_ctx_create_all_physical(device);
+
 		handle = gem_create(device, 4096);
 		gem_write(device, handle, 0, &bbe, sizeof(bbe));
 
@@ -955,57 +982,57 @@ igt_main
 	}
 
 	igt_subtest("basic-series")
-		series(device, handle, 2);
+		series(device, handle, ctx, 2);
 
 	igt_subtest("basic-parallel")
-		parallel(device, handle, 2);
+		parallel(device, handle, ctx, 2);
 
 	igt_subtest("basic-sequential")
-		sequential(device, handle, 0, 2);
+		sequential(device, handle, ctx, 0, 2);
 
 	igt_subtest_with_dynamic("single") {
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				single(device, handle, e);
+				single(device, handle, ctx, e);
 		}
 	}
 
 	igt_subtest_with_dynamic("signal") {
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				fence_signal(device, handle, e,
-					     e->name, 2);
+				fence_signal(device, handle, ctx,
+					     e, e->name, 2);
 		}
 	}
 
 	igt_subtest("signal-all")
 		/* NULL value means all engines */
-		fence_signal(device, handle, NULL, "all", 20);
+		fence_signal(device, handle, ctx, NULL, "all", 20);
 
 	igt_subtest("series")
-		series(device, handle, 20);
+		series(device, handle, ctx, 20);
 
 	igt_subtest("parallel")
-		parallel(device, handle, 20);
+		parallel(device, handle, ctx, 20);
 
 	igt_subtest("independent")
-		independent(device, handle, 20);
+		independent(device, handle, ctx, 20);
 
 	igt_subtest_with_dynamic("multiple") {
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				multiple(device, e, 20);
+				multiple(device, ctx, e, 20);
 		}
 	}
 
 	igt_subtest("sequential")
-		sequential(device, handle, 0, 20);
+		sequential(device, handle, ctx, 0, 20);
 
 	igt_subtest("forked-sequential")
-		sequential(device, handle, FORKED, 20);
+		sequential(device, handle, ctx, FORKED, 20);
 
 	igt_subtest("context-sequential")
-		sequential(device, handle, FORKED | CONTEXT, 20);
+		sequential(device, handle, ctx, FORKED | CONTEXT, 20);
 
 	igt_subtest_group {
 		igt_fixture {
@@ -1014,9 +1041,9 @@ igt_main
 			igt_require(gem_scheduler_has_preemption(device));
 		}
 		igt_subtest_with_dynamic("preempt") {
-			__for_each_physical_engine(device, e) {
+			for_each_ctx_engine(device, ctx, e) {
 				igt_dynamic_f("%s", e->name)
-					preempt(device, handle, e);
+					preempt(device, handle, ctx, e);
 			}
 		}
 	}
@@ -1027,29 +1054,30 @@ igt_main
 		}
 
 		igt_subtest_with_dynamic("poll") {
-			__for_each_physical_engine(device, e) {
+			for_each_ctx_engine(device, ctx, e) {
 				/* Requires master for STORE_DWORD on gen4/5 */
 				igt_dynamic_f("%s", e->name)
-					poll_ring(device, e, 20);
+					poll_ring(device, ctx, e, 20);
 			}
 		}
 
 		igt_subtest_with_dynamic("headless") {
-			__for_each_physical_engine(device, e) {
+			for_each_ctx_engine(device, ctx, e) {
 				igt_dynamic_f("%s", e->name)
 				/* Requires master for changing display modes */
-					headless(device, handle, e);
+					headless(device, handle, ctx, e);
 			}
 		}
 
 		igt_subtest("poll-sequential")
-			poll_sequential(device, "Sequential", 20);
+			poll_sequential(device, ctx, "Sequential", 20);
 
 	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
 		gem_close(device, handle);
+		intel_ctx_destroy(device, ctx);
 		close(device);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 21/74] tests/i915/gem_exec_reloc: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_reloc.c | 102 ++++++++++++++++++++++--------------
 1 file changed, 62 insertions(+), 40 deletions(-)

diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 397c335e..920dc61e 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -266,7 +266,7 @@ static void check_bo(int fd, uint32_t handle)
 	munmap(map, 4096);
 }
 
-static void active(int fd, unsigned engine)
+static void active(int fd, const intel_ctx_t *ctx, unsigned engine)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_relocation_entry reloc;
@@ -280,7 +280,7 @@ static void active(int fd, unsigned engine)
 	if (engine == ALL_ENGINES) {
 		const struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (gem_class_can_store_dword(fd, e->class))
 				engines[nengine++] = e->flags;
 		}
@@ -308,6 +308,7 @@ static void active(int fd, unsigned engine)
 	execbuf.buffer_count = 2;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	for (pass = 0; pass < 1024; pass++) {
 		uint32_t batch[16];
@@ -367,7 +368,8 @@ static uint64_t many_relocs(unsigned long count, unsigned long *out)
 	return to_user_pointer(reloc);
 }
 
-static void __many_active(int i915, unsigned engine, unsigned long count)
+static void __many_active(int i915, const intel_ctx_t *ctx, unsigned engine,
+			  unsigned long count)
 {
 	unsigned long reloc_sz;
 	struct drm_i915_gem_exec_object2 obj[2] = {{
@@ -379,10 +381,12 @@ static void __many_active(int i915, unsigned engine, unsigned long count)
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = engine | I915_EXEC_HANDLE_LUT,
+		.rsvd1 = ctx->id,
 	};
 	igt_spin_t *spin;
 
 	spin = __igt_spin_new(i915,
+			      .ctx = ctx,
 			      .engine = engine,
 			      .dependency = obj[0].handle,
 			      .flags = (IGT_SPIN_FENCE_OUT |
@@ -405,7 +409,7 @@ static void __many_active(int i915, unsigned engine, unsigned long count)
 	gem_close(i915, obj[0].handle);
 }
 
-static void many_active(int i915, unsigned engine)
+static void many_active(int i915, const intel_ctx_t *ctx, unsigned engine)
 {
 	const uint64_t max = 2048;
 	unsigned long count = 256;
@@ -418,7 +422,7 @@ static void many_active(int i915, unsigned engine)
 			break;
 
 		igt_debug("Testing count:%lu\n", count);
-		__many_active(i915, engine, count);
+		__many_active(i915, ctx, engine, count);
 
 		count <<= 1;
 		if (count >= max)
@@ -426,7 +430,8 @@ static void many_active(int i915, unsigned engine)
 	}
 }
 
-static void __wide_active(int i915, unsigned engine, unsigned long count)
+static void __wide_active(int i915, const intel_ctx_t *ctx, unsigned engine,
+			  unsigned long count)
 {
 	struct drm_i915_gem_relocation_entry *reloc =
 		calloc(count, sizeof(*reloc));
@@ -436,6 +441,7 @@ static void __wide_active(int i915, unsigned engine, unsigned long count)
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = count + 1,
 		.flags = engine | I915_EXEC_HANDLE_LUT,
+		.rsvd1 = ctx->id,
 	};
 	igt_spin_t *spin;
 
@@ -446,6 +452,7 @@ static void __wide_active(int i915, unsigned engine, unsigned long count)
 	}
 
 	spin = __igt_spin_new(i915,
+			      .ctx = ctx,
 			      .engine = engine,
 			      .flags = (IGT_SPIN_FENCE_OUT |
 					IGT_SPIN_NO_PREEMPTION));
@@ -475,7 +482,7 @@ static void __wide_active(int i915, unsigned engine, unsigned long count)
 	free(reloc);
 }
 
-static void wide_active(int i915, unsigned engine)
+static void wide_active(int i915, const intel_ctx_t *ctx, unsigned engine)
 {
 	const uint64_t max = gem_aperture_size(i915) / 4096 / 2;
 	unsigned long count = 256;
@@ -488,7 +495,7 @@ static void wide_active(int i915, unsigned engine)
 			break;
 
 		igt_debug("Testing count:%lu\n", count);
-		__wide_active(i915, engine, count);
+		__wide_active(i915, ctx, engine, count);
 
 		count <<= 1;
 		if (count >= max)
@@ -501,7 +508,7 @@ static unsigned int offset_in_page(void *addr)
 	return (uintptr_t)addr & 4095;
 }
 
-static void active_spin(int fd, unsigned engine)
+static void active_spin(int fd, const intel_ctx_t *ctx, unsigned engine)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_relocation_entry reloc;
@@ -510,6 +517,7 @@ static void active_spin(int fd, unsigned engine)
 	igt_spin_t *spin;
 
 	spin = igt_spin_new(fd,
+			    .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_NO_PREEMPTION);
 
@@ -529,6 +537,7 @@ static void active_spin(int fd, unsigned engine)
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
 	execbuf.flags = engine;
+	execbuf.rsvd1 = ctx->id;
 
 	gem_execbuf(fd, &execbuf);
 	gem_close(fd, obj[1].handle);
@@ -541,7 +550,7 @@ static void active_spin(int fd, unsigned engine)
 	igt_spin_free(fd, spin);
 }
 
-static void others_spin(int i915, unsigned engine)
+static void others_spin(int i915, const intel_ctx_t *ctx, unsigned engine)
 {
 	struct drm_i915_gem_relocation_entry reloc = {};
 	struct drm_i915_gem_exec_object2 obj = {
@@ -552,18 +561,20 @@ static void others_spin(int i915, unsigned engine)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = engine,
+		.rsvd1 = ctx->id,
 	};
 	const struct intel_execution_engine2 *e;
 	igt_spin_t *spin = NULL;
 	uint64_t addr;
 	int fence;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (e->flags == engine)
 			continue;
 
 		if (!spin) {
 			spin = igt_spin_new(i915,
+					    .ctx = ctx,
 					    .engine = e->flags,
 					    .flags = IGT_SPIN_FENCE_OUT);
 			fence = dup(spin->out_fence);
@@ -985,12 +996,13 @@ static void sighandler(int sig)
 	stop = 1;
 }
 
-static void parallel_child(int i915,
+static void parallel_child(int i915, const intel_ctx_t *ctx,
 			   const struct intel_execution_engine2 *engine,
 			   struct drm_i915_gem_relocation_entry *reloc,
 			   uint32_t common)
 {
-	igt_spin_t *spin = __igt_spin_new(i915, .engine = engine->flags);
+	igt_spin_t *spin = __igt_spin_new(i915, .ctx = ctx,
+					  .engine = engine->flags);
 	struct drm_i915_gem_exec_object2 reloc_target = {
 		.handle = gem_create(i915, 32 * 1024 * 8),
 		.relocation_count = 32 * 1024,
@@ -1005,6 +1017,7 @@ static void parallel_child(int i915,
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = engine->flags | I915_EXEC_HANDLE_LUT,
+		.rsvd1 = ctx->id,
 	};
 	struct sigaction act = {
 		.sa_handler = sighandler,
@@ -1032,7 +1045,7 @@ static void kill_children(int sig)
 	signal(sig, SIG_DFL);
 }
 
-static void parallel(int i915)
+static void parallel(int i915, const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_relocation_entry *reloc;
@@ -1043,16 +1056,16 @@ static void parallel(int i915)
 	reloc = parallel_relocs(32 * 1024, &reloc_sz);
 
 	stop = 0;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		igt_fork(child, 1)
-			parallel_child(i915, e, reloc, common);
+			parallel_child(i915, ctx, e, reloc, common);
 	}
 	sleep(2);
 
 	if (gem_scheduler_has_preemption(i915)) {
-		uint32_t ctx = gem_context_clone_with_engines(i915, 0);
+		const intel_ctx_t *tmp_ctx = intel_ctx_create(i915, &ctx->cfg);
 
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			struct drm_i915_gem_exec_object2 obj[2] = {
 				{ .handle = common },
 				{ .handle = batch },
@@ -1061,12 +1074,12 @@ static void parallel(int i915)
 				.buffers_ptr = to_user_pointer(obj),
 				.buffer_count = ARRAY_SIZE(obj),
 				.flags = e->flags,
-				.rsvd1 = ctx,
+				.rsvd1 = tmp_ctx->id,
 			};
 			gem_execbuf(i915, &execbuf);
 		}
 
-		gem_context_destroy(i915, ctx);
+		intel_ctx_destroy(i915, tmp_ctx);
 	}
 	gem_sync(i915, batch);
 	gem_close(i915, batch);
@@ -1120,7 +1133,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j)
 	u32[j] = tmp;
 }
 
-static void concurrent_child(int i915,
+static void concurrent_child(int i915, const intel_ctx_t *ctx,
 			     const struct intel_execution_engine2 *e,
 			     uint32_t *common, int num_common,
 			     int in, int out)
@@ -1133,6 +1146,7 @@ static void concurrent_child(int i915,
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = e->flags | I915_EXEC_HANDLE_LUT | (gen < 6 ? I915_EXEC_SECURE : 0),
+		.rsvd1 = ctx->id,
 	};
 	uint32_t *batch = &obj[num_common + 1].handle;
 	unsigned long count = 0;
@@ -1213,7 +1227,7 @@ static uint32_t create_concurrent_batch(int i915, unsigned int count)
 	return handle;
 }
 
-static void concurrent(int i915, int num_common)
+static void concurrent(int i915, const intel_ctx_t *ctx, int num_common)
 {
 	const struct intel_execution_engine2 *e;
 	int in[2], out[2];
@@ -1239,12 +1253,12 @@ static void concurrent(int i915, int num_common)
 		common[n] = gem_create(i915, 4 * 4 * CONCURRENT);
 
 	nchild = 0;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
 		igt_fork(child, 1)
-			concurrent_child(i915, e,
+			concurrent_child(i915, ctx, e,
 					 common, num_common,
 					 in[0], out[1]);
 
@@ -1308,6 +1322,7 @@ pin_scanout(igt_display_t *dpy, igt_output_t *output, struct igt_fb *fb)
 
 static void scanout(int i915,
 		    igt_display_t *dpy,
+		    const intel_ctx_t *ctx,
 		    const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_relocation_entry reloc = {};
@@ -1318,6 +1333,7 @@ static void scanout(int i915,
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = 2,
 		.flags = e->flags,
+		.rsvd1 = ctx->id,
 	};
 	igt_output_t *output;
 	struct igt_fb fb;
@@ -1437,6 +1453,7 @@ static void invalid_domains(int fd)
 
 igt_main
 {
+	const intel_ctx_t *ctx = 0;
 	const struct intel_execution_engine2 *e;
 	const struct mode {
 		const char *name;
@@ -1480,6 +1497,11 @@ igt_main
 		igt_require_gem(fd);
 		/* Check if relocations supported by platform */
 		igt_require(gem_has_relocations(fd));
+
+		if (gem_has_contexts(fd))
+			ctx = intel_ctx_create_all_physical(fd);
+		else
+			ctx = intel_ctx_0(fd);
 	}
 
 	for (f = flags; f->name; f++) {
@@ -1541,52 +1563,52 @@ igt_main
 
 	igt_subtest_with_dynamic("basic-active") {
 		igt_dynamic("all")
-			active(fd, ALL_ENGINES);
+			active(fd, ctx, ALL_ENGINES);
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (!gem_class_can_store_dword(fd, e->class))
 				continue;
 
 			igt_dynamic_f("%s", e->name)
-				active(fd, e->flags);
+				active(fd, ctx, e->flags);
 		}
 	}
 
 	igt_subtest_with_dynamic("basic-spin") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				active_spin(fd, e->flags);
+				active_spin(fd, ctx, e->flags);
 		}
 	}
 
 	igt_subtest_with_dynamic("basic-spin-others") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				others_spin(fd, e->flags);
+				others_spin(fd, ctx, e->flags);
 		}
 	}
 
 	igt_subtest_with_dynamic("basic-many-active") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				many_active(fd, e->flags);
+				many_active(fd, ctx, e->flags);
 		}
 	}
 
 	igt_subtest_with_dynamic("basic-wide-active") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				wide_active(fd, e->flags);
+				wide_active(fd, ctx, e->flags);
 		}
 	}
 
 	igt_subtest("basic-parallel")
-		parallel(fd);
+		parallel(fd, ctx);
 
 	igt_subtest("basic-concurrent0")
-		concurrent(fd, 0);
+		concurrent(fd, ctx, 0);
 	igt_subtest("basic-concurrent16")
-		concurrent(fd, 16);
+		concurrent(fd, ctx, 16);
 
 	igt_subtest("invalid-domains")
 		invalid_domains(fd);
@@ -1604,9 +1626,9 @@ igt_main
 		}
 
 		igt_subtest_with_dynamic("basic-scanout") {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				igt_dynamic_f("%s", e->name)
-					scanout(fd, &display, e);
+					scanout(fd, &display, ctx, e);
 			}
 		}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 22/74] tests/i915/gem_busy: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_busy.c | 77 +++++++++++++++++++++++++------------------
 1 file changed, 45 insertions(+), 32 deletions(-)

diff --git a/tests/i915/gem_busy.c b/tests/i915/gem_busy.c
index 77a55101..366f445f 100644
--- a/tests/i915/gem_busy.c
+++ b/tests/i915/gem_busy.c
@@ -67,6 +67,7 @@ static void __gem_busy(int fd,
 
 static bool exec_noop(int fd,
 		      uint32_t *handles,
+		      const intel_ctx_t *ctx,
 		      unsigned flags,
 		      bool write)
 {
@@ -84,6 +85,7 @@ static bool exec_noop(int fd,
 	execbuf.buffers_ptr = to_user_pointer(exec);
 	execbuf.buffer_count = 3;
 	execbuf.flags = flags;
+	execbuf.rsvd1 = ctx->id;
 	igt_debug("Queuing handle for %s on engine %d\n",
 		  write ? "writing" : "reading", flags);
 	return __gem_execbuf(fd, &execbuf) == 0;
@@ -96,7 +98,8 @@ static bool still_busy(int fd, uint32_t handle)
 	return write;
 }
 
-static void semaphore(int fd, const struct intel_execution_engine2 *e)
+static void semaphore(int fd, const intel_ctx_t *ctx,
+		      const struct intel_execution_engine2 *e)
 {
 	struct intel_execution_engine2 *__e;
 	uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -113,18 +116,19 @@ static void semaphore(int fd, const struct intel_execution_engine2 *e)
 	/* Create a long running batch which we can use to hog the GPU */
 	handle[BUSY] = gem_create(fd, 4096);
 	spin = igt_spin_new(fd,
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .dependency = handle[BUSY]);
 
 	/* Queue a batch after the busy, it should block and remain "busy" */
-	igt_assert(exec_noop(fd, handle, e->flags, false));
+	igt_assert(exec_noop(fd, handle, ctx, e->flags, false));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << e->class);
 	igt_assert_eq(write, 0);
 
 	/* Requeue with a write */
-	igt_assert(exec_noop(fd, handle, e->flags, true));
+	igt_assert(exec_noop(fd, handle, ctx, e->flags, true));
 	igt_assert(still_busy(fd, handle[BUSY]));
 	__gem_busy(fd, handle[TEST], &read, &write);
 	igt_assert_eq(read, 1 << e->class);
@@ -132,8 +136,8 @@ static void semaphore(int fd, const struct intel_execution_engine2 *e)
 
 	/* Now queue it for a read across all available rings */
 	active = 0;
-	__for_each_physical_engine(fd, __e) {
-		if (exec_noop(fd, handle, __e->flags, false))
+	for_each_ctx_engine(fd, ctx, __e) {
+		if (exec_noop(fd, handle, ctx, __e->flags, false))
 			active |= 1 << __e->class;
 	}
 	igt_assert(still_busy(fd, handle[BUSY]));
@@ -157,7 +161,8 @@ static void semaphore(int fd, const struct intel_execution_engine2 *e)
 
 #define PARALLEL 1
 #define HANG 2
-static void one(int fd, const struct intel_execution_engine2 *e, unsigned test_flags)
+static void one(int fd, const intel_ctx_t *ctx,
+		const struct intel_execution_engine2 *e, unsigned test_flags)
 {
 	uint32_t scratch = gem_create(fd, 4096);
 	uint32_t read[2], write[2];
@@ -167,6 +172,7 @@ static void one(int fd, const struct intel_execution_engine2 *e, unsigned test_f
 	int timeout;
 
 	spin = igt_spin_new(fd,
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .dependency = scratch,
 			    .flags = (test_flags & HANG) ? IGT_SPIN_NO_PREEMPTION : 0);
@@ -177,13 +183,13 @@ static void one(int fd, const struct intel_execution_engine2 *e, unsigned test_f
 	if (test_flags & PARALLEL) {
 		struct intel_execution_engine2 *e2;
 
-		__for_each_physical_engine(fd, e2) {
+		for_each_ctx_engine(fd, ctx, e2) {
 			if (e2->class == e->class &&
 			    e2->instance == e->instance)
 				continue;
 
 			igt_debug("Testing %s in parallel\n", e2->name);
-			one(fd, e2, 0);
+			one(fd, ctx, e2, 0);
 		}
 	}
 
@@ -228,7 +234,7 @@ static void xchg_u32(void *array, unsigned i, unsigned j)
 	u32[j] = tmp;
 }
 
-static void close_race(int fd)
+static void close_race(int fd, const intel_ctx_t *ctx)
 {
 	const unsigned int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	const unsigned int nhandles = gem_submission_measure(fd, ALL_ENGINES);
@@ -247,7 +253,7 @@ static void close_race(int fd)
 	 */
 
 	nengine = 0;
-	__for_each_physical_engine(fd, e)
+	for_each_ctx_engine(fd, ctx, e)
 		engines[nengine++] = e->flags;
 	igt_require(nengine);
 
@@ -295,6 +301,7 @@ static void close_race(int fd)
 
 		for (i = 0; i < nhandles; i++) {
 			spin[i] = __igt_spin_new(fd,
+						 .ctx = ctx,
 						 .engine = engines[rand() % nengine]);
 			handles[i] = spin[i]->handle;
 		}
@@ -303,6 +310,7 @@ static void close_race(int fd)
 			for (i = 0; i < nhandles; i++) {
 				igt_spin_free(fd, spin[i]);
 				spin[i] = __igt_spin_new(fd,
+							 .ctx = ctx,
 							 .engine = engines[rand() % nengine]);
 				handles[i] = spin[i]->handle;
 				__sync_synchronize();
@@ -354,10 +362,12 @@ static bool has_extended_busy_ioctl(int fd)
 	return read != 0;
 }
 
-static void basic(int fd, const struct intel_execution_engine2 *e, unsigned flags)
+static void basic(int fd, const intel_ctx_t *ctx,
+		  const struct intel_execution_engine2 *e, unsigned flags)
 {
 	igt_spin_t *spin =
 		igt_spin_new(fd,
+			     .ctx = ctx,
 			     .engine = e->flags,
 			     .flags = flags & HANG ?
 			     IGT_SPIN_NO_PREEMPTION | IGT_SPIN_INVALID_CS : 0);
@@ -384,32 +394,34 @@ static void basic(int fd, const struct intel_execution_engine2 *e, unsigned flag
 	igt_spin_free(fd, spin);
 }
 
-static void all(int i915)
+static void all(int i915, const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
 
-	__for_each_physical_engine(i915, e)
-		igt_fork(child, 1) basic(i915, e, 0);
+	for_each_ctx_engine(i915, ctx, e)
+		igt_fork(child, 1) basic(i915, ctx, e, 0);
 	igt_waitchildren();
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		igt_dynamic_f("%s", (e)->name)
 
-#define test_each_engine_store(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine_store(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if (gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	igt_subtest_group {
@@ -420,13 +432,13 @@ igt_main
 		igt_subtest_with_dynamic("busy") {
 			igt_dynamic("all") {
 				gem_quiescent_gpu(fd);
-				all(fd);
+				all(fd, ctx);
 			}
 
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				igt_dynamic_f("%s", e->name) {
 					gem_quiescent_gpu(fd);
-					basic(fd, e, 0);
+					basic(fd, ctx, e, 0);
 				}
 			}
 		}
@@ -437,15 +449,15 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			test_each_engine_store("extended", fd, e) {
+			test_each_engine_store("extended", fd, ctx, e) {
 				gem_quiescent_gpu(fd);
-				one(fd, e, 0);
+				one(fd, ctx, e, 0);
 				gem_quiescent_gpu(fd);
 			}
 
-			test_each_engine_store("parallel", fd, e) {
+			test_each_engine_store("parallel", fd, ctx, e) {
 				gem_quiescent_gpu(fd);
-				one(fd, e, PARALLEL);
+				one(fd, ctx, e, PARALLEL);
 				gem_quiescent_gpu(fd);
 			}
 		}
@@ -456,15 +468,15 @@ igt_main
 				igt_require(has_semaphores(fd));
 			}
 
-			test_each_engine("semaphore", fd, e) {
+			test_each_engine("semaphore", fd, ctx, e) {
 				gem_quiescent_gpu(fd);
-				semaphore(fd, e);
+				semaphore(fd, ctx, e);
 				gem_quiescent_gpu(fd);
 			}
 		}
 
 		igt_subtest("close-race")
-			close_race(fd);
+			close_race(fd, ctx);
 
 		igt_fixture {
 			igt_stop_hang_detector();
@@ -478,9 +490,9 @@ igt_main
 			hang = igt_allow_hang(fd, 0, 0);
 		}
 
-		test_each_engine("hang", fd, e) {
+		test_each_engine("hang", fd, ctx, e) {
 			gem_quiescent_gpu(fd);
-			basic(fd, e, HANG);
+			basic(fd, ctx, e, HANG);
 			gem_quiescent_gpu(fd);
 		}
 
@@ -490,9 +502,9 @@ igt_main
 				gem_require_mmap_wc(fd);
 			}
 
-			test_each_engine_store("hang-extended", fd, e) {
+			test_each_engine_store("hang-extended", fd, ctx, e) {
 				gem_quiescent_gpu(fd);
-				one(fd, e, HANG);
+				one(fd, ctx, e, HANG);
 				gem_quiescent_gpu(fd);
 			}
 		}
@@ -503,6 +515,7 @@ igt_main
 	}
 
 	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 23/74] tests/i915/gem_ctx_isolation: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ctx_isolation.c | 126 +++++++++++++++++----------------
 1 file changed, 66 insertions(+), 60 deletions(-)

diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index a57a6637..579aa0f9 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -232,7 +232,7 @@ static bool ignore_register(uint32_t offset, uint32_t mmio_base)
 }
 
 static void tmpl_regs(int fd,
-		      uint32_t ctx,
+		      const intel_ctx_t *ctx,
 		      const struct intel_execution_engine2 *e,
 		      uint32_t handle,
 		      uint32_t value)
@@ -277,7 +277,7 @@ static void tmpl_regs(int fd,
 }
 
 static uint32_t read_regs(int fd,
-			  uint32_t ctx,
+			  const intel_ctx_t *ctx,
 			  const struct intel_execution_engine2 *e,
 			  unsigned int flags)
 {
@@ -349,7 +349,7 @@ static uint32_t read_regs(int fd,
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
 	execbuf.flags = e->flags;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_close(fd, obj[1].handle);
 	free(reloc);
@@ -358,7 +358,7 @@ static uint32_t read_regs(int fd,
 }
 
 static void write_regs(int fd,
-		       uint32_t ctx,
+		       const intel_ctx_t *ctx,
 		       const struct intel_execution_engine2 *e,
 		       unsigned int flags,
 		       uint32_t value)
@@ -413,13 +413,13 @@ static void write_regs(int fd,
 	execbuf.buffers_ptr = to_user_pointer(&obj);
 	execbuf.buffer_count = 1;
 	execbuf.flags = e->flags;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_close(fd, obj.handle);
 }
 
 static void restore_regs(int fd,
-			 uint32_t ctx,
+			 const intel_ctx_t *ctx,
 			 const struct intel_execution_engine2 *e,
 			 unsigned int flags,
 			 uint32_t regs)
@@ -491,7 +491,7 @@ static void restore_regs(int fd,
 	execbuf.buffers_ptr = to_user_pointer(obj);
 	execbuf.buffer_count = 2;
 	execbuf.flags = e->flags;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_close(fd, obj[1].handle);
 }
@@ -595,7 +595,7 @@ static void compare_regs(int fd, const struct intel_execution_engine2 *e,
 		     num_errors, who);
 }
 
-static void nonpriv(int fd,
+static void nonpriv(int fd, const intel_ctx_cfg_t *cfg,
 		    const struct intel_execution_engine2 *e,
 		    unsigned int flags)
 {
@@ -620,33 +620,34 @@ static void nonpriv(int fd,
 
 	for (int v = 0; v < num_values; v++) {
 		igt_spin_t *spin = NULL;
-		uint32_t ctx, regs[2], tmpl;
+		const intel_ctx_t *ctx;
+		uint32_t regs[2], tmpl;
 
-		ctx = gem_context_clone_with_engines(fd, 0);
+		ctx = intel_ctx_create(fd, cfg);
 
 		tmpl = read_regs(fd, ctx, e, flags);
 		regs[0] = read_regs(fd, ctx, e, flags);
 
 		tmpl_regs(fd, ctx, e, tmpl, values[v]);
 
-		spin = igt_spin_new(fd, .ctx_id = ctx, .engine = e->flags);
+		spin = igt_spin_new(fd, .ctx = ctx, .engine = e->flags);
 
 		igt_debug("%s[%d]: Setting all registers to 0x%08x\n",
 			  __func__, v, values[v]);
 		write_regs(fd, ctx, e, flags, values[v]);
 
 		if (flags & DIRTY2) {
-			uint32_t sw = gem_context_clone_with_engines(fd, 0);
+			const intel_ctx_t *sw = intel_ctx_create(fd, &ctx->cfg);
 			igt_spin_t *syncpt, *dirt;
 
 			/* Explicit sync to keep the switch between write/read */
 			syncpt = igt_spin_new(fd,
-					      .ctx_id = ctx,
+					      .ctx = ctx,
 					      .engine = e->flags,
 					      .flags = IGT_SPIN_FENCE_OUT);
 
 			dirt = igt_spin_new(fd,
-					    .ctx_id = sw,
+					    .ctx = sw,
 					    .engine = e->flags,
 					    .fence = syncpt->out_fence,
 					    .flags = (IGT_SPIN_FENCE_IN |
@@ -654,14 +655,14 @@ static void nonpriv(int fd,
 			igt_spin_free(fd, syncpt);
 
 			syncpt = igt_spin_new(fd,
-					      .ctx_id = ctx,
+					      .ctx = ctx,
 					      .engine = e->flags,
 					      .fence = dirt->out_fence,
 					      .flags = IGT_SPIN_FENCE_IN);
 			igt_spin_free(fd, dirt);
 
 			igt_spin_free(fd, syncpt);
-			gem_context_destroy(fd, sw);
+			intel_ctx_destroy(fd, sw);
 		}
 
 		regs[1] = read_regs(fd, ctx, e, flags);
@@ -678,12 +679,12 @@ static void nonpriv(int fd,
 
 		for (int n = 0; n < ARRAY_SIZE(regs); n++)
 			gem_close(fd, regs[n]);
-		gem_context_destroy(fd, ctx);
+		intel_ctx_destroy(fd, ctx);
 		gem_close(fd, tmpl);
 	}
 }
 
-static void isolation(int fd,
+static void isolation(int fd, const intel_ctx_cfg_t *cfg,
 		      const struct intel_execution_engine2 *e,
 		      unsigned int flags)
 {
@@ -703,12 +704,13 @@ static void isolation(int fd,
 
 	for (int v = 0; v < num_values; v++) {
 		igt_spin_t *spin = NULL;
-		uint32_t ctx[2], regs[2], tmp;
+		const intel_ctx_t *ctx[2];
+		uint32_t regs[2], tmp;
 
-		ctx[0] = gem_context_clone_with_engines(fd, 0);
+		ctx[0] = intel_ctx_create(fd, cfg);
 		regs[0] = read_regs(fd, ctx[0], e, flags);
 
-		spin = igt_spin_new(fd, .ctx_id = ctx[0], .engine = e->flags);
+		spin = igt_spin_new(fd, .ctx = ctx[0], .engine = e->flags);
 
 		if (flags & DIRTY1) {
 			igt_debug("%s[%d]: Setting all registers of ctx 0 to 0x%08x\n",
@@ -724,7 +726,7 @@ static void isolation(int fd,
 		 * the default values from this context, but if goes badly we
 		 * see the corruption from the previous context instead!
 		 */
-		ctx[1] = gem_context_clone_with_engines(fd, 0);
+		ctx[1] = intel_ctx_create(fd, cfg);
 		regs[1] = read_regs(fd, ctx[1], e, flags);
 
 		if (flags & DIRTY2) {
@@ -749,7 +751,7 @@ static void isolation(int fd,
 
 		for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
 			gem_close(fd, regs[n]);
-			gem_context_destroy(fd, ctx[n]);
+			intel_ctx_destroy(fd, ctx[n]);
 		}
 		gem_close(fd, tmp);
 	}
@@ -762,21 +764,25 @@ static void isolation(int fd,
 #define S4 (4 << 8)
 #define SLEEP_MASK (0xf << 8)
 
-static uint32_t create_reset_context(int i915)
+static const intel_ctx_t *
+create_reset_context(int i915, const intel_ctx_cfg_t *cfg)
 {
+	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
 	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_clone_with_engines(i915, 0),
+		.ctx_id = ctx->id,
 		.param = I915_CONTEXT_PARAM_BANNABLE,
 	};
 
 	gem_context_set_param(i915, &param);
-	return param.ctx_id;
+	return ctx;
 }
 
-static void inject_reset_context(int fd, const struct intel_execution_engine2 *e)
+static void inject_reset_context(int fd, const intel_ctx_cfg_t *cfg,
+				 const struct intel_execution_engine2 *e)
 {
+	const intel_ctx_t *ctx = create_reset_context(fd, cfg);
 	struct igt_spin_factory opts = {
-		.ctx_id = create_reset_context(fd),
+		.ctx = ctx,
 		.engine = e->flags,
 		.flags = IGT_SPIN_FAST,
 	};
@@ -801,10 +807,10 @@ static void inject_reset_context(int fd, const struct intel_execution_engine2 *e
 	igt_force_gpu_reset(fd);
 
 	igt_spin_free(fd, spin);
-	gem_context_destroy(fd, opts.ctx_id);
+	intel_ctx_destroy(fd, ctx);
 }
 
-static void preservation(int fd,
+static void preservation(int fd, const intel_ctx_cfg_t *cfg,
 			 const struct intel_execution_engine2 *e,
 			 unsigned int flags)
 {
@@ -818,17 +824,17 @@ static void preservation(int fd,
 		0xdeadbeef
 	};
 	const unsigned int num_values = ARRAY_SIZE(values);
-	uint32_t ctx[num_values +1 ];
+	const intel_ctx_t *ctx[num_values +1 ];
 	uint32_t regs[num_values + 1][2];
 	igt_spin_t *spin;
 
 	gem_quiescent_gpu(fd);
 
-	ctx[num_values] = gem_context_clone_with_engines(fd, 0);
-	spin = igt_spin_new(fd, .ctx_id = ctx[num_values], .engine = e->flags);
+	ctx[num_values] = intel_ctx_create(fd, cfg);
+	spin = igt_spin_new(fd, .ctx = ctx[num_values], .engine = e->flags);
 	regs[num_values][0] = read_regs(fd, ctx[num_values], e, flags);
 	for (int v = 0; v < num_values; v++) {
-		ctx[v] = gem_context_clone_with_engines(fd, 0);
+		ctx[v] = intel_ctx_create(fd, cfg);
 		write_regs(fd, ctx[v], e, flags, values[v]);
 
 		regs[v][0] = read_regs(fd, ctx[v], e, flags);
@@ -838,7 +844,7 @@ static void preservation(int fd,
 	igt_spin_free(fd, spin);
 
 	if (flags & RESET)
-		inject_reset_context(fd, e);
+		inject_reset_context(fd, cfg, e);
 
 	switch (flags & SLEEP_MASK) {
 	case NOSLEEP:
@@ -865,7 +871,7 @@ static void preservation(int fd,
 		break;
 	}
 
-	spin = igt_spin_new(fd, .ctx_id = ctx[num_values], .engine = e->flags);
+	spin = igt_spin_new(fd, .ctx = ctx[num_values], .engine = e->flags);
 	for (int v = 0; v < num_values; v++)
 		regs[v][1] = read_regs(fd, ctx[v], e, flags);
 	regs[num_values][1] = read_regs(fd, ctx[num_values], e, flags);
@@ -879,10 +885,10 @@ static void preservation(int fd,
 
 		gem_close(fd, regs[v][0]);
 		gem_close(fd, regs[v][1]);
-		gem_context_destroy(fd, ctx[v]);
+		intel_ctx_destroy(fd, ctx[v]);
 	}
 	compare_regs(fd, e, regs[num_values][0], regs[num_values][1], "clean");
-	gem_context_destroy(fd, ctx[num_values]);
+	intel_ctx_destroy(fd, ctx[num_values]);
 }
 
 static unsigned int __has_context_isolation(int fd)
@@ -900,8 +906,8 @@ static unsigned int __has_context_isolation(int fd)
 	return value;
 }
 
-#define test_each_engine(e, i915, mask) \
-	__for_each_physical_engine(i915, e) \
+#define test_each_engine(e, i915, cfg, mask) \
+	for_each_ctx_cfg_engine(i915, cfg, e) \
 		for_each_if(mask & (1 << (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
@@ -909,6 +915,7 @@ igt_main
 {
 	unsigned int has_context_isolation = 0;
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg;
 	int i915 = -1;
 
 	igt_fixture {
@@ -917,6 +924,7 @@ igt_main
 		i915 = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(i915);
 		igt_require(gem_has_contexts(i915));
+		cfg = intel_ctx_cfg_all_physical(i915);
 
 		has_context_isolation = __has_context_isolation(i915);
 		igt_require(has_context_isolation);
@@ -928,50 +936,48 @@ igt_main
 		igt_skip_on(gen > LAST_KNOWN_GEN);
 	}
 
-	/* __for_each_physical_engine switches context to all engines. */
-
 	igt_fixture {
 		igt_fork_hang_detector(i915);
 	}
 
 	igt_subtest_with_dynamic("nonpriv") {
-		test_each_engine(e, i915, has_context_isolation)
-			nonpriv(i915, e, 0);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			nonpriv(i915, &cfg, e, 0);
 	}
 
 	igt_subtest_with_dynamic("nonpriv-switch") {
-		test_each_engine(e, i915, has_context_isolation)
-			nonpriv(i915, e, DIRTY2);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			nonpriv(i915, &cfg, e, DIRTY2);
 	}
 
 	igt_subtest_with_dynamic("clean") {
-		test_each_engine(e, i915, has_context_isolation)
-			isolation(i915, e, 0);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			isolation(i915, &cfg, e, 0);
 	}
 
 	igt_subtest_with_dynamic("dirty-create") {
-		test_each_engine(e, i915, has_context_isolation)
-			isolation(i915, e, DIRTY1);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			isolation(i915, &cfg, e, DIRTY1);
 	}
 
 	igt_subtest_with_dynamic("dirty-switch") {
-		test_each_engine(e, i915, has_context_isolation)
-			isolation(i915, e, DIRTY2);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			isolation(i915, &cfg, e, DIRTY2);
 	}
 
 	igt_subtest_with_dynamic("preservation") {
-		test_each_engine(e, i915, has_context_isolation)
-			preservation(i915, e, 0);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			preservation(i915, &cfg, e, 0);
 	}
 
 	igt_subtest_with_dynamic("preservation-S3") {
-		test_each_engine(e, i915, has_context_isolation)
-			preservation(i915, e, S3);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			preservation(i915, &cfg, e, S3);
 	}
 
 	igt_subtest_with_dynamic("preservation-S4") {
-		test_each_engine(e, i915, has_context_isolation)
-			preservation(i915, e, S4);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			preservation(i915, &cfg, e, S4);
 	}
 
 	igt_fixture {
@@ -981,8 +987,8 @@ igt_main
 	igt_subtest_with_dynamic("preservation-reset") {
 		igt_hang_t hang = igt_allow_hang(i915, 0, 0);
 
-		test_each_engine(e, i915, has_context_isolation)
-			preservation(i915, e, RESET);
+		test_each_engine(e, i915, &cfg, has_context_isolation)
+			preservation(i915, &cfg, e, RESET);
 
 		igt_disallow_hang(i915, hang);
 	}
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 24/74] tests/i915/gem_exec_async: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_async.c | 32 ++++++++++++++++++++------------
 1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_exec_async.c b/tests/i915/gem_exec_async.c
index 412ad737..121ef238 100644
--- a/tests/i915/gem_exec_async.c
+++ b/tests/i915/gem_exec_async.c
@@ -26,7 +26,7 @@
 
 IGT_TEST_DESCRIPTION("Check that we can issue concurrent writes across the engines.");
 
-static void store_dword(int fd, unsigned ring,
+static void store_dword(int fd, const intel_ctx_t *ctx, unsigned ring,
 			uint32_t target, uint32_t offset, uint32_t value)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -42,6 +42,7 @@ static void store_dword(int fd, unsigned ring,
 	execbuf.flags = ring;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = target;
@@ -79,7 +80,8 @@ static void store_dword(int fd, unsigned ring,
 	gem_close(fd, obj[1].handle);
 }
 
-static void one(int fd, unsigned engine, unsigned int flags)
+static void one(int fd, const intel_ctx_t *ctx,
+		unsigned engine, unsigned int flags)
 #define FORKED (1 << 0)
 {
 	const struct intel_execution_engine2 *e;
@@ -93,10 +95,11 @@ static void one(int fd, unsigned engine, unsigned int flags)
 	 * the scratch for write. Then on the other rings try and
 	 * write into that target. If it blocks we hang the GPU...
 	 */
-	spin = igt_spin_new(fd, .engine = engine, .dependency = scratch);
+	spin = igt_spin_new(fd, .ctx = ctx, .engine = engine,
+			    .dependency = scratch);
 
 	i = 0;
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		if (e->flags == engine)
 			continue;
 
@@ -105,9 +108,9 @@ static void one(int fd, unsigned engine, unsigned int flags)
 
 		if (flags & FORKED) {
 			igt_fork(child, 1)
-				store_dword(fd, e->flags, scratch, 4*i, ~i);
+				store_dword(fd, ctx, e->flags, scratch, 4*i, ~i);
 		} else {
-			store_dword(fd, e->flags, scratch, 4*i, ~i);
+			store_dword(fd, ctx, e->flags, scratch, 4*i, ~i);
 		}
 		i++;
 	}
@@ -134,13 +137,14 @@ static bool has_async_execbuf(int fd)
 	return async > 0;
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		igt_dynamic_f("%s", (e)->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
@@ -148,17 +152,21 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_mmap_wc(fd);
 		igt_require(has_async_execbuf(fd));
+
+		ctx = intel_ctx_create_all_physical(fd);
+
 		igt_fork_hang_detector(fd);
 	}
 
-	test_each_engine("concurrent-writes", fd, e)
-		one(fd, e->flags, 0);
+	test_each_engine("concurrent-writes", fd, ctx, e)
+		one(fd, ctx, e->flags, 0);
 
-	test_each_engine("forked-writes", fd, e)
-		one(fd, e->flags, FORKED);
+	test_each_engine("forked-writes", fd, ctx, e)
+		one(fd, ctx, e->flags, FORKED);
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 25/74] tests/i915/sysfs_clients: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/sysfs_clients.c | 87 ++++++++++++++++++++------------------
 1 file changed, 46 insertions(+), 41 deletions(-)

diff --git a/tests/i915/sysfs_clients.c b/tests/i915/sysfs_clients.c
index 0b7066c0..5e8fcb56 100644
--- a/tests/i915/sysfs_clients.c
+++ b/tests/i915/sysfs_clients.c
@@ -18,12 +18,12 @@
 
 #include "drmtest.h"
 #include "i915/gem.h"
-#include "i915/gem_context.h"
 #include "i915/gem_engine_topology.h"
 #include "i915/gem_mman.h"
 #include "igt_aux.h"
 #include "igt_dummyload.h"
 #include "igt_sysfs.h"
+#include "intel_ctx.h"
 #include "ioctl_wrappers.h"
 
 #define __require_within_epsilon(x, ref, tol_up, tol_down) \
@@ -392,34 +392,26 @@ static uint64_t measured_usleep(unsigned int usec)
 	return igt_nsec_elapsed(&tv);
 }
 
-static int reopen_client(int i915)
-{
-	int clone;
-
-	clone = gem_reopen_driver(i915);
-	gem_context_copy_engines(i915, 0, clone, 0);
-	close(i915);
-
-	return clone;
-}
-
 static void
-busy_one(int i915, int clients, const struct intel_execution_engine2 *e)
+busy_one(int i915, int clients, const intel_ctx_cfg_t *cfg,
+	 const struct intel_execution_engine2 *e)
 {
 	int64_t active, idle, old, other[MAX_CLASS];
 	struct timespec tv;
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin;
 	uint64_t delay;
 	int me;
 
 	/* Create a fresh client with 0 runtime */
-	i915 = reopen_client(i915);
+	i915 = gem_reopen_driver(i915);
 
 	me = find_me(clients, getpid());
 	igt_assert(me != -1);
 
+	ctx = intel_ctx_create(i915, cfg);
 	spin = igt_spin_new(i915,
-			    gem_context_clone_with_engines(i915, 0),
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .flags = IGT_SPIN_POLL_RUN);
 	igt_spin_busywait_until_started(spin);
@@ -471,7 +463,7 @@ busy_one(int i915, int clients, const struct intel_execution_engine2 *e)
 		igt_assert(idle >= active);
 	}
 
-	gem_context_destroy(i915, spin->execbuf.rsvd1);
+	intel_ctx_destroy(i915, ctx);
 
 	/* And finally after the executing context is no more */
 	old = read_runtime(me, e->class);
@@ -512,28 +504,29 @@ busy_one(int i915, int clients, const struct intel_execution_engine2 *e)
 	close(i915);
 }
 
-static void busy_all(int i915, int clients)
+static void busy_all(int i915, int clients, const intel_ctx_cfg_t *cfg)
 {
 	const struct intel_execution_engine2 *e;
 	int64_t active[MAX_CLASS];
 	int64_t idle[MAX_CLASS];
 	int64_t old[MAX_CLASS];
 	uint64_t classes = 0;
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin;
 	int expect = 0;
 	int64_t delay;
 	int me;
 
 	/* Create a fresh client with 0 runtime */
-	i915 = reopen_client(i915);
+	i915 = gem_reopen_driver(i915);
 
 	me = find_me(clients, getpid());
 	igt_assert(me != -1);
 
-	spin = igt_spin_new(i915,
-			    gem_context_clone_with_engines(i915, 0),
+	ctx = intel_ctx_create(i915, cfg);
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .flags = IGT_SPIN_POLL_RUN);
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
@@ -579,7 +572,7 @@ static void busy_all(int i915, int clients)
 		igt_assert(idle[i] >= active[i]);
 	}
 
-	gem_context_destroy(i915, spin->execbuf.rsvd1);
+	intel_ctx_destroy(i915, ctx);
 	igt_spin_free(i915, spin);
 
 	/* And finally after the executing context is no more */
@@ -596,17 +589,19 @@ static void busy_all(int i915, int clients)
 }
 
 static void
-split_child(int i915, int clients,
+split_child(int i915, int clients, const intel_ctx_cfg_t *cfg,
 	    const struct intel_execution_engine2 *e,
 	    int sv)
 {
 	int64_t runtime[2] = {};
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin;
 	int go = 1;
 
-	i915 = reopen_client(i915);
+	i915 = gem_reopen_driver(i915);
 
-	spin = igt_spin_new(i915, .engine = e->flags);
+	ctx = intel_ctx_create(i915, cfg);
+	spin = igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
 	igt_spin_end(spin);
 	gem_sync(i915, spin->handle);
 
@@ -626,12 +621,14 @@ split_child(int i915, int clients,
 	igt_spin_free(i915, spin);
 
 	runtime[0] = read_runtime(find_me(clients, getpid()), e->class);
+	intel_ctx_destroy(i915, ctx);
 	write(sv, runtime, sizeof(runtime));
 }
 
 static void
-__split(int i915, int clients, const struct intel_execution_engine2 *e, int f,
-	void (*fn)(int i915, int clients,
+__split(int i915, int clients, const intel_ctx_cfg_t *cfg,
+	const struct intel_execution_engine2 *e, int f,
+	void (*fn)(int i915, int clients, const intel_ctx_cfg_t *cfg,
 		   const struct intel_execution_engine2 *e,
 		   int sv))
 {
@@ -652,7 +649,7 @@ __split(int i915, int clients, const struct intel_execution_engine2 *e, int f,
 
 		igt_assert(socketpair(AF_UNIX, SOCK_DGRAM, 0, c->sv) == 0);
 		igt_fork(child, 1)
-			fn(i915, clients, e, c->sv[1]);
+			fn(i915, clients, cfg, e, c->sv[1]);
 
 		read(c->sv[0], &go, sizeof(go));
 	}
@@ -720,13 +717,14 @@ __split(int i915, int clients, const struct intel_execution_engine2 *e, int f,
 }
 
 static void
-split(int i915, int clients, const struct intel_execution_engine2 *e, int f)
+split(int i915, int clients, const intel_ctx_cfg_t *cfg,
+      const struct intel_execution_engine2 *e, int f)
 {
-	__split(i915, clients, e, f, split_child);
+	__split(i915, clients, cfg, e, f, split_child);
 }
 
 static void
-sema_child(int i915, int clients,
+sema_child(int i915, int clients, const intel_ctx_cfg_t *cfg,
 	   const struct intel_execution_engine2 *e,
 	   int sv)
 {
@@ -739,9 +737,12 @@ sema_child(int i915, int clients,
 		.buffer_count = 1,
 		.flags = e->flags,
 	};
+	const intel_ctx_t *ctx;
 	uint32_t *cs, *sema;
 
-	i915 = reopen_client(i915);
+	i915 = gem_reopen_driver(i915);
+	ctx = intel_ctx_create(i915, cfg);
+	execbuf.rsvd1 = ctx->id;
 
 	obj.handle = gem_create(i915, 4096);
 	obj.offset = obj.handle << 12;
@@ -771,6 +772,7 @@ sema_child(int i915, int clients,
 	*sema = 0;
 	gem_execbuf(i915, &execbuf);
 	gem_close(i915, obj.handle);
+	intel_ctx_destroy(i915, ctx);
 
 	write(sv, sema, sizeof(*sema));
 	read(sv, sema, sizeof(*sema));
@@ -794,9 +796,10 @@ sema_child(int i915, int clients,
 }
 
 static void
-sema(int i915, int clients, const struct intel_execution_engine2 *e, int f)
+sema(int i915, int clients, const intel_ctx_cfg_t *cfg,
+     const struct intel_execution_engine2 *e, int f)
 {
-	__split(i915, clients, e, f, sema_child);
+	__split(i915, clients, cfg, e, f, sema_child);
 }
 
 static int read_all(int clients, pid_t pid, int class, uint64_t *runtime)
@@ -944,21 +947,23 @@ static bool has_busy(int clients)
 static void test_busy(int i915, int clients)
 {
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg;
 	const int frac[] = { 10, 25, 50 };
 
 	igt_fixture {
 		igt_require(gem_has_contexts(i915));
 		igt_require(has_busy(clients));
+		cfg = intel_ctx_cfg_all_physical(i915);
 	}
 
 	igt_subtest_with_dynamic("busy") {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_cfg_engine(i915, &cfg, e) {
 			if (!gem_class_can_store_dword(i915, e->class))
 				continue;
 			igt_dynamic_f("%s", e->name) {
 				gem_quiescent_gpu(i915);
 				igt_fork(child, 1)
-					busy_one(i915, clients, e);
+					busy_one(i915, clients, &cfg, e);
 				igt_waitchildren();
 				gem_quiescent_gpu(i915);
 			}
@@ -967,7 +972,7 @@ static void test_busy(int i915, int clients)
 		igt_dynamic("all") {
 			gem_quiescent_gpu(i915);
 			igt_fork(child, 1)
-				busy_all(i915, clients);
+				busy_all(i915, clients, &cfg);
 			igt_waitchildren();
 			gem_quiescent_gpu(i915);
 		}
@@ -975,10 +980,10 @@ static void test_busy(int i915, int clients)
 
 	for (int i = 0; i < ARRAY_SIZE(frac); i++) {
 		igt_subtest_with_dynamic_f("split-%d", frac[i]) {
-			__for_each_physical_engine(i915, e) {
+			for_each_ctx_cfg_engine(i915, &cfg, e) {
 				igt_dynamic_f("%s", e->name) {
 					gem_quiescent_gpu(i915);
-					split(i915, clients, e, frac[i]);
+					split(i915, clients, &cfg, e, frac[i]);
 					gem_quiescent_gpu(i915);
 				}
 			}
@@ -993,13 +998,13 @@ static void test_busy(int i915, int clients)
 
 		for (int i = 0; i < ARRAY_SIZE(frac); i++) {
 			igt_subtest_with_dynamic_f("sema-%d", frac[i]) {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_cfg_engine(i915, &cfg, e) {
 					if (!gem_class_has_mutable_submission(i915, e->class))
 						continue;
 
 					igt_dynamic_f("%s", e->name) {
 						igt_drop_caches_set(i915, DROP_RESET_ACTIVE);
-						sema(i915, clients, e, frac[i]);
+						sema(i915, clients, &cfg, e, frac[i]);
 						gem_quiescent_gpu(i915);
 					}
 					igt_drop_caches_set(i915, DROP_RESET_ACTIVE);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 26/74] tests/i915/gem_exec_fair: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_fair.c | 112 +++++++++++++++++++++----------------
 1 file changed, 65 insertions(+), 47 deletions(-)

diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
index c1a71f77..5e7e9e66 100644
--- a/tests/i915/gem_exec_fair.c
+++ b/tests/i915/gem_exec_fair.c
@@ -224,7 +224,7 @@ static void delay(int i915,
 }
 
 static struct drm_i915_gem_exec_object2
-delay_create(int i915, uint32_t ctx,
+delay_create(int i915, const intel_ctx_t *ctx,
 	     const struct intel_execution_engine2 *e,
 	     uint64_t target_ns)
 {
@@ -235,7 +235,7 @@ delay_create(int i915, uint32_t ctx,
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 		.flags = e->flags,
 	};
 
@@ -325,7 +325,8 @@ static void tslog(int i915,
 }
 
 static struct drm_i915_gem_exec_object2
-tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e)
+tslog_create(int i915, const intel_ctx_t *ctx,
+	     const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_exec_object2 obj = {
 		.handle = batch_create(i915),
@@ -334,7 +335,7 @@ tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 		.flags = e->flags,
 	};
 
@@ -361,7 +362,8 @@ static int cmp_u32(const void *A, const void *B)
 }
 
 static uint32_t
-read_ctx_timestamp(int i915, const struct intel_execution_engine2 *e)
+read_ctx_timestamp(int i915, const intel_ctx_t *ctx,
+		   const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_relocation_entry reloc;
 	struct drm_i915_gem_exec_object2 obj = {
@@ -373,6 +375,7 @@ read_ctx_timestamp(int i915, const struct intel_execution_engine2 *e)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
+		.rsvd1 = ctx->id,
 		.flags = e->flags,
 	};
 	const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
@@ -414,23 +417,31 @@ read_ctx_timestamp(int i915, const struct intel_execution_engine2 *e)
 	return ts;
 }
 
-static bool has_ctx_timestamp(int i915, const struct intel_execution_engine2 *e)
+static bool has_ctx_timestamp(int i915, const intel_ctx_cfg_t *cfg,
+			      const struct intel_execution_engine2 *e)
 {
 	const int gen = intel_gen(intel_get_drm_devid(i915));
+	const intel_ctx_t *tmp_ctx;
+	uint32_t timestamp;
 
 	if (gen == 8 && e->class == I915_ENGINE_CLASS_VIDEO)
 		return false; /* looks fubar */
 
-	return read_ctx_timestamp(i915, e);
+	tmp_ctx = intel_ctx_create(i915, cfg);
+	timestamp = read_ctx_timestamp(i915, tmp_ctx, e);
+	intel_ctx_destroy(i915, tmp_ctx);
+
+	return timestamp;
 }
 
 static struct intel_execution_engine2
-pick_random_engine(int i915, const struct intel_execution_engine2 *not)
+pick_random_engine(int i915, const intel_ctx_cfg_t *cfg,
+		   const struct intel_execution_engine2 *not)
 {
 	const struct intel_execution_engine2 *e;
 	unsigned int count = 0;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (e->flags == not->flags)
 			continue;
 		if (!gem_class_has_mutable_submission(i915, e->class))
@@ -441,7 +452,7 @@ pick_random_engine(int i915, const struct intel_execution_engine2 *not)
 		return *not;
 
 	count = rand() % count;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (e->flags == not->flags)
 			continue;
 		if (!gem_class_has_mutable_submission(i915, e->class))
@@ -453,7 +464,7 @@ pick_random_engine(int i915, const struct intel_execution_engine2 *not)
 	return *e;
 }
 
-static void fair_child(int i915, uint32_t ctx,
+static void fair_child(int i915, const intel_ctx_t *ctx,
 		       const struct intel_execution_engine2 *e,
 		       uint64_t frame_ns,
 		       int timeline,
@@ -494,7 +505,7 @@ static void fair_child(int i915, uint32_t ctx,
 
 	srandom(getpid());
 	if (flags & F_PING)
-		ping = pick_random_engine(i915, e);
+		ping = pick_random_engine(i915, &ctx->cfg, e);
 	obj[0] = tslog_create(i915, ctx, &ping);
 
 	/* Synchronize with other children/parent upon construction */
@@ -514,7 +525,7 @@ static void fair_child(int i915, uint32_t ctx,
 		struct drm_i915_gem_execbuffer2 execbuf = {
 			.buffers_ptr = to_user_pointer(obj),
 			.buffer_count = 3,
-			.rsvd1 = ctx,
+			.rsvd1 = ctx->id,
 			.rsvd2 = -1,
 			.flags = aux_flags,
 		};
@@ -636,7 +647,7 @@ static void timeline_advance(int timeline, int delay_ns)
 	sw_sync_timeline_inc(timeline, 1);
 }
 
-static void fairness(int i915,
+static void fairness(int i915, const intel_ctx_cfg_t *cfg,
 		     const struct intel_execution_engine2 *e,
 		     int duration, unsigned int flags)
 {
@@ -649,7 +660,7 @@ static void fairness(int i915,
 		int parent[2];
 	} lnk;
 
-	igt_require(has_ctx_timestamp(i915, e));
+	igt_require(has_ctx_timestamp(i915, cfg, e));
 	igt_require(gem_class_has_mutable_submission(i915, e->class));
 	if (flags & (F_ISOLATE | F_PING))
 		igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
@@ -713,12 +724,12 @@ static void fairness(int i915,
 		if (flags & F_PING) { /* fill the others with light bg load */
 			struct intel_execution_engine2 *ping;
 
-			__for_each_physical_engine(i915, ping) {
+			for_each_ctx_cfg_engine(i915, cfg, ping) {
 				if (ping->flags == e->flags)
 					continue;
 
 				igt_fork(child, 1) {
-					uint32_t ctx = gem_context_clone_with_engines(i915, 0);
+					const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
 
 					fair_child(i915, ctx, ping,
 						   child_ns / 8,
@@ -727,7 +738,7 @@ static void fairness(int i915,
 						   &result[nchild],
 						   NULL, NULL, -1, -1);
 
-					gem_context_destroy(i915, ctx);
+					intel_ctx_destroy(i915, ctx);
 				}
 			}
 		}
@@ -735,26 +746,24 @@ static void fairness(int i915,
 		getrusage(RUSAGE_CHILDREN, &old_usage);
 		igt_nsec_elapsed(memset(&tv, 0, sizeof(tv)));
 		igt_fork(child, nchild) {
-			uint32_t ctx;
+			const intel_ctx_t *ctx;
 
 			if (flags & F_ISOLATE) {
-				int clone, dmabuf = -1;
+				int dmabuf = -1;
 
 				if (common)
 					dmabuf = prime_handle_to_fd(i915, common);
 
-				clone = gem_reopen_driver(i915);
-				gem_context_copy_engines(i915, 0, clone, 0);
-				i915 = clone;
+				i915 = gem_reopen_driver(i915);
 
 				if (dmabuf != -1)
 					common = prime_fd_to_handle(i915, dmabuf);
 			}
 
-			ctx = gem_context_clone_with_engines(i915, 0);
+			ctx = intel_ctx_create(i915, cfg);
 
 			if (flags & F_VIP && child == 0) {
-				gem_context_set_priority(i915, ctx, 1023);
+				gem_context_set_priority(i915, ctx->id, 1023);
 				flags |= F_FLOW;
 			}
 			if (flags & F_RRUL && child == 0)
@@ -766,7 +775,7 @@ static void fairness(int i915,
 				   &result[child], &iqr[child],
 				   lnk.child[1], lnk.parent[0]);
 
-			gem_context_destroy(i915, ctx);
+			intel_ctx_destroy(i915, ctx);
 		}
 
 		{
@@ -911,7 +920,7 @@ static void fairness(int i915,
 }
 
 static void deadline_child(int i915,
-			   uint32_t ctx,
+			   const intel_ctx_t *ctx,
 			   const struct intel_execution_engine2 *e,
 			   uint32_t handle,
 			   int timeline,
@@ -931,7 +940,7 @@ static void deadline_child(int i915,
 		.buffers_ptr = to_user_pointer(obj),
 		.buffer_count = ARRAY_SIZE(obj),
 		.flags = I915_EXEC_FENCE_OUT | e->flags,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 	};
 	unsigned int seq = 1;
 	int prev = -1, next = -1;
@@ -976,11 +985,12 @@ static void deadline_child(int i915,
 	close(prev);
 }
 
-static struct intel_execution_engine2 pick_default(int i915)
+static struct intel_execution_engine2
+pick_default(int i915, const intel_ctx_cfg_t *cfg)
 {
 	const struct intel_execution_engine2 *e;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (!e->flags)
 			return *e;
 	}
@@ -988,11 +998,12 @@ static struct intel_execution_engine2 pick_default(int i915)
 	return (struct intel_execution_engine2){};
 }
 
-static struct intel_execution_engine2 pick_engine(int i915, const char *name)
+static struct intel_execution_engine2
+pick_engine(int i915, const intel_ctx_cfg_t *cfg, const char *name)
 {
 	const struct intel_execution_engine2 *e;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (!strcmp(e->name, name))
 			return *e;
 	}
@@ -1029,15 +1040,16 @@ static uint64_t time_get_mono_ns(void)
 	return tv.tv_sec * NSEC64 + tv.tv_nsec;
 }
 
-static void deadline(int i915, int duration, unsigned int flags)
+static void deadline(int i915, const intel_ctx_cfg_t *cfg,
+		     int duration, unsigned int flags)
 {
 	const int64_t frame_ns = 33670 * 1000; /* 29.7fps */
 	const int64_t parent_ns = 400 * 1000;
 	const int64_t switch_ns = 50 * 1000;
 	const int64_t overhead_ns = /* estimate timeslicing overhead */
 		(frame_ns / 1000 / 1000 + 2) * switch_ns + parent_ns;
-	struct intel_execution_engine2 pe = pick_default(i915);
-	struct intel_execution_engine2 ve = pick_engine(i915, "vcs0");
+	struct intel_execution_engine2 pe = pick_default(i915, cfg);
+	struct intel_execution_engine2 ve = pick_engine(i915, cfg, "vcs0");
 	struct drm_i915_gem_exec_fence *fences = calloc(sizeof(*fences), 32);
 	struct drm_i915_gem_exec_object2 *obj = calloc(sizeof(*obj), 32);
 	struct drm_i915_gem_execbuffer2 execbuf = {
@@ -1048,14 +1060,15 @@ static void deadline(int i915, int duration, unsigned int flags)
 			I915_EXEC_FENCE_ARRAY |
 			I915_EXEC_FENCE_OUT
 	};
+	const intel_ctx_t *delay_ctx;
 	int *ctl;
 
 	igt_require(has_syncobj(i915));
 	igt_require(has_fence_array(i915));
 	igt_require(has_mi_math(i915, &pe));
-	igt_require(has_ctx_timestamp(i915, &pe));
+	igt_require(has_ctx_timestamp(i915, cfg, &pe));
 	igt_require(has_mi_math(i915, &ve));
-	igt_require(has_ctx_timestamp(i915, &ve));
+	igt_require(has_ctx_timestamp(i915, cfg, &ve));
 	igt_assert(obj && fences);
 	if (flags & DL_PRIO)
 		igt_require(gem_scheduler_has_preemption(i915));
@@ -1063,9 +1076,10 @@ static void deadline(int i915, int duration, unsigned int flags)
 	ctl = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 	igt_assert(ctl != MAP_FAILED);
 
-	obj[0] = delay_create(i915, 0, &pe, parent_ns);
+	delay_ctx = intel_ctx_create(i915, cfg);
+	obj[0] = delay_create(i915, delay_ctx, &pe, parent_ns);
 	if (flags & DL_PRIO)
-		gem_context_set_priority(i915, 0, 1023);
+		gem_context_set_priority(i915, delay_ctx->id, 1023);
 	if (intel_gen(intel_get_drm_devid(i915)) < 8)
 		execbuf.flags |= I915_EXEC_SECURE;
 	for (int n = 1; n <= 5; n++) {
@@ -1092,7 +1106,7 @@ static void deadline(int i915, int duration, unsigned int flags)
 
 		*ctl = 0;
 		igt_fork(child, num_children) {
-			uint32_t ctx = gem_context_clone_with_engines(i915, 0);
+			const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
 
 			deadline_child(i915, ctx, &ve, obj[child + 1].handle,
 				       timeline, child_ns,
@@ -1100,7 +1114,7 @@ static void deadline(int i915, int duration, unsigned int flags)
 				       link[child].parent[0],
 				       ctl, flags);
 
-			gem_context_destroy(i915, ctx);
+			intel_ctx_destroy(i915, ctx);
 		}
 
 		for (int i = 0; i < num_children; i++)
@@ -1174,6 +1188,7 @@ static void deadline(int i915, int duration, unsigned int flags)
 		gem_quiescent_gpu(i915);
 	}
 
+	intel_ctx_destroy(i915, delay_ctx);
 	gem_close(i915, obj[0].handle);
 	free(obj);
 	free(fences);
@@ -1281,6 +1296,7 @@ igt_main
 		{}
 	};
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg;
 	int i915 = -1;
 
 	igt_fixture {
@@ -1296,6 +1312,8 @@ igt_main
 		igt_require(gem_scheduler_enabled(i915));
 		igt_require(gem_scheduler_has_ctx_priority(i915));
 
+		cfg = intel_ctx_cfg_all_physical(i915);
+
 		igt_info("CS timestamp frequency: %d\n",
 			 read_timestamp_frequency(i915));
 		igt_require(has_mi_math(i915, NULL));
@@ -1309,7 +1327,7 @@ igt_main
 			continue;
 
 		igt_subtest_with_dynamic_f("basic-%s", f->name)  {
-			__for_each_physical_engine(i915, e) {
+			for_each_ctx_cfg_engine(i915, &cfg, e) {
 				if (!has_mi_math(i915, e))
 					continue;
 
@@ -1320,19 +1338,19 @@ igt_main
 					continue;
 
 				igt_dynamic_f("%s", e->name)
-					fairness(i915, e, 1, f->flags);
+					fairness(i915, &cfg, e, 1, f->flags);
 			}
 		}
 	}
 
 	igt_subtest("basic-deadline")
-		deadline(i915, 2, 0);
+		deadline(i915, &cfg, 2, 0);
 	igt_subtest("deadline-prio")
-		deadline(i915, 2, DL_PRIO);
+		deadline(i915, &cfg, 2, DL_PRIO);
 
 	for (typeof(*fair) *f = fair; f->name; f++) {
 		igt_subtest_with_dynamic_f("fair-%s", f->name)  {
-			__for_each_physical_engine(i915, e) {
+			for_each_ctx_cfg_engine(i915, &cfg, e) {
 				if (!has_mi_math(i915, e))
 					continue;
 
@@ -1343,7 +1361,7 @@ igt_main
 					continue;
 
 				igt_dynamic_f("%s", e->name)
-					fairness(i915, e, 5, f->flags);
+					fairness(i915, &cfg, e, 5, f->flags);
 			}
 		}
 	}
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 27/74] tests/i915/gem_spin_batch: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_spin_batch.c | 81 +++++++++++++++++++++----------------
 1 file changed, 46 insertions(+), 35 deletions(-)

diff --git a/tests/i915/gem_spin_batch.c b/tests/i915/gem_spin_batch.c
index db0af018..cc92c37c 100644
--- a/tests/i915/gem_spin_batch.c
+++ b/tests/i915/gem_spin_batch.c
@@ -34,7 +34,7 @@
 		     "'%s' != '%s' (%lld not within %d%% tolerance of %lld)\n",\
 		     #x, #ref, (long long)x, tolerance, (long long)ref)
 
-static void spin(int fd,
+static void spin(int fd, const intel_ctx_t *ctx_id,
 		 unsigned int engine,
 		 unsigned int flags,
 		 unsigned int timeout_sec)
@@ -46,10 +46,12 @@ static void spin(int fd,
 	struct timespec itv = { };
 	uint64_t elapsed;
 
-	spin = __igt_spin_new(fd, .engine = engine, .flags = flags);
+	spin = __igt_spin_new(fd, .ctx = ctx_id, .engine = engine,
+			      .flags = flags);
 	while ((elapsed = igt_nsec_elapsed(&tv)) >> 30 < timeout_sec) {
 		igt_spin_t *next =
-			__igt_spin_new(fd, .engine = engine, .flags = flags);
+			__igt_spin_new(fd, .ctx = ctx_id, .engine = engine,
+				       .flags = flags);
 
 		igt_spin_set_timeout(spin,
 				     timeout_100ms - igt_nsec_elapsed(&itv));
@@ -75,21 +77,25 @@ static void spin(int fd,
 #define RESUBMIT_NEW_CTX     (1 << 0)
 #define RESUBMIT_ALL_ENGINES (1 << 1)
 
-static void spin_resubmit(int fd, unsigned int engine, unsigned int flags)
+static void spin_resubmit(int fd, const intel_ctx_t *ctx,
+			  unsigned int engine, unsigned int flags)
 {
+	const intel_ctx_t *new_ctx = NULL;
 	igt_spin_t *spin;
 
 	if (flags & RESUBMIT_NEW_CTX)
 		igt_require(gem_has_contexts(fd));
 
-	spin = __igt_spin_new(fd, .engine = engine);
-	if (flags & RESUBMIT_NEW_CTX)
-		spin->execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
+	spin = __igt_spin_new(fd, .ctx = ctx, .engine = engine);
+	if (flags & RESUBMIT_NEW_CTX) {
+		new_ctx = intel_ctx_create(fd, &ctx->cfg);
+		spin->execbuf.rsvd1 = new_ctx->id;
+	}
 
 	if (flags & RESUBMIT_ALL_ENGINES) {
 		const struct intel_execution_engine2 *other;
 
-		for_each_context_engine(fd, spin->execbuf.rsvd1, other) {
+		for_each_ctx_engine(fd, ctx, other) {
 			spin->execbuf.flags &= ~0x3f;
 			spin->execbuf.flags |= other->flags;
 			gem_execbuf(fd, &spin->execbuf);
@@ -100,8 +106,8 @@ static void spin_resubmit(int fd, unsigned int engine, unsigned int flags)
 	igt_spin_end(spin);
 	gem_sync(fd, spin->handle);
 
-	if (spin->execbuf.rsvd1)
-		gem_context_destroy(fd, spin->execbuf.rsvd1);
+	if (flags & RESUBMIT_NEW_CTX)
+		intel_ctx_destroy(fd, new_ctx);
 
 	igt_spin_free(fd, spin);
 }
@@ -112,45 +118,44 @@ static void spin_exit_handler(int sig)
 }
 
 static void
-spin_on_all_engines(int fd, unsigned long flags, unsigned int timeout_sec)
+spin_on_all_engines(int fd, const intel_ctx_t *ctx,
+		    unsigned long flags, unsigned int timeout_sec)
 {
 	const struct intel_execution_engine2 *e2;
 
-	__for_each_physical_engine(fd, e2) {
+	for_each_ctx_engine(fd, ctx, e2) {
 		igt_fork(child, 1) {
 			igt_install_exit_handler(spin_exit_handler);
-			spin(fd, e2->flags, flags, timeout_sec);
+			spin(fd, ctx, e2->flags, flags, timeout_sec);
 		}
 	}
 
 	igt_waitchildren();
 }
 
-static void spin_all(int i915, unsigned int flags)
+static void spin_all(int i915, const intel_ctx_t *ctx, unsigned int flags)
 #define PARALLEL_SPIN_NEW_CTX BIT(0)
 {
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg = ctx->cfg;
 	struct igt_spin *spin, *n;
 	IGT_LIST_HEAD(list);
 
-	__for_each_physical_engine(i915, e) {
-		uint32_t ctx;
-
+	for_each_ctx_cfg_engine(i915, &cfg, e) {
 		if (!gem_class_can_store_dword(i915, e->class))
 			continue;
 
-		ctx = 0;
 		if (flags & PARALLEL_SPIN_NEW_CTX)
-			ctx = gem_context_clone_with_engines(i915, 0);
+			ctx = intel_ctx_create(i915, &cfg);
 
 		/* Prevent preemption so only one is allowed on each engine */
 		spin = igt_spin_new(i915,
-				    .ctx_id = ctx,
+				    .ctx = ctx,
 				    .engine = e->flags,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_NO_PREEMPTION));
-		if (ctx)
-			gem_context_destroy(i915, ctx);
+		if (flags & PARALLEL_SPIN_NEW_CTX)
+			intel_ctx_destroy(i915, ctx);
 
 		igt_spin_busywait_until_started(spin);
 		igt_list_move(&spin->link, &list);
@@ -187,11 +192,14 @@ igt_main
 {
 	const struct intel_execution_engine2 *e2;
 	const struct intel_execution_ring *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
+
 		igt_fork_hang_detector(fd);
 	}
 
@@ -202,53 +210,56 @@ igt_main
 				igt_dynamic_f("%s", e->name)
 
 	test_each_legacy_ring("legacy")
-		spin(fd, eb_ring(e), 0, 3);
+		spin(fd, intel_ctx_0(fd), eb_ring(e), 0, 3);
 	test_each_legacy_ring("legacy-resubmit")
-		spin_resubmit(fd, eb_ring(e), 0);
+		spin_resubmit(fd, intel_ctx_0(fd), eb_ring(e), 0);
 	test_each_legacy_ring("legacy-resubmit-new")
-		spin_resubmit(fd, eb_ring(e), RESUBMIT_NEW_CTX);
+		spin_resubmit(fd, intel_ctx_0(fd), eb_ring(e), RESUBMIT_NEW_CTX);
 
 #undef test_each_legcy_ring
 
 	igt_subtest("spin-all")
-		spin_all(fd, 0);
+		spin_all(fd, ctx, 0);
 	igt_subtest("spin-all-new")
-		spin_all(fd, PARALLEL_SPIN_NEW_CTX);
+		spin_all(fd, ctx, PARALLEL_SPIN_NEW_CTX);
 
 #define test_each_engine(test) \
 	igt_subtest_with_dynamic(test) \
-		__for_each_physical_engine(fd, e2) \
+		for_each_ctx_engine(fd, ctx, e2) \
 			igt_dynamic_f("%s", e2->name)
 
 	test_each_engine("engines")
-		spin(fd, e2->flags, 0, 3);
+		spin(fd, ctx, e2->flags, 0, 3);
 
 	test_each_engine("resubmit")
-		spin_resubmit(fd, e2->flags, 0);
+		spin_resubmit(fd, ctx, e2->flags, 0);
 
 	test_each_engine("resubmit-new")
-		spin_resubmit(fd, e2->flags, RESUBMIT_NEW_CTX);
+		spin_resubmit(fd, ctx, e2->flags,
+			      RESUBMIT_NEW_CTX);
 
 	test_each_engine("resubmit-all")
-		spin_resubmit(fd, e2->flags, RESUBMIT_ALL_ENGINES);
+		spin_resubmit(fd, ctx, e2->flags,
+			      RESUBMIT_ALL_ENGINES);
 
 	test_each_engine("resubmit-new-all")
-		spin_resubmit(fd, e2->flags,
+		spin_resubmit(fd, ctx, e2->flags,
 			      RESUBMIT_NEW_CTX |
 			      RESUBMIT_ALL_ENGINES);
 
 #undef test_each_engine
 
 	igt_subtest("spin-each")
-		spin_on_all_engines(fd, 0, 3);
+		spin_on_all_engines(fd, ctx, 0, 3);
 
 	igt_subtest("user-each") {
 		igt_require(has_userptr(fd));
-		spin_on_all_engines(fd, IGT_SPIN_USERPTR, 3);
+		spin_on_all_engines(fd, ctx, IGT_SPIN_USERPTR, 3);
 	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 28/74] tests/i915/gem_exec_store: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_store.c | 36 ++++++++++++++++++++++--------------
 1 file changed, 22 insertions(+), 14 deletions(-)

diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
index 771ee169..e8424439 100644
--- a/tests/i915/gem_exec_store.c
+++ b/tests/i915/gem_exec_store.c
@@ -36,7 +36,8 @@
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
 
-static void store_dword(int fd, const struct intel_execution_engine2 *e)
+static void store_dword(int fd, const intel_ctx_t *ctx,
+			const struct intel_execution_engine2 *e)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -52,6 +53,7 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e)
 	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, 4096);
@@ -93,7 +95,8 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e)
 }
 
 #define PAGES 1
-static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
+static void store_cachelines(int fd, const intel_ctx_t *ctx,
+			     const struct intel_execution_engine2 *e,
 			     unsigned int flags)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -113,6 +116,7 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
 	execbuf.flags = e->flags;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	obj = calloc(execbuf.buffer_count, sizeof(*obj));
 	igt_assert(obj);
@@ -170,7 +174,7 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
-static void store_all(int fd)
+static void store_all(int fd, const intel_ctx_t *ctx)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[2];
@@ -185,7 +189,7 @@ static void store_all(int fd)
 	int i, j;
 
 	nengine = 0;
-	__for_each_physical_engine(fd, engine) {
+	for_each_ctx_engine(fd, ctx, engine) {
 		if (!gem_class_can_store_dword(fd, engine->class))
 			continue;
 		nengine++;
@@ -206,6 +210,7 @@ static void store_all(int fd)
 	execbuf.buffer_count = 2;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
@@ -231,7 +236,7 @@ static void store_all(int fd)
 
 	nengine = 0;
 	intel_detect_and_clear_missed_interrupts(fd);
-	__for_each_physical_engine(fd, engine) {
+	for_each_ctx_engine(fd, ctx, engine) {
 		if (!gem_class_can_store_dword(fd, engine->class))
 			continue;
 
@@ -322,14 +327,15 @@ static int print_welcome(int fd)
 	return ffs(info->gen);
 }
 
-#define test_each_engine(T, i915, e)  \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e)  \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd;
 
 	igt_fixture {
@@ -342,24 +348,26 @@ igt_main
 			igt_device_set_master(fd);
 
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
 
 	igt_subtest("basic")
-		store_all(fd);
+		store_all(fd, ctx);
 
-	test_each_engine("dword", fd, e)
-		store_dword(fd, e);
+	test_each_engine("dword", fd, ctx, e)
+		store_dword(fd, ctx, e);
 
-	test_each_engine("cachelines", fd, e)
-		store_cachelines(fd, e, 0);
+	test_each_engine("cachelines", fd, ctx, e)
+		store_cachelines(fd, ctx, e, 0);
 
-	test_each_engine("pages", fd, e)
-		store_cachelines(fd, e, PAGES);
+	test_each_engine("pages", fd, ctx, e)
+		store_cachelines(fd, ctx, e, PAGES);
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 29/74] tests/amdgpu/amd_prime: Convert to intel_ctx_t

[Jason Ekstrand]

Written totally blind but I'm pretty sure it's right.
---
 tests/amdgpu/amd_prime.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/tests/amdgpu/amd_prime.c b/tests/amdgpu/amd_prime.c
index 537b0bcd..cf8a0ad9 100644
--- a/tests/amdgpu/amd_prime.c
+++ b/tests/amdgpu/amd_prime.c
@@ -172,6 +172,7 @@ static void unplug(struct cork *c)
 static void i915_to_amd(int i915, int amd, amdgpu_device_handle device)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	intel_ctx_cfg_t cfg;
 	struct drm_i915_gem_exec_object2 obj[2];
 	struct drm_i915_gem_execbuffer2 execbuf;
 	const struct intel_execution_engine2 *e;
@@ -180,8 +181,10 @@ static void i915_to_amd(int i915, int amd, amdgpu_device_handle device)
 	unsigned long count;
 	struct cork c;
 
+	cfg = intel_ctx_cfg_all_physical(i915);
+
 	nengine = 0;
-	__for_each_physical_engine(i915, e)
+	for_each_ctx_cfg_engine(i915, &cfg, e)
 		engines[nengine++] = e->flags;
 	igt_require(nengine);
 
@@ -198,14 +201,15 @@ static void i915_to_amd(int i915, int amd, amdgpu_device_handle device)
 
 	count = 0;
 	igt_until_timeout(5) {
-		execbuf.rsvd1 = gem_context_clone_with_engines(i915, 0);
+		const intel_ctx_t *ctx = intel_ctx_create(i915, &cfg);
+		execbuf.rsvd1 = ctx->id;
 
 		for (unsigned n = 0; n < nengine; n++) {
 			execbuf.flags = engines[n];
 			gem_execbuf(i915, &execbuf);
 		}
 
-		gem_context_destroy(i915, execbuf.rsvd1);
+		intel_ctx_destroy(i915, ctx);
 		count++;
 
 		if (!gem_uses_full_ppgtt(i915))
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 30/74] tests/i915/i915_hangman: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/i915_hangman.c | 37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 72e4d8b8..5e865743 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -204,7 +204,7 @@ static void check_error_state(const char *expected_ring_name,
 	igt_assert(found);
 }
 
-static void test_error_state_capture(unsigned ring_id,
+static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
 				     const char *ring_name)
 {
 	uint32_t *batch;
@@ -213,7 +213,7 @@ static void test_error_state_capture(unsigned ring_id,
 
 	clear_error_state();
 
-	hang = igt_hang_ctx(device, 0, ring_id, HANG_ALLOW_CAPTURE);
+	hang = igt_hang_ctx(device, ctx->id, ring_id, HANG_ALLOW_CAPTURE);
 	offset = hang.spin->obj[IGT_SPIN_BATCH].offset;
 
 	batch = gem_mmap__cpu(device, hang.spin->handle, 0, 4096, PROT_READ);
@@ -226,32 +226,34 @@ static void test_error_state_capture(unsigned ring_id,
 }
 
 static void
-test_engine_hang(const struct intel_execution_engine2 *e, unsigned int flags)
+test_engine_hang(const intel_ctx_t *ctx,
+		 const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	const struct intel_execution_engine2 *other;
+	const intel_ctx_t *tmp_ctx;
 	igt_spin_t *spin, *next;
 	IGT_LIST_HEAD(list);
-	uint32_t ctx;
 
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_has_cmdparser(device, e->flags));
 
 	/* Fill all the other engines with background load */
-	__for_each_physical_engine(device, other) {
+	for_each_ctx_engine(device, ctx, other) {
 		if (other->flags == e->flags)
 			continue;
 
-		ctx = gem_context_clone_with_engines(device, 0);
-		spin = __igt_spin_new(device, ctx,
+		tmp_ctx = intel_ctx_create(device, &ctx->cfg);
+		spin = __igt_spin_new(device, .ctx = tmp_ctx,
 				      .engine = other->flags,
 				      .flags = IGT_SPIN_FENCE_OUT);
-		gem_context_destroy(device, ctx);
+		intel_ctx_destroy(device, tmp_ctx);
 
 		igt_list_move(&spin->link, &list);
 	}
 
 	/* And on the target engine, we hang */
 	spin = igt_spin_new(device,
+			    .ctx = ctx,
 			    .engine = e->flags,
 			    .flags = (IGT_SPIN_FENCE_OUT |
 				      IGT_SPIN_NO_PREEMPTION |
@@ -310,13 +312,16 @@ static void hangcheck_unterminated(void)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	igt_hang_t hang = {};
 
 	igt_fixture {
 		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 
-		hang = igt_allow_hang(device, 0, HANG_ALLOW_CAPTURE);
+		ctx = intel_ctx_create_all_physical(device);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
 
 		sysfs = igt_sysfs_open(device);
 		igt_assert(sysfs != -1);
@@ -328,9 +333,9 @@ igt_main
 		test_error_state_basic();
 
 	igt_subtest_with_dynamic("error-state-capture") {
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_error_state_capture(e->flags, e->name);
+				test_error_state_capture(ctx, e->flags, e->name);
 		}
 	}
 
@@ -346,9 +351,9 @@ igt_main
                 ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
 		igt_require(has_gpu_reset > 1);
 
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(e, 0);
+				test_engine_hang(ctx, e, 0);
 		}
 	}
 
@@ -363,9 +368,9 @@ igt_main
 		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
 		igt_require(has_gpu_reset > 1);
 
-		__for_each_physical_engine(device, e) {
+		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(e, IGT_SPIN_INVALID_CS);
+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
 		}
 	}
 
@@ -374,5 +379,7 @@ igt_main
 
 	igt_fixture {
 		igt_disallow_hang(device, hang);
+		intel_ctx_destroy(device, ctx);
+		close(device);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 31/74] tests/i915/gem_ringfill: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ringfill.c | 48 +++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 20 deletions(-)

diff --git a/tests/i915/gem_ringfill.c b/tests/i915/gem_ringfill.c
index 78903707..4fbc7b5d 100644
--- a/tests/i915/gem_ringfill.c
+++ b/tests/i915/gem_ringfill.c
@@ -93,7 +93,7 @@ static void fill_ring(int fd,
 	}
 }
 
-static void setup_execbuf(int fd,
+static void setup_execbuf(int fd, const intel_ctx_t *ctx,
 			  struct drm_i915_gem_execbuffer2 *execbuf,
 			  struct drm_i915_gem_exec_object2 *obj,
 			  struct drm_i915_gem_relocation_entry *reloc,
@@ -114,6 +114,8 @@ static void setup_execbuf(int fd,
 	if (gen > 3 && gen < 6)
 		execbuf->flags |= I915_EXEC_SECURE;
 
+	execbuf->rsvd1 = ctx->id;
+
 	obj[0].handle = gem_create(fd, 4096);
 	gem_write(fd, obj[0].handle, 0, &bbe, sizeof(bbe));
 	execbuf->buffer_count = 1;
@@ -167,7 +169,8 @@ static void setup_execbuf(int fd,
 	check_bo(fd, obj[0].handle);
 }
 
-static void run_test(int fd, unsigned ring, unsigned flags, unsigned timeout)
+static void run_test(int fd, const intel_ctx_t *ctx, unsigned ring,
+		     unsigned flags, unsigned timeout)
 {
 	struct drm_i915_gem_exec_object2 obj[2];
 	struct drm_i915_gem_relocation_entry reloc[1024];
@@ -175,15 +178,15 @@ static void run_test(int fd, unsigned ring, unsigned flags, unsigned timeout)
 	igt_hang_t hang;
 
 	if (flags & (SUSPEND | HIBERNATE)) {
-		run_test(fd, ring, 0, 0);
+		run_test(fd, ctx, ring, 0, 0);
 		gem_quiescent_gpu(fd);
 	}
 
-	setup_execbuf(fd, &execbuf, obj, reloc, ring);
+	setup_execbuf(fd, ctx, &execbuf, obj, reloc, ring);
 
 	memset(&hang, 0, sizeof(hang));
 	if (flags & HANG)
-		hang = igt_hang_ring(fd, ring & ~(3<<13));
+		hang = igt_hang_ctx(fd, ctx->id, ring & ~(3<<13), 0);
 
 	if (flags & (CHILD | FORKED | BOMB)) {
 		int nchild;
@@ -197,16 +200,19 @@ static void run_test(int fd, unsigned ring, unsigned flags, unsigned timeout)
 
 		igt_debug("Forking %d children\n", nchild);
 		igt_fork(child, nchild) {
+			const intel_ctx_t *child_ctx = NULL;
 			if (flags & NEWFD) {
 				int this;
 
 				this = gem_reopen_driver(fd);
-				gem_context_copy_engines(fd, 0, this, 0);
+				child_ctx = intel_ctx_create(fd, &ctx->cfg);
 				fd = this;
 
-				setup_execbuf(fd, &execbuf, obj, reloc, ring);
+				setup_execbuf(fd, child_ctx, &execbuf, obj, reloc, ring);
 			}
 			fill_ring(fd, &execbuf, flags, timeout);
+			if (child_ctx)
+				intel_ctx_destroy(fd, child_ctx);
 		}
 
 		if (flags & SUSPEND)
@@ -234,7 +240,7 @@ static void run_test(int fd, unsigned ring, unsigned flags, unsigned timeout)
 
 	if (flags & (SUSPEND | HIBERNATE)) {
 		gem_quiescent_gpu(fd);
-		run_test(fd, ring, 0, 0);
+		run_test(fd, ctx, ring, 0, 0);
 	}
 }
 
@@ -285,6 +291,7 @@ igt_main
 		{ NULL }
 	}, *m;
 	bool master = false;
+	const intel_ctx_t *ctx;
 	int fd = -1;
 
 	igt_fixture {
@@ -304,22 +311,20 @@ igt_main
 		ring_size = gem_measure_ring_inflight(fd, ALL_ENGINES, 0);
 		igt_info("Ring size: %d batches\n", ring_size);
 		igt_require(ring_size);
+
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	/* Legacy path for selecting "rings". */
 	for (m = modes; m->suffix; m++) {
 		igt_subtest_with_dynamic_f("legacy-%s", m->suffix) {
-			const struct intel_execution_ring *e;
-
 			igt_skip_on(m->flags & NEWFD && master);
 
-			for (e = intel_execution_rings; e->name; e++) {
-				if (!gem_has_ring(fd, eb_ring(e)))
-					continue;
-
+			for_each_ring(e, fd) {
 				igt_dynamic_f("%s", e->name) {
 					igt_require(gem_can_store_dword(fd, eb_ring(e)));
-					run_test(fd, eb_ring(e),
+					run_test(fd, intel_ctx_0(fd),
+						 eb_ring(e),
 						 m->flags,
 						 m->timeout);
 					gem_quiescent_gpu(fd);
@@ -334,12 +339,13 @@ igt_main
 			const struct intel_execution_engine2 *e;
 
 			igt_skip_on(m->flags & NEWFD && master);
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				if (!gem_class_can_store_dword(fd, e->class))
 					continue;
 
 				igt_dynamic_f("%s", e->name) {
-					run_test(fd, e->flags,
+					run_test(fd, ctx,
+						 e->flags,
 						 m->flags,
 						 m->timeout);
 					gem_quiescent_gpu(fd);
@@ -351,17 +357,19 @@ igt_main
 	igt_subtest("basic-all") {
 		const struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (!gem_class_can_store_dword(fd, e->class))
 				continue;
 
 			igt_fork(child, 1)
-				run_test(fd, e->flags, 0, 1);
+				run_test(fd, ctx, e->flags, 0, 1);
 		}
 
 		igt_waitchildren();
 	}
 
-	igt_fixture
+	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
+	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 32/74] tests/prime_busy: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/prime_busy.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/tests/prime_busy.c b/tests/prime_busy.c
index aec76393..5c8e44ab 100644
--- a/tests/prime_busy.c
+++ b/tests/prime_busy.c
@@ -39,7 +39,7 @@ static bool prime_busy(struct pollfd *pfd, bool excl)
 #define HANG 0x4
 #define POLL 0x8
 
-static void busy(int fd, unsigned ring, unsigned flags)
+static void busy(int fd, const intel_ctx_t *ctx, unsigned ring, unsigned flags)
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 	const uint32_t _bbe = MI_BATCH_BUFFER_END;
@@ -62,6 +62,7 @@ static void busy(int fd, unsigned ring, unsigned flags)
 	execbuf.flags = ring;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[SCRATCH].handle = gem_create(fd, 4096);
@@ -185,7 +186,7 @@ static void busy(int fd, unsigned ring, unsigned flags)
 	close(pfd[SCRATCH].fd);
 }
 
-static void test_mode(int fd, unsigned int flags)
+static void test_mode(int fd, const intel_ctx_t *ctx, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e;
 	igt_hang_t hang = {};
@@ -195,7 +196,7 @@ static void test_mode(int fd, unsigned int flags)
 	else
 		hang = igt_allow_hang(fd, 0, 0);
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		if (!gem_class_can_store_dword(fd, e->class))
 			continue;
 
@@ -203,7 +204,7 @@ static void test_mode(int fd, unsigned int flags)
 			continue;
 
 		igt_dynamic_f("%s", e->name)
-			busy(fd, e->flags, flags);
+			busy(fd, ctx, e->flags, flags);
 	}
 
 	if ((flags & HANG) == 0)
@@ -214,11 +215,13 @@ static void test_mode(int fd, unsigned int flags)
 
 igt_main
 {
+	const intel_ctx_t *ctx;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	igt_subtest_group {
@@ -237,13 +240,15 @@ igt_main
 
 		for (const struct mode *m = modes; m->name; m++) {
 			igt_subtest_with_dynamic(m->name)
-				test_mode(fd, m->flags);
+				test_mode(fd, ctx, m->flags);
 
 			igt_subtest_with_dynamic_f("%s-wait", m->name)
-				test_mode(fd, m->flags | POLL);
+				test_mode(fd, ctx, m->flags | POLL);
 		}
 	}
 
-	igt_fixture
+	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
+	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 33/74] tests/prime_vgem: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/prime_vgem.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/tests/prime_vgem.c b/tests/prime_vgem.c
index 07ff69a2..3b3b679a 100644
--- a/tests/prime_vgem.c
+++ b/tests/prime_vgem.c
@@ -558,7 +558,7 @@ static bool prime_busy(int fd, bool excl)
 	return poll(&pfd, 1, 0) == 0;
 }
 
-static void work(int i915, int dmabuf, unsigned ring)
+static void work(int i915, int dmabuf, const intel_ctx_t *ctx, unsigned ring)
 {
 	const int SCRATCH = 0;
 	const int BATCH = 1;
@@ -577,6 +577,7 @@ static void work(int i915, int dmabuf, unsigned ring)
 	execbuf.flags = ring;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[SCRATCH].handle = prime_fd_to_handle(i915, dmabuf);
@@ -653,7 +654,7 @@ static void work(int i915, int dmabuf, unsigned ring)
 	igt_assert(read_busy && write_busy);
 }
 
-static void test_busy(int i915, int vgem, unsigned ring)
+static void test_busy(int i915, int vgem, const intel_ctx_t *ctx, unsigned ring)
 {
 	struct vgem_bo scratch;
 	struct timespec tv;
@@ -667,7 +668,7 @@ static void test_busy(int i915, int vgem, unsigned ring)
 	vgem_create(vgem, &scratch);
 	dmabuf = prime_handle_to_fd(vgem, scratch.handle);
 
-	work(i915, dmabuf, ring);
+	work(i915, dmabuf, ctx, ring);
 
 	/* Calling busy in a loop should be enough to flush the rendering */
 	memset(&tv, 0, sizeof(tv));
@@ -683,7 +684,7 @@ static void test_busy(int i915, int vgem, unsigned ring)
 	close(dmabuf);
 }
 
-static void test_wait(int i915, int vgem, unsigned ring)
+static void test_wait(int i915, int vgem, const intel_ctx_t *ctx, unsigned ring)
 {
 	struct vgem_bo scratch;
 	struct pollfd pfd;
@@ -696,7 +697,7 @@ static void test_wait(int i915, int vgem, unsigned ring)
 	vgem_create(vgem, &scratch);
 	pfd.fd = prime_handle_to_fd(vgem, scratch.handle);
 
-	work(i915, pfd.fd, ring);
+	work(i915, pfd.fd, ctx, ring);
 
 	pfd.events = POLLIN;
 	igt_assert_eq(poll(&pfd, 1, 10000), 1);
@@ -710,7 +711,7 @@ static void test_wait(int i915, int vgem, unsigned ring)
 	close(pfd.fd);
 }
 
-static void test_sync(int i915, int vgem, unsigned ring)
+static void test_sync(int i915, int vgem, const intel_ctx_t *ctx, unsigned ring)
 {
 	struct vgem_bo scratch;
 	uint32_t *ptr;
@@ -727,7 +728,7 @@ static void test_sync(int i915, int vgem, unsigned ring)
 	igt_assert(ptr != MAP_FAILED);
 	gem_close(vgem, scratch.handle);
 
-	work(i915, dmabuf, ring);
+	work(i915, dmabuf, ctx, ring);
 
 	prime_sync_start(dmabuf, false);
 	for (i = 0; i < 1024; i++)
@@ -738,7 +739,7 @@ static void test_sync(int i915, int vgem, unsigned ring)
 	munmap(ptr, scratch.size);
 }
 
-static void test_fence_wait(int i915, int vgem, unsigned ring)
+static void test_fence_wait(int i915, int vgem, const intel_ctx_t *ctx, unsigned ring)
 {
 	struct vgem_bo scratch;
 	uint32_t fence;
@@ -759,7 +760,7 @@ static void test_fence_wait(int i915, int vgem, unsigned ring)
 	igt_assert(ptr != MAP_FAILED);
 
 	igt_fork(child, 1)
-		work(i915, dmabuf, ring);
+		work(i915, dmabuf, ctx, ring);
 
 	sleep(1);
 
@@ -799,7 +800,7 @@ static void test_fence_hang(int i915, int vgem, unsigned flags)
 	igt_assert(ptr != MAP_FAILED);
 	gem_close(vgem, scratch.handle);
 
-	work(i915, dmabuf, 0);
+	work(i915, dmabuf, 0, 0);
 
 	/* The work should have been cancelled */
 
@@ -1041,12 +1042,15 @@ static void test_flip(int i915, int vgem, unsigned hang)
 }
 
 static void test_each_engine(const char *name, int vgem, int i915,
-			     void (*fn)(int i915, int vgem, unsigned int flags))
+			     void (*fn)(int i915, int vgem,
+					const intel_ctx_t *ctx,
+					unsigned int flags))
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = intel_ctx_create_all_physical(i915);
 
 	igt_subtest_with_dynamic(name) {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			if (!gem_class_can_store_dword(i915, e->class))
 				continue;
 
@@ -1055,10 +1059,12 @@ static void test_each_engine(const char *name, int vgem, int i915,
 
 			igt_dynamic_f("%s", e->name) {
 				gem_quiescent_gpu(i915);
-				fn(i915, vgem, e->flags);
+				fn(i915, vgem, ctx, e->flags);
 			}
 		}
 	}
+
+	intel_ctx_destroy(i915, ctx);
 }
 
 igt_main
@@ -1109,7 +1115,8 @@ igt_main
 	{
 		static const struct {
 			const char *name;
-			void (*fn)(int i915, int vgem, unsigned int engine);
+			void (*fn)(int i915, int vgem, const intel_ctx_t *ctx,
+				   unsigned int engine);
 		} tests[] = {
 			{ "sync", test_sync },
 			{ "busy", test_busy },
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 34/74] tests/gem_exec_whisper: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_whisper.c | 83 +++++++++++++++++++++++------------
 1 file changed, 54 insertions(+), 29 deletions(-)

diff --git a/tests/i915/gem_exec_whisper.c b/tests/i915/gem_exec_whisper.c
index 71bd610c..d66cc056 100644
--- a/tests/i915/gem_exec_whisper.c
+++ b/tests/i915/gem_exec_whisper.c
@@ -28,12 +28,14 @@
  */
 
 #include "i915/gem.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 #include "igt_debugfs.h"
 #include "igt_rapl.h"
 #include "igt_gt.h"
 #include "igt_rand.h"
 #include "igt_sysfs.h"
+#include "intel_ctx.h"
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
 
@@ -81,13 +83,14 @@ static void verify_reloc(int fd, uint32_t handle,
 #define BASIC 0x400
 
 struct hang {
+	const intel_ctx_t *ctx;
 	struct drm_i915_gem_exec_object2 obj;
 	struct drm_i915_gem_relocation_entry reloc;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	int fd;
 };
 
-static void init_hang(struct hang *h, int fd)
+static void init_hang(struct hang *h, int fd, const intel_ctx_cfg_t *cfg)
 {
 	uint32_t *batch;
 	int i, gen;
@@ -97,6 +100,13 @@ static void init_hang(struct hang *h, int fd)
 
 	gen = intel_gen(intel_get_drm_devid(h->fd));
 
+	if (gem_has_contexts(fd)) {
+		h->ctx = intel_ctx_create(h->fd, cfg);
+		h->execbuf.rsvd1 = h->ctx->id;
+	} else {
+		h->ctx = NULL;
+	}
+
 	memset(&h->execbuf, 0, sizeof(h->execbuf));
 	h->execbuf.buffers_ptr = to_user_pointer(&h->obj);
 	h->execbuf.buffer_count = 1;
@@ -156,6 +166,7 @@ static void submit_hang(struct hang *h, unsigned *engines, int nengine, unsigned
 
 static void fini_hang(struct hang *h)
 {
+	intel_ctx_destroy(h->fd, h->ctx);
 	close(h->fd);
 }
 
@@ -165,7 +176,8 @@ static void ctx_set_random_priority(int fd, uint32_t ctx)
 	gem_context_set_priority(fd, ctx, prio);
 }
 
-static void whisper(int fd, unsigned engine, unsigned flags)
+static void whisper(int fd, const intel_ctx_t *ctx,
+		    unsigned engine, unsigned flags)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -179,7 +191,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 	const struct intel_execution_engine2 *e;
 	struct hang hang;
 	int fds[64];
-	uint32_t contexts[64];
+	intel_ctx_cfg_t local_cfg;
+	const intel_ctx_t *contexts[64];
 	unsigned nengine;
 	uint32_t batch[16];
 	unsigned int relocations = 0;
@@ -203,7 +216,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 
 	nengine = 0;
 	if (engine == ALL_ENGINES) {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (gem_class_can_store_dword(fd, e->class))
 				engines[nengine++] = e->flags;
 		}
@@ -220,10 +233,10 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 		gem_require_contexts(fd);
 
 	if (flags & QUEUES)
-		igt_require(gem_has_queues(fd));
+		igt_require(gem_has_vm(fd));
 
 	if (flags & HANG)
-		init_hang(&hang, fd);
+		init_hang(&hang, fd, &ctx->cfg);
 
 	nchild = 1;
 	if (flags & FORKED)
@@ -272,6 +285,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 			execbuf.flags |= I915_EXEC_NO_RELOC;
 			if (gen < 6)
 				execbuf.flags |= I915_EXEC_SECURE;
+			execbuf.rsvd1 = ctx->id;
 			igt_require(__gem_execbuf(fd, &execbuf) == 0);
 			scratch = tmp[0];
 			store = tmp[1];
@@ -293,18 +307,20 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 		igt_assert(loc == sizeof(uint32_t) * i);
 		batch[++i] = MI_BATCH_BUFFER_END;
 
-		if (flags & CONTEXTS) {
-			for (n = 0; n < 64; n++)
-				contexts[n] = gem_context_clone_with_engines(fd, 0);
-		}
-		if (flags & QUEUES) {
-			for (n = 0; n < 64; n++)
-				contexts[n] = gem_queue_create(fd);
-		}
 		if (flags & FDS) {
 			for (n = 0; n < 64; n++) {
 				fds[n] = gem_reopen_driver(fd);
-				gem_context_copy_engines(fd, 0, fds[n], 0);
+			}
+		}
+		if (flags & (CONTEXTS | QUEUES | FDS)) {
+			local_cfg = ctx->cfg;
+			if (flags & QUEUES) {
+				igt_assert(!(flags & FDS));
+				local_cfg.vm = gem_vm_create(fd);
+			}
+			for (n = 0; n < 64; n++) {
+				int this_fd = (flags & FDS) ? fds[n] : fd;
+				contexts[n] = intel_ctx_create(this_fd, &local_cfg);
 			}
 		}
 
@@ -413,8 +429,8 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 						execbuf.flags &= ~ENGINE_MASK;
 						execbuf.flags |= engines[rand() % nengine];
 					}
-					if (flags & (CONTEXTS | QUEUES)) {
-						execbuf.rsvd1 = contexts[rand() % 64];
+					if (flags & (CONTEXTS | QUEUES | FDS)) {
+						execbuf.rsvd1 = contexts[rand() % 64]->id;
 						if (flags & PRIORITY)
 							ctx_set_random_priority(this_fd, execbuf.rsvd1);
 					}
@@ -442,7 +458,7 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 					}
 				}
 				execbuf.flags &= ~ENGINE_MASK;
-				execbuf.rsvd1 = 0;
+				execbuf.rsvd1 = ctx->id;
 				execbuf.buffers_ptr = to_user_pointer(&tmp);
 
 				tmp[0] = tmp[1];
@@ -492,16 +508,22 @@ static void whisper(int fd, unsigned engine, unsigned flags)
 		gem_close(fd, scratch.handle);
 		gem_close(fd, store.handle);
 
+		if (flags & (CONTEXTS | QUEUES | FDS)) {
+			for (n = 0; n < 64; n++) {
+				int this_fd = (flags & FDS) ? fds[n] : fd;
+				intel_ctx_destroy(this_fd, contexts[n]);
+			}
+			if (local_cfg.vm) {
+				igt_assert(!(flags & FDS));
+				gem_vm_destroy(fd, local_cfg.vm);
+			}
+		}
+		for (n = 0; n < QLEN; n++)
+			gem_close(fd, batches[n].handle);
 		if (flags & FDS) {
 			for (n = 0; n < 64; n++)
 				close(fds[n]);
 		}
-		if (flags & (CONTEXTS | QUEUES)) {
-			for (n = 0; n < 64; n++)
-				gem_context_destroy(fd, contexts[n]);
-		}
-		for (n = 0; n < QLEN; n++)
-			gem_close(fd, batches[n].handle);
 	}
 
 	igt_waitchildren();
@@ -554,6 +576,7 @@ igt_main
 		{ NULL }
 	};
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int fd = -1;
 
 	igt_fixture {
@@ -561,6 +584,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(gem_can_store_dword(fd, 0));
 		gem_submission_print_method(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
@@ -568,10 +592,10 @@ igt_main
 	for (const struct mode *m = modes; m->name; m++) {
 		igt_subtest_f("%s%s",
 			      m->flags & BASIC ? "basic-" : "", m->name)
-			whisper(fd, ALL_ENGINES, m->flags);
+			whisper(fd, ctx, ALL_ENGINES, m->flags);
 		igt_subtest_f("%s%s-all",
 			      m->flags & BASIC ? "basic-" : "", m->name)
-			whisper(fd, ALL_ENGINES, m->flags | ALL);
+			whisper(fd, ctx, ALL_ENGINES, m->flags | ALL);
 	}
 
 	for (const struct mode *m = modes; m->name; m++) {
@@ -579,12 +603,12 @@ igt_main
 			continue;
 
 		igt_subtest_with_dynamic_f("%s", m->name) {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				if (!gem_class_can_store_dword(fd, e->class))
 					continue;
 
 				igt_dynamic_f("%s", e->name)
-					whisper(fd, e->flags, m->flags);
+					whisper(fd, ctx, e->flags, m->flags);
 			}
 		}
 	}
@@ -598,11 +622,12 @@ igt_main
 			if (m->flags & INTERRUPTIBLE)
 				continue;
 			igt_subtest_f("hang-%s", m->name)
-				whisper(fd, ALL_ENGINES, m->flags | HANG);
+				whisper(fd, ctx, ALL_ENGINES, m->flags | HANG);
 		}
 	}
 
 	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 35/74] tests/i915/gem_ctx_exec: Stop cloning contexts in close_race

[Jason Ekstrand]

Nothing in this subtest sets the set of engines on ctx0 so there's no
point in cloning them.
---
 tests/i915/gem_ctx_exec.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index 03c66bf7..95b286b2 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -350,7 +350,7 @@ static void close_race(int i915)
 	igt_assert(contexts != MAP_FAILED);
 
 	for (int child = 0; child < ncpus; child++)
-		contexts[child] = gem_context_clone_with_engines(i915, 0);
+		contexts[child] = gem_context_create(i915);
 
 	igt_fork(child, ncpus) {
 		spin = __igt_spin_new(i915, .flags = IGT_SPIN_POLL_RUN);
@@ -404,8 +404,7 @@ static void close_race(int i915)
 		 */
 		for (int child = 0; child < ncpus; child++) {
 			gem_context_destroy(i915, contexts[child]);
-			contexts[child] =
-				gem_context_clone_with_engines(i915, 0);
+			contexts[child] = gem_context_create(i915);
 		}
 		usleep(1000 + hars_petruska_f54_1_random_unsafe() % 2000);
 	}
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 36/74] tests/i915/gem_ctx_exec: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ctx_exec.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_ctx_exec.c b/tests/i915/gem_ctx_exec.c
index 95b286b2..54374b7b 100644
--- a/tests/i915/gem_ctx_exec.c
+++ b/tests/i915/gem_ctx_exec.c
@@ -267,7 +267,7 @@ static void nohangcheck_hostile(int i915)
 	const struct intel_execution_engine2 *e;
 	igt_hang_t hang;
 	int fence = -1;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 	int err = 0;
 	int dir;
 
@@ -281,12 +281,12 @@ static void nohangcheck_hostile(int i915)
 	dir = igt_params_open(i915);
 	igt_require(dir != -1);
 
-	ctx = gem_context_create(i915);
-	hang = igt_allow_hang(i915, ctx, 0);
+	ctx = intel_ctx_create_all_physical(i915);
+	hang = igt_allow_hang(i915, ctx->id, 0);
 
 	igt_require(__enable_hangcheck(dir, false));
 
-	____for_each_physical_engine(i915, ctx, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		igt_spin_t *spin;
 		int new;
 
@@ -294,7 +294,7 @@ static void nohangcheck_hostile(int i915)
 		gem_engine_property_printf(i915, e->name,
 					   "preempt_timeout_ms", "%d", 50);
 
-		spin = __igt_spin_new(i915, ctx,
+		spin = __igt_spin_new(i915, .ctx = ctx,
 				      .engine = e->flags,
 				      .flags = (IGT_SPIN_NO_PREEMPTION |
 						IGT_SPIN_FENCE_OUT));
@@ -315,7 +315,7 @@ static void nohangcheck_hostile(int i915)
 			fence = tmp;
 		}
 	}
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 	igt_assert(fence != -1);
 
 	if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 37/74] tests/i915/gem_exec_suspend: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_suspend.c | 52 +++++++++++++++++++----------------
 1 file changed, 29 insertions(+), 23 deletions(-)

diff --git a/tests/i915/gem_exec_suspend.c b/tests/i915/gem_exec_suspend.c
index b6558a14..0f663bf3 100644
--- a/tests/i915/gem_exec_suspend.c
+++ b/tests/i915/gem_exec_suspend.c
@@ -50,7 +50,8 @@
 #define CACHED (1<<8)
 #define HANG (2<<8)
 
-static void run_test(int fd, unsigned engine, unsigned flags);
+static void run_test(int fd, const intel_ctx_t *ctx,
+		     unsigned engine, unsigned flags);
 
 static void check_bo(int fd, uint32_t handle)
 {
@@ -65,12 +66,13 @@ static void check_bo(int fd, uint32_t handle)
 	munmap(map, 4096);
 }
 
-static void test_all(int fd, unsigned flags)
+static void test_all(int fd, const intel_ctx_t *ctx, unsigned flags)
 {
-	run_test(fd, ALL_ENGINES, flags & ~0xff);
+	run_test(fd, ctx, ALL_ENGINES, flags & ~0xff);
 }
 
-static void run_test(int fd, unsigned engine, unsigned flags)
+static void run_test(int fd, const intel_ctx_t *ctx,
+		     unsigned engine, unsigned flags)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -85,7 +87,7 @@ static void run_test(int fd, unsigned engine, unsigned flags)
 	if (engine == ALL_ENGINES) {
 		const struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (gem_class_can_store_dword(fd, e->class))
 				engines[nengine++] = e->flags;
 		}
@@ -96,7 +98,7 @@ static void run_test(int fd, unsigned engine, unsigned flags)
 
 	/* Before suspending, check normal operation */
 	if (mode(flags) != NOSLEEP)
-		test_all(fd, flags);
+		test_all(fd, ctx, flags);
 
 	gem_quiescent_gpu(fd);
 
@@ -106,6 +108,7 @@ static void run_test(int fd, unsigned engine, unsigned flags)
 	execbuf.flags = 1 << 11;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, 4096);
@@ -202,7 +205,7 @@ static void run_test(int fd, unsigned engine, unsigned flags)
 
 	/* After resume, make sure it still works */
 	if (mode(flags) != NOSLEEP)
-		test_all(fd, flags);
+		test_all(fd, ctx, flags);
 }
 
 struct battery_sample {
@@ -229,7 +232,8 @@ static double d_time(const struct battery_sample *after,
 		(after->tv.tv_nsec - before->tv.tv_nsec) * 1e-9); /* s */
 }
 
-static void power_test(int i915, unsigned engine, unsigned flags)
+static void power_test(int i915, const intel_ctx_t *ctx,
+		       unsigned engine, unsigned flags)
 {
 	struct battery_sample before, after;
 	char *status;
@@ -249,7 +253,7 @@ static void power_test(int i915, unsigned engine, unsigned flags)
 	igt_set_autoresume_delay(5 * 60); /* 5 minutes; longer == more stable */
 
 	igt_assert(get_power(dir, &before));
-	run_test(i915, engine, flags);
+	run_test(i915, ctx, engine, flags);
 	igt_assert(get_power(dir, &after));
 
 	igt_set_autoresume_delay(0);
@@ -273,45 +277,47 @@ igt_main
 	}, *m;
 	const struct intel_execution_engine2 *e;
 	igt_hang_t hang;
+	const intel_ctx_t *ctx;
 	int fd;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
 		igt_require(gem_can_store_dword(fd, 0));
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
 
 	igt_subtest("basic")
-		run_test(fd, ALL_ENGINES, NOSLEEP);
+		run_test(fd, ctx, ALL_ENGINES, NOSLEEP);
 	igt_subtest("basic-S0")
-		run_test(fd, ALL_ENGINES, IDLE);
+		run_test(fd, ctx, ALL_ENGINES, IDLE);
 	igt_subtest("basic-S3-devices")
-		run_test(fd, ALL_ENGINES, SUSPEND_DEVICES);
+		run_test(fd, ctx, ALL_ENGINES, SUSPEND_DEVICES);
 	igt_subtest("basic-S3")
-		run_test(fd, ALL_ENGINES, SUSPEND);
+		run_test(fd, ctx, ALL_ENGINES, SUSPEND);
 	igt_subtest("basic-S4-devices")
-		run_test(fd, ALL_ENGINES, HIBERNATE_DEVICES);
+		run_test(fd, ctx, ALL_ENGINES, HIBERNATE_DEVICES);
 	igt_subtest("basic-S4")
-		run_test(fd, ALL_ENGINES, HIBERNATE);
+		run_test(fd, ctx, ALL_ENGINES, HIBERNATE);
 
 	for (m = modes; m->suffix; m++) {
 		igt_subtest_with_dynamic_f("uncached%s", m->suffix) {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				if (!gem_class_can_store_dword(fd, e->class))
 					continue;
 				igt_dynamic_f("%s", e->name)
-					run_test(fd, e->flags, m->mode | UNCACHED);
+					run_test(fd, ctx, e->flags, m->mode | UNCACHED);
 			}
 		}
 
 		igt_subtest_with_dynamic_f("cached%s", m->suffix) {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				if (!gem_class_can_store_dword(fd, e->class))
 					continue;
 				igt_dynamic_f("%s", e->name)
-					run_test(fd, e->flags, m->mode | CACHED);
+					run_test(fd, ctx, e->flags, m->mode | CACHED);
 			}
 		}
 	}
@@ -322,14 +328,14 @@ igt_main
 	}
 
 	igt_subtest("hang-S3")
-		run_test(fd, 0, SUSPEND | HANG);
+		run_test(fd, intel_ctx_0(fd), 0, SUSPEND | HANG);
 	igt_subtest("hang-S4")
-		run_test(fd, 0, HIBERNATE | HANG);
+		run_test(fd, intel_ctx_0(fd), 0, HIBERNATE | HANG);
 
 	igt_subtest("power-S0")
-		power_test(fd, 0, IDLE);
+		power_test(fd, intel_ctx_0(fd), 0, IDLE);
 	igt_subtest("power-S3")
-		power_test(fd, 0, SUSPEND);
+		power_test(fd, intel_ctx_0(fd), 0, SUSPEND);
 
 	igt_fixture {
 		igt_disallow_hang(fd, hang);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 38/74] tests/i915/gem_sync: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_sync.c | 159 ++++++++++++++++++++++++------------------
 1 file changed, 90 insertions(+), 69 deletions(-)

diff --git a/tests/i915/gem_sync.c b/tests/i915/gem_sync.c
index 58781a5e..5ff7b79f 100644
--- a/tests/i915/gem_sync.c
+++ b/tests/i915/gem_sync.c
@@ -96,38 +96,33 @@ filter_engines_can_store_dword(int fd, struct intel_engine_data *ied)
 	ied->nengines = count;
 }
 
-static struct intel_engine_data list_store_engines(int fd, unsigned ring)
+static struct intel_engine_data
+list_engines(int fd, const intel_ctx_t *ctx, unsigned ring)
 {
 	struct intel_engine_data ied = { };
 
 	if (ring == ALL_ENGINES) {
-		ied = intel_init_engine_list(fd, 0);
-		filter_engines_can_store_dword(fd, &ied);
+		ied = intel_engine_list_for_ctx_cfg(fd, &ctx->cfg);
+	} else if (ctx->cfg.num_engines) {
+		igt_assert(ring < ctx->cfg.num_engines);
+		ied.engines[ied.nengines].flags = ring;
+		strcpy(ied.engines[ied.nengines].name, " ");
+		ied.nengines++;
 	} else {
-		if (gem_has_ring(fd, ring) && gem_can_store_dword(fd, ring)) {
-			ied.engines[ied.nengines].flags = ring;
-			strcpy(ied.engines[ied.nengines].name, " ");
-			ied.nengines++;
-		}
+		igt_assert(gem_has_ring(fd, ring));
+		ied.engines[ied.nengines].flags = ring;
+		strcpy(ied.engines[ied.nengines].name, " ");
+		ied.nengines++;
 	}
 
 	return ied;
 }
 
-static struct intel_engine_data list_engines(int fd, unsigned ring)
+static struct intel_engine_data
+list_store_engines(int fd, const intel_ctx_t *ctx, unsigned ring)
 {
-	struct intel_engine_data ied = { };
-
-	if (ring == ALL_ENGINES) {
-		ied = intel_init_engine_list(fd, 0);
-	} else {
-		if (gem_has_ring(fd, ring)) {
-			ied.engines[ied.nengines].flags = ring;
-			strcpy(ied.engines[ied.nengines].name, " ");
-			ied.nengines++;
-		}
-	}
-
+	struct intel_engine_data ied = list_engines(fd, ctx, ring);
+	filter_engines_can_store_dword(fd, &ied);
 	return ied;
 }
 
@@ -149,11 +144,12 @@ static void xchg_engine(void *array, unsigned i, unsigned j)
 }
 
 static void
-sync_ring(int fd, unsigned ring, int num_children, int timeout)
+sync_ring(int fd, const intel_ctx_t *ctx,
+	  unsigned ring, int num_children, int timeout)
 {
 	struct intel_engine_data ied;
 
-	ied = list_engines(fd, ring);
+	ied = list_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 	num_children *= ied.nengines;
 
@@ -173,6 +169,7 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = ied_flags(&ied, child);
+		execbuf.rsvd1 = ctx->id;
 		gem_execbuf(fd, &execbuf);
 		gem_sync(fd, object.handle);
 
@@ -195,7 +192,8 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
 }
 
 static void
-idle_ring(int fd, unsigned int ring, int num_children, int timeout)
+idle_ring(int fd, const intel_ctx_t *ctx, unsigned int ring,
+	  int num_children, int timeout)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_exec_object2 object;
@@ -213,6 +211,7 @@ idle_ring(int fd, unsigned int ring, int num_children, int timeout)
 	execbuf.buffers_ptr = to_user_pointer(&object);
 	execbuf.buffer_count = 1;
 	execbuf.flags = ring;
+	execbuf.rsvd1 = ctx->id;
 	gem_execbuf(fd, &execbuf);
 	gem_sync(fd, object.handle);
 
@@ -234,11 +233,12 @@ idle_ring(int fd, unsigned int ring, int num_children, int timeout)
 }
 
 static void
-wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
+wakeup_ring(int fd, const intel_ctx_t *ctx, unsigned ring,
+	    int timeout, int wlen)
 {
 	struct intel_engine_data ied;
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -258,8 +258,10 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = ied_flags(&ied, child);
+		execbuf.rsvd1 = ctx->id;
 
 		spin = __igt_spin_new(fd,
+				      .ctx = ctx,
 				      .engine = execbuf.flags,
 				      .flags = (IGT_SPIN_POLL_RUN |
 						IGT_SPIN_FAST));
@@ -326,12 +328,12 @@ wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
-static void active_ring(int fd, unsigned int ring,
+static void active_ring(int fd, const intel_ctx_t *ctx, unsigned int ring,
 			int num_children, int timeout)
 {
 	struct intel_engine_data ied;
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -341,10 +343,12 @@ static void active_ring(int fd, unsigned int ring,
 		igt_spin_t *spin[2];
 
 		spin[0] = __igt_spin_new(fd,
+					 .ctx = ctx,
 					 .engine = ied_flags(&ied, child),
 					 .flags = IGT_SPIN_FAST);
 
 		spin[1] = __igt_spin_new(fd,
+					 .ctx = ctx,
 					 .engine = ied_flags(&ied, child),
 					 .flags = IGT_SPIN_FAST);
 
@@ -376,11 +380,12 @@ static void active_ring(int fd, unsigned int ring,
 }
 
 static void
-active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
+active_wakeup_ring(int fd, const intel_ctx_t *ctx, unsigned ring,
+		   int timeout, int wlen)
 {
 	struct intel_engine_data ied;
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -400,6 +405,7 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = ied_flags(&ied, child);
+		execbuf.rsvd1 = ctx->id;
 
 		spin[0] = __igt_spin_new(fd,
 					 .engine = execbuf.flags,
@@ -490,12 +496,13 @@ active_wakeup_ring(int fd, unsigned ring, int timeout, int wlen)
 }
 
 static void
-store_ring(int fd, unsigned ring, int num_children, int timeout)
+store_ring(int fd, const intel_ctx_t *ctx, unsigned ring,
+	   int num_children, int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct intel_engine_data ied;
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 	num_children *= ied.nengines;
 
@@ -516,6 +523,7 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 		execbuf.flags |= I915_EXEC_HANDLE_LUT;
 		if (gen < 6)
 			execbuf.flags |= I915_EXEC_SECURE;
+		execbuf.rsvd1 = ctx->id;
 
 		memset(object, 0, sizeof(object));
 		object[0].handle = gem_create(fd, 4096);
@@ -586,14 +594,15 @@ store_ring(int fd, unsigned ring, int num_children, int timeout)
 }
 
 static void
-switch_ring(int fd, unsigned ring, int num_children, int timeout)
+switch_ring(int fd, const intel_ctx_t *ctx, unsigned ring,
+	    int num_children, int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct intel_engine_data ied;
 
 	gem_require_contexts(fd);
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 	num_children *= ied.nengines;
 
@@ -603,6 +612,7 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			struct drm_i915_gem_exec_object2 object[2];
 			struct drm_i915_gem_relocation_entry reloc[1024];
 			struct drm_i915_gem_execbuffer2 execbuf;
+			const intel_ctx_t *ctx;
 		} contexts[2];
 		double elapsed, baseline;
 		unsigned long cycles;
@@ -620,7 +630,9 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 			c->execbuf.flags |= I915_EXEC_HANDLE_LUT;
 			if (gen < 6)
 				c->execbuf.flags |= I915_EXEC_SECURE;
-			c->execbuf.rsvd1 = gem_context_create(fd);
+
+			c->ctx = intel_ctx_create(fd, &ctx->cfg);
+			c->execbuf.rsvd1 = c->ctx->id;
 
 			memset(c->object, 0, sizeof(c->object));
 			c->object[0].handle = gem_create(fd, 4096);
@@ -716,7 +728,7 @@ switch_ring(int fd, unsigned ring, int num_children, int timeout)
 		for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
 			gem_close(fd, contexts[i].object[1].handle);
 			gem_close(fd, contexts[i].object[0].handle);
-			gem_context_destroy(fd, contexts[i].execbuf.rsvd1);
+			intel_ctx_destroy(fd, contexts[i].ctx);
 		}
 	}
 	igt_waitchildren_timeout(timeout+10, NULL);
@@ -765,7 +777,8 @@ static void *waiter(void *arg)
 }
 
 static void
-__store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
+__store_many(int fd, const intel_ctx_t *ctx, unsigned ring,
+	     int timeout, unsigned long *cycles)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -784,6 +797,7 @@ __store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(object, 0, sizeof(object));
 	object[0].handle = gem_create(fd, 4096);
@@ -893,7 +907,8 @@ __store_many(int fd, unsigned ring, int timeout, unsigned long *cycles)
 }
 
 static void
-store_many(int fd, unsigned int ring, int num_children, int timeout)
+store_many(int fd, const intel_ctx_t *ctx, unsigned int ring,
+	   int num_children, int timeout)
 {
 	struct intel_engine_data ied;
 	unsigned long *shared;
@@ -901,14 +916,14 @@ store_many(int fd, unsigned int ring, int num_children, int timeout)
 	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 	igt_assert(shared != MAP_FAILED);
 
-	ied = list_store_engines(fd, ring);
+	ied = list_store_engines(fd, ctx, ring);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
 
 	for (int n = 0; n < ied.nengines; n++) {
 		igt_fork(child, 1)
-			__store_many(fd,
+			__store_many(fd, ctx,
 				     ied_flags(&ied, n),
 				     timeout,
 				     &shared[n]);
@@ -924,11 +939,11 @@ store_many(int fd, unsigned int ring, int num_children, int timeout)
 }
 
 static void
-sync_all(int fd, int num_children, int timeout)
+sync_all(int fd, const intel_ctx_t *ctx, int num_children, int timeout)
 {
 	struct intel_engine_data ied;
 
-	ied = list_engines(fd, ALL_ENGINES);
+	ied = list_engines(fd, ctx, ALL_ENGINES);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -946,6 +961,7 @@ sync_all(int fd, int num_children, int timeout)
 		memset(&execbuf, 0, sizeof(execbuf));
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
+		execbuf.rsvd1 = ctx->id;
 		gem_execbuf(fd, &execbuf);
 		gem_sync(fd, object.handle);
 
@@ -970,12 +986,12 @@ sync_all(int fd, int num_children, int timeout)
 }
 
 static void
-store_all(int fd, int num_children, int timeout)
+store_all(int fd, const intel_ctx_t *ctx, int num_children, int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct intel_engine_data ied;
 
-	ied = list_store_engines(fd, ALL_ENGINES);
+	ied = list_store_engines(fd, ctx, ALL_ENGINES);
 	igt_require(ied.nengines);
 
 	intel_detect_and_clear_missed_interrupts(fd);
@@ -994,6 +1010,7 @@ store_all(int fd, int num_children, int timeout)
 		execbuf.flags |= I915_EXEC_HANDLE_LUT;
 		if (gen < 6)
 			execbuf.flags |= I915_EXEC_SECURE;
+		execbuf.rsvd1 = ctx->id;
 
 		memset(object, 0, sizeof(object));
 		object[0].handle = gem_create(fd, 4096);
@@ -1069,20 +1086,21 @@ store_all(int fd, int num_children, int timeout)
 }
 
 static void
-preempt(int fd, unsigned ring, int num_children, int timeout)
+preempt(int fd, const intel_ctx_t *ctx, unsigned ring,
+	int num_children, int timeout)
 {
 	struct intel_engine_data ied;
-	uint32_t ctx[2];
+	const intel_ctx_t *tmp_ctx[2];
 
-	ied = list_engines(fd, ALL_ENGINES);
+	ied = list_engines(fd, ctx, ALL_ENGINES);
 	igt_require(ied.nengines);
 	num_children *= ied.nengines;
 
-	ctx[0] = gem_context_create(fd);
-	gem_context_set_priority(fd, ctx[0], MIN_PRIO);
+	tmp_ctx[0] = intel_ctx_create(fd, &ctx->cfg);
+	gem_context_set_priority(fd, tmp_ctx[0]->id, MIN_PRIO);
 
-	ctx[1] = gem_context_create(fd);
-	gem_context_set_priority(fd, ctx[1], MAX_PRIO);
+	tmp_ctx[1] = intel_ctx_create(fd, &ctx->cfg);
+	gem_context_set_priority(fd, tmp_ctx[1]->id, MAX_PRIO);
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	igt_fork(child, num_children) {
@@ -1100,7 +1118,7 @@ preempt(int fd, unsigned ring, int num_children, int timeout)
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		execbuf.flags = ied_flags(&ied, child);
-		execbuf.rsvd1 = ctx[1];
+		execbuf.rsvd1 = tmp_ctx[1]->id;
 		gem_execbuf(fd, &execbuf);
 		gem_sync(fd, object.handle);
 
@@ -1109,7 +1127,7 @@ preempt(int fd, unsigned ring, int num_children, int timeout)
 		do {
 			igt_spin_t *spin =
 				__igt_spin_new(fd,
-					       .ctx_id = ctx[0],
+					       .ctx = tmp_ctx[0],
 					       .engine = execbuf.flags);
 
 			do {
@@ -1128,8 +1146,8 @@ preempt(int fd, unsigned ring, int num_children, int timeout)
 	igt_waitchildren_timeout(timeout+10, NULL);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 
-	gem_context_destroy(fd, ctx[1]);
-	gem_context_destroy(fd, ctx[0]);
+	intel_ctx_destroy(fd, tmp_ctx[1]);
+	intel_ctx_destroy(fd, tmp_ctx[0]);
 }
 
 igt_main
@@ -1137,7 +1155,7 @@ igt_main
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	const struct {
 		const char *name;
-		void (*func)(int fd, unsigned int engine,
+		void (*func)(int fd, const intel_ctx_t *ctx, unsigned int engine,
 			     int num_children, int timeout);
 		int num_children;
 		int timeout;
@@ -1172,6 +1190,7 @@ igt_main
 #define for_each_test(t, T) for(typeof(*T) *t = T; t->name; t++)
 
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int fd = -1;
 
 	igt_fixture {
@@ -1179,6 +1198,7 @@ igt_main
 		igt_require_gem(fd);
 		gem_submission_print_method(fd);
 		gem_scheduler_print_capability(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
@@ -1188,7 +1208,7 @@ igt_main
 		igt_subtest_with_dynamic_f("%s", t->name) {
 			for (const struct intel_execution_ring *l = intel_execution_rings; l->name; l++) {
 				igt_dynamic_f("%s", l->name) {
-					t->func(fd, eb_ring(l),
+					t->func(fd, intel_ctx_0(fd), eb_ring(l),
 						t->num_children, t->timeout);
 				}
 			}
@@ -1196,30 +1216,30 @@ igt_main
 	}
 
 	igt_subtest("basic-all")
-		sync_all(fd, 1, 2);
+		sync_all(fd, ctx, 1, 2);
 	igt_subtest("basic-store-all")
-		store_all(fd, 1, 2);
+		store_all(fd, ctx, 1, 2);
 
 	igt_subtest("all")
-		sync_all(fd, 1, 20);
+		sync_all(fd, ctx, 1, 20);
 	igt_subtest("store-all")
-		store_all(fd, 1, 20);
+		store_all(fd, ctx, 1, 20);
 	igt_subtest("forked-all")
-		sync_all(fd, ncpus, 20);
+		sync_all(fd, ctx, ncpus, 20);
 	igt_subtest("forked-store-all")
-		store_all(fd, ncpus, 20);
+		store_all(fd, ctx, ncpus, 20);
 
 	for_each_test(t, all) {
 		igt_subtest_f("%s", t->name)
-			t->func(fd, ALL_ENGINES, t->num_children, t->timeout);
+			t->func(fd, ctx, ALL_ENGINES, t->num_children, t->timeout);
 	}
 
 	/* New way of selecting engines. */
 	for_each_test(t, individual) {
 		igt_subtest_with_dynamic_f("%s", t->name) {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				igt_dynamic_f("%s", e->name) {
-					t->func(fd, e->flags,
+					t->func(fd, ctx, e->flags,
 						t->num_children, t->timeout);
 				}
 			}
@@ -1234,17 +1254,18 @@ igt_main
 		}
 
 		igt_subtest("preempt-all")
-			preempt(fd, ALL_ENGINES, 1, 20);
+			preempt(fd, ctx, ALL_ENGINES, 1, 20);
 		igt_subtest_with_dynamic("preempt") {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				igt_dynamic_f("%s", e->name)
-					preempt(fd, e->flags, ncpus, 20);
+					preempt(fd, ctx, e->flags, ncpus, 20);
 			}
 		}
 	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 39/74] tests/i915/gem_userptr_blits: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_userptr_blits.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 7a80c016..b5450751 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -623,7 +623,7 @@ static void test_nohangcheck_hostile(int i915)
 {
 	const struct intel_execution_engine2 *e;
 	igt_hang_t hang;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 	int fence = -1;
 	int err = 0;
 	int dir;
@@ -638,11 +638,11 @@ static void test_nohangcheck_hostile(int i915)
 	dir = igt_params_open(i915);
 	igt_require(dir != -1);
 
-	ctx = gem_context_create(i915);
-	hang = igt_allow_hang(i915, ctx, 0);
+	ctx = intel_ctx_create_all_physical(i915);
+	hang = igt_allow_hang(i915, ctx->id, 0);
 	igt_require(__enable_hangcheck(dir, false));
 
-	____for_each_physical_engine(i915, ctx, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		igt_spin_t *spin;
 		int new;
 
@@ -650,7 +650,7 @@ static void test_nohangcheck_hostile(int i915)
 		gem_engine_property_printf(i915, e->name,
 					   "preempt_timeout_ms", "%d", 50);
 
-		spin = __igt_spin_new(i915, ctx,
+		spin = __igt_spin_new(i915, .ctx = ctx,
 				      .engine = e->flags,
 				      .flags = (IGT_SPIN_NO_PREEMPTION |
 						IGT_SPIN_USERPTR |
@@ -672,7 +672,7 @@ static void test_nohangcheck_hostile(int i915)
 			fence = tmp;
 		}
 	}
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 	igt_assert(fence != -1);
 
 	if (sync_fence_wait(fence, MSEC_PER_SEC)) { /* 640ms preempt-timeout */
@@ -1352,7 +1352,8 @@ static int test_dmabuf(void)
 	return 0;
 }
 
-static void store_dword_rand(int i915, unsigned int engine,
+static void store_dword_rand(int i915, const intel_ctx_t *ctx,
+			     unsigned int engine,
 			     uint32_t target, uint64_t sz,
 			     int count)
 {
@@ -1384,6 +1385,7 @@ static void store_dword_rand(int i915, unsigned int engine,
 	exec.flags = engine;
 	if (gen < 6)
 		exec.flags |= I915_EXEC_SECURE;
+	exec.rsvd1 = ctx->id;
 
 	i = 0;
 	for (int n = 0; n < count; n++) {
@@ -1501,17 +1503,19 @@ static void test_readonly(int i915)
 
 	igt_fork(child, 1) {
 		const struct intel_execution_engine2 *e;
+		const intel_ctx_t *ctx;
 		char *orig;
 
 		orig = g_compute_checksum_for_data(G_CHECKSUM_SHA1, pages, sz);
 
 		gem_userptr(i915, space, total, true, userptr_flags, &rhandle);
 
-		__for_each_physical_engine(i915, e) {
+		ctx = intel_ctx_create_all_physical(i915);
+		for_each_ctx_engine(i915, ctx, e) {
 			char *ref, *result;
 
 			/* First tweak the backing store through the write */
-			store_dword_rand(i915, e->flags, whandle, sz, 64);
+			store_dword_rand(i915, ctx, e->flags, whandle, sz, 64);
 			gem_sync(i915, whandle);
 			ref = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
 							  pages, sz);
@@ -1520,7 +1524,7 @@ static void test_readonly(int i915)
 			igt_assert(strcmp(ref, orig));
 
 			/* Now try the same through the read-only handle */
-			store_dword_rand(i915, e->flags, rhandle, total, 64);
+			store_dword_rand(i915, ctx, e->flags, rhandle, total, 64);
 			gem_sync(i915, rhandle);
 			result = g_compute_checksum_for_data(G_CHECKSUM_SHA1,
 							     pages, sz);
@@ -1536,6 +1540,7 @@ static void test_readonly(int i915)
 			g_free(orig);
 			orig = ref;
 		}
+		intel_ctx_destroy(i915, ctx);
 
 		gem_close(i915, rhandle);
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 40/74] tests/i915/gem_wait: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_wait.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/tests/i915/gem_wait.c b/tests/i915/gem_wait.c
index 7b2b1c2b..695d5076 100644
--- a/tests/i915/gem_wait.c
+++ b/tests/i915/gem_wait.c
@@ -74,13 +74,15 @@ static void invalid_buf(int fd)
 
 #define timespec_isset(x) ((x)->tv_sec | (x)->tv_nsec)
 
-static void basic(int fd, unsigned engine, unsigned flags)
+static void basic(int fd, const intel_ctx_t *ctx, unsigned engine,
+		  unsigned flags)
 {
 	IGT_CORK_HANDLE(cork);
 	uint32_t plug =
 		flags & (WRITE | AWAIT) ? igt_cork_plug(&cork, fd) : 0;
 	igt_spin_t *spin =
 		igt_spin_new(fd,
+			     .ctx = ctx,
 			     .engine = engine,
 			     .dependency = plug,
 			     .flags = (flags & HANG) ? IGT_SPIN_NO_PREEMPTION : 0);
@@ -146,21 +148,22 @@ static void basic(int fd, unsigned engine, unsigned flags)
 	igt_spin_free(fd, spin);
 }
 
-static void test_all_engines(const char *name, int i915, unsigned int test)
+static void test_all_engines(const char *name, int i915, const intel_ctx_t *ctx,
+			     unsigned int test)
 {
 	const struct intel_execution_engine2 *e;
 
 	igt_subtest_with_dynamic(name) {
 		igt_dynamic("all") {
 			gem_quiescent_gpu(i915);
-			basic(i915, ALL_ENGINES, test);
+			basic(i915, ctx, ALL_ENGINES, test);
 			gem_quiescent_gpu(i915);
 		}
 
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			igt_dynamic_f("%s", e->name) {
 				gem_quiescent_gpu(i915);
-				basic(i915, e->flags, test);
+				basic(i915, ctx, e->flags, test);
 				gem_quiescent_gpu(i915);
 			}
 		}
@@ -169,11 +172,13 @@ static void test_all_engines(const char *name, int i915, unsigned int test)
 
 igt_main
 {
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	igt_subtest("invalid-flags")
@@ -201,7 +206,7 @@ igt_main
 		}
 
 		for (const typeof(*tests) *t = tests; t->name; t++)
-			test_all_engines(t->name, fd, t->flags);
+			test_all_engines(t->name, fd, ctx, t->flags);
 
 		igt_fixture {
 			igt_stop_signal_helper();
@@ -228,7 +233,7 @@ igt_main
 		}
 
 		for (const typeof(*tests) *t = tests; t->name; t++)
-			test_all_engines(t->name, fd, t->flags);
+			test_all_engines(t->name, fd, ctx, t->flags);
 
 		igt_fixture {
 			igt_stop_signal_helper();
@@ -237,6 +242,7 @@ igt_main
 	}
 
 	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 41/74] tests/i915/gem_request_retire: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_request_retire.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tests/i915/gem_request_retire.c b/tests/i915/gem_request_retire.c
index c23ddfb7..3df54f2a 100644
--- a/tests/i915/gem_request_retire.c
+++ b/tests/i915/gem_request_retire.c
@@ -62,24 +62,26 @@ static void
 test_retire_vma_not_inactive(int fd)
 {
 	struct intel_execution_engine2 *e;
-
+	const intel_ctx_t *ctx;
 	igt_spin_t *bg = NULL;
 
-	__for_each_physical_engine(fd, e) {
+	ctx = intel_ctx_create_all_physical(fd);
+
+	for_each_ctx_engine(fd, ctx, e) {
 		igt_spin_t *spin;
-		uint32_t ctx;
+		const intel_ctx_t *spin_ctx;
 
 		if (!bg) {
-			bg = igt_spin_new(fd, .engine = e->flags);
+			bg = igt_spin_new(fd, .ctx = ctx, .engine = e->flags);
 			continue;
 		}
 
-		ctx = gem_context_clone_with_engines(fd, 0);
-		spin = igt_spin_new(fd, ctx,
+		spin_ctx = intel_ctx_create(fd, &ctx->cfg);
+		spin = igt_spin_new(fd, .ctx = spin_ctx,
 				    .engine = e->flags,
 				    .dependency = bg->handle,
 				    .flags = IGT_SPIN_SOFTDEP);
-		gem_context_destroy(fd, ctx);
+		intel_ctx_destroy(fd, spin_ctx);
 		igt_spin_end(spin);
 
 		gem_sync(fd, spin->handle);
@@ -88,6 +90,7 @@ test_retire_vma_not_inactive(int fd)
 
 	igt_drop_caches_set(fd, DROP_RETIRE);
 	igt_spin_free(fd, bg);
+	intel_ctx_destroy(fd, ctx);
 }
 
 int fd;
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 42/74] tests/i915/gem_ctx_shared: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ctx_shared.c | 262 ++++++++++++++++++++----------------
 1 file changed, 145 insertions(+), 117 deletions(-)

diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index e3e8a9be..1c7458c0 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -39,6 +39,7 @@
 
 #include "i915/gem.h"
 #include "i915/gem_engine_topology.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 #include "igt_rand.h"
 #include "igt_vgem.h"
@@ -108,11 +109,13 @@ static void create_shared_gtt(int i915, unsigned int flags)
 	gem_close(i915, obj.handle);
 }
 
-static void disjoint_timelines(int i915)
+static void disjoint_timelines(int i915, const intel_ctx_cfg_t *cfg)
 {
 	IGT_CORK_HANDLE(cork);
+	intel_ctx_cfg_t vm_cfg;
+	const intel_ctx_t *ctx[2];
 	igt_spin_t *spin[2];
-	uint32_t plug, child;
+	uint32_t plug;
 
 	igt_require(gem_has_execlists(i915));
 
@@ -121,11 +124,15 @@ static void disjoint_timelines(int i915)
 	 * distinct timelines. A request queued to one context should be
 	 * independent of any shared contexts.
 	 */
-	child = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0);
+	vm_cfg = *cfg;
+	vm_cfg.vm = gem_vm_create(i915);
+	ctx[0] = intel_ctx_create(i915, &vm_cfg);
+	ctx[1] = intel_ctx_create(i915, &vm_cfg);
+
 	plug = igt_cork_plug(&cork, i915);
 
-	spin[0] = __igt_spin_new(i915, .ctx_id = 0, .dependency = plug);
-	spin[1] = __igt_spin_new(i915, .ctx_id = child);
+	spin[0] = __igt_spin_new(i915, .ctx = ctx[0], .dependency = plug);
+	spin[1] = __igt_spin_new(i915, .ctx = ctx[1]);
 
 	/* Wait for the second spinner, will hang if stuck behind the first */
 	igt_spin_end(spin[1]);
@@ -135,6 +142,10 @@ static void disjoint_timelines(int i915)
 
 	igt_spin_free(i915, spin[1]);
 	igt_spin_free(i915, spin[0]);
+
+	intel_ctx_destroy(i915, ctx[0]);
+	intel_ctx_destroy(i915, ctx[1]);
+	gem_vm_destroy(i915, vm_cfg.vm);
 }
 
 static void exhaust_shared_gtt(int i915, unsigned int flags)
@@ -184,7 +195,8 @@ static void exhaust_shared_gtt(int i915, unsigned int flags)
 	igt_waitchildren();
 }
 
-static void exec_shared_gtt(int i915, unsigned int ring)
+static void exec_shared_gtt(int i915, const intel_ctx_cfg_t *cfg,
+			    unsigned int ring)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -194,14 +206,18 @@ static void exec_shared_gtt(int i915, unsigned int ring)
 		.buffer_count = 1,
 		.flags = ring,
 	};
-	uint32_t clone;
+	intel_ctx_cfg_t vm_cfg;
+	const intel_ctx_t *ctx[2];
 	uint32_t scratch, *s;
 	uint32_t batch, cs[16];
 	uint64_t offset;
 	int timeline;
 	int i;
 
-	clone = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0);
+	vm_cfg = *cfg;
+	vm_cfg.vm = gem_vm_create(i915);
+	ctx[0] = intel_ctx_create(i915, &vm_cfg);
+	ctx[1] = intel_ctx_create(i915, &vm_cfg);
 
 	/* Find a hole big enough for both objects later */
 	scratch = gem_create(i915, 16384);
@@ -209,9 +225,9 @@ static void exec_shared_gtt(int i915, unsigned int ring)
 	obj.handle = scratch;
 	gem_execbuf(i915, &execbuf);
 	obj.flags |= EXEC_OBJECT_PINNED; /* reuse this address */
-	execbuf.rsvd1 = clone; /* and bind the second context image */
+	execbuf.rsvd1 = ctx[1]->id; /* and bind the second context image */
 	gem_execbuf(i915, &execbuf);
-	execbuf.rsvd1 = 0;
+	execbuf.rsvd1 = ctx[0]->id;
 	gem_close(i915, scratch);
 
 	timeline = sw_sync_timeline_create();
@@ -255,7 +271,7 @@ static void exec_shared_gtt(int i915, unsigned int ring)
 
 	obj.handle = batch;
 	obj.offset += 8192; /* make sure we don't cause an eviction! */
-	execbuf.rsvd1 = clone;
+	execbuf.rsvd1 = ctx[1]->id;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 	gem_execbuf(i915, &execbuf);
@@ -287,10 +303,13 @@ static void exec_shared_gtt(int i915, unsigned int ring)
 	munmap(s, 4096);
 	gem_close(i915, scratch);
 
-	gem_context_destroy(i915, clone);
+	intel_ctx_destroy(i915, ctx[0]);
+	intel_ctx_destroy(i915, ctx[1]);
+	gem_vm_destroy(i915, vm_cfg.vm);
 }
 
-static int nop_sync(int i915, uint32_t ctx, unsigned int ring, int64_t timeout)
+static int nop_sync(int i915, const intel_ctx_t *ctx, unsigned int ring,
+		    int64_t timeout)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_exec_object2 obj = {
@@ -300,7 +319,7 @@ static int nop_sync(int i915, uint32_t ctx, unsigned int ring, int64_t timeout)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = ring,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 	};
 	int err;
 
@@ -316,22 +335,24 @@ static bool has_single_timeline(int i915)
 {
 	uint32_t ctx = 0;
 
-	__gem_context_clone(i915, 0, 0,
-			    I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE,
-			    &ctx);
+	__gem_context_create_ext(i915,
+				 I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE,
+				 0, /* extensions */ &ctx);
 	if (ctx)
 		gem_context_destroy(i915, ctx);
 
 	return ctx != 0;
 }
 
-static void single_timeline(int i915)
+static void single_timeline(int i915, const intel_ctx_cfg_t *cfg)
 {
 	const struct intel_execution_engine2 *e;
 	struct sync_fence_info rings[64];
 	struct sync_file_info sync_file_info = {
 		.num_fences = 1,
 	};
+	intel_ctx_cfg_t st_cfg;
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin;
 	int n;
 
@@ -346,11 +367,12 @@ static void single_timeline(int i915)
 	 * to, it reports the same timeline name and fence context. However,
 	 * the fence context is not reported through the sync_fence_info.
 	 */
-	spin->execbuf.rsvd1 =
-		gem_context_clone(i915, 0, 0,
-				  I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
+	st_cfg = *cfg;
+	st_cfg.flags |= I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE;
+	ctx = intel_ctx_create(i915, &st_cfg);
+	spin->execbuf.rsvd1 = ctx->id;
 	n = 0;
-	____for_each_physical_engine(i915, spin->execbuf.rsvd1, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		spin->execbuf.flags = e->flags | I915_EXEC_FENCE_OUT;
 
 		gem_execbuf_wr(i915, &spin->execbuf);
@@ -369,32 +391,35 @@ static void single_timeline(int i915)
 		igt_assert(!strcmp(rings[0].driver_name, rings[i].driver_name));
 		igt_assert(!strcmp(rings[0].obj_name, rings[i].obj_name));
 	}
+	intel_ctx_destroy(i915, ctx);
 }
 
-static void exec_single_timeline(int i915, unsigned int engine)
+static void exec_single_timeline(int i915, const intel_ctx_cfg_t *cfg,
+				 unsigned int engine)
 {
 	const struct intel_execution_engine2 *e;
 	igt_spin_t *spin;
-	uint32_t ctx;
+	intel_ctx_cfg_t st_cfg;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * On an ordinary context, a blockage on one engine doesn't prevent
 	 * execution on an other.
 	 */
-	ctx = 0;
+	ctx = intel_ctx_create(i915, cfg);
 	spin = NULL;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (e->flags == engine)
 			continue;
 
 		if (spin == NULL) {
-			spin = __igt_spin_new(i915, .ctx_id = ctx, .engine = e->flags);
+			spin = __igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 execbuf = {
 				.buffers_ptr = spin->execbuf.buffers_ptr,
 				.buffer_count = spin->execbuf.buffer_count,
 				.flags = e->flags,
-				.rsvd1 = ctx,
+				.rsvd1 = ctx->id,
 			};
 			gem_execbuf(i915, &execbuf);
 		}
@@ -402,27 +427,29 @@ static void exec_single_timeline(int i915, unsigned int engine)
 	igt_require(spin);
 	igt_assert_eq(nop_sync(i915, ctx, engine, NSEC_PER_SEC), 0);
 	igt_spin_free(i915, spin);
+	intel_ctx_destroy(i915, ctx);
 
 	/*
 	 * But if we create a context with just a single shared timeline,
 	 * then it will block waiting for the earlier requests on the
 	 * other engines.
 	 */
-	ctx = gem_context_clone(i915, 0, 0,
-				I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
+	st_cfg = *cfg;
+	st_cfg.flags |= I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE;
+	ctx = intel_ctx_create(i915, &st_cfg);
 	spin = NULL;
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_cfg_engine(i915, cfg, e) {
 		if (e->flags == engine)
 			continue;
 
 		if (spin == NULL) {
-			spin = __igt_spin_new(i915, .ctx_id = ctx, .engine = e->flags);
+			spin = __igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
 		} else {
 			struct drm_i915_gem_execbuffer2 execbuf = {
 				.buffers_ptr = spin->execbuf.buffers_ptr,
 				.buffer_count = spin->execbuf.buffer_count,
 				.flags = e->flags,
-				.rsvd1 = ctx,
+				.rsvd1 = ctx->id,
 			};
 			gem_execbuf(i915, &execbuf);
 		}
@@ -430,9 +457,10 @@ static void exec_single_timeline(int i915, unsigned int engine)
 	igt_assert(spin);
 	igt_assert_eq(nop_sync(i915, ctx, engine, NSEC_PER_SEC), -ETIME);
 	igt_spin_free(i915, spin);
+	intel_ctx_destroy(i915, ctx);
 }
 
-static void store_dword(int i915, uint32_t ctx, unsigned ring,
+static void store_dword(int i915, const intel_ctx_t *ctx, unsigned ring,
 			uint32_t target, uint32_t offset, uint32_t value,
 			uint32_t cork, unsigned write_domain)
 {
@@ -449,7 +477,7 @@ static void store_dword(int i915, uint32_t ctx, unsigned ring,
 	execbuf.flags = ring;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
-	execbuf.rsvd1 = ctx;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = cork;
@@ -490,31 +518,30 @@ static void store_dword(int i915, uint32_t ctx, unsigned ring,
 	gem_close(i915, obj[2].handle);
 }
 
-static uint32_t create_highest_priority(int i915)
+static const intel_ctx_t *
+create_highest_priority(int i915, const intel_ctx_cfg_t *cfg)
 {
-	uint32_t ctx = gem_context_clone_with_engines(i915, 0);
+	const intel_ctx_t *ctx = intel_ctx_create(i915, cfg);
 
 	/*
 	 * If there is no priority support, all contexts will have equal
 	 * priority (and therefore the max user priority), so no context
 	 * can overtake us, and we effectively can form a plug.
 	 */
-	__gem_context_set_priority(i915, ctx, MAX_PRIO);
+	__gem_context_set_priority(i915, ctx->id, MAX_PRIO);
 
 	return ctx;
 }
 
-static void unplug_show_queue(int i915, struct igt_cork *c, unsigned int engine)
+static void unplug_show_queue(int i915, struct igt_cork *c,
+			      const intel_ctx_cfg_t *cfg, unsigned int engine)
 {
 	igt_spin_t *spin[MAX_ELSP_QLEN];
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
-		const struct igt_spin_factory opts = {
-			.ctx_id = create_highest_priority(i915),
-			.engine = engine,
-		};
-		spin[n] = __igt_spin_factory(i915, &opts);
-		gem_context_destroy(i915, opts.ctx_id);
+		const intel_ctx_t *ctx = create_highest_priority(i915, cfg);
+		spin[n] = __igt_spin_new(i915, .ctx = ctx, .engine = engine);
+		intel_ctx_destroy(i915, ctx);
 	}
 
 	igt_cork_unplug(c); /* batches will now be queued on the engine */
@@ -525,7 +552,8 @@ static void unplug_show_queue(int i915, struct igt_cork *c, unsigned int engine)
 }
 
 static uint32_t store_timestamp(int i915,
-				uint32_t ctx, unsigned ring,
+				const intel_ctx_t *ctx,
+				unsigned ring,
 				unsigned mmio_base,
 				int fence,
 				int offset)
@@ -548,7 +576,7 @@ static uint32_t store_timestamp(int i915,
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = ring | I915_EXEC_FENCE_IN,
-		.rsvd1 = ctx,
+		.rsvd1 = ctx->id,
 		.rsvd2 = fence
 	};
 	uint32_t batch[] = {
@@ -576,7 +604,7 @@ static void kick_tasklets(void)
 	sched_yield();
 }
 
-static void independent(int i915,
+static void independent(int i915, const intel_ctx_cfg_t *cfg,
 			const struct intel_execution_engine2 *e,
 			unsigned flags)
 {
@@ -591,22 +619,19 @@ static void independent(int i915,
 	igt_require_f(mmio_base, "mmio base not known\n");
 
 	for (int n = 0; n < ARRAY_SIZE(spin); n++) {
-		const struct igt_spin_factory opts = {
-			.ctx_id = create_highest_priority(i915),
-			.engine = e->flags,
-		};
-		spin[n] = __igt_spin_factory(i915, &opts);
-		gem_context_destroy(i915, opts.ctx_id);
+		const intel_ctx_t *ctx = create_highest_priority(i915, cfg);
+		spin[n] = __igt_spin_new(i915, .ctx = ctx, .engine = e->flags);
+		intel_ctx_destroy(i915, ctx);
 	}
 
 	fence = igt_cork_plug(&cork, i915);
 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
-		uint32_t ctx = gem_queue_create(i915);
-		gem_context_set_priority(i915, ctx, priorities[i]);
+		const intel_ctx_t *ctx = create_highest_priority(i915, cfg);
+		gem_context_set_priority(i915, ctx->id, priorities[i]);
 		handle[i] = store_timestamp(i915, ctx,
 					    e->flags, mmio_base,
 					    fence, TIMESTAMP);
-		gem_context_destroy(i915, ctx);
+		intel_ctx_destroy(i915, ctx);
 	}
 	close(fence);
 	kick_tasklets(); /* XXX try to hide cmdparser delays XXX */
@@ -635,20 +660,21 @@ static void independent(int i915,
 	igt_assert((int32_t)(handle[HI] - handle[LO]) < 0);
 }
 
-static void reorder(int i915, unsigned ring, unsigned flags)
+static void reorder(int i915, const intel_ctx_cfg_t *cfg,
+		    unsigned ring, unsigned flags)
 #define EQUAL 1
 {
 	IGT_CORK_HANDLE(cork);
 	uint32_t scratch;
 	uint32_t *ptr;
-	uint32_t ctx[2];
+	const intel_ctx_t *ctx[2];
 	uint32_t plug;
 
-	ctx[LO] = gem_queue_create(i915);
-	gem_context_set_priority(i915, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(i915, cfg);
+	gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO);
 
-	ctx[HI] = gem_queue_create(i915);
-	gem_context_set_priority(i915, ctx[HI], flags & EQUAL ? MIN_PRIO : 0);
+	ctx[HI] = intel_ctx_create(i915, cfg);
+	gem_context_set_priority(i915, ctx[HI]->id, flags & EQUAL ? MIN_PRIO : 0);
 
 	scratch = gem_create(i915, 4096);
 	plug = igt_cork_plug(&cork, i915);
@@ -656,43 +682,43 @@ static void reorder(int i915, unsigned ring, unsigned flags)
 	/* We expect the high priority context to be executed first, and
 	 * so the final result will be value from the low priority context.
 	 */
-	store_dword(i915, ctx[LO], ring, scratch, 0, ctx[LO], plug, 0);
-	store_dword(i915, ctx[HI], ring, scratch, 0, ctx[HI], plug, 0);
+	store_dword(i915, ctx[LO], ring, scratch, 0, ctx[LO]->id, plug, 0);
+	store_dword(i915, ctx[HI], ring, scratch, 0, ctx[HI]->id, plug, 0);
 
-	unplug_show_queue(i915, &cork, ring);
+	unplug_show_queue(i915, &cork, cfg, ring);
 	gem_close(i915, plug);
 
-	gem_context_destroy(i915, ctx[LO]);
-	gem_context_destroy(i915, ctx[HI]);
-
 	ptr = gem_mmap__device_coherent(i915, scratch, 0, 4096, PROT_READ);
 	gem_set_domain(i915, scratch, /* no write hazard lies! */
 		       I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	gem_close(i915, scratch);
 
 	if (flags & EQUAL) /* equal priority, result will be fifo */
-		igt_assert_eq_u32(ptr[0], ctx[HI]);
+		igt_assert_eq_u32(ptr[0], ctx[HI]->id);
 	else
-		igt_assert_eq_u32(ptr[0], ctx[LO]);
+		igt_assert_eq_u32(ptr[0], ctx[LO]->id);
 	munmap(ptr, 4096);
+
+	intel_ctx_destroy(i915, ctx[LO]);
+	intel_ctx_destroy(i915, ctx[HI]);
 }
 
-static void promotion(int i915, unsigned ring)
+static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring)
 {
 	IGT_CORK_HANDLE(cork);
 	uint32_t result, dep;
 	uint32_t *ptr;
-	uint32_t ctx[3];
+	const intel_ctx_t *ctx[3];
 	uint32_t plug;
 
-	ctx[LO] = gem_queue_create(i915);
-	gem_context_set_priority(i915, ctx[LO], MIN_PRIO);
+	ctx[LO] = intel_ctx_create(i915, cfg);
+	gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO);
 
-	ctx[HI] = gem_queue_create(i915);
-	gem_context_set_priority(i915, ctx[HI], 0);
+	ctx[HI] = intel_ctx_create(i915, cfg);
+	gem_context_set_priority(i915, ctx[HI]->id, 0);
 
-	ctx[NOISE] = gem_queue_create(i915);
-	gem_context_set_priority(i915, ctx[NOISE], MIN_PRIO/2);
+	ctx[NOISE] = intel_ctx_create(i915, cfg);
+	gem_context_set_priority(i915, ctx[NOISE]->id, MIN_PRIO/2);
 
 	result = gem_create(i915, 4096);
 	dep = gem_create(i915, 4096);
@@ -704,28 +730,24 @@ static void promotion(int i915, unsigned ring)
 	 * fifo would be NOISE, LO, HI.
 	 * strict priority would be  HI, NOISE, LO
 	 */
-	store_dword(i915, ctx[NOISE], ring, result, 0, ctx[NOISE], plug, 0);
-	store_dword(i915, ctx[LO], ring, result, 0, ctx[LO], plug, 0);
+	store_dword(i915, ctx[NOISE], ring, result, 0, ctx[NOISE]->id, plug, 0);
+	store_dword(i915, ctx[LO], ring, result, 0, ctx[LO]->id, plug, 0);
 
 	/* link LO <-> HI via a dependency on another buffer */
-	store_dword(i915, ctx[LO], ring, dep, 0, ctx[LO], 0, I915_GEM_DOMAIN_INSTRUCTION);
-	store_dword(i915, ctx[HI], ring, dep, 0, ctx[HI], 0, 0);
+	store_dword(i915, ctx[LO], ring, dep, 0, ctx[LO]->id, 0, I915_GEM_DOMAIN_INSTRUCTION);
+	store_dword(i915, ctx[HI], ring, dep, 0, ctx[HI]->id, 0, 0);
 
-	store_dword(i915, ctx[HI], ring, result, 0, ctx[HI], 0, 0);
+	store_dword(i915, ctx[HI], ring, result, 0, ctx[HI]->id, 0, 0);
 
-	unplug_show_queue(i915, &cork, ring);
+	unplug_show_queue(i915, &cork, cfg, ring);
 	gem_close(i915, plug);
 
-	gem_context_destroy(i915, ctx[NOISE]);
-	gem_context_destroy(i915, ctx[LO]);
-	gem_context_destroy(i915, ctx[HI]);
-
 	ptr = gem_mmap__device_coherent(i915, dep, 0, 4096, PROT_READ);
 	gem_set_domain(i915, dep, /* no write hazard lies! */
 			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	gem_close(i915, dep);
 
-	igt_assert_eq_u32(ptr[0], ctx[HI]);
+	igt_assert_eq_u32(ptr[0], ctx[HI]->id);
 	munmap(ptr, 4096);
 
 	ptr = gem_mmap__device_coherent(i915, result, 0, 4096, PROT_READ);
@@ -733,11 +755,16 @@ static void promotion(int i915, unsigned ring)
 			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	gem_close(i915, result);
 
-	igt_assert_eq_u32(ptr[0], ctx[NOISE]);
+	igt_assert_eq_u32(ptr[0], ctx[NOISE]->id);
 	munmap(ptr, 4096);
+
+	intel_ctx_destroy(i915, ctx[NOISE]);
+	intel_ctx_destroy(i915, ctx[LO]);
+	intel_ctx_destroy(i915, ctx[HI]);
 }
 
-static void smoketest(int i915, unsigned ring, unsigned timeout)
+static void smoketest(int i915, const intel_ctx_cfg_t *cfg,
+		      unsigned ring, unsigned timeout)
 {
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	unsigned engines[I915_EXEC_RING_MASK + 1];
@@ -750,7 +777,7 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
 	if (ring == -1) {
 		const struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(i915, e)
+		for_each_ctx_cfg_engine(i915, cfg, e)
 			engines[nengine++] = e->flags;
 	} else {
 		engines[nengine++] = ring;
@@ -760,16 +787,16 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
 	scratch = gem_create(i915, 4096);
 	igt_fork(child, ncpus) {
 		unsigned long count = 0;
-		uint32_t ctx;
+		const intel_ctx_t *ctx;
 
 		hars_petruska_f54_1_random_perturb(child);
 
-		ctx = gem_queue_create(i915);
+		ctx = intel_ctx_create(i915, cfg);
 		igt_until_timeout(timeout) {
 			int prio;
 
 			prio = hars_petruska_f54_1_random_unsafe_max(MAX_PRIO - MIN_PRIO) + MIN_PRIO;
-			gem_context_set_priority(i915, ctx, prio);
+			gem_context_set_priority(i915, ctx->id, prio);
 
 			engine = engines[hars_petruska_f54_1_random_unsafe_max(nengine)];
 			store_dword(i915, ctx, engine, scratch,
@@ -780,7 +807,7 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
 					    8*child + 4, count++,
 					    0, 0);
 		}
-		gem_context_destroy(i915, ctx);
+		intel_ctx_destroy(i915, ctx);
 	}
 	igt_waitchildren();
 
@@ -802,19 +829,21 @@ static void smoketest(int i915, unsigned ring, unsigned timeout)
 	munmap(ptr, 4096);
 }
 
-#define for_each_queue(e, i915) \
-	__for_each_physical_engine(i915, e) \
+#define for_each_queue(e, i915, cfg) \
+	for_each_ctx_cfg_engine(i915, cfg, e) \
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", e->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg;
 	int i915 = -1;
 
 	igt_fixture {
 		i915 = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(i915);
+		cfg = intel_ctx_cfg_all_physical(i915);
 	}
 
 	igt_subtest_group {
@@ -830,20 +859,20 @@ igt_main
 			create_shared_gtt(i915, DETACHED);
 
 		igt_subtest("disjoint-timelines")
-			disjoint_timelines(i915);
+			disjoint_timelines(i915, &cfg);
 
 		igt_subtest("single-timeline")
-			single_timeline(i915);
+			single_timeline(i915, &cfg);
 
 		igt_subtest_with_dynamic("exec-shared-gtt") {
-			for_each_queue(e, i915)
-				exec_shared_gtt(i915, e->flags);
+			for_each_queue(e, i915, &cfg)
+				exec_shared_gtt(i915, &cfg, e->flags);
 		}
 
 		igt_subtest_with_dynamic("exec-single-timeline") {
 			igt_require(has_single_timeline(i915));
-			for_each_queue(e, i915)
-				exec_single_timeline(i915, e->flags);
+			for_each_queue(e, i915, &cfg)
+				exec_single_timeline(i915, &cfg, e->flags);
 		}
 
 		/*
@@ -855,38 +884,37 @@ igt_main
 		 */
 		igt_subtest_group {
 			igt_fixture {
-				igt_require(gem_has_queues(i915));
 				igt_require(gem_scheduler_enabled(i915));
 				igt_require(gem_scheduler_has_ctx_priority(i915));
 			}
 
 			igt_subtest_with_dynamic("Q-independent") {
-				for_each_queue(e, i915)
-					independent(i915, e, 0);
+				for_each_queue(e, i915, &cfg)
+					independent(i915, &cfg, e, 0);
 			}
 
 			igt_subtest_with_dynamic("Q-in-order") {
-				for_each_queue(e, i915)
-					reorder(i915, e->flags, EQUAL);
+				for_each_queue(e, i915, &cfg)
+					reorder(i915, &cfg, e->flags, EQUAL);
 			}
 
 			igt_subtest_with_dynamic("Q-out-order") {
-				for_each_queue(e, i915)
-					reorder(i915, e->flags, 0);
+				for_each_queue(e, i915, &cfg)
+					reorder(i915, &cfg, e->flags, 0);
 			}
 
 			igt_subtest_with_dynamic("Q-promotion") {
-				for_each_queue(e, i915)
-					promotion(i915, e->flags);
+				for_each_queue(e, i915, &cfg)
+					promotion(i915, &cfg, e->flags);
 			}
 
 			igt_subtest_with_dynamic("Q-smoketest") {
-				for_each_queue(e, i915)
-					smoketest(i915, e->flags, 5);
+				for_each_queue(e, i915, &cfg)
+					smoketest(i915, &cfg, e->flags, 5);
 			}
 
 			igt_subtest("Q-smoketest-all")
-				smoketest(i915, -1, 30);
+				smoketest(i915, &cfg, -1, 30);
 		}
 
 		igt_subtest("exhaust-shared-gtt")
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 43/74] tests/i915/gem_ctx_shared: Stop cloning contexts

[Jason Ekstrand]

Instead use either GET/SET_CONTEXT_PARAM or a create ext.
---
 tests/i915/gem_ctx_shared.c | 77 ++++++++++++++++++++++++++++++-------
 1 file changed, 63 insertions(+), 14 deletions(-)

diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c
index 1c7458c0..84dd956e 100644
--- a/tests/i915/gem_ctx_shared.c
+++ b/tests/i915/gem_ctx_shared.c
@@ -62,6 +62,48 @@ static int priorities[] = {
 
 IGT_TEST_DESCRIPTION("Test shared contexts.");
 
+static int __get_vm(int i915, uint32_t ctx, uint32_t *vm)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_VM,
+	};
+	int err = __gem_context_get_param(i915, &p);
+	if (err)
+		return err;
+
+	igt_assert(p.value > 0 && p.value < UINT32_MAX);
+	*vm = p.value;
+
+	return 0;
+}
+
+static uint32_t get_vm(int i915, uint32_t ctx)
+{
+	uint32_t vm;
+	igt_assert_eq(__get_vm(i915, ctx, &vm), 0);
+	return vm;
+}
+
+static void set_vm(int i915, uint32_t ctx, uint32_t vm)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_VM,
+		.value = vm
+	};
+	gem_context_set_param(i915, &p);
+}
+
+static void copy_vm(int i915, uint32_t dst, uint32_t src)
+{
+	uint32_t vm = get_vm(i915, src);
+	set_vm(i915, dst, vm);
+
+	/* GETPARAM gets a reference to the VM which we have to drop */
+	gem_vm_destroy(i915, vm);
+}
+
 static void create_shared_gtt(int i915, unsigned int flags)
 #define DETACHED 0x1
 {
@@ -82,9 +124,9 @@ static void create_shared_gtt(int i915, unsigned int flags)
 	child = flags & DETACHED ? gem_context_create(i915) : 0;
 	igt_until_timeout(2) {
 		parent = flags & DETACHED ? child : 0;
-		child = gem_context_clone(i915,
-					  parent, I915_CONTEXT_CLONE_VM,
-					  0);
+		child = gem_context_create(i915);
+		copy_vm(i915, child, parent);
+
 		execbuf.rsvd1 = child;
 		gem_execbuf(i915, &execbuf);
 
@@ -98,9 +140,7 @@ static void create_shared_gtt(int i915, unsigned int flags)
 
 		execbuf.rsvd1 = parent;
 		igt_assert_eq(__gem_execbuf(i915, &execbuf), -ENOENT);
-		igt_assert_eq(__gem_context_clone(i915,
-						  parent, I915_CONTEXT_CLONE_VM,
-						  0, &parent), -ENOENT);
+		igt_assert_eq(__get_vm(i915, parent, &parent), -ENOENT);
 	}
 	if (flags & DETACHED)
 		gem_context_destroy(i915, child);
@@ -151,8 +191,19 @@ static void disjoint_timelines(int i915, const intel_ctx_cfg_t *cfg)
 static void exhaust_shared_gtt(int i915, unsigned int flags)
 #define EXHAUST_LRC 0x1
 {
+	struct drm_i915_gem_context_create_ext_setparam vm_create_ext = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_VM,
+		},
+	};
+
 	i915 = gem_reopen_driver(i915);
 
+	vm_create_ext.param.value = gem_vm_create(i915);
+
 	igt_fork(pid, 1) {
 		const uint32_t bbe = MI_BATCH_BUFFER_END;
 		struct drm_i915_gem_exec_object2 obj = {
@@ -162,23 +213,21 @@ static void exhaust_shared_gtt(int i915, unsigned int flags)
 			.buffers_ptr = to_user_pointer(&obj),
 			.buffer_count = 1,
 		};
-		uint32_t parent, child;
 		unsigned long count = 0;
 		int err;
 
 		gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
 
-		child = 0;
 		for (;;) {
-			parent = child;
-			err = __gem_context_clone(i915,
-						  parent, I915_CONTEXT_CLONE_VM,
-						  0, &child);
+			uint32_t ctx;
+			err = __gem_context_create_ext(i915, 0,
+						       to_user_pointer(&vm_create_ext),
+						       &ctx);
 			if (err)
 				break;
 
 			if (flags & EXHAUST_LRC) {
-				execbuf.rsvd1 = child;
+				execbuf.rsvd1 = ctx;
 				err = __gem_execbuf(i915, &execbuf);
 				if (err)
 					break;
@@ -848,7 +897,7 @@ igt_main
 
 	igt_subtest_group {
 		igt_fixture {
-			igt_require(gem_contexts_has_shared_gtt(i915));
+			igt_require(gem_has_vm(i915));
 			igt_fork_hang_detector(i915);
 		}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 44/74] tests/i915/gem_create: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_create.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index ce985053..890dd8e8 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -245,20 +245,24 @@ static void always_clear(int i915, int timeout)
 static void busy_create(int i915, int timeout)
 {
 	struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	igt_spin_t *spin[I915_EXEC_RING_MASK + 1];
 	unsigned long count = 0;
 
+	ctx = intel_ctx_create_all_physical(i915);
+
 	igt_fork_hang_detector(i915);
-	__for_each_physical_engine(i915, e)
-		spin[e->flags] = igt_spin_new(i915, .engine = e->flags);
+	for_each_ctx_engine(i915, ctx, e)
+		spin[e->flags] = igt_spin_new(i915, .ctx = ctx,
+					      .engine = e->flags);
 
 	igt_until_timeout(timeout) {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			uint32_t handle;
 			igt_spin_t *next;
 
 			handle = gem_create(i915, 4096);
-			next = igt_spin_new(i915,
+			next = igt_spin_new(i915, .ctx = ctx,
 					    .engine = e->flags,
 					    .dependency = handle,
 					    .flags = IGT_SPIN_SOFTDEP);
@@ -271,6 +275,8 @@ static void busy_create(int i915, int timeout)
 		}
 	}
 
+	intel_ctx_destroy(i915, ctx);
+
 	igt_info("Created %ld objects while busy\n", count);
 
 	gem_quiescent_gpu(i915);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 45/74] tests/i915/gem_ctx_switch: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ctx_switch.c | 115 ++++++++++++++++++++----------------
 1 file changed, 64 insertions(+), 51 deletions(-)

diff --git a/tests/i915/gem_ctx_switch.c b/tests/i915/gem_ctx_switch.c
index 6208dacd..4f85f3b7 100644
--- a/tests/i915/gem_ctx_switch.c
+++ b/tests/i915/gem_ctx_switch.c
@@ -42,6 +42,7 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "i915/gem_ring.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 
 #define INTERRUPTIBLE 0x1
@@ -53,18 +54,18 @@ static double elapsed(const struct timespec *start, const struct timespec *end)
 		(end->tv_nsec - start->tv_nsec)*1e-9);
 }
 
-static int measure_qlen(int fd,
+static int measure_qlen(int fd, const intel_ctx_cfg_t *cfg,
 			struct drm_i915_gem_execbuffer2 *execbuf,
 			const struct intel_engine_data *engines,
 			int timeout)
 {
 	const struct drm_i915_gem_exec_object2 * const obj =
 		(struct drm_i915_gem_exec_object2 *)(uintptr_t)execbuf->buffers_ptr;
-	uint32_t ctx[64];
+	const intel_ctx_t *ctx[64];
 	int min = INT_MAX, max = 0;
 
 	for (int i = 0; i < ARRAY_SIZE(ctx); i++)
-		ctx[i] = gem_context_clone_with_engines(fd, 0);
+		ctx[i] = intel_ctx_create(fd, cfg);
 
 	for (unsigned int n = 0; n < engines->nengines; n++) {
 		uint64_t saved = execbuf->flags;
@@ -74,14 +75,14 @@ static int measure_qlen(int fd,
 		execbuf->flags |= engines->engines[n].flags;
 
 		for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
-			execbuf->rsvd1 = ctx[i];
+			execbuf->rsvd1 = ctx[i]->id;
 			gem_execbuf(fd, execbuf);
 		}
 		gem_sync(fd, obj->handle);
 
 		igt_nsec_elapsed(&tv);
 		for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
-			execbuf->rsvd1 = ctx[i];
+			execbuf->rsvd1 = ctx[i]->id;
 			gem_execbuf(fd, execbuf);
 		}
 		gem_sync(fd, obj->handle);
@@ -101,13 +102,14 @@ static int measure_qlen(int fd,
 	}
 
 	for (int i = 0; i < ARRAY_SIZE(ctx); i++)
-		gem_context_destroy(fd, ctx[i]);
+		intel_ctx_destroy(fd, ctx[i]);
 
 	igt_debug("Estimated qlen: {min:%d, max:%d}\n", min, max);
 	return min;
 }
 
 static void single(int fd, uint32_t handle,
+		   const intel_ctx_cfg_t *base_cfg,
 		   const struct intel_execution_engine2 *e2,
 		   unsigned flags,
 		   const int ncpus,
@@ -116,7 +118,8 @@ static void single(int fd, uint32_t handle,
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj;
 	struct drm_i915_gem_relocation_entry reloc;
-	uint32_t contexts[64];
+	intel_ctx_cfg_t cfg;
+	const intel_ctx_t *contexts[64];
 	struct {
 		double elapsed;
 		unsigned long count;
@@ -126,12 +129,12 @@ static void single(int fd, uint32_t handle,
 	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 	igt_assert(shared != MAP_FAILED);
 
-	for (n = 0; n < 64; n++) {
-		if (flags & QUEUE)
-			contexts[n] = gem_queue_clone_with_engines(fd, 0);
-		else
-			contexts[n] = gem_context_clone_with_engines(fd, 0);
-	}
+	cfg = *base_cfg;
+	if (flags & QUEUE)
+		cfg.vm = gem_vm_create(fd);
+
+	for (n = 0; n < 64; n++)
+		contexts[n] = intel_ctx_create(fd, &cfg);
 
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = handle;
@@ -150,7 +153,7 @@ static void single(int fd, uint32_t handle,
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&obj);
 	execbuf.buffer_count = 1;
-	execbuf.rsvd1 = contexts[0];
+	execbuf.rsvd1 = contexts[0]->id;
 	execbuf.flags = e2->flags;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
@@ -168,7 +171,7 @@ static void single(int fd, uint32_t handle,
 
 		/* Warmup to bind all objects into each ctx before we begin */
 		for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
-			execbuf.rsvd1 = contexts[i];
+			execbuf.rsvd1 = contexts[i]->id;
 			gem_execbuf(fd, &execbuf);
 		}
 		gem_sync(fd, handle);
@@ -177,7 +180,7 @@ static void single(int fd, uint32_t handle,
 		do {
 			igt_while_interruptible(flags & INTERRUPTIBLE) {
 				for (int loop = 0; loop < 64; loop++) {
-					execbuf.rsvd1 = contexts[loop % 64];
+					execbuf.rsvd1 = contexts[loop % 64]->id;
 					reloc.presumed_offset = -1;
 					gem_execbuf(fd, &execbuf);
 				}
@@ -214,28 +217,30 @@ static void single(int fd, uint32_t handle,
 	}
 
 	for (n = 0; n < 64; n++)
-		gem_context_destroy(fd, contexts[n]);
+		intel_ctx_destroy(fd, contexts[n]);
 
 	munmap(shared, 4096);
 }
 
-static void all(int fd, uint32_t handle, unsigned flags, int timeout)
+static void all(int fd, uint32_t handle, const intel_ctx_cfg_t *base_cfg,
+		unsigned flags, int timeout)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj[2];
 	struct intel_engine_data engines = { };
-	uint32_t contexts[65];
+	intel_ctx_cfg_t cfg;
+	const intel_ctx_t *contexts[65];
 	int n, qlen;
 
-	engines = intel_init_engine_list(fd, 0);
+	engines = intel_engine_list_for_ctx_cfg(fd, base_cfg);
 	igt_require(engines.nengines);
 
-	for (n = 0; n < ARRAY_SIZE(contexts); n++) {
-		if (flags & QUEUE)
-			contexts[n] = gem_queue_clone_with_engines(fd, 0);
-		else
-			contexts[n] = gem_context_clone_with_engines(fd, 0);
-	}
+	cfg = *base_cfg;
+	if (flags & QUEUE)
+		cfg.vm = gem_vm_create(fd);
+
+	for (n = 0; n < 64; n++)
+		contexts[n] = intel_ctx_create(fd, &cfg);
 
 	memset(obj, 0, sizeof(obj));
 	obj[1].handle = handle;
@@ -243,13 +248,13 @@ static void all(int fd, uint32_t handle, unsigned flags, int timeout)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(obj + 1);
 	execbuf.buffer_count = 1;
-	execbuf.rsvd1 = contexts[0];
+	execbuf.rsvd1 = contexts[0]->id;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
 	igt_require(__gem_execbuf(fd, &execbuf) == 0);
 	gem_sync(fd, handle);
 
-	qlen = measure_qlen(fd, &execbuf, &engines, timeout);
+	qlen = measure_qlen(fd, base_cfg, &execbuf, &engines, timeout);
 	igt_info("Using timing depth of %d batches\n", qlen);
 
 	execbuf.buffers_ptr = to_user_pointer(obj);
@@ -266,7 +271,7 @@ static void all(int fd, uint32_t handle, unsigned flags, int timeout)
 				for (int loop = 0;
 				     loop < ARRAY_SIZE(contexts);
 				     loop++) {
-					execbuf.rsvd1 = contexts[loop];
+					execbuf.rsvd1 = contexts[loop]->id;
 					gem_execbuf(fd, &execbuf);
 				}
 				gem_sync(fd, obj[0].handle);
@@ -275,7 +280,7 @@ static void all(int fd, uint32_t handle, unsigned flags, int timeout)
 				do {
 					for (int loop = 0; loop < qlen; loop++) {
 						execbuf.rsvd1 =
-							contexts[loop % nctx];
+							contexts[loop % nctx]->id;
 						gem_execbuf(fd, &execbuf);
 					}
 					count += qlen;
@@ -299,7 +304,7 @@ static void all(int fd, uint32_t handle, unsigned flags, int timeout)
 	}
 
 	for (n = 0; n < ARRAY_SIZE(contexts); n++)
-		gem_context_destroy(fd, contexts[n]);
+		intel_ctx_destroy(fd, contexts[n]);
 }
 
 igt_main
@@ -307,6 +312,8 @@ igt_main
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	const struct intel_execution_engine2 *e2;
 	const struct intel_execution_ring *e;
+	const intel_ctx_cfg_t legacy_cfg = {};
+	intel_ctx_cfg_t engines_cfg;
 	static const struct {
 		const char *name;
 		unsigned int flags;
@@ -314,8 +321,8 @@ igt_main
 	} phases[] = {
 		{ "", 0, NULL },
 		{ "-interruptible", INTERRUPTIBLE, NULL },
-		{ "-queue", QUEUE, gem_has_queues },
-		{ "-queue-interruptible", QUEUE | INTERRUPTIBLE, gem_has_queues },
+		{ "-queue", QUEUE, gem_has_vm },
+		{ "-queue-interruptible", QUEUE | INTERRUPTIBLE, gem_has_vm },
 		{ }
 	};
 	uint32_t light = 0, heavy;
@@ -329,6 +336,8 @@ igt_main
 
 		gem_require_contexts(fd);
 
+		engines_cfg = intel_ctx_cfg_all_physical(fd);
+
 		light = gem_create(fd, 4096);
 		gem_write(fd, light, 0, &bbe, sizeof(bbe));
 
@@ -357,24 +366,26 @@ igt_main
 				}
 
 				igt_subtest_f("legacy-%s%s", e->name, p->name)
-					single(fd, light, e2, p->flags, 1, 2);
+					single(fd, light, &legacy_cfg, e2,
+					       p->flags, 1, 2);
 				igt_subtest_f("legacy-%s-heavy%s",
 					      e->name, p->name)
-					single(fd, heavy, e2, p->flags, 1, 2);
+					single(fd, heavy, &legacy_cfg, e2,
+					       p->flags, 1, 2);
 				igt_subtest_f("legacy-%s-forked%s",
 					      e->name, p->name)
-					single(fd, light, e2, p->flags, ncpus,
-					       20);
+					single(fd, light, &legacy_cfg, e2,
+					       p->flags, ncpus, 20);
 				igt_subtest_f("legacy-%s-forked-heavy%s",
 					      e->name, p->name)
-					single(fd, heavy, e2, p->flags, ncpus,
-					       20);
+					single(fd, heavy, &legacy_cfg, e2,
+					       p->flags, ncpus, 20);
 			}
 		}
 	}
 
 	/* Must come after legacy subtests. */
-	__for_each_physical_engine(fd, e2) {
+	for_each_ctx_cfg_engine(fd, &engines_cfg, e2) {
 		for (typeof(*phases) *p = phases; p->name; p++) {
 			igt_subtest_group {
 				igt_fixture {
@@ -383,33 +394,35 @@ igt_main
 				}
 
 				igt_subtest_f("%s%s", e2->name, p->name)
-					single(fd, light, e2, p->flags, 1, 2);
+					single(fd, light, &engines_cfg, e2,
+					       p->flags, 1, 2);
 				igt_subtest_f("%s-heavy%s", e2->name, p->name)
-					single(fd, heavy, e2, p->flags, 1, 2);
+					single(fd, heavy, &engines_cfg, e2,
+					       p->flags, 1, 2);
 				igt_subtest_f("%s-forked%s", e2->name, p->name)
-					single(fd, light, e2, p->flags, ncpus,
-					       20);
+					single(fd, light, &engines_cfg, e2,
+					       p->flags, ncpus, 20);
 				igt_subtest_f("%s-forked-heavy%s",
 					      e2->name, p->name)
-					single(fd, heavy, e2, p->flags, ncpus,
-					       20);
+					single(fd, heavy, &engines_cfg, e2,
+					       p->flags, ncpus, 20);
 			}
 		}
 	}
 
 	igt_subtest("all-light")
-		all(fd, light, 0, 2);
+		all(fd, light, &engines_cfg, 0, 2);
 	igt_subtest("all-heavy")
-		all(fd, heavy, 0, 2);
+		all(fd, heavy, &engines_cfg, 0, 2);
 
 	igt_subtest_group {
 		igt_fixture {
-			igt_require(gem_has_queues(fd));
+			gem_require_vm(fd);
 		}
 		igt_subtest("queue-light")
-			all(fd, light, QUEUE, 2);
+			all(fd, light, &engines_cfg, QUEUE, 2);
 		igt_subtest("queue-heavy")
-			all(fd, heavy, QUEUE, 2);
+			all(fd, heavy, &engines_cfg, QUEUE, 2);
 	}
 
 	igt_fixture {
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 46/74] tests/i915/gem_exec_parallel: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_parallel.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/tests/i915/gem_exec_parallel.c b/tests/i915/gem_exec_parallel.c
index c9cf9d7a..89330c20 100644
--- a/tests/i915/gem_exec_parallel.c
+++ b/tests/i915/gem_exec_parallel.c
@@ -56,6 +56,7 @@ struct thread {
 	unsigned flags;
 	uint32_t *scratch;
 	unsigned id;
+	const intel_ctx_t *ctx;
 	unsigned engine;
 	uint32_t used;
 	int fd, gen, *go;
@@ -67,6 +68,7 @@ static void *thread(void *data)
 	struct drm_i915_gem_exec_object2 obj[2];
 	struct drm_i915_gem_relocation_entry reloc;
 	struct drm_i915_gem_execbuffer2 execbuf;
+	const intel_ctx_t *tmp_ctx = NULL;
 	uint32_t batch[16];
 	uint16_t used;
 	int fd, i;
@@ -78,7 +80,6 @@ static void *thread(void *data)
 
 	if (t->flags & FDS) {
 		fd = gem_reopen_driver(t->fd);
-		gem_context_copy_engines(t->fd, 0, fd, 0);
 	} else {
 		fd = t->fd;
 	}
@@ -121,8 +122,11 @@ static void *thread(void *data)
 	execbuf.flags |= I915_EXEC_NO_RELOC;
 	if (t->gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
-	if (t->flags & CONTEXTS) {
-		execbuf.rsvd1 = gem_context_clone_with_engines(fd, 0);
+	if (t->flags & (CONTEXTS | FDS)) {
+		tmp_ctx = intel_ctx_create(fd, &t->ctx->cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
+	} else {
+		execbuf.rsvd1 = t->ctx->id;
 	}
 
 	used = 0;
@@ -141,8 +145,8 @@ static void *thread(void *data)
 			gem_close(fd, obj[0].handle);
 	}
 
-	if (t->flags & CONTEXTS)
-		gem_context_destroy(fd, execbuf.rsvd1);
+	if (t->flags & (CONTEXTS | FDS))
+		intel_ctx_destroy(fd, tmp_ctx);
 	gem_close(fd, obj[1].handle);
 	if (t->flags & FDS)
 		close(fd);
@@ -196,7 +200,8 @@ static void handle_close(int fd, unsigned int flags, uint32_t handle, void *data
 	gem_close(fd, handle);
 }
 
-static void all(int fd, struct intel_execution_engine2 *engine, unsigned flags)
+static void all(int fd, const intel_ctx_t *ctx,
+		struct intel_execution_engine2 *engine, unsigned flags)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	unsigned engines[I915_EXEC_RING_MASK + 1], nengine;
@@ -219,7 +224,7 @@ static void all(int fd, struct intel_execution_engine2 *engine, unsigned flags)
 	nengine = 0;
 	if (!engine) {
 		struct intel_execution_engine2 *e;
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (gem_class_can_store_dword(fd, e->class))
 				engines[nengine++] = e->flags;
 		}
@@ -246,6 +251,7 @@ static void all(int fd, struct intel_execution_engine2 *engine, unsigned flags)
 		threads[i].id = i;
 		threads[i].fd = fd;
 		threads[i].gen = gen;
+		threads[i].ctx = ctx;
 		threads[i].engine = engines[i % nengine];
 		threads[i].flags = flags;
 		threads[i].scratch = scratch;
@@ -287,11 +293,13 @@ igt_main
 		{ "userptr", USERPTR },
 		{ NULL }
 	};
+	const intel_ctx_t *ctx = NULL;
 	int fd;
 
 	igt_fixture {
 		fd = drm_open_driver_master(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 
 		igt_fork_hang_detector(fd);
 	}
@@ -300,21 +308,22 @@ igt_main
 		for (const struct mode *m = modes; m->name; m++)
 			igt_dynamic(m->name)
 				/* NULL value means all engines */
-				all(fd, NULL, m->flags);
+				all(fd, ctx, NULL, m->flags);
 	}
 
 	for (const struct mode *m = modes; m->name; m++) {
 		igt_subtest_with_dynamic(m->name) {
-			__for_each_physical_engine(fd, e) {
+			for_each_ctx_engine(fd, ctx, e) {
 				if (gem_class_can_store_dword(fd, e->class))
 					igt_dynamic(e->name)
-						all(fd, e, m->flags);
+						all(fd, ctx, e, m->flags);
 			}
 		}
 	}
 
 	igt_fixture {
 		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, ctx);
 		close(fd);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 47/74] tests/i915/gem_exec_latency: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_latency.c | 120 +++++++++++++++++++---------------
 1 file changed, 66 insertions(+), 54 deletions(-)

diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
index e6466965..663d1bad 100644
--- a/tests/i915/gem_exec_latency.c
+++ b/tests/i915/gem_exec_latency.c
@@ -58,9 +58,11 @@ static unsigned int ring_size;
 static double rcs_clock;
 static struct intel_mmio_data mmio_data;
 
-static void poll_ring(int fd, const struct intel_execution_engine2 *e)
+static void poll_ring(int fd, const intel_ctx_t *ctx,
+		      const struct intel_execution_engine2 *e)
 {
 	const struct igt_spin_factory opts = {
+		.ctx = ctx,
 		.engine = e->flags,
 		.flags = IGT_SPIN_POLL_RUN | IGT_SPIN_FAST,
 	};
@@ -100,7 +102,7 @@ static void poll_ring(int fd, const struct intel_execution_engine2 *e)
 }
 
 #define TIMESTAMP (0x358)
-static void latency_on_ring(int fd,
+static void latency_on_ring(int fd, const intel_ctx_t *ctx,
 			    const struct intel_execution_engine2 *e,
 			    unsigned flags)
 {
@@ -127,6 +129,7 @@ static void latency_on_ring(int fd,
 	execbuf.buffer_count = 2;
 	execbuf.flags = e->flags;
 	execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT;
+	execbuf.rsvd1 = ctx->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[1].handle = gem_create(fd, 4096);
@@ -249,7 +252,7 @@ static void latency_on_ring(int fd,
 	gem_close(fd, obj[2].handle);
 }
 
-static void latency_from_ring(int fd,
+static void latency_from_ring(int fd, const intel_ctx_t *base_ctx,
 			      const struct intel_execution_engine2 *e,
 			      unsigned flags)
 {
@@ -262,17 +265,17 @@ static void latency_from_ring(int fd,
 	const unsigned int repeats = ring_size / 2;
 	const struct intel_execution_engine2 *other;
 	uint32_t *map, *results;
-	uint32_t ctx[2] = {};
+	const intel_ctx_t *ctx[2] = {base_ctx, base_ctx};
 	int i, j;
 
 	igt_require(mmio_base);
 
 	if (flags & PREEMPT) {
-		ctx[0] = gem_context_clone_with_engines(fd, 0);
-		gem_context_set_priority(fd, ctx[0], -1023);
+		ctx[0] = intel_ctx_create(fd, &base_ctx->cfg);
+		gem_context_set_priority(fd, ctx[0]->id, -1023);
 
-		ctx[1] = gem_context_clone_with_engines(fd, 0);
-		gem_context_set_priority(fd, ctx[1], 1023);
+		ctx[1] = intel_ctx_create(fd, &base_ctx->cfg);
+		gem_context_set_priority(fd, ctx[1]->id, 1023);
 	}
 
 	memset(&execbuf, 0, sizeof(execbuf));
@@ -280,7 +283,7 @@ static void latency_from_ring(int fd,
 	execbuf.buffer_count = 2;
 	execbuf.flags = e->flags;
 	execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT;
-	execbuf.rsvd1 = ctx[1];
+	execbuf.rsvd1 = ctx[1]->id;
 
 	memset(obj, 0, sizeof(obj));
 	obj[1].handle = gem_create(fd, 4096);
@@ -308,7 +311,7 @@ static void latency_from_ring(int fd,
 	reloc.presumed_offset = obj[1].offset;
 	reloc.target_handle = flags & CORK ? 1 : 0;
 
-	__for_each_physical_engine(fd, other) {
+	for_each_ctx_engine(fd, base_ctx, other) {
 		igt_spin_t *spin = NULL;
 		IGT_CORK_HANDLE(c);
 
@@ -318,7 +321,7 @@ static void latency_from_ring(int fd,
 
 		if (flags & PREEMPT)
 			spin = __igt_spin_new(fd,
-					      .ctx_id = ctx[0],
+					      .ctx = ctx[0],
 					      .engine = e->flags);
 
 		if (flags & CORK) {
@@ -402,12 +405,13 @@ static void latency_from_ring(int fd,
 	gem_close(fd, obj[2].handle);
 
 	if (flags & PREEMPT) {
-		gem_context_destroy(fd, ctx[1]);
-		gem_context_destroy(fd, ctx[0]);
+		intel_ctx_destroy(fd, ctx[1]);
+		intel_ctx_destroy(fd, ctx[0]);
 	}
 }
 
-static void execution_latency(int i915, const struct intel_execution_engine2 *e)
+static void execution_latency(int i915, const intel_ctx_t *ctx,
+			      const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_exec_object2 obj = {
 		.handle = gem_create(i915, 4095),
@@ -416,6 +420,7 @@ static void execution_latency(int i915, const struct intel_execution_engine2 *e)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = e->flags | I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT,
+		.rsvd1 = ctx->id,
 	};
 	const uint32_t mmio_base = gem_engine_mmio_base(i915, e->name);
 	const unsigned int cs_timestamp = mmio_base + 0x358;
@@ -488,7 +493,8 @@ static void execution_latency(int i915, const struct intel_execution_engine2 *e)
 	gem_close(i915, obj.handle);
 }
 
-static void wakeup_latency(int i915, const struct intel_execution_engine2 *e)
+static void wakeup_latency(int i915, const intel_ctx_t *ctx,
+			   const struct intel_execution_engine2 *e)
 {
 	struct drm_i915_gem_exec_object2 obj = {
 		.handle = gem_create(i915, 4095),
@@ -497,6 +503,7 @@ static void wakeup_latency(int i915, const struct intel_execution_engine2 *e)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = e->flags | I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT,
+		.rsvd1 = ctx->id,
 	};
 	const uint32_t mmio_base = gem_engine_mmio_base(i915, e->name);
 	const unsigned int cs_timestamp = mmio_base + 0x358;
@@ -597,7 +604,8 @@ static bool __spin_wait(int fd, igt_spin_t *spin)
  * Test whether RT thread which hogs the CPU a lot can submit work with
  * reasonable latency.
  */
-static void rthog_latency_on_ring(int fd, const struct intel_execution_engine2 *e)
+static void rthog_latency_on_ring(int fd, const intel_ctx_t *ctx,
+				  const struct intel_execution_engine2 *e)
 {
 	const char *passname[] = {
 		"warmup",
@@ -613,6 +621,7 @@ static void rthog_latency_on_ring(int fd, const struct intel_execution_engine2 *
 #define NPASS ARRAY_SIZE(passname)
 #define MMAP_SZ (64 << 10)
 	const struct igt_spin_factory opts = {
+		.ctx = ctx,
 		.engine = e->flags,
 		.flags = IGT_SPIN_POLL_RUN | IGT_SPIN_FAST,
 	};
@@ -735,7 +744,7 @@ static void rthog_latency_on_ring(int fd, const struct intel_execution_engine2 *
 	munmap(results, MMAP_SZ);
 }
 
-static void context_switch(int i915,
+static void context_switch(int i915, const intel_ctx_t *ctx,
 			   const struct intel_execution_engine2 *e,
 			   unsigned int flags)
 {
@@ -745,17 +754,17 @@ static void context_switch(int i915,
 	uint32_t *cs, *bbe, *results, v;
 	const uint32_t mmio_base = gem_engine_mmio_base(i915, e->name);
 	struct igt_mean mean;
-	uint32_t ctx[2];
+	const intel_ctx_t *tmp_ctx[2];
 
 	igt_require(mmio_base);
 	igt_require(gem_class_has_mutable_submission(i915, e->class));
 
-	for (int i = 0; i < ARRAY_SIZE(ctx); i++)
-		ctx[i] = gem_context_clone_with_engines(i915, 0);
+	for (int i = 0; i < ARRAY_SIZE(tmp_ctx); i++)
+		tmp_ctx[i] = intel_ctx_create(i915, &ctx->cfg);
 
 	if (flags & PREEMPT) {
-		gem_context_set_priority(i915, ctx[0], -1023);
-		gem_context_set_priority(i915, ctx[1], +1023);
+		gem_context_set_priority(i915, tmp_ctx[0]->id, -1023);
+		gem_context_set_priority(i915, tmp_ctx[1]->id, +1023);
 	}
 
 	memset(obj, 0, sizeof(obj));
@@ -815,14 +824,14 @@ static void context_switch(int i915,
 	v = 0;
 	igt_mean_init(&mean);
 	igt_until_timeout(5) {
-		eb.rsvd1 = ctx[0];
+		eb.rsvd1 = tmp_ctx[0]->id;
 		eb.batch_start_offset = 0;
 		gem_execbuf(i915, &eb);
 
 		while (results[0] == v)
 			igt_assert(gem_bo_busy(i915, obj[1].handle));
 
-		eb.rsvd1 = ctx[1];
+		eb.rsvd1 = tmp_ctx[1]->id;
 		eb.batch_start_offset = 64 * sizeof(*cs);
 		gem_execbuf(i915, &eb);
 
@@ -843,8 +852,8 @@ static void context_switch(int i915,
 	for (int i = 0; i < ARRAY_SIZE(obj); i++)
 		gem_close(i915, obj[i].handle);
 
-	for (int i = 0; i < ARRAY_SIZE(ctx); i++)
-		gem_context_destroy(i915, ctx[i]);
+	for (int i = 0; i < ARRAY_SIZE(tmp_ctx); i++)
+		intel_ctx_destroy(i915, tmp_ctx[i]);
 }
 
 static double clockrate(int i915, int reg)
@@ -879,20 +888,22 @@ static double clockrate(int i915, int reg)
 	return (r_end - r_start) * 1e9 / elapsed;
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int device = -1;
 
 	igt_fixture {
 		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 		gem_require_mmap_wc(device);
+		ctx = intel_ctx_create_all_physical(device);
 
 		gem_submission_print_method(device);
 
@@ -914,31 +925,31 @@ igt_main
 		igt_fixture
 			igt_require(intel_gen(intel_get_drm_devid(device)) >= 7);
 
-		test_each_engine("rthog-submit", device, e)
-			rthog_latency_on_ring(device, e);
+		test_each_engine("rthog-submit", device, ctx, e)
+			rthog_latency_on_ring(device, ctx, e);
 
-		test_each_engine("dispatch", device, e)
-			latency_on_ring(device, e, 0);
-		test_each_engine("dispatch-queued", device, e)
-			latency_on_ring(device, e, CORK);
+		test_each_engine("dispatch", device, ctx, e)
+			latency_on_ring(device, ctx, e, 0);
+		test_each_engine("dispatch-queued", device, ctx, e)
+			latency_on_ring(device, ctx, e, CORK);
 
-		test_each_engine("live-dispatch", device, e)
-			latency_on_ring(device, e, LIVE);
-		test_each_engine("live-dispatch-queued", device, e)
-			latency_on_ring(device, e, LIVE | CORK);
+		test_each_engine("live-dispatch", device, ctx, e)
+			latency_on_ring(device, ctx, e, LIVE);
+		test_each_engine("live-dispatch-queued", device, ctx, e)
+			latency_on_ring(device, ctx, e, LIVE | CORK);
 
-		test_each_engine("poll", device, e)
-			poll_ring(device, e);
+		test_each_engine("poll", device, ctx, e)
+			poll_ring(device, ctx, e);
 
-		test_each_engine("synchronisation", device, e)
-			latency_from_ring(device, e, 0);
-		test_each_engine("synchronisation-queued", device, e)
-			latency_from_ring(device, e, CORK);
+		test_each_engine("synchronisation", device, ctx, e)
+			latency_from_ring(device, ctx, e, 0);
+		test_each_engine("synchronisation-queued", device, ctx, e)
+			latency_from_ring(device, ctx, e, CORK);
 
-		test_each_engine("execution-latency", device, e)
-			execution_latency(device, e);
-		test_each_engine("wakeup-latency", device, e)
-			wakeup_latency(device, e);
+		test_each_engine("execution-latency", device, ctx, e)
+			execution_latency(device, ctx, e);
+		test_each_engine("wakeup-latency", device, ctx, e)
+			wakeup_latency(device, ctx, e);
 
 		igt_subtest_group {
 			igt_fixture {
@@ -946,17 +957,18 @@ igt_main
 				igt_require(gem_scheduler_has_preemption(device));
 			}
 
-			test_each_engine("preemption", device, e)
-				latency_from_ring(device, e, PREEMPT);
-			test_each_engine("context-switch", device, e)
-				context_switch(device, e, 0);
-			test_each_engine("context-preempt", device, e)
-				context_switch(device, e, PREEMPT);
+			test_each_engine("preemption", device, ctx, e)
+				latency_from_ring(device, ctx, e, PREEMPT);
+			test_each_engine("context-switch", device, ctx, e)
+				context_switch(device, ctx, e, 0);
+			test_each_engine("context-preempt", device, ctx, e)
+				context_switch(device, ctx, e, PREEMPT);
 		}
 	}
 
 	igt_fixture {
 		intel_register_access_fini(&mmio_data);
+		intel_ctx_destroy(device, ctx);
 		close(device);
 	}
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 48/74] tests/i915/gem_watchdog: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_watchdog.c | 169 +++++++++++---------------------------
 1 file changed, 46 insertions(+), 123 deletions(-)

diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
index 22acf15c..15709682 100644
--- a/tests/i915/gem_watchdog.c
+++ b/tests/i915/gem_watchdog.c
@@ -30,36 +30,13 @@
 #include <sched.h>
 
 #include "i915/gem.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 #include "igt_params.h"
 #include "sw_sync.h"
 
 #define EWATCHDOG EINTR
 
-static struct drm_i915_query_engine_info *__engines__;
-
-static int __i915_query(int fd, struct drm_i915_query *q)
-{
-	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
-		return -errno;
-	return 0;
-}
-
-static int
-__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
-{
-	struct drm_i915_query q = {
-		.num_items = n_items,
-		.items_ptr = to_user_pointer(items),
-	};
-	return __i915_query(fd, &q);
-}
-
-#define i915_query_items(fd, items, n_items) do { \
-		igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
-		errno = 0; \
-	} while (0)
-
 static unsigned int default_timeout_wait_s;
 static const unsigned int watchdog_us = 500 * 1000;
 
@@ -127,56 +104,43 @@ static unsigned int spin_flags(void)
 	return IGT_SPIN_POLL_RUN | IGT_SPIN_FENCE_OUT;
 }
 
-static void physical(int i915)
+static void physical(int i915, const intel_ctx_t *ctx)
 {
 	const unsigned int wait_us = default_timeout_wait_s * USEC_PER_SEC;
-	unsigned int num_engines = __engines__->num_engines, i, count;
+	unsigned int num_engines, i, count;
 	const struct intel_execution_engine2 *e;
-	unsigned int expect = num_engines;
-	igt_spin_t *spin[num_engines];
+	igt_spin_t *spin[GEM_MAX_ENGINES];
 
 	i = 0;
-	__for_each_physical_engine(i915, e) {
-		spin[i] = igt_spin_new(i915,
+	for_each_ctx_engine(i915, ctx, e) {
+		spin[i] = igt_spin_new(i915, .ctx = ctx,
 				       .engine = e->flags,
 				       .flags = spin_flags());
 		i++;
 	}
+	num_engines = i;
 
-	count = wait_timeout(i915, spin, num_engines, wait_us, expect);
+	count = wait_timeout(i915, spin, num_engines, wait_us, num_engines);
 
 	for (i = 0; i < num_engines; i++)
 		igt_spin_free(i915, spin[i]);
 
-	igt_assert_eq(count, expect);
+	igt_assert_eq(count, num_engines);
 }
 
 static struct i915_engine_class_instance *
-list_engines(unsigned int class, unsigned int *out)
+list_engines(const intel_ctx_cfg_t *cfg,
+	     unsigned int class, unsigned int *out)
 {
 	struct i915_engine_class_instance *ci;
-	unsigned int count = 0, size = 64, i;
+	unsigned int count = 0, i;
 
-	ci = malloc(size * sizeof(*ci));
+	ci = malloc(cfg->num_engines * sizeof(*ci));
 	igt_assert(ci);
 
-	for (i = 0; i < __engines__->num_engines; i++) {
-		struct drm_i915_engine_info *engine =
-			(struct drm_i915_engine_info *)&__engines__->engines[i];
-
-		if (class != engine->engine.engine_class)
-			continue;
-
-		if (count == size) {
-			size *= 2;
-			ci = realloc(ci, size * sizeof(*ci));
-			igt_assert(ci);
-		}
-
-		ci[count++] = (struct i915_engine_class_instance){
-			.engine_class = class,
-			.engine_instance = engine->engine.engine_instance,
-		};
+	for (i = 0; i < cfg->num_engines; i++) {
+		if (class == cfg->engines[i].engine_class)
+			ci[count++] = cfg->engines[i];
 	}
 
 	if (!count) {
@@ -243,49 +207,27 @@ static void set_load_balancer(int i915, uint32_t ctx,
 	igt_assert_eq(__set_load_balancer(i915, ctx, ci, count, ext), 0);
 }
 
-static void ctx_set_vm(int i915, uint32_t ctx, uint32_t vm)
-{
-	struct drm_i915_gem_context_param arg = {
-		.param = I915_CONTEXT_PARAM_VM,
-		.ctx_id = ctx,
-		.value = vm,
-	};
-
-	gem_context_set_param(i915, &arg);
-}
-
-static uint32_t ctx_get_vm(int i915, uint32_t ctx)
-{
-        struct drm_i915_gem_context_param arg;
-
-        memset(&arg, 0, sizeof(arg));
-        arg.param = I915_CONTEXT_PARAM_VM;
-        arg.ctx_id = ctx;
-        gem_context_get_param(i915, &arg);
-        igt_assert(arg.value);
-
-        return arg.value;
-}
-
-static void virtual(int i915)
+static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
 {
 	const unsigned int wait_us = default_timeout_wait_s * USEC_PER_SEC;
-	unsigned int num_engines = __engines__->num_engines, i, count;
+	unsigned int num_engines = base_cfg->num_engines, i, count;
 	igt_spin_t *spin[num_engines];
 	unsigned int expect = num_engines;
-	uint32_t ctx[num_engines];
-	uint32_t vm;
+	intel_ctx_cfg_t cfg = *base_cfg;
+	const intel_ctx_t *ctx[num_engines];
 
 	igt_require(gem_has_execlists(i915));
 
 	igt_debug("%u virtual engines\n", num_engines);
 	igt_require(num_engines);
 
+	cfg.vm = gem_vm_create(i915);
+
 	i = 0;
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *ci;
 
-		ci = list_engines(class, &count);
+		ci = list_engines(base_cfg, class, &count);
 		if (!ci)
 			continue;
 
@@ -295,17 +237,12 @@ static void virtual(int i915)
 
 			igt_assert(i < num_engines);
 
-			ctx[i] = gem_context_create(i915);
+			ctx[i] = intel_ctx_create(i915, &cfg);
 
-			if (!i)
-				vm = ctx_get_vm(i915, ctx[i]);
-			else
-				ctx_set_vm(i915, ctx[i], vm);
-
-			set_load_balancer(i915, ctx[i], ci, count, NULL);
+			set_load_balancer(i915, ctx[i]->id, ci, count, NULL);
 
 			spin[i] = igt_spin_new(i915,
-					       .ctx_id = ctx[i],
+					       .ctx = ctx[i],
 					       .flags = spin_flags());
 			i++;
 		}
@@ -316,8 +253,8 @@ static void virtual(int i915)
 	count = wait_timeout(i915, spin, num_engines, wait_us, expect);
 
 	for (i = 0; i < num_engines && spin[i]; i++) {
-		gem_context_destroy(i915, ctx[i]);
 		igt_spin_free(i915, spin[i]);
+		intel_ctx_destroy(i915, ctx[i]);
 	}
 
 	igt_assert_eq(count, expect);
@@ -498,17 +435,6 @@ delay_create(int i915, uint32_t ctx,
 	return obj;
 }
 
-static uint32_t vm_clone(int i915)
-{
-	uint32_t ctx = 0;
-	__gem_context_clone(i915, 0,
-			    I915_CONTEXT_CLONE_VM |
-			    I915_CONTEXT_CLONE_ENGINES,
-			    I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE,
-			    &ctx);
-	return ctx;
-}
-
 static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
 {
 	int err;
@@ -525,6 +451,7 @@ static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
 
 static uint32_t
 far_delay(int i915, unsigned long delay, unsigned int target,
+	  const intel_ctx_t *ctx,
 	  const struct intel_execution_engine2 *e, int *fence)
 {
 	struct drm_i915_gem_exec_object2 obj = delay_create(i915, 0, e, delay);
@@ -539,6 +466,7 @@ far_delay(int i915, unsigned long delay, unsigned int target,
 		.buffer_count = 2,
 		.flags = e->flags,
 	};
+	intel_ctx_cfg_t cfg = ctx->cfg;
 	uint32_t handle = gem_create(i915, 4096);
 	unsigned long count, submit;
 
@@ -551,23 +479,27 @@ far_delay(int i915, unsigned long delay, unsigned int target,
 	submit *= NSEC_PER_SEC;
 	submit /= 2 * delay;
 
+	if (gem_has_vm(i915))
+		cfg.vm = gem_vm_create(i915);
+
 	/*
 	 * Submit a few long chains of individually short pieces of work
 	 * against a shared object.
 	 */
 	for (count = 0; count < submit;) {
-		execbuf.rsvd1 = vm_clone(i915);
+		const intel_ctx_t *tmp_ctx = intel_ctx_create(i915, &cfg);
+		execbuf.rsvd1 = tmp_ctx->id;
 		if (!execbuf.rsvd1)
 			break;
 
 		batch[1] = obj;
 		while (__execbuf(i915, &execbuf) == 0)
 			count++;
-		gem_context_destroy(i915, execbuf.rsvd1);
+		intel_ctx_destroy(i915, tmp_ctx);
 	}
 
 	execbuf.flags |= I915_EXEC_FENCE_OUT;
-	execbuf.rsvd1 = 0;
+	execbuf.rsvd1 = ctx->id;
 	batch[1] = batch[0];
 	batch[1].flags &= ~EXEC_OBJECT_WRITE;
 	batch[0].handle = handle;
@@ -583,11 +515,12 @@ far_delay(int i915, unsigned long delay, unsigned int target,
 }
 
 static void
-far_fence(int i915, int timeout, const struct intel_execution_engine2 *e)
+far_fence(int i915, int timeout, const intel_ctx_t *ctx,
+	  const struct intel_execution_engine2 *e)
 {
 	int fence = -1;
 	uint32_t handle =
-		far_delay(i915, NSEC_PER_SEC / 250, timeout, e, &fence);
+		far_delay(i915, NSEC_PER_SEC / 250, timeout, ctx, e, &fence);
 
 	gem_close(i915, handle);
 
@@ -626,10 +559,10 @@ far_fence(int i915, int timeout, const struct intel_execution_engine2 *e)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int i915 = -1;
 
 	igt_fixture {
-		struct drm_i915_query_item item;
 		char *tmp;
 
 		i915 = drm_open_driver_master(DRIVER_INTEL);
@@ -651,32 +584,22 @@ igt_main
 		}
 
 		i915 = gem_reopen_driver(i915); /* Apply modparam. */
-
-		__engines__ = malloc(4096);
-		igt_assert(__engines__);
-		memset(__engines__, 0, 4096);
-		memset(&item, 0, sizeof(item));
-		item.query_id = DRM_I915_QUERY_ENGINE_INFO;
-		item.data_ptr = to_user_pointer(__engines__);
-		item.length = 4096;
-		i915_query_items(i915, &item, 1);
-		igt_assert(item.length >= 0);
-		igt_assert(item.length <= 4096);
-		igt_assert(__engines__->num_engines > 0);
+		ctx = intel_ctx_create_all_physical(i915);
 	}
 
 	igt_subtest_group {
 		igt_subtest("default-physical")
-			physical(i915);
+			physical(i915, ctx);
 
 		igt_subtest("default-virtual")
-			virtual(i915);
+			virtual(i915, &ctx->cfg);
 	}
 
 	igt_subtest_with_dynamic("far-fence") {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				far_fence(i915, default_timeout_wait_s * 3, e);
+				far_fence(i915, default_timeout_wait_s * 3,
+					  ctx, e);
 		}
 	}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 49/74] tests/i915/gem_shrink: Convert to intel_ctx_t

[Jason Ekstrand]

Only one subtest actually needs to iterate over engines.
---
 tests/i915/gem_shrink.c | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
index 2269da49..51f27bf0 100644
--- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c
@@ -37,8 +37,6 @@
 #define MADV_FREE 8
 #endif
 
-static unsigned int engines[I915_EXEC_RING_MASK + 1], nengine;
-
 static void get_pages(int fd, uint64_t alloc)
 {
 	uint32_t handle = gem_create(fd, alloc);
@@ -163,8 +161,10 @@ static void execbufN(int fd, uint64_t alloc)
 static void execbufX(int fd, uint64_t alloc)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	const struct intel_execution_engine2 *e;
 	struct drm_i915_gem_exec_object2 *obj;
 	struct drm_i915_gem_execbuffer2 execbuf;
+	const intel_ctx_t *ctx;
 	int count = alloc >> 20;
 	uint64_t obj_size;
 
@@ -174,23 +174,32 @@ static void execbufX(int fd, uint64_t alloc)
 	obj[count].handle = gem_create(fd, 4096);
 	gem_write(fd, obj[count].handle, 0, &bbe, sizeof(bbe));
 
-	for (int i = 1; i <= count; i++) {
-		int j = count - i;
+	ctx = intel_ctx_create_all_physical(fd);
 
-		obj[j+1].flags = 0;
+	for (int i = 1; i <= count;) {
+		for_each_ctx_engine(fd, ctx, e) {
+			int j = count - i;
 
-		obj[j].handle = gem_create(fd, 1 << 20);
-		obj[j].flags = EXEC_OBJECT_WRITE;
+			obj[j+1].flags = 0;
 
-		execbuf.buffers_ptr = to_user_pointer(&obj[j]);
-		execbuf.buffer_count = i + 1;
-		execbuf.flags = engines[j % nengine];
-		gem_execbuf(fd, &execbuf);
+			obj[j].handle = gem_create(fd, 1 << 20);
+			obj[j].flags = EXEC_OBJECT_WRITE;
+
+			execbuf.buffers_ptr = to_user_pointer(&obj[j]);
+			execbuf.buffer_count = i + 1;
+			execbuf.flags = e->flags;
+			execbuf.rsvd1 = ctx->id;
+			gem_execbuf(fd, &execbuf);
+
+			i++;
+		}
 	}
 
 	for (int i = 0; i <= count; i++)
 		gem_madvise(fd, obj[i].handle, I915_MADV_DONTNEED);
 	munmap(obj, obj_size);
+
+	intel_ctx_destroy(fd, ctx);
 }
 
 static void hang(int fd, uint64_t alloc)
@@ -428,7 +437,6 @@ igt_main
 	igt_fixture {
 		const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 		uint64_t mem_size = intel_get_total_ram_mb();
-		const struct intel_execution_engine2 *e;
 		int fd;
 
 		fd = drm_open_driver(DRIVER_INTEL);
@@ -450,11 +458,6 @@ igt_main
 		intel_require_memory(num_processes, alloc_size,
 				     CHECK_SWAP | CHECK_RAM);
 
-		nengine = 0;
-		__for_each_physical_engine(fd, e)
-			engines[nengine++] = e->flags;
-		igt_require(nengine);
-
 		close(fd);
 	}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 50/74] tests/i915/gem_exec_params: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_params.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_params.c b/tests/i915/gem_exec_params.c
index 6840cf40..05052882 100644
--- a/tests/i915/gem_exec_params.c
+++ b/tests/i915/gem_exec_params.c
@@ -298,8 +298,10 @@ static void test_larger_than_life_batch(int fd)
 {
 	const struct intel_execution_engine2 *e;
 	uint64_t size = 1ULL << 32; /* batch_len is __u32 as per the ABI */
+	const intel_ctx_t *ctx = intel_ctx_create_all_physical(fd);
 	struct drm_i915_gem_exec_object2 exec = {
 		.handle = batch_create_size(fd, size),
+		.rsvd1 = ctx->id,
 	};
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&exec),
@@ -315,7 +317,7 @@ static void test_larger_than_life_batch(int fd)
 	igt_require(size < gem_aperture_size(fd));
 	intel_require_memory(2, size, CHECK_RAM); /* batch + shadow */
 
-	__for_each_physical_engine(fd, e) {
+	for_each_ctx_engine(fd, ctx, e) {
 		/* Keep the batch_len implicit [0] */
 		execbuf.flags = e->flags;
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 51/74] tests/i915/gem_exec_gttfill: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_gttfill.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c
index c0e27c9b..d375d671 100644
--- a/tests/i915/gem_exec_gttfill.c
+++ b/tests/i915/gem_exec_gttfill.c
@@ -105,7 +105,7 @@ static void submit(int fd, int gen,
 	gem_sync(fd, obj.handle);
 }
 
-static void fillgtt(int fd, unsigned ring, int timeout)
+static void fillgtt(int fd, const intel_ctx_t *ctx, unsigned ring, int timeout)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -125,7 +125,7 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	if (ring == ALL_ENGINES) {
 		struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			if (!gem_class_can_store_dword(fd, e->class))
 				continue;
 
@@ -154,6 +154,7 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	execbuf.buffer_count = 1;
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	batches = calloc(count, sizeof(*batches));
 	igt_assert(batches);
@@ -208,29 +209,31 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int i915 = -1;
 
 	igt_fixture {
 		i915 = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(i915);
+		ctx = intel_ctx_create_all_physical(i915);
 		igt_fork_hang_detector(i915);
 	}
 
 	igt_subtest("basic") /* just enough to run a single pass */
-		fillgtt(i915, ALL_ENGINES, 1);
+		fillgtt(i915, ctx, ALL_ENGINES, 1);
 
 	igt_subtest_with_dynamic("engines") {
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_engine(i915, ctx, e) {
 			if (!gem_class_can_store_dword(i915, e->class))
 				continue;
 
 			igt_dynamic_f("%s", e->name)
-				fillgtt(i915, e->flags, 20);
+				fillgtt(i915, ctx, e->flags, 20);
 		}
 	}
 
 	igt_subtest("all")
-		fillgtt(i915, ALL_ENGINES, 20);
+		fillgtt(i915, ctx, ALL_ENGINES, 20);
 
 	igt_fixture {
 		igt_stop_hang_detector();
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 52/74] tests/i915/gem_exec_capture: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_capture.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 3da78d63..e0bb5b4d 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -60,7 +60,8 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
 	igt_assert(found);
 }
 
-static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
+static void __capture1(int fd, int dir, const intel_ctx_t *ctx,
+		       unsigned ring, uint32_t target)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
 	struct drm_i915_gem_exec_object2 obj[4];
@@ -147,6 +148,7 @@ static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
 	execbuf.flags = ring;
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
 
 	igt_assert(!READ_ONCE(*seqno));
 	gem_execbuf(fd, &execbuf);
@@ -167,12 +169,12 @@ static void __capture1(int fd, int dir, unsigned ring, uint32_t target)
 	gem_close(fd, obj[SCRATCH].handle);
 }
 
-static void capture(int fd, int dir, unsigned ring)
+static void capture(int fd, int dir, const intel_ctx_t *ctx, unsigned ring)
 {
 	uint32_t handle;
 
 	handle = gem_create(fd, 4096);
-	__capture1(fd, dir, ring, handle);
+	__capture1(fd, dir, ctx, ring, handle);
 	gem_close(fd, handle);
 }
 
@@ -495,7 +497,8 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
 	free(offsets);
 }
 
-static void prioinv(int fd, int dir, unsigned ring, const char *name)
+static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
+		    unsigned ring, const char *name)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_exec_object2 obj = {
@@ -505,6 +508,7 @@ static void prioinv(int fd, int dir, unsigned ring, const char *name)
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
 		.flags = ring,
+		.rsvd1 = ctx->id,
 	};
 	int64_t timeout = NSEC_PER_SEC; /* 1s, feeling generous, blame debug */
 	uint64_t ram, gtt, size = 4 << 20;
@@ -572,7 +576,7 @@ static void userptr(int fd, int dir)
 	igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
 	igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
 
-	__capture1(fd, dir, 0, handle);
+	__capture1(fd, dir, intel_ctx_0(fd), 0, handle);
 
 	gem_close(fd, handle);
 	free(ptr);
@@ -595,14 +599,15 @@ static size_t safer_strlen(const char *s)
 	return s ? strlen(s) : 0;
 }
 
-#define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+#define test_each_engine(T, i915, ctx, e) \
+	igt_subtest_with_dynamic(T) for_each_ctx_engine(i915, ctx, e) \
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	igt_hang_t hang;
 	int fd = -1;
 	int dir = -1;
@@ -619,15 +624,16 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_mmap_wc(fd);
 		igt_require(has_capture(fd));
-		igt_allow_hang(fd, 0, HANG_ALLOW_CAPTURE);
+		ctx = intel_ctx_create_all_physical(fd);
+		igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE);
 
 		dir = igt_sysfs_open(fd);
 		igt_require(igt_sysfs_set(dir, "error", "Begone!"));
 		igt_require(safer_strlen(igt_sysfs_get(dir, "error")) > 0);
 	}
 
-	test_each_engine("capture", fd, e)
-		capture(fd, dir, e->flags);
+	test_each_engine("capture", fd, ctx, e)
+		capture(fd, dir, ctx, e->flags);
 
 	igt_subtest_f("many-4K-zero") {
 		igt_require(gem_can_store_dword(fd, 0));
@@ -661,8 +667,8 @@ igt_main
 		userptr(fd, dir);
 	}
 
-	test_each_engine("pi", fd, e)
-		prioinv(fd, dir, e->flags, e->name);
+	test_each_engine("pi", fd, ctx, e)
+		prioinv(fd, dir, ctx, e->flags, e->name);
 
 	igt_fixture {
 		close(dir);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 53/74] tests/i915/gem_exec_create: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_create.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_create.c b/tests/i915/gem_exec_create.c
index 6529da7e..7434b3e4 100644
--- a/tests/i915/gem_exec_create.c
+++ b/tests/i915/gem_exec_create.c
@@ -60,16 +60,21 @@ static void all(int fd, unsigned flags, int timeout, int ncpus)
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj;
 	unsigned engines[I915_EXEC_RING_MASK + 1], nengine;
+	const intel_ctx_t *ctx;
 
 	nengine = 0;
 	if (flags & ENGINES) { /* Modern API to iterate over *all* engines */
 		const struct intel_execution_engine2 *e;
 
-		__for_each_physical_engine(fd, e)
+		ctx = intel_ctx_create_all_physical(fd);
+
+		for_each_ctx_engine(fd, ctx, e)
 			engines[nengine++] = e->flags;
 
 		/* Note: modifies engine map on context 0 */
 	} else {
+		ctx = intel_ctx_0(fd);
+
 		for_each_physical_ring(e, fd)
 			engines[nengine++] = eb_ring(e);
 	}
@@ -84,6 +89,7 @@ static void all(int fd, unsigned flags, int timeout, int ncpus)
 	execbuf.buffer_count = 1;
 	execbuf.flags |= I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= I915_EXEC_NO_RELOC;
+	execbuf.rsvd1 = ctx->id;
 	if (__gem_execbuf(fd, &execbuf)) {
 		execbuf.flags = 0;
 		gem_execbuf(fd, &execbuf);
@@ -131,6 +137,7 @@ static void all(int fd, unsigned flags, int timeout, int ncpus)
 	}
 	igt_waitchildren();
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+	intel_ctx_destroy(fd, ctx);
 }
 
 igt_main
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 54/74] tests/i915/gem_exec_await: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_exec_await.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/tests/i915/gem_exec_await.c b/tests/i915/gem_exec_await.c
index e64d2a94..8d26a173 100644
--- a/tests/i915/gem_exec_await.c
+++ b/tests/i915/gem_exec_await.c
@@ -62,16 +62,19 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 		struct drm_i915_gem_exec_object2 exec[2];
 		struct drm_i915_gem_relocation_entry reloc;
 		struct drm_i915_gem_execbuffer2 execbuf;
+		const intel_ctx_t *ctx;
 		uint32_t *cmd;
 	} *exec;
 	struct drm_i915_gem_exec_object2 *obj;
 	struct drm_i915_gem_execbuffer2 execbuf;
+	const intel_ctx_t *ctx;
 	unsigned engines[I915_EXEC_RING_MASK + 1], nengine;
 	unsigned long count;
 	double time;
 
+	ctx = intel_ctx_create_all_physical(fd);
 	nengine = 0;
-	__for_each_physical_engine(fd, engine) {
+	for_each_ctx_engine(fd, ctx, engine) {
 		if (!gem_class_has_mutable_submission(fd, engine->class))
 			continue;
 
@@ -105,7 +108,10 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 					 I915_EXEC_HANDLE_LUT);
 
 		if (flags & CONTEXTS) {
-			exec[e].execbuf.rsvd1 = gem_context_create(fd);
+			exec[e].ctx = intel_ctx_create(fd, &ctx->cfg);
+			exec[e].execbuf.rsvd1 = exec[e].ctx->id;
+		} else {
+			exec[e].execbuf.rsvd1 = ctx->id;
 		}
 
 		exec[e].exec[0].handle = gem_create(fd, 4096);
@@ -150,9 +156,9 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 			int i;
 
 			if (flags & CONTEXTS) {
-				gem_context_destroy(fd, exec[e].execbuf.rsvd1);
-				exec[e].execbuf.rsvd1 =
-					gem_context_clone_with_engines(fd, 0);
+				intel_ctx_destroy(fd, exec[e].ctx);
+				exec[e].ctx = intel_ctx_create(fd, &ctx->cfg);
+				exec[e].execbuf.rsvd1 = exec[e].ctx->id;
 			}
 
 			exec[e].reloc.presumed_offset = exec[e].exec[1].offset;
@@ -192,6 +198,7 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 			execbuf.flags = (engines[e] |
 					 I915_EXEC_NO_RELOC |
 					 I915_EXEC_HANDLE_LUT);
+			execbuf.rsvd1 = ctx->id;
 			gem_execbuf(fd, &execbuf);
 		}
 		clock_gettime(CLOCK_MONOTONIC, &now);
@@ -213,7 +220,7 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 
 	for (unsigned e = 0; e < nengine; e++) {
 		if (flags & CONTEXTS)
-			gem_context_destroy(fd, exec[e].execbuf.rsvd1);
+			intel_ctx_destroy(fd, exec[e].ctx);
 
 		for (unsigned n = 0; n < ring_size; n++)
 			gem_close(fd, exec[e].obj[n].handle);
@@ -222,6 +229,7 @@ static void wide(int fd, int ring_size, int timeout, unsigned int flags)
 		munmap(exec[e].cmd, 4096);
 		gem_close(fd, exec[e].exec[1].handle);
 	}
+	intel_ctx_destroy(fd, ctx);
 	free(exec);
 }
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 55/74] tests/i915/gem_ctx_persistence: Drop the clone subtest

[Jason Ekstrand]

---
 tests/i915/gem_ctx_persistence.c | 30 ------------------------------
 1 file changed, 30 deletions(-)

diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index 10d057f1..91c30176 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -147,33 +147,6 @@ static void test_idempotent(int i915)
 	igt_assert_eq(p.value, expected);
 }
 
-static void test_clone(int i915)
-{
-	struct drm_i915_gem_context_param p = {
-		.param = I915_CONTEXT_PARAM_PERSISTENCE,
-	};
-	uint32_t ctx, clone;
-
-	/*
-	 * Check that persistence is inherited across a clone.
-	 */
-	igt_require( __gem_context_create(i915, &ctx) == 0);
-
-	p.ctx_id = ctx;
-	p.value = 0;
-	gem_context_set_param(i915, &p);
-
-	clone = gem_context_clone(i915, ctx, I915_CONTEXT_CLONE_FLAGS, 0);
-	gem_context_destroy(i915, ctx);
-
-	p.ctx_id = clone;
-	p.value = -1;
-	gem_context_get_param(i915, &p);
-	igt_assert_eq(p.value, 0);
-
-	gem_context_destroy(i915, clone);
-}
-
 static void test_persistence(int i915, unsigned int engine)
 {
 	igt_spin_t *spin;
@@ -1366,9 +1339,6 @@ igt_main
 	igt_subtest("idempotent")
 		test_idempotent(i915);
 
-	igt_subtest("clone")
-		test_clone(i915);
-
 	igt_subtest("file")
 		test_nonpersistent_file(i915);
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 56/74] tests/i915/gem_ctx_persistence: Drop the engine replace subtests

[Jason Ekstrand]

We're going to start disallowing non-trivial uses of setparam for
engines precisely to make races like this impossible.  It'll also make
these test cases invalid.
---
 tests/i915/gem_ctx_persistence.c | 210 -------------------------------
 1 file changed, 210 deletions(-)

diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index 91c30176..59077cc0 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -1085,191 +1085,6 @@ static void many_contexts(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void replace_engines(int i915, const struct intel_execution_engine2 *e)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
-		.engines = {{ e->class, e->instance }}
-	};
-	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
-	};
-	igt_spin_t *spin[2];
-	int64_t timeout;
-
-	/*
-	 * Suppose the user tries to hide a hanging batch by replacing
-	 * the set of engines on the context so that it's not visible
-	 * at the time of closure? Then we must act when they replace
-	 * the engines!
-	 */
-
-	gem_context_set_persistence(i915, param.ctx_id, false);
-
-	gem_context_set_param(i915, &param);
-	spin[0] = igt_spin_new(i915, param.ctx_id);
-
-	gem_context_set_param(i915, &param);
-	spin[1] = igt_spin_new(i915, param.ctx_id);
-
-	gem_context_destroy(i915, param.ctx_id);
-
-	timeout = reset_timeout_ms * NSEC_PER_MSEC;
-	igt_assert_eq(gem_wait(i915, spin[1]->handle, &timeout), 0);
-
-	timeout = reset_timeout_ms * NSEC_PER_MSEC;
-	igt_assert_eq(gem_wait(i915, spin[0]->handle, &timeout), 0);
-
-	igt_spin_free(i915, spin[1]);
-	igt_spin_free(i915, spin[0]);
-	gem_quiescent_gpu(i915);
-}
-
-static void race_set_engines(int i915, int in, int out)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
-		.engines = {}
-	};
-	struct drm_i915_gem_context_param param = {
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
-	};
-	igt_spin_t *spin;
-
-	spin = igt_spin_new(i915);
-	igt_spin_end(spin);
-
-	while (read(in, &param.ctx_id, sizeof(param.ctx_id)) > 0) {
-		if (!param.ctx_id)
-			break;
-
-		__gem_context_set_param(i915, &param);
-
-		spin->execbuf.rsvd1 = param.ctx_id;
-		__gem_execbuf(i915, &spin->execbuf);
-
-		write(out, &param.ctx_id, sizeof(param.ctx_id));
-	}
-
-	igt_spin_free(i915, spin);
-}
-
-static void close_replace_race(int i915)
-{
-	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
-	int fence = -1;
-	int out[2], in[2];
-
-	cleanup(i915);
-
-	/*
-	 * If we time the submission of a hanging batch to one set of engines
-	 * and then simultaneously replace the engines in one thread, and
-	 * close the context in another, it might be possible for the kernel
-	 * to lose track of the old engines believing that the non-persisten
-	 * context is already closed and the hanging requests cancelled.
-	 *
-	 * Our challenge is try and expose any such race condition.
-	 */
-
-	igt_assert(pipe(out) == 0);
-	igt_assert(pipe(in) == 0);
-	igt_fork(child, ncpus) {
-		close(out[1]);
-		close(in[0]);
-		race_set_engines(i915, out[0], in[1]);
-	}
-	for (int i = 0; i < ncpus; i++)
-		close(out[0]);
-
-	igt_until_timeout(5) {
-		igt_spin_t *spin;
-		uint32_t ctx;
-
-		ctx = gem_context_clone_with_engines(i915, 0);
-		gem_context_set_persistence(i915, ctx, false);
-
-		spin = igt_spin_new(i915, ctx, .flags = IGT_SPIN_FENCE_OUT);
-		for (int i = 0; i < ncpus; i++)
-			write(out[1], &ctx, sizeof(ctx));
-
-		gem_context_destroy(i915, ctx);
-		for (int i = 0; i < ncpus; i++)
-			read(in[0], &ctx, sizeof(ctx));
-
-		if (fence < 0) {
-			fence = spin->out_fence;
-		} else {
-			int tmp;
-
-			tmp = sync_fence_merge(fence, spin->out_fence);
-			close(fence);
-			close(spin->out_fence);
-
-			fence = tmp;
-		}
-		spin->out_fence = -1;
-	}
-	close(in[0]);
-
-	for (int i = 0; i < ncpus; i++) {
-		uint32_t end = 0;
-
-		write(out[1], &end, sizeof(end));
-	}
-	close(out[1]);
-
-	if (sync_fence_wait(fence, MSEC_PER_SEC / 2)) {
-		igt_debugfs_dump(i915, "i915_engine_info");
-		igt_assert(sync_fence_wait(fence, MSEC_PER_SEC / 2) == 0);
-	}
-	close(fence);
-
-	igt_waitchildren();
-	gem_quiescent_gpu(i915);
-}
-
-static void replace_engines_hostile(int i915,
-				    const struct intel_execution_engine2 *e)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
-		.engines = {{ e->class, e->instance }}
-	};
-	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
-	};
-	int64_t timeout = reset_timeout_ms * NSEC_PER_MSEC;
-	igt_spin_t *spin;
-
-	/*
-	 * Suppose the user tries to hide a hanging batch by replacing
-	 * the set of engines on the context so that it's not visible
-	 * at the time of closure? Then we must act when they replace
-	 * the engines!
-	 */
-
-	gem_context_set_persistence(i915, param.ctx_id, false);
-
-	gem_context_set_param(i915, &param);
-	spin = igt_spin_new(i915, param.ctx_id,
-			    .flags = IGT_SPIN_NO_PREEMPTION);
-
-	param.size = 8;
-	gem_context_set_param(i915, &param);
-	gem_context_destroy(i915, param.ctx_id);
-
-	igt_assert_eq(gem_wait(i915, spin->handle, &timeout), 0);
-
-	igt_spin_free(i915, spin);
-	gem_quiescent_gpu(i915);
-}
-
 static void do_test(void (*test)(int i915, unsigned int engine),
 		    int i915, unsigned int engine,
 		    const char *name)
@@ -1422,31 +1237,6 @@ igt_main
 			smoketest(i915);
 	}
 
-	/* Check interactions with set-engines */
-	igt_subtest_group {
-		const struct intel_execution_engine2 *e;
-
-		igt_fixture
-			gem_require_contexts(i915);
-
-		igt_subtest_with_dynamic("replace") {
-			__for_each_physical_engine(i915, e) {
-				igt_dynamic_f("%s", e->name)
-					replace_engines(i915, e);
-			}
-		}
-
-		igt_subtest_with_dynamic("replace-hostile") {
-			__for_each_physical_engine(i915, e) {
-				igt_dynamic_f("%s", e->name)
-					replace_engines_hostile(i915, e);
-			}
-		}
-
-		igt_subtest("close-replace-race")
-			close_replace_race(i915);
-	}
-
 	igt_fixture {
 		close(i915);
 	}
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 57/74] tests/i915/gem_ctx_persistence: Convert to intel_ctx_t

[Jason Ekstrand]

---
 lib/intel_ctx.c                  |  13 ++
 lib/intel_ctx.h                  |   2 +
 tests/i915/gem_ctx_persistence.c | 201 ++++++++++++++++---------------
 3 files changed, 122 insertions(+), 94 deletions(-)

diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index 75c77fbd..9983fcc5 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -64,6 +64,7 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
 	uint64_t ext_root = 0;
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
 	struct drm_i915_gem_context_create_ext_setparam engines_param, vm_param;
+	struct drm_i915_gem_context_create_ext_setparam persist_param;
 	uint32_t i;
 
 	if (cfg->vm) {
@@ -79,6 +80,18 @@ __context_create_cfg(int fd, const intel_ctx_cfg_t *cfg, uint32_t *ctx_id)
 		add_user_ext(&ext_root, &vm_param.base);
 	}
 
+	if (cfg->nopersist) {
+		persist_param = (struct drm_i915_gem_context_create_ext_setparam) {
+			.base = {
+				.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			},
+			.param = {
+				.param = I915_CONTEXT_PARAM_PERSISTENCE,
+			},
+		};
+		add_user_ext(&ext_root, &persist_param.base);
+	}
+
 	if (cfg->num_engines) {
 		memset(&engines, 0, sizeof(engines));
 		for (i = 0; i < cfg->num_engines; i++)
diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h
index e61d6c91..f3f97484 100644
--- a/lib/intel_ctx.h
+++ b/lib/intel_ctx.h
@@ -34,6 +34,7 @@
  * intel_ctx_cfg_t:
  * @flags: Context create flags
  * @vm: VM to inherit or 0 for using a per-context VM
+ * @nopersist: set I915_CONTEXT_PARAM_PERSISTENCE to 0
  * @num_engines: Number of client-specified engines or 0 for legacy mode
  * @engines: Client-specified engines
  *
@@ -42,6 +43,7 @@
 typedef struct intel_ctx_cfg {
 	uint32_t flags;
 	uint32_t vm;
+	bool nopersist;
 	unsigned int num_engines;
 	struct i915_engine_class_instance engines[GEM_MAX_ENGINES];
 } intel_ctx_cfg_t;
diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c
index 59077cc0..78b2258f 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -147,24 +147,32 @@ static void test_idempotent(int i915)
 	igt_assert_eq(p.value, expected);
 }
 
-static void test_persistence(int i915, unsigned int engine)
+static const intel_ctx_t *
+ctx_create_persistence(int i915, const intel_ctx_cfg_t *base_cfg, bool persist)
+{
+	intel_ctx_cfg_t cfg = *base_cfg;
+	cfg.nopersist = !persist;
+	return intel_ctx_create(i915, &cfg);
+}
+
+static void test_persistence(int i915, const intel_ctx_cfg_t *cfg,
+			     unsigned int engine)
 {
 	igt_spin_t *spin;
 	int64_t timeout;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * Default behaviour are contexts remain alive until their last active
 	 * request is retired -- no early termination.
 	 */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, true);
+	ctx = ctx_create_persistence(i915, cfg, true);
 
-	spin = igt_spin_new(i915, ctx,
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_FENCE_OUT);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	timeout = reset_timeout_ms * NSEC_PER_MSEC;
 	igt_assert_eq(gem_wait(i915, spin->handle, &timeout), -ETIME);
@@ -178,24 +186,24 @@ static void test_persistence(int i915, unsigned int engine)
 	igt_spin_free(i915, spin);
 }
 
-static void test_nonpersistent_cleanup(int i915, unsigned int engine)
+static void test_nonpersistent_cleanup(int i915, const intel_ctx_cfg_t *cfg,
+				       unsigned int engine)
 {
 	int64_t timeout = reset_timeout_ms * NSEC_PER_MSEC;
 	igt_spin_t *spin;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * A nonpersistent context is terminated immediately upon closure,
 	 * any inflight request is cancelled.
 	 */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
+	ctx = ctx_create_persistence(i915, cfg, false);
 
-	spin = igt_spin_new(i915, ctx,
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_FENCE_OUT);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_assert_eq(gem_wait(i915, spin->handle, &timeout), 0);
 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
@@ -203,7 +211,8 @@ static void test_nonpersistent_cleanup(int i915, unsigned int engine)
 	igt_spin_free(i915, spin);
 }
 
-static void test_nonpersistent_mixed(int i915, unsigned int engine)
+static void test_nonpersistent_mixed(int i915, const intel_ctx_cfg_t *cfg,
+				     unsigned int engine)
 {
 	int fence[3];
 
@@ -215,15 +224,14 @@ static void test_nonpersistent_mixed(int i915, unsigned int engine)
 
 	for (int i = 0; i < ARRAY_SIZE(fence); i++) {
 		igt_spin_t *spin;
-		uint32_t ctx;
+		const intel_ctx_t *ctx;
 
-		ctx = gem_context_clone_with_engines(i915, 0);
-		gem_context_set_persistence(i915, ctx, i & 1);
+		ctx = ctx_create_persistence(i915, cfg, i & 1);
 
-		spin = igt_spin_new(i915, ctx,
+		spin = igt_spin_new(i915, .ctx = ctx,
 				    .engine = engine,
 				    .flags = IGT_SPIN_FENCE_OUT);
-		gem_context_destroy(i915, ctx);
+		intel_ctx_destroy(i915, ctx);
 
 		fence[i] = spin->out_fence;
 	}
@@ -236,11 +244,12 @@ static void test_nonpersistent_mixed(int i915, unsigned int engine)
 	igt_assert_eq(sync_fence_wait(fence[1], 0), -ETIME);
 }
 
-static void test_nonpersistent_hostile(int i915, unsigned int engine)
+static void test_nonpersistent_hostile(int i915, const intel_ctx_cfg_t *cfg,
+				       unsigned int engine)
 {
 	int64_t timeout = reset_timeout_ms * NSEC_PER_MSEC;
 	igt_spin_t *spin;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * If we cannot cleanly cancel the non-persistent context on closure,
@@ -248,24 +257,24 @@ static void test_nonpersistent_hostile(int i915, unsigned int engine)
 	 * the requests and cleanup the context.
 	 */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
+	ctx = ctx_create_persistence(i915, cfg, false);
 
-	spin = igt_spin_new(i915, ctx,
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_NO_PREEMPTION);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_assert_eq(gem_wait(i915, spin->handle, &timeout), 0);
 
 	igt_spin_free(i915, spin);
 }
 
-static void test_nonpersistent_hostile_preempt(int i915, unsigned int engine)
+static void test_nonpersistent_hostile_preempt(int i915, const intel_ctx_cfg_t *cfg,
+					       unsigned int engine)
 {
 	int64_t timeout = reset_timeout_ms * NSEC_PER_MSEC;
 	igt_spin_t *spin[2];
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * Double plus ungood.
@@ -278,24 +287,22 @@ static void test_nonpersistent_hostile_preempt(int i915, unsigned int engine)
 
 	igt_require(gem_scheduler_has_preemption(i915));
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, true);
-	gem_context_set_priority(i915, ctx, 0);
-	spin[0] = igt_spin_new(i915, ctx,
+	ctx = ctx_create_persistence(i915, cfg, true);
+	gem_context_set_priority(i915, ctx->id, 0);
+	spin[0] = igt_spin_new(i915, .ctx = ctx,
 			       .engine = engine,
 			       .flags = (IGT_SPIN_NO_PREEMPTION |
 					 IGT_SPIN_POLL_RUN));
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_spin_busywait_until_started(spin[0]);
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
-	gem_context_set_priority(i915, ctx, 1); /* higher priority than 0 */
-	spin[1] = igt_spin_new(i915, ctx,
+	ctx = ctx_create_persistence(i915, cfg, false);
+	gem_context_set_priority(i915, ctx->id, 1); /* higher priority than 0 */
+	spin[1] = igt_spin_new(i915, .ctx = ctx,
 			       .engine = engine,
 			       .flags = IGT_SPIN_NO_PREEMPTION);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_assert_eq(gem_wait(i915, spin[1]->handle, &timeout), 0);
 
@@ -303,24 +310,24 @@ static void test_nonpersistent_hostile_preempt(int i915, unsigned int engine)
 	igt_spin_free(i915, spin[0]);
 }
 
-static void test_nonpersistent_hang(int i915, unsigned int engine)
+static void test_nonpersistent_hang(int i915, const intel_ctx_cfg_t *cfg,
+				    unsigned int engine)
 {
 	int64_t timeout = reset_timeout_ms * NSEC_PER_MSEC;
 	igt_spin_t *spin;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * The user made a simple mistake and submitted an invalid batch,
 	 * but fortunately under a nonpersistent context. Do we detect it?
 	 */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
+	ctx = ctx_create_persistence(i915, cfg, false);
 
-	spin = igt_spin_new(i915, ctx,
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_INVALID_CS);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_assert_eq(gem_wait(i915, spin->handle, &timeout), 0);
 
@@ -578,22 +585,22 @@ static void alarm_handler(int sig)
 {
 }
 
-static void test_nonpersistent_queued(int i915, unsigned int engine)
+static void test_nonpersistent_queued(int i915, const intel_ctx_cfg_t *cfg,
+				      unsigned int engine)
 {
 	struct sigaction old_sa, sa = { .sa_handler = alarm_handler };
 	struct itimerval itv;
 	igt_spin_t *spin;
 	int fence = -1;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 
 	/*
 	 * Not only must the immediate batch be cancelled, but
 	 * all pending batches in the context.
 	 */
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
-	spin = igt_spin_new(i915, ctx,
+	ctx = ctx_create_persistence(i915, cfg, false);
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine,
 			    .flags = IGT_SPIN_FENCE_OUT);
 
@@ -621,7 +628,7 @@ static void test_nonpersistent_queued(int i915, unsigned int engine)
 	setitimer(ITIMER_REAL, &itv, NULL);
 	sigaction(SIGALRM, &old_sa, NULL);
 
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	igt_assert_eq(wait_for_status(spin->out_fence, reset_timeout_ms), -EIO);
 	igt_assert_eq(wait_for_status(fence, reset_timeout_ms), -EIO);
@@ -752,7 +759,8 @@ static void test_userptr(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void test_process_mixed(int pfd, unsigned int engine)
+static void test_process_mixed(int pfd, const intel_ctx_cfg_t *cfg,
+			       unsigned int engine)
 {
 	int fence[2], sv[2];
 
@@ -772,13 +780,10 @@ static void test_process_mixed(int pfd, unsigned int engine)
 
 		for (int persists = 0; persists <= 1; persists++) {
 			igt_spin_t *spin;
-			uint32_t ctx;
+			const intel_ctx_t *ctx;
 
-			ctx = gem_context_create(i915);
-			gem_context_copy_engines(pfd, 0, i915, ctx);
-			gem_context_set_persistence(i915, ctx, persists);
-
-			spin = igt_spin_new(i915, ctx,
+			ctx = ctx_create_persistence(i915, cfg, persists);
+			spin = igt_spin_new(i915, .ctx = ctx,
 					    .engine = engine,
 					    .flags = IGT_SPIN_FENCE_OUT);
 
@@ -810,11 +815,12 @@ static void test_process_mixed(int pfd, unsigned int engine)
 }
 
 static void
-test_saturated_hostile(int i915, const struct intel_execution_engine2 *engine)
+test_saturated_hostile(int i915, const intel_ctx_t *base_ctx,
+		       const struct intel_execution_engine2 *engine)
 {
 	const struct intel_execution_engine2 *other;
 	igt_spin_t *spin;
-	uint32_t ctx;
+	const intel_ctx_t *ctx;
 	int fence = -1;
 
 	cleanup(i915);
@@ -831,11 +837,11 @@ test_saturated_hostile(int i915, const struct intel_execution_engine2 *engine)
 	 * reset other users whenever they chose.]
 	 */
 
-	__for_each_physical_engine(i915, other) {
+	for_each_ctx_engine(i915, base_ctx, other) {
 		if (other->flags == engine->flags)
 			continue;
 
-		spin = igt_spin_new(i915,
+		spin = igt_spin_new(i915, .ctx = base_ctx,
 				   .engine = other->flags,
 				   .flags = (IGT_SPIN_NO_PREEMPTION |
 					     IGT_SPIN_FENCE_OUT));
@@ -855,15 +861,14 @@ test_saturated_hostile(int i915, const struct intel_execution_engine2 *engine)
 	}
 	igt_require(fence != -1);
 
-	ctx = gem_context_clone_with_engines(i915, 0);
-	gem_context_set_persistence(i915, ctx, false);
-	spin = igt_spin_new(i915, ctx,
+	ctx = ctx_create_persistence(i915, &base_ctx->cfg, false);
+	spin = igt_spin_new(i915, .ctx = ctx,
 			    .engine = engine->flags,
 			    .flags = (IGT_SPIN_NO_PREEMPTION |
 				      IGT_SPIN_POLL_RUN |
 				      IGT_SPIN_FENCE_OUT));
 	igt_spin_busywait_until_started(spin);
-	gem_context_destroy(i915, ctx);
+	intel_ctx_destroy(i915, ctx);
 
 	/* Hostile request requires a GPU reset to terminate */
 	igt_assert_eq(wait_for_status(spin->out_fence, reset_timeout_ms), -EIO);
@@ -950,7 +955,7 @@ static void test_processes(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void __smoker(int i915,
+static void __smoker(int i915, const intel_ctx_cfg_t *cfg,
 		     unsigned int engine,
 		     unsigned int timeout,
 		     int expected)
@@ -958,11 +963,12 @@ static void __smoker(int i915,
 	igt_spin_t *spin;
 	int fence = -1;
 	int fd, extra;
+	const intel_ctx_t *ctx;
 
 	fd = gem_reopen_driver(i915);
-	gem_context_copy_engines(i915, 0, fd, 0);
-	gem_context_set_persistence(fd, 0, expected > 0);
-	spin = igt_spin_new(fd, .engine = engine, .flags = IGT_SPIN_FENCE_OUT);
+	ctx = ctx_create_persistence(fd, cfg, expected > 0);
+	spin = igt_spin_new(fd, .ctx = ctx, .engine = engine,
+			    .flags = IGT_SPIN_FENCE_OUT);
 
 	extra = rand() % 8;
 	while (extra--) {
@@ -974,6 +980,8 @@ static void __smoker(int i915,
 		fence = spin->execbuf.rsvd2 >> 32;
 	}
 
+	intel_ctx_destroy(fd, ctx);
+
 	close(fd);
 	flush_delayed_fput(i915);
 
@@ -990,18 +998,18 @@ static void __smoker(int i915,
 	igt_spin_free(fd, spin);
 }
 
-static void smoker(int i915,
+static void smoker(int i915, const intel_ctx_cfg_t *cfg,
 		   unsigned int engine,
 		   unsigned int timeout,
 		   unsigned int *ctl)
 {
 	while (!READ_ONCE(*ctl)) {
-		__smoker(i915, engine, timeout, -EIO);
-		__smoker(i915, engine, timeout, 1);
+		__smoker(i915, cfg, engine, timeout, -EIO);
+		__smoker(i915, cfg, engine, timeout, 1);
 	}
 }
 
-static void smoketest(int i915)
+static void smoketest(int i915, const intel_ctx_cfg_t *cfg)
 {
 	const int SMOKE_LOAD_FACTOR = 4;
 	const struct intel_execution_engine2 *e;
@@ -1021,9 +1029,9 @@ static void smoketest(int i915)
 		*ctl = 0;
 
 		igt_debug("Applying load factor: %d\n", i);
-		__for_each_physical_engine(i915, e) {
+		for_each_ctx_cfg_engine(i915, cfg, e) {
 			igt_fork(child, i)
-				smoker(i915,
+				smoker(i915, cfg,
 				       e->flags,
 				       i * reset_timeout_ms,
 				       ctl);
@@ -1038,7 +1046,7 @@ static void smoketest(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void many_contexts(int i915)
+static void many_contexts(int i915, const intel_ctx_cfg_t *cfg)
 {
 	const struct intel_execution_engine2 *e;
 	int64_t timeout = NSEC_PER_SEC;
@@ -1059,17 +1067,16 @@ static void many_contexts(int i915)
 	igt_spin_reset(spin);
 
 	igt_until_timeout(30) {
-		__for_each_physical_engine(i915, e) {
-			uint32_t ctx;
+		for_each_ctx_cfg_engine(i915, cfg, e) {
+			const intel_ctx_t *ctx;
 
-			ctx = gem_context_clone_with_engines(i915, 0);
-			gem_context_set_persistence(i915, ctx, false);
+			ctx = ctx_create_persistence(i915, cfg, false);
 
-			spin->execbuf.rsvd1 = ctx;
+			spin->execbuf.rsvd1 = ctx->id;
 			spin->execbuf.flags &= ~63;
 			spin->execbuf.flags |= e->flags;
 			gem_execbuf(i915, &spin->execbuf);
-			gem_context_destroy(i915, ctx);
+			intel_ctx_destroy(i915, ctx);
 		}
 	}
 	igt_debugfs_dump(i915, "i915_engine_info");
@@ -1085,9 +1092,10 @@ static void many_contexts(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void do_test(void (*test)(int i915, unsigned int engine),
-		    int i915, unsigned int engine,
-		    const char *name)
+static void do_test(void (*test)(int i915, const intel_ctx_cfg_t *cfg,
+				 unsigned int engine),
+		    int i915, const intel_ctx_cfg_t *cfg,
+		    unsigned int engine, const char *name)
 {
 #define ATTR "preempt_timeout_ms"
 	int timeout = -1;
@@ -1101,7 +1109,7 @@ static void do_test(void (*test)(int i915, unsigned int engine),
 		reset_timeout_ms = 200;
 	}
 
-	test(i915, engine);
+	test(i915, cfg, engine);
 
 	if (timeout != -1) {
 		gem_engine_property_printf(i915, name, ATTR, "%d", timeout);
@@ -1122,7 +1130,8 @@ igt_main
 {
 	struct {
 		const char *name;
-		void (*func)(int fd, unsigned int engine);
+		void (*func)(int fd, const intel_ctx_cfg_t *cfg,
+			     unsigned int engine);
 	} *test, tests[] = {
 		{ "persistence", test_persistence },
 		{ "cleanup", test_nonpersistent_cleanup },
@@ -1134,6 +1143,7 @@ igt_main
 		{ "hang", test_nonpersistent_hang },
 		{ NULL, NULL },
 	};
+	const intel_ctx_t *ctx;
 
 	igt_fixture {
 		i915 = drm_open_driver(DRIVER_INTEL);
@@ -1145,6 +1155,8 @@ igt_main
 		enable_hangcheck(i915);
 		igt_install_exit_handler(exit_handler);
 
+		ctx = intel_ctx_create_all_physical(i915);
+
 		igt_require(has_persistence(i915));
 		igt_allow_hang(i915, 0, 0);
 	}
@@ -1189,10 +1201,11 @@ igt_main
 		for (test = tests; test->name; test++) {
 			igt_subtest_with_dynamic_f("legacy-engines-%s",
 						   test->name) {
+				const intel_ctx_cfg_t empty_cfg = {};
 				for_each_physical_ring(e, i915) {
 					igt_dynamic_f("%s", e->name) {
-						do_test(test->func,
-							i915, eb_ring(e),
+						do_test(test->func, i915,
+							&empty_cfg, eb_ring(e),
 							e->full_name);
 					}
 				}
@@ -1213,10 +1226,10 @@ igt_main
 
 		for (test = tests; test->name; test++) {
 			igt_subtest_with_dynamic_f("engines-%s", test->name) {
-				__for_each_physical_engine(i915, e) {
+				for_each_ctx_engine(i915, ctx, e) {
 					igt_dynamic_f("%s", e->name) {
-						do_test(test->func,
-							i915, e->flags,
+						do_test(test->func, i915,
+							&ctx->cfg, e->flags,
 							e->name);
 					}
 				}
@@ -1224,17 +1237,17 @@ igt_main
 		}
 
 		igt_subtest_with_dynamic_f("saturated-hostile") {
-			__for_each_physical_engine(i915, e) {
+			for_each_ctx_engine(i915, ctx, e) {
 				igt_dynamic_f("%s", e->name)
-					test_saturated_hostile(i915, e);
+					test_saturated_hostile(i915, ctx, e);
 			}
 		}
 
 		igt_subtest("many-contexts")
-			many_contexts(i915);
+			many_contexts(i915, &ctx->cfg);
 
 		igt_subtest("smoketest")
-			smoketest(i915);
+			smoketest(i915, &ctx->cfg);
 	}
 
 	igt_fixture {
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 58/74] tests/i915/module_load: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/i915_module_load.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 03dec60d..35696366 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -64,6 +64,7 @@ static void store_all(int i915)
 		.buffer_count = 2,
 	};
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int reloc_sz = sizeof(uint32_t);
 	unsigned int nengine, value;
 	void *cs;
@@ -88,7 +89,9 @@ static void store_all(int i915)
 
 	nengine = 0;
 	cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE);
-	__for_each_physical_engine(i915, e) {
+
+	ctx = intel_ctx_create_all_physical(i915);
+	for_each_ctx_engine(i915, ctx, e) {
 		uint64_t addr;
 
 		igt_assert(reloc.presumed_offset != -1);
@@ -103,6 +106,7 @@ static void store_all(int i915)
 		if (gen < 6)
 			execbuf.flags |= I915_EXEC_SECURE;
 		execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT;
+		execbuf.rsvd1 = ctx->id;
 
 		memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch));
 		memcpy(cs + reloc.offset, &addr, reloc_sz);
@@ -121,6 +125,7 @@ static void store_all(int i915)
 	memset(engines, 0xdeadbeef, sizeof(engines));
 	gem_read(i915, obj[0].handle, 0, engines, nengine * sizeof(engines[0]));
 	gem_close(i915, obj[0].handle);
+	intel_ctx_destroy(i915, ctx);
 
 	for (i = 0; i < nengine; i++)
 		igt_assert_eq_u32(engines[i], i);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 59/74] tests/i915/pm_rc6_residency: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/i915_pm_rc6_residency.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_pm_rc6_residency.c b/tests/i915/i915_pm_rc6_residency.c
index d484121e..ceb506aa 100644
--- a/tests/i915/i915_pm_rc6_residency.c
+++ b/tests/i915/i915_pm_rc6_residency.c
@@ -454,6 +454,7 @@ static void rc6_fence(int i915)
 	const int tolerance = 20; /* Some RC6 is better than none! */
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	struct power_sample sample[2];
 	unsigned long slept;
 	uint64_t rc6, ts[2];
@@ -483,14 +484,15 @@ static void rc6_fence(int i915)
 	assert_within_epsilon(rc6, ts[1] - ts[0], 5);
 
 	/* Submit but delay execution, we should be idle and conserving power */
-	__for_each_physical_engine(i915, e) {
+	ctx = intel_ctx_create_all_physical(i915);
+	for_each_ctx_engine(i915, ctx, e) {
 		igt_spin_t *spin;
 		int timeline;
 		int fence;
 
 		timeline = sw_sync_timeline_create();
 		fence = sw_sync_timeline_create_fence(timeline, 1);
-		spin = igt_spin_new(i915,
+		spin = igt_spin_new(i915, .ctx = ctx,
 				    .engine = e->flags,
 				    .fence = fence,
 				    .flags = IGT_SPIN_FENCE_IN);
@@ -518,6 +520,7 @@ static void rc6_fence(int i915)
 		assert_within_epsilon(rc6, ts[1] - ts[0], tolerance);
 		gem_quiescent_gpu(i915);
 	}
+	intel_ctx_destroy(i915, ctx);
 
 	rapl_close(&rapl);
 	close(fd);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 60/74] tests/i915/gem_cs_tlb: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_cs_tlb.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/tests/i915/gem_cs_tlb.c b/tests/i915/gem_cs_tlb.c
index f72879c3..d87aa829 100644
--- a/tests/i915/gem_cs_tlb.c
+++ b/tests/i915/gem_cs_tlb.c
@@ -90,7 +90,8 @@ mmap_coherent(int fd, uint32_t handle, int size)
 	return ptr;
 }
 
-static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
+static void run_on_ring(int fd, const intel_ctx_t *ctx,
+			unsigned ring_id, const char *ring_name)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 execobj;
@@ -116,6 +117,7 @@ static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&execobj);
 	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
 	execbuf.flags = ring_id;
 
 	/* Execute once to allocate a gtt-offset */
@@ -143,17 +145,19 @@ static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx = NULL;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
+		ctx = intel_ctx_create_all_physical(fd);
 	}
 
 	igt_subtest_with_dynamic("engines") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_engine(fd, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				run_on_ring(fd, e->flags, e->name);
+				run_on_ring(fd, ctx, e->flags, e->name);
 		}
 	}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 61/74] tests/core_hotplug: Convert to intel_ctx_t

[Jason Ekstrand]

---
 tests/core_hotunplug.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c
index 56a88fef..32b07501 100644
--- a/tests/core_hotunplug.c
+++ b/tests/core_hotunplug.c
@@ -256,6 +256,7 @@ static int local_i915_healthcheck(int i915, const char *prefix)
 		.buffer_count = 1,
 	};
 	const struct intel_execution_engine2 *engine;
+	const intel_ctx_t *ctx;
 	int fence = -1, err = 0, status = 1;
 
 	local_debug("%s%s\n", prefix, "running i915 GPU healthcheck");
@@ -267,7 +268,9 @@ static int local_i915_healthcheck(int i915, const char *prefix)
 	gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
 
 	/* As soon as a fence is open, don't fail before closing it */
-	__for_each_physical_engine(i915, engine) {
+	ctx = intel_ctx_create_all_physical(i915);
+	for_each_ctx_engine(i915, ctx, engine) {
+		execbuf.rsvd1 = ctx->id;
 		execbuf.flags = engine->flags | I915_EXEC_FENCE_OUT;
 		err = __gem_execbuf_wr(i915, &execbuf);
 		if (igt_warn_on_f(err < 0, "__gem_execbuf_wr() returned %d\n",
@@ -281,6 +284,7 @@ static int local_i915_healthcheck(int i915, const char *prefix)
 			break;
 		}
 	}
+	intel_ctx_destroy(i915, ctx);
 	if (fence >= 0) {
 		status = sync_fence_wait(fence, -1);
 		if (igt_warn_on_f(status < 0, "sync_fence_wait() returned %d\n",
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 62/74] tests/i915/gem_exec_balancer: Stop cloning engines

[Jason Ekstrand]

We have the list of engines and bonding info in each case.  Using clone
is just being lazy for no good reason.
---
 tests/i915/gem_exec_balancer.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index c1b64578..44c9b05d 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -826,8 +826,7 @@ static void bonded_slice(int i915)
 		igt_fork(child, count + 1) { /* C: arbitrary background load */
 			igt_list_del(&spin->link);
 
-			ctx = gem_context_clone(i915, ctx,
-						I915_CONTEXT_CLONE_ENGINES, 0);
+			ctx = load_balancer_create(i915, siblings, count);
 
 			while (!READ_ONCE(*stop)) {
 				spin = igt_spin_new(i915,
@@ -2279,7 +2278,8 @@ static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf)
 	return err;
 }
 
-static uint32_t *sema(int i915, uint32_t ctx)
+static uint32_t *sema(int i915, struct i915_engine_class_instance *ci,
+		      unsigned int count)
 {
 	uint32_t *ctl;
 	struct drm_i915_gem_exec_object2 batch = {
@@ -2290,7 +2290,7 @@ static uint32_t *sema(int i915, uint32_t ctx)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&batch),
 		.buffer_count = 1,
-		.rsvd1 = gem_context_clone_with_engines(i915, ctx),
+		.rsvd1 = load_balancer_create(i915, ci, count),
 	};
 
 	for (int n = 1; n <= 32; n++) {
@@ -2312,12 +2312,14 @@ static uint32_t *sema(int i915, uint32_t ctx)
 	return ctl;
 }
 
-static void __waits(int i915, int timeout, uint32_t ctx, unsigned int count)
+static void __waits(int i915, int timeout,
+		    struct i915_engine_class_instance *ci,
+		    unsigned int count)
 {
 	uint32_t *semaphores[count + 1];
 
 	for (int i = 0; i <= count; i++)
-		semaphores[i] = sema(i915, ctx);
+		semaphores[i] = sema(i915, ci, count);
 
 	igt_until_timeout(timeout) {
 		int i = rand() % (count + 1);
@@ -2329,7 +2331,7 @@ static void __waits(int i915, int timeout, uint32_t ctx, unsigned int count)
 		if ((*semaphores[i] += rand() % 32) >= 32) {
 			*semaphores[i] = 0xffffffff;
 			munmap(semaphores[i], 4096);
-			semaphores[i] = sema(i915, ctx);
+			semaphores[i] = sema(i915, ci, count);
 		}
 	}
 
@@ -2358,7 +2360,7 @@ static void waits(int i915, int timeout)
 		if (count > 1) {
 			uint32_t ctx = load_balancer_create(i915, ci, count);
 
-			__waits(i915, timeout, ctx, count);
+			__waits(i915, timeout, ci, count);
 
 			gem_context_destroy(i915, ctx);
 		}
@@ -2442,8 +2444,7 @@ static void nop(int i915)
 				.buffers_ptr = to_user_pointer(&batch),
 				.buffer_count = 1,
 				.flags = child + 1,
-				.rsvd1 = gem_context_clone(i915, ctx,
-							   I915_CONTEXT_CLONE_ENGINES, 0),
+				.rsvd1 = load_balancer_create(i915, ci, count),
 			};
 			struct timespec tv = {};
 			unsigned long nops;
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 63/74] tests/i915/gem_exec_balancer: Don't reset engines on a context

[Jason Ekstrand]

Instead of resetting the set of engines to break implicit dependencies,
just use a new context.  This does drop a theoretical bit of test
coverage in the bonded chain tests because we can't drop the timeline
easily.  However, those tests also use the FENCE_SUBMIT pattern in a way
that the set of engines is swapped out between the first and second half
of the bonded pair.  That seems pretty sketchy.
---
 tests/i915/gem_exec_balancer.c | 163 +++++++++++++++++----------------
 1 file changed, 86 insertions(+), 77 deletions(-)

diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 44c9b05d..9fc5fe6d 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -27,6 +27,7 @@
 #include <sys/signal.h>
 
 #include "i915/gem.h"
+#include "i915/gem_vm.h"
 #include "igt.h"
 #include "igt_gt.h"
 #include "igt_perf.h"
@@ -122,6 +123,21 @@ static bool has_perf_engines(int i915)
 	return i915_perf_type_id(i915);
 }
 
+static int __set_vm(int i915, uint32_t ctx, uint32_t vm)
+{
+	struct drm_i915_gem_context_param p = {
+		.ctx_id = ctx,
+		.param = I915_CONTEXT_PARAM_VM,
+		.value = vm
+	};
+	return __gem_context_set_param(i915, &p);
+}
+
+static void set_vm(int i915, uint32_t ctx, uint32_t vm)
+{
+	igt_assert_eq(__set_vm(i915, ctx, vm), 0);
+}
+
 static int __set_engines(int i915, uint32_t ctx,
 			 const struct i915_engine_class_instance *ci,
 			 unsigned int count)
@@ -543,8 +559,6 @@ static void check_individual_engine(int i915,
 
 static void individual(int i915)
 {
-	uint32_t ctx;
-
 	/*
 	 * I915_CONTEXT_PARAM_ENGINE allows us to index into the user
 	 * supplied array from gem_execbuf(). Our check is to build the
@@ -553,8 +567,6 @@ static void individual(int i915)
 	 * was busy.
 	 */
 
-	ctx = gem_context_create(i915);
-
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *ci;
 		unsigned int count;
@@ -564,17 +576,20 @@ static void individual(int i915)
 			continue;
 
 		for (int pass = 0; pass < count; pass++) { /* approx. count! */
+			uint32_t ctx;
+
 			igt_assert(sizeof(*ci) == sizeof(int));
 			igt_permute_array(ci, count, igt_exchange_int);
+			ctx = gem_context_create(i915);
 			set_load_balancer(i915, ctx, ci, count, NULL);
 			for (unsigned int n = 0; n < count; n++)
 				check_individual_engine(i915, ctx, ci, n);
+			gem_context_destroy(i915, ctx);
 		}
 
 		free(ci);
 	}
 
-	gem_context_destroy(i915, ctx);
 	gem_quiescent_gpu(i915);
 }
 
@@ -583,7 +598,7 @@ static void bonded(int i915, unsigned int flags)
 {
 	I915_DEFINE_CONTEXT_ENGINES_BOND(bonds[16], 1);
 	struct i915_engine_class_instance *master_engines;
-	uint32_t master;
+	uint32_t vm;
 
 	/*
 	 * I915_CONTEXT_PARAM_ENGINE provides an extension that allows us
@@ -591,7 +606,7 @@ static void bonded(int i915, unsigned int flags)
 	 * request submitted to another engine.
 	 */
 
-	master = gem_queue_create(i915);
+	vm = gem_vm_create(i915);
 
 	memset(bonds, 0, sizeof(bonds));
 	for (int n = 0; n < ARRAY_SIZE(bonds); n++) {
@@ -604,7 +619,7 @@ static void bonded(int i915, unsigned int flags)
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *siblings;
 		unsigned int count, limit, *order;
-		uint32_t ctx;
+		uint32_t master, ctx;
 		int n;
 
 		siblings = list_engines(i915, 1u << class, &count);
@@ -617,6 +632,8 @@ static void bonded(int i915, unsigned int flags)
 		}
 
 		master_engines = list_engines(i915, ~(1u << class), &limit);
+		master = gem_context_create_ext(i915, I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE, 0);
+		set_vm(i915, master, vm);
 		set_engines(i915, master, master_engines, limit);
 
 		limit = min(count, limit);
@@ -626,9 +643,9 @@ static void bonded(int i915, unsigned int flags)
 			bonds[n].engines[0] = siblings[n];
 		}
 
-		ctx = gem_context_clone(i915,
-					master, I915_CONTEXT_CLONE_VM,
-					I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
+		ctx = gem_context_create_ext(i915, I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE, 0);
+		set_vm(i915, master, vm);
+		set_engines(i915, master, master_engines, limit);
 		set_load_balancer(i915, ctx, siblings, count, &bonds[limit - 1]);
 
 		order = malloc(sizeof(*order) * 8 * limit);
@@ -710,12 +727,11 @@ static void bonded(int i915, unsigned int flags)
 		}
 
 		free(order);
+		gem_context_destroy(i915, master);
 		gem_context_destroy(i915, ctx);
 		free(master_engines);
 		free(siblings);
 	}
-
-	gem_context_destroy(i915, master);
 }
 
 #define VIRTUAL_ENGINE (1u << 0)
@@ -760,7 +776,6 @@ static uint32_t create_semaphore_to_spinner(int i915, igt_spin_t *spin)
 
 static void bonded_slice(int i915)
 {
-	uint32_t ctx;
 	int *stop;
 
 	/*
@@ -773,13 +788,12 @@ static void bonded_slice(int i915)
 	stop = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 	igt_assert(stop != MAP_FAILED);
 
-	ctx = gem_context_create(i915); /* NB timeline per engine */
-
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *siblings;
 		struct drm_i915_gem_exec_object2 obj[3] = {};
 		struct drm_i915_gem_execbuffer2 eb = {};
 		unsigned int count;
+		uint32_t ctx;
 		igt_spin_t *spin;
 
 		siblings = list_engines(i915, 1u << class, &count);
@@ -803,6 +817,7 @@ static void bonded_slice(int i915)
 		 * XXX add explicit bonding options for A->B
 		 */
 
+		ctx = gem_context_create(i915); /* NB timeline per engine */
 		set_load_balancer(i915, ctx, siblings, count, NULL);
 
 		spin = __igt_spin_new(i915,
@@ -864,13 +879,13 @@ static void bonded_slice(int i915)
 
 		gem_close(i915, obj[2].handle);
 		igt_spin_free(i915, spin);
+		gem_context_destroy(i915, ctx);
 	}
 
-	gem_context_destroy(i915, ctx);
 	munmap(stop, 4096);
 }
 
-static void __bonded_chain(int i915, uint32_t ctx,
+static void __bonded_chain(int i915,
 			   const struct i915_engine_class_instance *siblings,
 			   unsigned int count)
 {
@@ -881,12 +896,14 @@ static void __bonded_chain(int i915, uint32_t ctx,
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&batch),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
 	};
 	igt_spin_t *spin;
 
 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
+		uint32_t ctx;
 		/* A: spin forever on engine 1 */
+
+		ctx = gem_context_create(i915);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
 		if (priorities[i] < 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
@@ -896,17 +913,13 @@ static void __bonded_chain(int i915, uint32_t ctx,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_FENCE_OUT));
 		igt_spin_busywait_until_started(spin);
-		gem_context_set_priority(i915, ctx, 0);
-
-		/*
-		 * Note we replace the timelines between each execbuf, so
-		 * that any pair of requests on the same engine could be
-		 * re-ordered by the scheduler -- if the dependency tracking
-		 * is subpar.
-		 */
 
 		/* B: waits for A on engine 2 */
+		gem_context_destroy(i915, ctx);
+		ctx = gem_context_create(i915);
+		gem_context_set_priority(i915, ctx, 0);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
+		execbuf.rsvd1 = ctx;
 		execbuf.rsvd2 = spin->out_fence;
 		execbuf.flags = I915_EXEC_FENCE_IN | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 2; /* opposite engine to spinner */
@@ -915,7 +928,6 @@ static void __bonded_chain(int i915, uint32_t ctx,
 		/* B': run in parallel with B on engine 1, i.e. not before A! */
 		if (priorities[i] > 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
-		set_load_balancer(i915, ctx, siblings, count, NULL);
 		execbuf.flags = I915_EXEC_FENCE_SUBMIT | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 1; /* same engine as spinner */
 		execbuf.rsvd2 >>= 32;
@@ -937,6 +949,7 @@ static void __bonded_chain(int i915, uint32_t ctx,
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 0);
 
 		igt_spin_free(i915, spin);
+		gem_context_destroy(i915, ctx);
 		gem_sync(i915, batch.handle);
 
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 & 0xffffffff), 1);
@@ -949,7 +962,7 @@ static void __bonded_chain(int i915, uint32_t ctx,
 	gem_close(i915, batch.handle);
 }
 
-static void __bonded_chain_inv(int i915, uint32_t ctx,
+static void __bonded_chain_inv(int i915,
 			       const struct i915_engine_class_instance *siblings,
 			       unsigned int count)
 {
@@ -960,12 +973,14 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&batch),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
 	};
 	igt_spin_t *spin;
 
 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
+		uint32_t ctx;
+
 		/* A: spin forever on engine 1 */
+		ctx = gem_context_create(i915);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
 		if (priorities[i] < 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
@@ -975,17 +990,13 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 				    .flags = (IGT_SPIN_POLL_RUN |
 					      IGT_SPIN_FENCE_OUT));
 		igt_spin_busywait_until_started(spin);
-		gem_context_set_priority(i915, ctx, 0);
-
-		/*
-		 * Note we replace the timelines between each execbuf, so
-		 * that any pair of requests on the same engine could be
-		 * re-ordered by the scheduler -- if the dependency tracking
-		 * is subpar.
-		 */
 
 		/* B: waits for A on engine 1 */
+		gem_context_destroy(i915, ctx);
+		ctx = gem_context_create(i915);
+		gem_context_set_priority(i915, ctx, 0);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
+		execbuf.rsvd1 = ctx;
 		execbuf.rsvd2 = spin->out_fence;
 		execbuf.flags = I915_EXEC_FENCE_IN | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 1; /* same engine as spinner */
@@ -994,7 +1005,6 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 		/* B': run in parallel with B on engine 2, i.e. not before A! */
 		if (priorities[i] > 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
-		set_load_balancer(i915, ctx, siblings, count, NULL);
 		execbuf.flags = I915_EXEC_FENCE_SUBMIT | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 2; /* opposite engine to spinner */
 		execbuf.rsvd2 >>= 32;
@@ -1017,6 +1027,7 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 
 		igt_spin_free(i915, spin);
 		gem_sync(i915, batch.handle);
+		gem_context_destroy(i915, ctx);
 
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 & 0xffffffff), 1);
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1);
@@ -1030,32 +1041,26 @@ static void __bonded_chain_inv(int i915, uint32_t ctx,
 
 static void bonded_chain(int i915)
 {
-	uint32_t ctx;
-
 	/*
 	 * Given batches A, B and B', where B and B' are a bonded pair, with
 	 * B' depending on B with a submit fence and B depending on A as
 	 * an ordinary fence; prove B' cannot complete before A.
 	 */
 
-	ctx = gem_context_create(i915);
-
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *siblings;
 		unsigned int count;
 
 		siblings = list_engines(i915, 1u << class, &count);
 		if (count > 1) {
-			__bonded_chain(i915, ctx, siblings, count);
-			__bonded_chain_inv(i915, ctx, siblings, count);
+			__bonded_chain(i915, siblings, count);
+			__bonded_chain_inv(i915, siblings, count);
 		}
 		free(siblings);
 	}
-
-	gem_context_destroy(i915, ctx);
 }
 
-static void __bonded_sema(int i915, uint32_t ctx,
+static void __bonded_sema(int i915,
 			  const struct i915_engine_class_instance *siblings,
 			  unsigned int count)
 {
@@ -1066,11 +1071,12 @@ static void __bonded_sema(int i915, uint32_t ctx,
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&batch),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
 	};
 	igt_spin_t *spin;
 
 	for (int i = 0; i < ARRAY_SIZE(priorities); i++) {
+		uint32_t ctx;
+
 		/* A: spin forever on seperate render engine */
 		spin = igt_spin_new(i915,
 				    .flags = (IGT_SPIN_POLL_RUN |
@@ -1085,16 +1091,21 @@ static void __bonded_sema(int i915, uint32_t ctx,
 		 */
 
 		/* B: waits for A (using a semaphore) on engine 1 */
+		ctx = gem_context_create(i915);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
+		execbuf.rsvd1 = ctx;
 		execbuf.rsvd2 = spin->out_fence;
 		execbuf.flags = I915_EXEC_FENCE_IN | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 1;
 		gem_execbuf_wr(i915, &execbuf);
 
 		/* B': run in parallel with B on engine 2 */
+		gem_context_destroy(i915, ctx);
+		ctx = gem_context_create(i915);
 		if (priorities[i] > 0)
 			gem_context_set_priority(i915, ctx, priorities[i]);
 		set_load_balancer(i915, ctx, siblings, count, NULL);
+		execbuf.rsvd1 = ctx;
 		execbuf.flags = I915_EXEC_FENCE_SUBMIT | I915_EXEC_FENCE_OUT;
 		execbuf.flags |= 2;
 		execbuf.rsvd2 >>= 32;
@@ -1117,6 +1128,7 @@ static void __bonded_sema(int i915, uint32_t ctx,
 
 		igt_spin_free(i915, spin);
 		gem_sync(i915, batch.handle);
+		gem_context_destroy(i915, ctx);
 
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 & 0xffffffff), 1);
 		igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1);
@@ -1130,8 +1142,6 @@ static void __bonded_sema(int i915, uint32_t ctx,
 
 static void bonded_semaphore(int i915)
 {
-	uint32_t ctx;
-
 	/*
 	 * Given batches A, B and B', where B and B' are a bonded pair, with
 	 * B' depending on B with a submit fence and B depending on A as
@@ -1141,19 +1151,15 @@ static void bonded_semaphore(int i915)
 	 */
 	igt_require(gem_scheduler_has_semaphores(i915));
 
-	ctx = gem_context_create(i915);
-
 	for (int class = 1; class < 32; class++) {
 		struct i915_engine_class_instance *siblings;
 		unsigned int count;
 
 		siblings = list_engines(i915, 1u << class, &count);
 		if (count > 1)
-			__bonded_sema(i915, ctx, siblings, count);
+			__bonded_sema(i915, siblings, count);
 		free(siblings);
 	}
-
-	gem_context_destroy(i915, ctx);
 }
 
 static void __bonded_pair(int i915,
@@ -1804,7 +1810,7 @@ static void indices(int i915)
 	gem_quiescent_gpu(i915);
 }
 
-static void __bonded_early(int i915, uint32_t ctx,
+static void __bonded_early(int i915,
 			   const struct i915_engine_class_instance *siblings,
 			   unsigned int count,
 			   unsigned int flags)
@@ -1817,8 +1823,8 @@ static void __bonded_early(int i915, uint32_t ctx,
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&batch),
 		.buffer_count = 1,
-		.rsvd1 = ctx,
 	};
+	uint32_t vm, ctx;
 	igt_spin_t *spin;
 
 	memset(bonds, 0, sizeof(bonds));
@@ -1832,6 +1838,11 @@ static void __bonded_early(int i915, uint32_t ctx,
 		bonds[n].engines[0] = siblings[(n + 1) % count];
 	}
 
+	/* We share a VM so that the spin cancel will work without a reloc */
+	vm = gem_vm_create(i915);
+
+	ctx = gem_context_create(i915);
+	set_vm(i915, ctx, vm);
 	set_load_balancer(i915, ctx, siblings, count,
 			  flags & VIRTUAL_ENGINE ? &bonds : NULL);
 
@@ -1842,6 +1853,7 @@ static void __bonded_early(int i915, uint32_t ctx,
 			    .flags = IGT_SPIN_NO_PREEMPTION);
 
 	/* B: runs after A on engine 1 */
+	execbuf.rsvd1 = ctx;
 	execbuf.flags = I915_EXEC_FENCE_OUT;
 	execbuf.flags |= spin->execbuf.flags & 63;
 	gem_execbuf_wr(i915, &execbuf);
@@ -1859,9 +1871,14 @@ static void __bonded_early(int i915, uint32_t ctx,
 
 	igt_debugfs_dump(i915, "i915_engine_info");
 
-	/* D: cancel the spinner from engine 2 (new timeline) */
-	set_load_balancer(i915, ctx, siblings, count, NULL);
+	/* D: cancel the spinner from engine 2 (new context) */
+	gem_context_destroy(i915, ctx);
+	ctx = gem_context_create(i915);
+	set_vm(i915, ctx, vm);
+	set_load_balancer(i915, ctx, siblings, count,
+			  flags & VIRTUAL_ENGINE ? &bonds : NULL);
 	batch.handle = create_semaphore_to_spinner(i915, spin);
+	execbuf.rsvd1 = ctx;
 	execbuf.flags = 0;
 	if(!(flags & VIRTUAL_ENGINE))
 		execbuf.flags |= 2;
@@ -1878,14 +1895,13 @@ static void __bonded_early(int i915, uint32_t ctx,
 	close(execbuf.rsvd2);
 	close(execbuf.rsvd2 >> 32);
 
+	gem_context_destroy(i915, ctx);
 	gem_close(i915, handle);
 	igt_spin_free(i915, spin);
 }
 
 static void bonded_early(int i915)
 {
-	uint32_t ctx;
-
 	/*
 	 * Our goal is to start the bonded payloads at roughly the same time.
 	 * We do not want to start the secondary batch too early as it will
@@ -1901,21 +1917,17 @@ static void bonded_early(int i915)
 	 * hang.
 	 */
 
-	ctx = gem_context_create(i915);
-
 	for (int class = 0; class < 32; class++) {
 		struct i915_engine_class_instance *siblings;
 		unsigned int count;
 
 		siblings = list_engines(i915, 1u << class, &count);
 		if (count > 1) {
-			__bonded_early(i915, ctx, siblings, count, 0);
-			__bonded_early(i915, ctx, siblings, count, VIRTUAL_ENGINE);
+			__bonded_early(i915, siblings, count, 0);
+			__bonded_early(i915, siblings, count, VIRTUAL_ENGINE);
 		}
 		free(siblings);
 	}
-
-	gem_context_destroy(i915, ctx);
 }
 
 static void busy(int i915)
@@ -2570,7 +2582,7 @@ static void ping(int i915, uint32_t ctx, unsigned int engine)
 
 static void semaphore(int i915)
 {
-	uint32_t block[2], scratch;
+	uint32_t scratch;
 	igt_spin_t *spin[3];
 
 	/*
@@ -2580,15 +2592,12 @@ static void semaphore(int i915)
 	 */
 	igt_require(gem_scheduler_has_preemption(i915));
 
-	block[0] = gem_context_create(i915);
-	block[1] = gem_context_create(i915);
-
 	scratch = gem_create(i915, 4096);
 	spin[2] = igt_spin_new(i915, .dependency = scratch);
 	for (int class = 1; class < 32; class++) {
 		struct i915_engine_class_instance *ci;
 		unsigned int count;
-		uint32_t vip;
+		uint32_t block[2], vip;
 
 		ci = list_engines(i915, 1u << class, &count);
 		if (!ci)
@@ -2601,6 +2610,7 @@ static void semaphore(int i915)
 		count = ARRAY_SIZE(block);
 
 		for (int i = 0; i < count; i++) {
+			block[i] = gem_context_create(i915);
 			set_load_balancer(i915, block[i], ci, count, NULL);
 			spin[i] = __igt_spin_new(i915,
 						 .ctx_id = block[i],
@@ -2616,17 +2626,16 @@ static void semaphore(int i915)
 		ping(i915, vip, 0);
 		gem_context_destroy(i915, vip);
 
-		for (int i = 0; i < count; i++)
+		for (int i = 0; i < count; i++) {
 			igt_spin_free(i915, spin[i]);
+			gem_context_destroy(i915, block[i]);
+		}
 
 		free(ci);
 	}
 	igt_spin_free(i915, spin[2]);
 	gem_close(i915, scratch);
 
-	gem_context_destroy(i915, block[1]);
-	gem_context_destroy(i915, block[0]);
-
 	gem_quiescent_gpu(i915);
 }
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 64/74] tests/i915/gem_exec_balancer: Stop munging ctx0 engines

[Jason Ekstrand]

---
 tests/i915/gem_exec_balancer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index 9fc5fe6d..5844b25c 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -3080,7 +3080,7 @@ static void noheartbeat(int i915)
 	 * heartbeat has already been disabled.
 	 */
 
-	__for_each_physical_engine(i915, e)
+	for_each_physical_engine(i915, e)
 		set_heartbeat(i915, e->name, 0);
 
 	for (int class = 0; class < 32; class++) {
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 65/74] tests/i915/gem_exec_endless: Stop munging ctx0 engines

[Jason Ekstrand]

---
 tests/i915/gem_exec_endless.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_endless.c b/tests/i915/gem_exec_endless.c
index a3e2fa49..5eed8f21 100644
--- a/tests/i915/gem_exec_endless.c
+++ b/tests/i915/gem_exec_endless.c
@@ -308,7 +308,7 @@ static void endless_dispatch(int i915, const struct intel_execution_engine2 *e)
 }
 
 #define test_each_engine(T, i915, e) \
-	igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
+	igt_subtest_with_dynamic(T) for_each_physical_engine(i915, e) \
 		for_each_if(gem_class_can_store_dword(i915, (e)->class)) \
 			igt_dynamic_f("%s", (e)->name)
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 66/74] lib/i915: Use for_each_physical_ring for submission tests

[Jason Ekstrand]

This does make the assumption that ctx0 has the default set of engines
but, now that we've converted everything to intel_ctx_t, this assumption
should be ok.
---
 lib/i915/gem_submission.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index 051f9d04..c13dfdce 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915/gem.h"
 #include "i915/gem_engine_topology.h"
+#include "i915/gem_ring.h"
 #include "i915/gem_submission.h"
 
 #include "igt_core.h"
@@ -199,10 +200,8 @@ void gem_test_engine(int i915, unsigned int engine)
 	gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
 
 	if (engine == ALL_ENGINES) {
-		const struct intel_execution_engine2 *e2;
-
-		__for_each_physical_engine(i915, e2) {
-			execbuf.flags = e2->flags;
+		for_each_physical_ring(e, i915) {
+			execbuf.flags = eb_ring(e);
 			gem_execbuf(i915, &execbuf);
 		}
 	} else {
@@ -381,11 +380,9 @@ unsigned int gem_submission_measure(int i915, unsigned int engine)
 		fcntl(i915, F_SETFL, fcntl(i915, F_GETFL) | O_NONBLOCK);
 
 	if (engine == ALL_ENGINES) {
-		struct intel_execution_engine2 *e;
-
 		size = -1;
-		__for_each_physical_engine(i915, e) {
-			unsigned int this =  __measure_ringsize(i915, e->flags);
+		for_each_physical_ring(e, i915) {
+			unsigned int this =  __measure_ringsize(i915, eb_ring(e));
 			if (this < size)
 				size = this;
 		}
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 67/74] tests/i915/gem_ctx_engines: Rework execute-one*

[Jason Ekstrand]

Instead of switching out the set of engines constantly, create a new
context for every set of engines.  This means, among other things, that
there's no point in testing whether or not the context is in a "default"
because there's no more resetting it.
---
 tests/i915/gem_ctx_engines.c | 53 +++++++++++++-----------------------
 1 file changed, 19 insertions(+), 34 deletions(-)

diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index 058b2cc2..be9671dd 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -318,7 +318,6 @@ static void execute_one(int i915)
 {
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, I915_EXEC_RING_MASK + 1);
 	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
 		.param = I915_CONTEXT_PARAM_ENGINES,
 		.value = to_user_pointer(&engines),
 		/* .size to be filled in later */
@@ -329,28 +328,13 @@ static void execute_one(int i915)
 	struct drm_i915_gem_execbuffer2 execbuf = {
 		.buffers_ptr = to_user_pointer(&obj),
 		.buffer_count = 1,
-		.rsvd1 = param.ctx_id,
 	};
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	const struct intel_execution_engine2 *e;
-	igt_spin_t *spin;
-
-	/* Prewarm the spinner */
-	spin = igt_spin_new(i915, .ctx_id = param.ctx_id,
-			    .flags = (IGT_SPIN_NO_PREEMPTION |
-				      IGT_SPIN_POLL_RUN));
 
 	gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe));
 
-	/* Unadulterated I915_EXEC_DEFAULT should work */
-	execbuf.flags = 0;
-	gem_execbuf(i915, &execbuf);
-	obj.flags |= EXEC_OBJECT_PINNED;
-
-	igt_spin_end(spin);
-	gem_sync(i915, obj.handle);
-
-	__for_each_physical_engine(i915, e) {
+	for_each_physical_engine(i915, e) {
 		struct drm_i915_gem_busy busy = { .handle = obj.handle };
 
 		if (!gem_class_can_store_dword(i915, e->class))
@@ -359,19 +343,26 @@ static void execute_one(int i915)
 		igt_debug("Testing [%s...]\n", e->name);
 
 		for (int i = -1; i <= I915_EXEC_RING_MASK; i++) {
+			igt_spin_t *spin;
+
 			memset(&engines, 0, sizeof(engines));
 			engine_class(&engines, 0) = e->class;
 			engine_instance(&engines, 0) = e->instance;
 			param.size = offsetof(typeof(engines), engines[1]);
+			param.ctx_id = gem_context_create(i915);
 			gem_context_set_param(i915, &param);
 
-			gem_sync(i915, spin->handle);
-			igt_spin_reset(spin);
-			gem_execbuf(i915, &spin->execbuf);
+			spin = igt_spin_new(i915, .ctx_id = param.ctx_id,
+					    .flags = (IGT_SPIN_NO_PREEMPTION |
+						      IGT_SPIN_POLL_RUN));
 
 			do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
 			igt_assert_eq(busy.busy, 0);
 
+			/* Create a new context with a lot of engines */
+			gem_context_destroy(i915, param.ctx_id);
+			param.ctx_id = gem_context_create(i915);
+
 			igt_debug("Testing with map of %d engines\n", i + 1);
 			memset(&engines.engines, -1, sizeof(engines.engines));
 			if (i != -1) {
@@ -385,6 +376,7 @@ static void execute_one(int i915)
 			for (int j = 0; j <= I915_EXEC_RING_MASK; j++) {
 				int expected = j == i ? 0 : -EINVAL;
 
+				execbuf.rsvd1 = param.ctx_id;
 				execbuf.flags = j;
 				igt_assert_f(__gem_execbuf(i915, &execbuf) == expected,
 					     "Failed to report the %s engine for slot %d (valid at %d)\n",
@@ -395,38 +387,31 @@ static void execute_one(int i915)
 			igt_assert_eq(batch_busy(busy.busy),
 				      i != -1 ? 1 << e->class : 0);
 
-			igt_spin_end(spin);
+			igt_spin_free(i915, spin);
 
 			gem_sync(i915, obj.handle);
+			gem_context_destroy(i915, param.ctx_id);
 			do_ioctl(i915, DRM_IOCTL_I915_GEM_BUSY, &busy);
 			igt_assert_eq(busy.busy, 0);
 		}
 	}
 
-	/* Restore the defaults and check I915_EXEC_DEFAULT works again. */
-	param.size = 0;
-	gem_context_set_param(i915, &param);
-	execbuf.flags = 0;
-	gem_execbuf(i915, &execbuf);
-
-	igt_spin_free(i915, spin);
-
 	gem_close(i915, obj.handle);
-	gem_context_destroy(i915, param.ctx_id);
 }
 
 static void execute_oneforall(int i915)
 {
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, I915_EXEC_RING_MASK + 1);
 	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_create(i915),
 		.param = I915_CONTEXT_PARAM_ENGINES,
 		.value = to_user_pointer(&engines),
 		.size = sizeof(engines),
 	};
 	const struct intel_execution_engine2 *e;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_physical_engine(i915, e) {
+		param.ctx_id = gem_context_create(i915);
+
 		memset(&engines, 0, sizeof(engines));
 		for (int i = 0; i <= I915_EXEC_RING_MASK; i++) {
 			engine_class(&engines, i) = e->class;
@@ -448,9 +433,9 @@ static void execute_oneforall(int i915)
 
 			igt_spin_free(i915, spin);
 		}
-	}
 
-	gem_context_destroy(i915, param.ctx_id);
+		gem_context_destroy(i915, param.ctx_id);
+	}
 }
 
 static void execute_allforone(int i915)
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 68/74] tests/i915/gem_ctx_engines: Use better engine iteration

[Jason Ekstrand]

---
 tests/i915/gem_ctx_engines.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index be9671dd..94ccd28f 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -451,7 +451,7 @@ static void execute_allforone(int i915)
 
 	i = 0;
 	memset(&engines, 0, sizeof(engines));
-	__for_each_physical_engine(i915, e) {
+	for_each_physical_engine(i915, e) {
 		engine_class(&engines, i) = e->class;
 		engine_instance(&engines, i) = e->instance;
 		i++;
@@ -460,7 +460,7 @@ static void execute_allforone(int i915)
 	gem_context_set_param(i915, &param);
 
 	i = 0;
-	__for_each_physical_engine(i915, e) {
+	for_each_physical_engine(i915, e) {
 		struct drm_i915_gem_busy busy = {};
 		igt_spin_t *spin;
 
@@ -497,7 +497,8 @@ static bool has_cs_timestamp(const struct intel_execution_engine2 *e, int gen)
 	return e->class == I915_ENGINE_CLASS_RENDER;
 }
 
-static void independent(int i915, const struct intel_execution_engine2 *e)
+static void independent(int i915, const intel_ctx_t *base_ctx,
+			const struct intel_execution_engine2 *e)
 {
 #define RCS_TIMESTAMP (mmio_base + 0x358)
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
@@ -505,7 +506,6 @@ static void independent(int i915, const struct intel_execution_engine2 *e)
 	const int has_64bit_reloc = gen >= 8;
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, I915_EXEC_RING_MASK + 1);
 	struct drm_i915_gem_context_param param = {
-		.ctx_id = gem_context_clone_with_engines(i915, 0),
 		.param = I915_CONTEXT_PARAM_ENGINES,
 		.value = to_user_pointer(&engines),
 		.size = sizeof(engines),
@@ -525,7 +525,7 @@ static void independent(int i915, const struct intel_execution_engine2 *e)
 		struct drm_i915_gem_execbuffer2 execbuf = {
 			.buffers_ptr = to_user_pointer(&results),
 			.buffer_count = 1,
-			.rsvd1 = param.ctx_id,
+			.rsvd1 = base_ctx->id,
 			.flags = e->flags,
 		};
 		gem_write(i915, results.handle, 0, &bbe, sizeof(bbe));
@@ -538,6 +538,7 @@ static void independent(int i915, const struct intel_execution_engine2 *e)
 		engine_class(&engines, i) = e->class;
 		engine_instance(&engines, i) = e->instance;
 	}
+	param.ctx_id = gem_context_create(i915);
 	gem_context_set_param(i915, &param);
 
 	gem_set_caching(i915, results.handle, I915_CACHING_CACHED);
@@ -597,19 +598,20 @@ static void independent(int i915, const struct intel_execution_engine2 *e)
 	gem_context_destroy(i915, param.ctx_id);
 }
 
-static void independent_all(int i915)
+static void independent_all(int i915, const intel_ctx_t *ctx)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
 	const struct intel_execution_engine2 *e;
 	igt_spin_t *spin = NULL;
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (spin) {
 			spin->execbuf.flags &= ~63;
 			spin->execbuf.flags |= e->flags;
 			gem_execbuf(i915, &spin->execbuf);
 		} else {
-			spin = igt_spin_new(i915, .engine = e->flags,
+			spin = igt_spin_new(i915, .ctx = ctx,
+					    .engine = e->flags,
 					    .flags = (IGT_SPIN_NO_PREEMPTION |
 						      IGT_SPIN_POLL_RUN));
 		}
@@ -617,7 +619,7 @@ static void independent_all(int i915)
 	igt_require(spin);
 	igt_spin_busywait_until_started(spin);
 
-	__for_each_physical_engine(i915, e) {
+	for_each_ctx_engine(i915, ctx, e) {
 		if (!gem_engine_mmio_base(i915, e->name))
 			continue;
 
@@ -625,7 +627,7 @@ static void independent_all(int i915)
 			continue;
 
 		igt_fork(child, 1)
-			independent(i915, e);
+			independent(i915, ctx, e);
 	}
 	sched_yield();
 	igt_spin_free(i915, spin);
@@ -734,14 +736,18 @@ igt_main
 		execute_allforone(i915);
 
 	igt_subtest_with_dynamic("independent") {
+		const intel_ctx_t *ctx;
+
 		igt_require(gem_scheduler_enabled(i915));
 		igt_require(intel_gen(intel_get_drm_devid(i915) >= 6));
-		__for_each_physical_engine(i915, e) {
+
+		ctx = intel_ctx_create_all_physical(i915);
+		for_each_ctx_engine(i915, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				independent(i915, e);
+				independent(i915, ctx, e);
 		}
 		igt_dynamic("all")
-			independent_all(i915);
+			independent_all(i915, ctx);
 	}
 
 	igt_subtest("libapi")
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 69/74] tests/i915/gem_ctx_engines: Drop the idempotent subtest

[Jason Ekstrand]

This just tests the engines CONTEXT_GETPARAM which we're going to be
dropping from i915.
---
 tests/i915/gem_ctx_engines.c | 79 ------------------------------------
 1 file changed, 79 deletions(-)

diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index 94ccd28f..c353eae7 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -173,82 +173,6 @@ out:
 	gem_context_destroy(i915, param.ctx_id);
 }
 
-static void idempotent(int i915)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, I915_EXEC_RING_MASK + 1);
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(expected, I915_EXEC_RING_MASK + 1);
-	struct drm_i915_gem_context_param p = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-		.size = sizeof(engines),
-	};
-	const size_t base = sizeof(struct i915_context_param_engines);
-	const struct intel_execution_engine2 *e;
-	int idx;
-
-	/* What goes in, must come out. And what comes out, must go in */
-
-	gem_context_get_param(i915, &p);
-	igt_assert_eq(p.size, 0); /* atm default is to use legacy ring mask */
-
-	idx = 0;
-	memset(&engines, 0, sizeof(engines));
-	__for_each_physical_engine(i915, e) {
-		engines.engines[idx].engine_class = e->class;
-		engines.engines[idx].engine_instance = e->instance;
-		idx++;
-	}
-	idx *= sizeof(*engines.engines);
-	p.size = base + idx;
-	gem_context_set_param(i915, &p);
-
-	memcpy(&expected, &engines, sizeof(expected));
-
-	gem_context_get_param(i915, &p);
-	igt_assert_eq(p.size, base + idx);
-	igt_assert(!memcmp(&expected, &engines, idx));
-
-	p.size = base;
-	gem_context_set_param(i915, &p);
-	gem_context_get_param(i915, &p);
-	igt_assert_eq(p.size, base);
-
-	/* and it should not have overwritten the previous contents */
-	igt_assert(!memcmp(&expected, &engines, idx));
-
-	memset(&engines, 0, sizeof(engines));
-	engines.engines[0].engine_class = I915_ENGINE_CLASS_INVALID;
-	engines.engines[0].engine_instance = I915_ENGINE_CLASS_INVALID_NONE;
-	idx = sizeof(*engines.engines);
-	p.size = base + idx;
-	gem_context_set_param(i915, &p);
-
-	memcpy(&expected, &engines, sizeof(expected));
-
-	gem_context_get_param(i915, &p);
-	igt_assert_eq(p.size, base + idx);
-	igt_assert(!memcmp(&expected, &engines, idx));
-
-	p.size = sizeof(engines);
-	__for_each_physical_engine(i915, e) {
-		memset(&engines, 0, sizeof(engines));
-		for (int n = 0; n < I915_EXEC_RING_MASK + 1; n++) {
-			engine_class(&engines, n) = e->class;
-			engine_instance(&engines, n) = e->instance;
-		}
-		gem_context_set_param(i915, &p);
-
-		memcpy(&expected, &engines, sizeof(expected));
-
-		gem_context_get_param(i915, &p);
-		igt_assert_eq(p.size, sizeof(engines));
-		igt_assert(!memcmp(&expected, &engines, p.size));
-	}
-
-	gem_context_destroy(i915, p.ctx_id);
-}
-
 static uint32_t batch_create(int i915)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -720,9 +644,6 @@ igt_main
 	igt_subtest("invalid-engines")
 		invalid_engines(i915);
 
-	igt_subtest("idempotent")
-		idempotent(i915);
-
 	igt_subtest("none")
 		none(i915);
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 70/74] tests/i915/gem_ctx_create: Convert benchmarks to intel_ctx_t

[Jason Ekstrand]

---
 tests/i915/gem_ctx_create.c | 76 +++++++++++++++++++------------------
 1 file changed, 40 insertions(+), 36 deletions(-)

diff --git a/tests/i915/gem_ctx_create.c b/tests/i915/gem_ctx_create.c
index 9a512a03..bc78162f 100644
--- a/tests/i915/gem_ctx_create.c
+++ b/tests/i915/gem_ctx_create.c
@@ -78,7 +78,8 @@ static double elapsed(const struct timespec *start,
 	return (end->tv_sec - start->tv_sec) + 1e-9*(end->tv_nsec - start->tv_nsec);
 }
 
-static void files(int core, int timeout, const int ncpus)
+static void files(int core, const intel_ctx_cfg_t *cfg,
+		  int timeout, const int ncpus)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -97,18 +98,22 @@ static void files(int core, int timeout, const int ncpus)
 	igt_fork(child, ncpus) {
 		struct timespec start, end;
 		unsigned count = 0;
+		const intel_ctx_t *ctx;
 		int fd;
 
 		clock_gettime(CLOCK_MONOTONIC, &start);
 		do {
 			fd = gem_reopen_driver(core);
-			gem_context_copy_engines(core, 0, fd, 0);
+
+			ctx = intel_ctx_create(fd, cfg);
+			execbuf.rsvd1 = ctx->id;
 
 			obj.handle = gem_open(fd, name);
 			execbuf.flags &= ~ENGINE_FLAGS;
 			execbuf.flags |= ppgtt_engines[count % ppgtt_nengine];
 			gem_execbuf(fd, &execbuf);
 
+			intel_ctx_destroy(fd, ctx);
 			close(fd);
 			count++;
 
@@ -125,7 +130,8 @@ static void files(int core, int timeout, const int ncpus)
 	gem_close(core, batch);
 }
 
-static void active(int fd, const struct intel_execution_engine2 *e,
+static void active(int fd, const intel_ctx_cfg_t *cfg,
+		   const struct intel_execution_engine2 *e,
 		   int timeout, int ncpus)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -157,19 +163,19 @@ static void active(int fd, const struct intel_execution_engine2 *e,
 	if (ncpus < 0) {
 		igt_fork(child, ppgtt_nengine) {
 			unsigned long count = 0;
-			int i915;
+			const intel_ctx_t *ctx;
 
-			i915 = gem_reopen_driver(fd);
 			/*
 			 * Ensure the gpu is idle by launching
 			 * a nop execbuf and stalling for it
 			 */
-			gem_quiescent_gpu(i915);
-			gem_context_copy_engines(fd, 0, i915, 0);
+			gem_quiescent_gpu(fd);
 
 			if (ppgtt_engines[child] == e->flags)
 				continue;
 
+			ctx = intel_ctx_create(fd, cfg);
+			execbuf.rsvd1 = ctx->id;
 			execbuf.flags = ppgtt_engines[child];
 
 			while (!READ_ONCE(*shared)) {
@@ -182,6 +188,7 @@ static void active(int fd, const struct intel_execution_engine2 *e,
 			}
 
 			igt_debug("hog[%d]: cycles=%lu\n", child, count);
+			intel_ctx_destroy(fd, ctx);
 		}
 		ncpus = -ncpus;
 	}
@@ -189,33 +196,27 @@ static void active(int fd, const struct intel_execution_engine2 *e,
 	igt_fork(child, ncpus) {
 		struct timespec start, end;
 		unsigned count = 0;
-		int i915;
-		uint32_t ctx;
 
-		i915 = gem_reopen_driver(fd);
 		/*
 		 * Ensure the gpu is idle by launching
 		 * a nop execbuf and stalling for it.
 		 */
-		gem_quiescent_gpu(i915);
-		ctx = gem_context_create(i915);
-		gem_context_copy_engines(fd, 0, i915, ctx);
+		gem_quiescent_gpu(fd);
 
 		clock_gettime(CLOCK_MONOTONIC, &start);
 		do {
-			execbuf.rsvd1 = gem_context_clone_with_engines(fd, ctx);
+			const intel_ctx_t *ctx = intel_ctx_create(fd, cfg);
+			execbuf.rsvd1 = ctx->id;
 			for (unsigned n = 0; n < nengine; n++) {
 				execbuf.flags = engines[n];
 				gem_execbuf(fd, &execbuf);
 			}
-			gem_context_destroy(fd, execbuf.rsvd1);
+			intel_ctx_destroy(fd, ctx);
 			count++;
 
 			clock_gettime(CLOCK_MONOTONIC, &end);
 		} while (elapsed(&start, &end) < timeout);
 
-		gem_context_destroy(fd, ctx);
-
 		gem_sync(fd, obj.handle);
 		clock_gettime(CLOCK_MONOTONIC, &end);
 		igt_info("[%d] Context creation + execution: %.3f us\n",
@@ -276,7 +277,8 @@ static uint64_t total_avail_mem(unsigned mode)
 	return total << 20;
 }
 
-static void maximum(int fd, int ncpus, unsigned mode)
+static void maximum(int fd, const intel_ctx_cfg_t *cfg,
+		    int ncpus, unsigned mode)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct drm_i915_gem_execbuffer2 execbuf;
@@ -299,9 +301,7 @@ static void maximum(int fd, int ncpus, unsigned mode)
 
 		err = -ENOMEM;
 		if (avail_mem > (count + 1) * ctx_size)
-			err =  __gem_context_clone(fd, 0,
-						   I915_CONTEXT_CLONE_ENGINES,
-						   0, &ctx_id);
+			err =  __gem_context_create(fd, &ctx_id);
 		if (err) {
 			igt_info("Created %lu contexts, before failing with '%s' [%d]\n",
 				 count, strerror(-err), -err);
@@ -322,6 +322,7 @@ static void maximum(int fd, int ncpus, unsigned mode)
 
 	igt_fork(child, ncpus) {
 		struct timespec start, end;
+		const intel_ctx_t *ctx;
 		int i915;
 
 		i915 = gem_reopen_driver(fd);
@@ -330,7 +331,7 @@ static void maximum(int fd, int ncpus, unsigned mode)
 		 * a nop execbuf and stalling for it.
 		 */
 		gem_quiescent_gpu(i915);
-		gem_context_copy_engines(fd, 0, i915, 0);
+		ctx = intel_ctx_create(i915, cfg);
 
 		hars_petruska_f54_1_random_perturb(child);
 		obj[0].handle = gem_create(i915, 4096);
@@ -351,6 +352,7 @@ static void maximum(int fd, int ncpus, unsigned mode)
 		gem_sync(i915, obj[0].handle);
 		clock_gettime(CLOCK_MONOTONIC, &end);
 		gem_close(i915, obj[0].handle);
+		intel_ctx_destroy(i915, ctx);
 
 		igt_info("[%d] Context execution: %.3f us\n", child,
 			 elapsed(&start, &end) / (3 * count * all_nengine) * 1e6);
@@ -560,6 +562,7 @@ igt_main
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	struct drm_i915_gem_context_create create;
 	const struct intel_execution_engine2 *e;
+	intel_ctx_cfg_t cfg;
 	int fd = -1;
 
 	igt_fixture {
@@ -567,7 +570,8 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_contexts(fd);
 
-		__for_each_physical_engine(fd, e)
+		cfg = intel_ctx_cfg_all_physical(fd);
+		for_each_ctx_cfg_engine(fd, &cfg, e)
 			all_engines[all_nengine++] = e->flags;
 		igt_require(all_nengine);
 
@@ -597,39 +601,39 @@ igt_main
 		iris_pipeline(fd);
 
 	igt_subtest("maximum-mem")
-		maximum(fd, ncpus, CHECK_RAM);
+		maximum(fd, &cfg, ncpus, CHECK_RAM);
 	igt_subtest("maximum-swap")
-		maximum(fd, ncpus, CHECK_RAM | CHECK_SWAP);
+		maximum(fd, &cfg, ncpus, CHECK_RAM | CHECK_SWAP);
 
 	igt_subtest("basic-files")
-		files(fd, 2, 1);
+		files(fd, &cfg, 2, 1);
 	igt_subtest("files")
-		files(fd, 20, 1);
+		files(fd, &cfg, 20, 1);
 	igt_subtest("forked-files")
-		files(fd, 20, ncpus);
+		files(fd, &cfg, 20, ncpus);
 
 	/* NULL value means all engines */
 	igt_subtest("active-all")
-		active(fd, NULL, 20, 1);
+		active(fd, &cfg, NULL, 20, 1);
 	igt_subtest("forked-active-all")
-		active(fd, NULL, 20, ncpus);
+		active(fd, &cfg, NULL, 20, ncpus);
 
 	igt_subtest_with_dynamic("active") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_cfg_engine(fd, &cfg, e) {
 			igt_dynamic_f("%s", e->name)
-				active(fd, e, 20, 1);
+				active(fd, &cfg, e, 20, 1);
 		}
 	}
 	igt_subtest_with_dynamic("forked-active") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_cfg_engine(fd, &cfg, e) {
 			igt_dynamic_f("%s", e->name)
-				active(fd, e, 20, ncpus);
+				active(fd, &cfg, e, 20, ncpus);
 		}
 	}
 	igt_subtest_with_dynamic("hog") {
-		__for_each_physical_engine(fd, e) {
+		for_each_ctx_cfg_engine(fd, &cfg, e) {
 			igt_dynamic_f("%s", e->name)
-				active(fd, e, 20, -1);
+				active(fd, &cfg, e, 20, -1);
 		}
 	}
 
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 71/74] lib/i915/gem_context: Delete all the context clone/copy stuff

[Jason Ekstrand]

---
 lib/i915/gem_context.c | 149 -----------------------------------------
 lib/i915/gem_context.h |  16 -----
 2 files changed, 165 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 49ed7120..b4bf7ef6 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -391,125 +391,6 @@ bool gem_context_has_persistence(int i915)
 	return __gem_context_get_param(i915, &param) == 0;
 }
 
-int
-__gem_context_clone(int i915,
-		    uint32_t src, unsigned int share,
-		    unsigned int flags,
-		    uint32_t *out)
-{
-	struct drm_i915_gem_context_create_ext_clone clone = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.clone_id = src,
-		.flags = share,
-	};
-	struct drm_i915_gem_context_create_ext arg = {
-		.flags = flags | I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&clone),
-	};
-	int err;
-
-	err = create_ext_ioctl(i915, &arg);
-	if (err)
-		return err;
-
-	*out = arg.ctx_id;
-	return 0;
-}
-
-static bool __gem_context_has(int i915, uint32_t share, unsigned int flags)
-{
-	uint32_t ctx = 0;
-
-	__gem_context_clone(i915, 0, share, flags, &ctx);
-	if (ctx)
-		gem_context_destroy(i915, ctx);
-
-	errno = 0;
-	return ctx;
-}
-
-bool gem_contexts_has_shared_gtt(int i915)
-{
-	return __gem_context_has(i915, I915_CONTEXT_CLONE_VM, 0);
-}
-
-bool gem_has_queues(int i915)
-{
-	return __gem_context_has(i915,
-				 I915_CONTEXT_CLONE_VM,
-				 I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
-}
-
-uint32_t gem_context_clone(int i915,
-			   uint32_t src, unsigned int share,
-			   unsigned int flags)
-{
-	uint32_t ctx;
-
-	igt_assert_eq(__gem_context_clone(i915, src, share, flags, &ctx), 0);
-
-	return ctx;
-}
-
-bool gem_has_context_clone(int i915)
-{
-	struct drm_i915_gem_context_create_ext_clone ext = {
-		{ .name = I915_CONTEXT_CREATE_EXT_CLONE },
-		.clone_id = -1,
-	};
-	struct drm_i915_gem_context_create_ext create = {
-		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
-		.extensions = to_user_pointer(&ext),
-	};
-
-	return create_ext_ioctl(i915, &create) == -ENOENT;
-}
-
-/**
- * gem_context_clone_with_engines:
- * @i915: open i915 drm file descriptor
- * @src: i915 context id
- *
- * Special purpose wrapper to create a new context by cloning engines from @src.
- *
- * In can be called regardless of whether the kernel supports context cloning.
- *
- * Intended purpose is to use for creating contexts against which work will be
- * submitted and the engine index came from external source, derived from a
- * default context potentially configured with an engine map.
- */
-uint32_t gem_context_clone_with_engines(int i915, uint32_t src)
-{
-	if (!gem_has_context_clone(i915))
-		return gem_context_create(i915);
-	else
-		return gem_context_clone(i915, src, I915_CONTEXT_CLONE_ENGINES,
-					 0);
-}
-
-uint32_t gem_queue_create(int i915)
-{
-	return gem_context_clone(i915, 0,
-				 I915_CONTEXT_CLONE_VM |
-				 I915_CONTEXT_CLONE_ENGINES,
-				 I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
-}
-
-/**
- * gem_queue_clone_with_engines:
- * @i915: open i915 drm file descriptor
- * @src: i915 context id
- *
- * See gem_context_clone_with_engines.
- */
-uint32_t gem_queue_clone_with_engines(int i915, uint32_t src)
-{
-	return gem_context_clone(i915, src,
-				 I915_CONTEXT_CLONE_ENGINES |
-				 I915_CONTEXT_CLONE_VM,
-				 I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE);
-}
-
 bool gem_context_has_engine(int fd, uint32_t ctx, uint64_t engine)
 {
 	struct drm_i915_gem_exec_object2 exec = {};
@@ -535,36 +416,6 @@ bool gem_context_has_engine(int fd, uint32_t ctx, uint64_t engine)
 	return __gem_execbuf(fd, &execbuf) == -ENOENT;
 }
 
-/**
- * gem_context_copy_engines:
- * @src_fd: open i915 drm file descriptor where @src context belongs to
- * @src: source engine map context id
- * @dst_fd: open i915 drm file descriptor where @dst context belongs to
- * @dst: destination engine map context id
- *
- * Special purpose helper for copying engine map from one context to another.
- *
- * In can be called regardless of whether the kernel supports context engine
- * maps and is a no-op if not supported.
- */
-void
-gem_context_copy_engines(int src_fd, uint32_t src, int dst_fd, uint32_t dst)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, I915_EXEC_RING_MASK + 1);
-	struct drm_i915_gem_context_param param = {
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.ctx_id = src,
-		.size = sizeof(engines),
-		.value = to_user_pointer(&engines),
-	};
-
-	if (__gem_context_get_param(src_fd, &param))
-		return;
-
-	param.ctx_id = dst;
-	gem_context_set_param(dst_fd, &param);
-}
-
 uint32_t gem_context_create_for_engine(int i915, unsigned int class, unsigned int inst)
 {
 	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 91bb9e7f..1ba405ca 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -40,20 +40,6 @@ int __gem_context_destroy(int fd, uint32_t ctx_id);
 uint32_t gem_context_create_for_engine(int fd, unsigned int class, unsigned int inst);
 uint32_t gem_context_create_for_class(int i915, unsigned int class, unsigned int *count);
 
-int __gem_context_clone(int i915,
-			uint32_t src, unsigned int share,
-			unsigned int flags,
-			uint32_t *out);
-uint32_t gem_context_clone(int i915,
-			   uint32_t src, unsigned int share,
-			   unsigned int flags);
-uint32_t gem_context_clone_with_engines(int i915, uint32_t src);
-void gem_context_copy_engines(int src_fd, uint32_t src,
-			      int dst_fd, uint32_t dst);
-
-uint32_t gem_queue_create(int i915);
-uint32_t gem_queue_clone_with_engines(int i915, uint32_t src);
-
 bool gem_contexts_has_shared_gtt(int i915);
 bool gem_has_queues(int i915);
 
@@ -62,8 +48,6 @@ void gem_require_contexts(int fd);
 void gem_context_require_bannable(int fd);
 void gem_context_require_param(int fd, uint64_t param);
 
-bool gem_has_context_clone(int i915);
-
 void gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
 void gem_context_set_param(int fd, struct drm_i915_gem_context_param *p);
 int __gem_context_set_param(int fd, struct drm_i915_gem_context_param *p);
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 72/74] tests/i915/gem_ctx_engines: Delete the libapi subtest

[Jason Ekstrand]

It just tests enumeration APIs that we're about to delete.
---
 tests/i915/gem_ctx_engines.c | 71 ------------------------------------
 1 file changed, 71 deletions(-)

diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index c353eae7..3009912b 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -558,74 +558,6 @@ static void independent_all(int i915, const intel_ctx_t *ctx)
 	igt_waitchildren();
 }
 
-static void libapi(int i915)
-{
-	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 64) = {};
-	struct drm_i915_gem_context_param p = {
-		.ctx_id = gem_context_create(i915),
-		.param = I915_CONTEXT_PARAM_ENGINES,
-		.value = to_user_pointer(&engines),
-	};
-	const struct intel_execution_engine2 *e;
-	unsigned int count, idx;
-
-	p.size = sizeof(struct i915_context_param_engines);
-	gem_context_set_param(i915, &p);
-
-	/* An empty context should be a short loop */
-	count = 0;
-	for_each_context_engine(i915, p.ctx_id, e)
-		count++;
-	igt_assert_eq(count, 0);
-
-	p.size += sizeof(struct i915_engine_class_instance);
-	engine_class(&engines, 0) = -1;
-	engine_instance(&engines, 0) = -1;
-	gem_context_set_param(i915, &p);
-
-	/* We report all engines from the context, even if invalid/unusable */
-	count = 0;
-	for_each_context_engine(i915, p.ctx_id, e) {
-		igt_assert_eq(e->class, engine_class(&engines, 0));
-		igt_assert_eq(e->instance, engine_instance(&engines, 0));
-		count++;
-	}
-	igt_assert_eq(count, 1);
-
-	/* Check that every known engine can be found from the context map */
-	idx = 0;
-	p.size = sizeof(struct i915_context_param_engines);
-	p.size += sizeof(struct i915_engine_class_instance);
-	for (engine_class(&engines, idx) = 0;
-	     engine_class(&engines, idx) < 16;
-	     engine_class(&engines, idx)++) {
-		for (engine_instance(&engines, idx) = 0;
-		     engine_instance(&engines, idx) < 16;
-		     engine_instance(&engines, idx)++) {
-			if (__gem_context_set_param(i915, &p))
-				break;
-
-			count = 0;
-			for_each_context_engine(i915, p.ctx_id, e) {
-				igt_assert_eq(e->class,
-					      engine_class(&engines, count));
-				igt_assert_eq(e->instance,
-					      engine_instance(&engines, count));
-				count++;
-			}
-			igt_assert_eq(count, idx + 1);
-
-			engines.engines[(idx + 1) % 64] = engines.engines[idx];
-			idx = (idx + 1) % 64;
-
-			p.size = sizeof(struct i915_context_param_engines);
-			p.size += (idx + 1) * sizeof(struct i915_engine_class_instance);
-		}
-	}
-
-	gem_context_destroy(i915, p.ctx_id);
-}
-
 igt_main
 {
 	const struct intel_execution_engine2 *e;
@@ -671,9 +603,6 @@ igt_main
 			independent_all(i915, ctx);
 	}
 
-	igt_subtest("libapi")
-		libapi(i915);
-
 	igt_fixture
 		igt_stop_hang_detector();
 }
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 73/74] lib/igt_dummyload: Stop supporting ALL_ENGINES without an intel_ctx_t

[Jason Ekstrand]

---
 lib/igt_dummyload.c | 21 ++++++---------------
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index ac83b331..ae6c9542 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -129,22 +129,13 @@ emit_recursive_batch(igt_spin_t *spin,
 	if (opts->engine == ALL_ENGINES) {
 		struct intel_execution_engine2 *engine;
 
-		if (opts->ctx) {
-			for_each_ctx_engine(fd, opts->ctx, engine) {
-				if (opts->flags & IGT_SPIN_POLL_RUN &&
-				    !gem_class_can_store_dword(fd, engine->class))
-					continue;
+		igt_assert(opts->ctx);
+		for_each_ctx_engine(fd, opts->ctx, engine) {
+			if (opts->flags & IGT_SPIN_POLL_RUN &&
+			    !gem_class_can_store_dword(fd, engine->class))
+				continue;
 
-				flags[nengine++] = engine->flags;
-			}
-		} else {
-			for_each_context_engine(fd, opts->ctx_id, engine) {
-				if (opts->flags & IGT_SPIN_POLL_RUN &&
-				    !gem_class_can_store_dword(fd, engine->class))
-					continue;
-
-				flags[nengine++] = engine->flags;
-			}
+			flags[nengine++] = engine->flags;
 		}
 	} else {
 		flags[nengine++] = opts->engine;
-- 
2.31.1

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[igt-dev] [PATCH i-g-t 74/74] lib/i915/gem_engine_topology: Delete the old physical engine iterators

[Jason Ekstrand]

---
 lib/i915/gem_engine_topology.c | 58 ----------------------------------
 lib/i915/gem_engine_topology.h | 15 ---------
 2 files changed, 73 deletions(-)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index ec891dab..38da2003 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -79,25 +79,6 @@ int __gem_query_engines(int fd,
 	return __gem_query(fd, &query);
 }
 
-static void ctx_map_engines(int fd, struct intel_engine_data *ed,
-			    struct drm_i915_gem_context_param *param)
-{
-	struct i915_context_param_engines *engines =
-			from_user_pointer(param->value);
-	int i = 0;
-
-	for (typeof(engines->engines[0]) *p = &engines->engines[0];
-	     i < ed->nengines; i++, p++) {
-		p->engine_class = ed->engines[i].class;
-		p->engine_instance = ed->engines[i].instance;
-	}
-
-	param->size = offsetof(typeof(*engines), engines[i]);
-	engines->extensions = 0;
-
-	gem_context_set_param(fd, param);
-}
-
 static const char *class_names[] = {
 	[I915_ENGINE_CLASS_RENDER]	  = "rcs",
 	[I915_ENGINE_CLASS_COPY]	  = "bcs",
@@ -158,11 +139,6 @@ static int __query_engine_list(int fd, struct intel_engine_data *ed)
 	return 0;
 }
 
-static void query_engine_list(int fd, struct intel_engine_data *ed)
-{
-	igt_assert_eq(__query_engine_list(fd, ed), 0);
-}
-
 struct intel_execution_engine2 *
 intel_get_current_engine(struct intel_engine_data *ed)
 {
@@ -267,40 +243,6 @@ static int gem_topology_get_param(int fd,
 	return 0;
 }
 
-struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
-{
-	DEFINE_CONTEXT_ENGINES_PARAM(engines, param, ctx_id, GEM_MAX_ENGINES);
-	struct intel_engine_data engine_data = { };
-	int i;
-
-	if (gem_topology_get_param(fd, &param)) {
-		/* if kernel does not support engine/context mapping */
-		return intel_engine_list_for_static(fd);
-	}
-
-	if (!param.size) {
-		query_engine_list(fd, &engine_data);
-		ctx_map_engines(fd, &engine_data, &param);
-	} else {
-		/* engine count can be inferred from size */
-		param.size -= sizeof(struct i915_context_param_engines);
-		param.size /= sizeof(struct i915_engine_class_instance);
-
-		igt_assert_f(param.size <= GEM_MAX_ENGINES,
-			     "unsupported engine count\n");
-
-		for (i = 0; i < param.size; i++)
-			init_engine(&engine_data.engines[i],
-				    engines.engines[i].engine_class,
-				    engines.engines[i].engine_instance,
-				    i);
-
-		engine_data.nengines = i;
-	}
-
-	return engine_data;
-}
-
 int gem_context_lookup_engine(int fd, uint64_t engine, uint32_t ctx_id,
 			      struct intel_execution_engine2 *e)
 {
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index b2e15c1e..d0fa4590 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -43,7 +43,6 @@ bool gem_has_engine_topology(int fd);
 struct intel_engine_data intel_engine_list_of_physical(int fd);
 struct intel_engine_data
 intel_engine_list_for_ctx_cfg(int fd, const intel_ctx_cfg_t *cfg);
-struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
 
 /* iteration functions */
 struct intel_execution_engine2 *
@@ -76,25 +75,11 @@ struct intel_execution_engine2 gem_eb_flags_to_engine(unsigned int flags);
 #define for_each_ctx_engine(fd__, ctx__, e__) \
 	for_each_ctx_cfg_engine(fd__, &(ctx__)->cfg, e__)
 
-#define for_each_context_engine(fd__, ctx__, e__) \
-	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
-	     ((e__) = intel_get_current_engine(&i__)); \
-	     intel_next_engine(&i__))
-
 #define for_each_physical_engine(fd__, e__) \
 	for (struct intel_engine_data i__##e__ = intel_engine_list_of_physical(fd__); \
 	     ((e__) = intel_get_current_physical_engine(&i__##e__)); \
 	     intel_next_engine(&i__##e__))
 
-/* needs to replace "for_each_physical_engine" when conflicts are fixed */
-#define ____for_each_physical_engine(fd__, ctx__, e__) \
-	for (struct intel_engine_data i__##e__ = intel_init_engine_list(fd__, ctx__); \
-	     ((e__) = intel_get_current_physical_engine(&i__##e__)); \
-	     intel_next_engine(&i__##e__))
-
-#define __for_each_physical_engine(fd__, e__) \
-	____for_each_physical_engine(fd__, 0, e__)
-
 __attribute__((format(scanf, 4, 5)))
 int gem_engine_property_scanf(int i915, const char *engine, const char *attr,
 			      const char *fmt, ...);
-- 
2.31.1

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[igt-dev] ✓ Fi.CI.BAT: success for Stop depending on context mutation (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 2706 bytes --]

== Series Details ==

Series: Stop depending on context mutation (rev3)
URL   : https://patchwork.freedesktop.org/series/88986/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9976 -> IGTPW_5748
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/index.html

Known issues
------------

  Here are the changes found in IGTPW_5748 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        NOTRUN -> [INCOMPLETE][1] ([i915#2782])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-tgl-y:           [DMESG-WARN][2] ([i915#1982] / [k.org#205379]) -> [PASS][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/fi-tgl-y/igt@i915_module_load@reload.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/fi-tgl-y/igt@i915_module_load@reload.html

  
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (45 -> 40)
------------------------------

  Missing    (5): fi-ilk-m540 fi-bsw-cyan fi-dg1-1 fi-icl-y fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6067 -> IGTPW_5748

  CI-20190529: 20190529
  CI_DRM_9976: 73739c865de5c4c504adff6d9873ca5dea2dc704 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5748: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/index.html
  IGT_6067: 14317b92a672d9a20cd04fc3b0c80e2fb12d51d5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

-igt@gem_ctx_clone@engines
-igt@gem_ctx_clone@flags
-igt@gem_ctx_clone@invalid
-igt@gem_ctx_clone@scheduler
-igt@gem_ctx_clone@vm
-igt@gem_ctx_engines@idempotent
-igt@gem_ctx_engines@libapi
-igt@gem_ctx_param@non-root-set-no-zeromap
-igt@gem_ctx_param@root-set-no-zeromap-disabled
-igt@gem_ctx_param@root-set-no-zeromap-enabled
-igt@gem_ctx_persistence@clone
-igt@gem_ctx_persistence@close-replace-race
-igt@gem_ctx_persistence@replace
-igt@gem_ctx_persistence@replace-hostile
-igt@gem_ctx_ringsize@active
-igt@gem_ctx_ringsize@clone
-igt@gem_ctx_ringsize@create
-igt@gem_ctx_ringsize@idempotent
-igt@gem_ctx_ringsize@idle
-igt@gem_ctx_ringsize@invalid
-igt@gem_ctx_ringsize@plugged
-igt@gem_exec_balancer@ringsize

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/index.html

[-- Attachment #1.2: Type: text/html, Size: 3445 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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[igt-dev] ✓ Fi.CI.IGT: success for Stop depending on context mutation (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 30259 bytes --]

== Series Details ==

Series: Stop depending on context mutation (rev3)
URL   : https://patchwork.freedesktop.org/series/88986/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9976_full -> IGTPW_5748_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/index.html

Known issues
------------

  Here are the changes found in IGTPW_5748_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-3x:
    - shard-tglb:         NOTRUN -> [SKIP][1] ([i915#1839])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb5/igt@feature_discovery@display-3x.html

  * igt@gem_ctx_persistence@smoketest:
    - shard-snb:          NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb2/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_ctx_shared@detached-shared-gtt:
    - shard-snb:          [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-snb7/igt@gem_ctx_shared@detached-shared-gtt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb6/igt@gem_ctx_shared@detached-shared-gtt.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][16] ([fdo#109283])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@gem_exec_params@no-vebox.html
    - shard-tglb:         NOTRUN -> [SKIP][17] ([fdo#109283])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb8/igt@gem_exec_params@no-vebox.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][18] ([i915#2658])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb5/igt@gem_pread@exhaustion.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
    - shard-kbl:          NOTRUN -> [SKIP][19] ([fdo#109271]) +116 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl6/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_softpin@evict-snoop:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([fdo#109312])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb6/igt@gem_softpin@evict-snoop.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3323])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl1/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][22] ([i915#3323])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb4/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-glk:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3323])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk7/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#3323])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@set-cache-level:
    - shard-snb:          NOTRUN -> [FAIL][25] ([i915#3324])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb6/igt@gem_userptr_blits@set-cache-level.html
    - shard-apl:          NOTRUN -> [FAIL][26] ([i915#3324])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl1/igt@gem_userptr_blits@set-cache-level.html
    - shard-glk:          NOTRUN -> [FAIL][27] ([i915#3324])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk6/igt@gem_userptr_blits@set-cache-level.html

  * igt@gen7_exec_parse@basic-allowed:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([fdo#109289]) +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb2/igt@gen7_exec_parse@basic-allowed.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#112306])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb1/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([i915#2856])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb5/igt@gen9_exec_parse@shadow-peek.html
    - shard-iclb:         NOTRUN -> [SKIP][31] ([i915#2856])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb4/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglb:         NOTRUN -> [WARN][32] ([i915#2681])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html
    - shard-iclb:         NOTRUN -> [WARN][33] ([i915#1804] / [i915#2684])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#109506] / [i915#2411])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#109293] / [fdo#109506])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_query@query-topology-unsupported:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109302])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb7/igt@i915_query@query-topology-unsupported.html
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#109302])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb7/igt@i915_query@query-topology-unsupported.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#110725] / [fdo#111614]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb1/igt@kms_big_fb@linear-64bpp-rotate-270.html
    - shard-tglb:         NOTRUN -> [SKIP][39] ([fdo#111614]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb2/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([fdo#111615])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#110723])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#2705])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo:
    - shard-snb:          NOTRUN -> [SKIP][43] ([fdo#109271]) +391 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb6/igt@kms_ccs@pipe-a-ccs-on-another-bo.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb1/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
    - shard-snb:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-snb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium@vga-edid-read:
    - shard-glk:          NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk1/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_chamelium@vga-hpd:
    - shard-apl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +24 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl8/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-75:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb8/igt@kms_color_chamelium@pipe-b-ctm-0-75.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][50] ([i915#1319]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@mei_interface:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109300] / [fdo#111066])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb4/igt@kms_content_protection@mei_interface.html
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#111828])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb3/igt@kms_content_protection@mei_interface.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#3319] / [i915#3359])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([i915#3319]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-random:
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271]) +69 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk7/igt@kms_cursor_crc@pipe-b-cursor-max-size-random.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3359])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109274] / [fdo#109278])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-glk:          [PASS][58] -> [FAIL][59] ([i915#2346])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-glk:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533]) +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk5/igt@kms_cursor_legacy@pipe-d-single-bo.html
    - shard-kbl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl4/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][62] ([fdo#109274]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][63] -> [FAIL][64] ([i915#2122])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][65] -> [DMESG-WARN][66] ([i915#180]) +9 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
    - shard-apl:          [PASS][67] -> [DMESG-WARN][68] ([i915#180])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-kbl:          NOTRUN -> [FAIL][69] ([i915#2641])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2672])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2642])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2642])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-kbl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2672])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][74] ([fdo#111825]) +24 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109280]) +13 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_hdr@static-swap:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([i915#1187])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb8/igt@kms_hdr@static-swap.html
    - shard-iclb:         NOTRUN -> [SKIP][77] ([i915#1187])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@kms_hdr@static-swap.html

  * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
    - shard-iclb:         NOTRUN -> [SKIP][78] ([fdo#109289]) +2 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb8/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533]) +4 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][80] ([i915#180] / [i915#533])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][81] ([i915#265])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-glk:          NOTRUN -> [FAIL][82] ([fdo#108145] / [i915#265])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
    - shard-apl:          NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-glk:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
    - shard-iclb:         NOTRUN -> [SKIP][85] ([i915#658])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658]) +4 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][87] -> [SKIP][88] ([fdo#109441]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb5/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         NOTRUN -> [SKIP][89] ([fdo#109441]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][90] ([i915#180] / [i915#295])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-modeset-rpm:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([fdo#109278]) +13 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb1/igt@kms_vblank@pipe-d-ts-continuation-modeset-rpm.html

  * igt@kms_vrr@flip-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109502])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb7/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-apl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2437]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl8/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-glk:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2437])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk9/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@nouveau_crc@pipe-b-source-outp-inactive:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([i915#2530])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@nouveau_crc@pipe-b-source-outp-inactive.html

  * igt@nouveau_crc@pipe-d-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#2530]) +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb6/igt@nouveau_crc@pipe-d-ctx-flip-detection.html
    - shard-iclb:         NOTRUN -> [SKIP][97] ([fdo#109278] / [i915#2530])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb2/igt@nouveau_crc@pipe-d-ctx-flip-detection.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][98] ([fdo#109271]) +265 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl6/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
    - shard-iclb:         NOTRUN -> [SKIP][99] ([fdo#109291]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb6/igt@prime_nv_api@nv_i915_import_twice_check_flink_name.html

  * igt@prime_nv_api@nv_self_import_to_different_fd:
    - shard-tglb:         NOTRUN -> [SKIP][100] ([fdo#109291]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb1/igt@prime_nv_api@nv_self_import_to_different_fd.html

  * igt@sysfs_clients@busy:
    - shard-apl:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@sysfs_clients@busy.html

  * igt@sysfs_clients@pidname:
    - shard-kbl:          NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2994])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl7/igt@sysfs_clients@pidname.html

  
#### Possible fixes ####

  * igt@gem_create@create-clear:
    - shard-glk:          [FAIL][103] ([i915#1888] / [i915#3160]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk3/igt@gem_create@create-clear.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk2/igt@gem_create@create-clear.html

  * igt@gem_ctx_shared@q-smoketest-all:
    - shard-glk:          [DMESG-WARN][105] ([i915#118] / [i915#95]) -> [PASS][106] +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk2/igt@gem_ctx_shared@q-smoketest-all.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk6/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][107] ([i915#2842]) -> [PASS][108] +2 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][109] ([i915#2842]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-iclb:         [FAIL][111] ([i915#307]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [DMESG-WARN][113] ([i915#180]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-kbl3/igt@i915_suspend@debugfs-reader.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-kbl1/igt@i915_suspend@debugfs-reader.html

  * igt@kms_color@pipe-b-ctm-0-75:
    - shard-tglb:         [INCOMPLETE][115] ([i915#1149]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-tglb6/igt@kms_color@pipe-b-ctm-0-75.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-tglb5/igt@kms_color@pipe-b-ctm-0-75.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-apl:          [DMESG-WARN][117] ([i915#180]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [FAIL][119] ([i915#72]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [SKIP][121] ([fdo#109441]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb2/igt@kms_psr@psr2_sprite_render.html

  * igt@prime_vgem@coherency-blt:
    - shard-glk:          [INCOMPLETE][123] ([i915#2944]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk5/igt@prime_vgem@coherency-blt.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk3/igt@prime_vgem@coherency-blt.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][125] ([i915#2681] / [i915#2684]) -> [WARN][126] ([i915#1804] / [i915#2684])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
    - shard-iclb:         [SKIP][127] ([i915#2920]) -> [SKIP][128] ([i915#658]) +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][129] ([i915#658]) -> [SKIP][130] ([i915#2920]) +2 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002]) -> ([FAIL][135], [FAIL][136]) ([i915#180] / [i915#3002])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl2/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl1/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl2/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-apl8/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl7/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-apl2/igt@runner@aborted.html
    - shard-glk:          ([FAIL][137], [FAIL][138], [FAIL][139]) ([i915#2722] / [i915#3002] / [i915#409] / [k.org#202321]) -> ([FAIL][140], [FAIL][141]) ([i915#3002] / [k.org#202321])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk8/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk5/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9976/shard-glk5/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk9/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/shard-glk9/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bug

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5748/index.html

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Re: [igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation

[Ruhl, Michael J]

>-----Original Message-----
>From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Jason
>Ekstrand
>Sent: Thursday, April 15, 2021 3:11 PM
>To: igt-dev@lists.freedesktop.org
>Cc: Daniel Vetter <daniel@ffwll.ch>
>Subject: [igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation
>
>I'm trying to clean up some of our uAPI technical debt in i915.  One of the
>biggest areas we have right now is context mutability.  There's no good
>reason why things like the set of engines or the VM should be able to be
>changed on the fly and no "real" userspace actually relies on this
>functionality.  It does, however, make for a good excuse for tests and lots
>of bug reports as things like swapping out the set of engines under load
>break randomly.  The solution here is to stop allowing that behavior and
>simplify the i915 internals.
>
>In particular, we'd like to remove the following from the i915 API:
>
> 1. I915_CONTEXT_CLONE_*.  These are only used by IGT and have never
>been
>    used by any "real" userspace.
>
> 2. Changing the VM or set of engines via SETPARAM after they've been
>    "used" by an execbuf or similar.  This would effectively make those
>    parameters create params rather than mutable state.  We can't drop
>    setparam entirely for those because media does use it but we can
>    enforce some rules.
>
> 3. Unused (by non-IGT userspace) GETPARAM for things like engines.
>
>As much as we'd love to do that, we have a bit of a problem in IGT.  The
>way we handle multi-engine testing today relies heavily on this soon-to-be-
>deprecated functionality.  In particular, the standard flow is usually
>something like this:
>
>    static void run_test1(int fd, uint32_t engine)
>    {
>        igt_spin_t *spin;
>
>        ctx = = gem_context_clone_with_engines(fd, 0);
>        __igt_spin_new(fd, ctx, .engine = engine);
>
>        /* do some testing with ctx */
>
>        igt_spin_free(fd, spin);
>        gem_destroy_context(fd, ctx);
>    }
>
>    igt_main
>    {
>        struct intel_execution_engine2 *e;
>
>        /* Usual fixture code */
>
>        __for_each_physical_engine(fd, e)
>            run_test1(fd, e->flags);
>
>        __for_each_physical_engine(fd, e)
>            run_test2(fd, e->flags);
>    }
>
>Let's walk through what this does:
>
> 1. __for_each_physical_engine calls intel_init_engine_list() which resets
>    the set of engines on ctx0 to the full set of engines available as per
>    the engine query.  On older kernels/hardware where we don't have the
>    engines query, it leaves the set alone.
>
> 2. intel_init_engine_list() also returns a set of engines for iteration
>    and __for_each_physical_engine() sets up a for loop to walk the set.
>
> 3. gem_context_clone_with_engines() creates a new context using
>    I915_CONTEXT_CONTEXT_CLONE_ENGINES (not used by anything other
>than
>    IGT) to ask that the newly created context has the same set of engines
>    as ctx0.  Remember we changed that at the start of loop iteration!
>
> 4. When the context is passed to __igt_spin_new(), it calls
>    gem_context_lookup_engine which does a GETPARAM to introspet the set
>of
>    engines on the context and figure out the engine class.
>
>If you've been keeping track, this trivial and extremely common example
>uses every single one of these soon-to-be-deprecated APIs even though the
>test author may be completely obvious to it.  It also means that getting

I think you mean

s/obvious/oblivious/

?

M

>rid of IGT's use of them is going to require some fairly deep surgery.
>
>The approach proposed and partially implemented here is to add a new
>wrapper struct intel_ctx_t which wraps a GEM context handle as well as the
>full set of parameters used to create it, represented by intel_ctx_cfg_t.
>We can then use the context anywhere we would regularly use a context, we
>just have to do ctx->id.  If we want to clone it, we can do so by re-using
>the create parameters by calling intel_ctx_create(fd, &old_ctx->cfg);
>
>Along with the above rework (which got long, sorry) I've got a few other
>patches in here which delete tests which exist expressly to test APIs that
>are on the chopping block.
>
>--Jason
>
>
>Cc: Daniel Vetter <daniel@ffwll.ch>
>
>Jason Ekstrand (74):
>  tests/i915: Drop gem_ctx_ringsize
>  tests/i915/gem_exec_balancer: Drop the ringsize subtest
>  tests/i915/gem_exec_endless: Stop setting the ring size
>  tests/i915/gem_ctx_param: Drop the zeromap subtests
>  tests/i915: Drop gem_ctx_clone
>  lib/i915/gem_engine_topology: Expose the __query_engines helper
>  lib/i915/gem_context: Add gem_context_create_ext helpers
>  lib: Add an intel_ctx wrapper struct and helpers (v2)
>  lib/i915/gem_engine_topology: Rework query_engine_list()
>  lib/i915/gem_engine_topology: Factor out static engine listing
>  lib/i915/gem_engine_topology: Add an iterator which doesn't munge
>    contexts
>  lib/i915/gem_engine_topology: Add an iterator for intel_ctx_t
>  tests/i915/gem_exec_basic: Convert to intel_ctx_t
>  lib/igt_spin: Rename igt_spin_factory::ctx to ctx_id
>  lib/igt_spin: Support intel_ctx_t
>  tests/i915/gem_exec_fence: Move the engine data into
>    inter_engine_context
>  tests/i915/gem_exec_fence: Convert to intel_ctx_t
>  tests/i915/gem_exec_schedule: Convert to intel_ctx_t
>  tests/i915/perf_pmu: Convert to intel_ctx_t
>  tests/i915/gem_exec_nop: Convert to intel_ctx_t
>  tests/i915/gem_exec_reloc: Convert to intel_ctx_t
>  tests/i915/gem_busy: Convert to intel_ctx_t
>  tests/i915/gem_ctx_isolation: Convert to intel_ctx_t
>  tests/i915/gem_exec_async: Convert to intel_ctx_t
>  tests/i915/sysfs_clients: Convert to intel_ctx_t
>  tests/i915/gem_exec_fair: Convert to intel_ctx_t
>  tests/i915/gem_spin_batch: Convert to intel_ctx_t
>  tests/i915/gem_exec_store: Convert to intel_ctx_t
>  tests/amdgpu/amd_prime: Convert to intel_ctx_t
>  tests/i915/i915_hangman: Convert to intel_ctx_t
>  tests/i915/gem_ringfill: Convert to intel_ctx_t
>  tests/prime_busy: Convert to intel_ctx_t
>  tests/prime_vgem: Convert to intel_ctx_t
>  tests/gem_exec_whisper: Convert to intel_ctx_t
>  tests/i915/gem_ctx_exec: Stop cloning contexts in close_race
>  tests/i915/gem_ctx_exec: Convert to intel_ctx_t
>  tests/i915/gem_exec_suspend: Convert to intel_ctx_t
>  tests/i915/gem_sync: Convert to intel_ctx_t
>  tests/i915/gem_userptr_blits: Convert to intel_ctx_t
>  tests/i915/gem_wait: Convert to intel_ctx_t
>  tests/i915/gem_request_retire: Convert to intel_ctx_t
>  tests/i915/gem_ctx_shared: Convert to intel_ctx_t
>  tests/i915/gem_ctx_shared: Stop cloning contexts
>  tests/i915/gem_create: Convert to intel_ctx_t
>  tests/i915/gem_ctx_switch: Convert to intel_ctx_t
>  tests/i915/gem_exec_parallel: Convert to intel_ctx_t
>  tests/i915/gem_exec_latency: Convert to intel_ctx_t
>  tests/i915/gem_watchdog: Convert to intel_ctx_t
>  tests/i915/gem_shrink: Convert to intel_ctx_t
>  tests/i915/gem_exec_params: Convert to intel_ctx_t
>  tests/i915/gem_exec_gttfill: Convert to intel_ctx_t
>  tests/i915/gem_exec_capture: Convert to intel_ctx_t
>  tests/i915/gem_exec_create: Convert to intel_ctx_t
>  tests/i915/gem_exec_await: Convert to intel_ctx_t
>  tests/i915/gem_ctx_persistence: Drop the clone subtest
>  tests/i915/gem_ctx_persistence: Drop the engine replace subtests
>  tests/i915/gem_ctx_persistence: Convert to intel_ctx_t
>  tests/i915/module_load: Convert to intel_ctx_t
>  tests/i915/pm_rc6_residency: Convert to intel_ctx_t
>  tests/i915/gem_cs_tlb: Convert to intel_ctx_t
>  tests/core_hotplug: Convert to intel_ctx_t
>  tests/i915/gem_exec_balancer: Stop cloning engines
>  tests/i915/gem_exec_balancer: Don't reset engines on a context
>  tests/i915/gem_exec_balancer: Stop munging ctx0 engines
>  tests/i915/gem_exec_endless: Stop munging ctx0 engines
>  lib/i915: Use for_each_physical_ring for submission tests
>  tests/i915/gem_ctx_engines: Rework execute-one*
>  tests/i915/gem_ctx_engines: Use better engine iteration
>  tests/i915/gem_ctx_engines: Drop the idempotent subtest
>  tests/i915/gem_ctx_create: Convert benchmarks to intel_ctx_t
>  lib/i915/gem_context: Delete all the context clone/copy stuff
>  tests/i915/gem_ctx_engines: Delete the libapi subtest
>  lib/igt_dummyload: Stop supporting ALL_ENGINES without an intel_ctx_t
>  lib/i915/gem_engine_topology: Delete the old physical engine iterators
>
> lib/i915/gem_context.c             | 206 ++-----
> lib/i915/gem_context.h             |  19 +-
> lib/i915/gem_engine_topology.c     | 142 +++--
> lib/i915/gem_engine_topology.h     |  29 +-
> lib/i915/gem_submission.c          |  13 +-
> lib/igt_dummyload.c                |  13 +-
> lib/igt_dummyload.h                |   6 +-
> lib/igt_gt.c                       |   2 +-
> lib/intel_ctx.c                    | 177 ++++++
> lib/intel_ctx.h                    | 112 ++++
> lib/meson.build                    |   1 +
> tests/amdgpu/amd_prime.c           |  10 +-
> tests/core_hotunplug.c             |   6 +-
> tests/i915/gem_busy.c              |  77 +--
> tests/i915/gem_create.c            |  14 +-
> tests/i915/gem_cs_tlb.c            |  10 +-
> tests/i915/gem_ctx_clone.c         | 450 ---------------
> tests/i915/gem_ctx_create.c        |  76 +--
> tests/i915/gem_ctx_engines.c       | 239 ++------
> tests/i915/gem_ctx_exec.c          |  19 +-
> tests/i915/gem_ctx_isolation.c     | 112 ++--
> tests/i915/gem_ctx_param.c         |  33 --
> tests/i915/gem_ctx_persistence.c   | 435 ++++----------
> tests/i915/gem_ctx_ringsize.c      | 345 ------------
> tests/i915/gem_ctx_shared.c        | 335 ++++++-----
> tests/i915/gem_ctx_switch.c        | 115 ++--
> tests/i915/gem_eio.c               |   2 +-
> tests/i915/gem_exec_async.c        |  32 +-
> tests/i915/gem_exec_await.c        |  20 +-
> tests/i915/gem_exec_balancer.c     | 293 ++++------
> tests/i915/gem_exec_basic.c        |   7 +-
> tests/i915/gem_exec_capture.c      |  30 +-
> tests/i915/gem_exec_create.c       |   9 +-
> tests/i915/gem_exec_endless.c      |  14 +-
> tests/i915/gem_exec_fair.c         | 112 ++--
> tests/i915/gem_exec_fence.c        | 302 +++++-----
> tests/i915/gem_exec_gttfill.c      |  15 +-
> tests/i915/gem_exec_latency.c      | 118 ++--
> tests/i915/gem_exec_nop.c          | 156 ++---
> tests/i915/gem_exec_parallel.c     |  29 +-
> tests/i915/gem_exec_params.c       |   4 +-
> tests/i915/gem_exec_reloc.c        | 102 ++--
> tests/i915/gem_exec_schedule.c     | 876 +++++++++++++++--------------
> tests/i915/gem_exec_store.c        |  36 +-
> tests/i915/gem_exec_suspend.c      |  52 +-
> tests/i915/gem_exec_whisper.c      |  83 ++-
> tests/i915/gem_request_retire.c    |  17 +-
> tests/i915/gem_ringfill.c          |  48 +-
> tests/i915/gem_shrink.c            |  37 +-
> tests/i915/gem_spin_batch.c        |  79 +--
> tests/i915/gem_sync.c              | 159 +++---
> tests/i915/gem_userptr_blits.c     |  25 +-
> tests/i915/gem_vm_create.c         |   4 +-
> tests/i915/gem_wait.c              |  20 +-
> tests/i915/gem_watchdog.c          | 167 ++----
> tests/i915/gem_workarounds.c       |   2 +-
> tests/i915/i915_hangman.c          |  37 +-
> tests/i915/i915_module_load.c      |   7 +-
> tests/i915/i915_pm_rc6_residency.c |   7 +-
> tests/i915/perf_pmu.c              | 226 ++++----
> tests/i915/sysfs_clients.c         |  87 +--
> tests/meson.build                  |   2 -
> tests/prime_busy.c                 |  19 +-
> tests/prime_vgem.c                 |  35 +-
> 64 files changed, 2785 insertions(+), 3481 deletions(-)
> create mode 100644 lib/intel_ctx.c
> create mode 100644 lib/intel_ctx.h
> delete mode 100644 tests/i915/gem_ctx_clone.c
> delete mode 100644 tests/i915/gem_ctx_ringsize.c
>
>--
>2.31.1
>
>_______________________________________________
>igt-dev mailing list
>igt-dev@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation

[Jason Ekstrand]

I just rebased on top of the reloc/allocator stuff and sent to trybot again.

On Mon, Apr 12, 2021 at 10:53 PM Jason Ekstrand <jason@jlekstrand.net> wrote:
>
> I'm trying to clean up some of our uAPI technical debt in i915.  One of the
> biggest areas we have right now is context mutability.  There's no good
> reason why things like the set of engines or the VM should be able to be
> changed on the fly and no "real" userspace actually relies on this
> functionality.  It does, however, make for a good excuse for tests and lots
> of bug reports as things like swapping out the set of engines under load
> break randomly.  The solution here is to stop allowing that behavior and
> simplify the i915 internals.
>
> In particular, we'd like to remove the following from the i915 API:
>
>  1. I915_CONTEXT_CLONE_*.  These are only used by IGT and have never been
>     used by any "real" userspace.
>
>  2. Changing the VM or set of engines via SETPARAM after they've been
>     "used" by an execbuf or similar.  This would effectively make those
>     parameters create params rather than mutable state.  We can't drop
>     setparam entirely for those because media does use it but we can
>     enforce some rules.
>
>  3. Unused (by non-IGT userspace) GETPARAM for things like engines.
>
> As much as we'd love to do that, we have a bit of a problem in IGT.  The
> way we handle multi-engine testing today relies heavily on this soon-to-be-
> deprecated functionality.  In particular, the standard flow is usually
> something like this:
>
>     static void run_test1(int fd, uint32_t engine)
>     {
>         igt_spin_t *spin;
>
>         ctx = = gem_context_clone_with_engines(fd, 0);
>         __igt_spin_new(fd, ctx, .engine = engine);
>
>         /* do some testing with ctx */
>
>         igt_spin_free(fd, spin);
>         gem_destroy_context(fd, ctx);
>     }
>
>     igt_main
>     {
>         struct intel_execution_engine2 *e;
>
>         /* Usual fixture code */
>
>         __for_each_physical_engine(fd, e)
>             run_test1(fd, e->flags);
>
>         __for_each_physical_engine(fd, e)
>             run_test2(fd, e->flags);
>     }
>
> Let's walk through what this does:
>
>  1. __for_each_physical_engine calls intel_init_engine_list() which resets
>     the set of engines on ctx0 to the full set of engines available as per
>     the engine query.  On older kernels/hardware where we don't have the
>     engines query, it leaves the set alone.
>
>  2. intel_init_engine_list() also returns a set of engines for iteration
>     and __for_each_physical_engine() sets up a for loop to walk the set.
>
>  3. gem_context_clone_with_engines() creates a new context using
>     I915_CONTEXT_CONTEXT_CLONE_ENGINES (not used by anything other than
>     IGT) to ask that the newly created context has the same set of engines
>     as ctx0.  Remember we changed that at the start of loop iteration!
>
>  4. When the context is passed to __igt_spin_new(), it calls
>     gem_context_lookup_engine which does a GETPARAM to introspet the set of
>     engines on the context and figure out the engine class.
>
> If you've been keeping track, this trivial and extremely common example
> uses every single one of these soon-to-be-deprecated APIs even though the
> test author may be completely obvious to it.  It also means that getting
> rid of IGT's use of them is going to require some fairly deep surgery.
>
> The approach proposed and partially implemented here is to add a new
> wrapper struct intel_ctx_t which wraps a GEM context handle as well as the
> full set of parameters used to create it, represented by intel_ctx_cfg_t.
> We can then use the context anywhere we would regularly use a context, we
> just have to do ctx->id.  If we want to clone it, we can do so by re-using
> the create parameters by calling intel_ctx_create(fd, &old_ctx->cfg);
>
> Along with the above rework (which got long, sorry) I've got a few other
> patches in here which delete tests which exist expressly to test APIs that
> are on the chopping block.
>
> --Jason
>
>
> Cc: Daniel Vetter <daniel@ffwll.ch>
>
> Jason Ekstrand (74):
>   tests/i915: Drop gem_ctx_ringsize
>   tests/i915/gem_exec_balancer: Drop the ringsize subtest
>   tests/i915/gem_exec_endless: Stop setting the ring size
>   tests/i915/gem_ctx_param: Drop the zeromap subtests
>   tests/i915: Drop gem_ctx_clone
>   lib/i915/gem_engine_topology: Expose the __query_engines helper
>   lib/i915/gem_context: Add gem_context_create_ext helpers
>   lib: Add an intel_ctx wrapper struct and helpers (v2)
>   lib/i915/gem_engine_topology: Rework query_engine_list()
>   lib/i915/gem_engine_topology: Factor out static engine listing
>   lib/i915/gem_engine_topology: Add an iterator which doesn't munge
>     contexts
>   lib/i915/gem_engine_topology: Add an iterator for intel_ctx_t
>   tests/i915/gem_exec_basic: Convert to intel_ctx_t
>   lib/igt_spin: Rename igt_spin_factory::ctx to ctx_id
>   lib/igt_spin: Support intel_ctx_t
>   tests/i915/gem_exec_fence: Move the engine data into
>     inter_engine_context
>   tests/i915/gem_exec_fence: Convert to intel_ctx_t
>   tests/i915/gem_exec_schedule: Convert to intel_ctx_t
>   tests/i915/perf_pmu: Convert to intel_ctx_t
>   tests/i915/gem_exec_nop: Convert to intel_ctx_t
>   tests/i915/gem_exec_reloc: Convert to intel_ctx_t
>   tests/i915/gem_busy: Convert to intel_ctx_t
>   tests/i915/gem_ctx_isolation: Convert to intel_ctx_t
>   tests/i915/gem_exec_async: Convert to intel_ctx_t
>   tests/i915/sysfs_clients: Convert to intel_ctx_t
>   tests/i915/gem_exec_fair: Convert to intel_ctx_t
>   tests/i915/gem_spin_batch: Convert to intel_ctx_t
>   tests/i915/gem_exec_store: Convert to intel_ctx_t
>   tests/amdgpu/amd_prime: Convert to intel_ctx_t
>   tests/i915/i915_hangman: Convert to intel_ctx_t
>   tests/i915/gem_ringfill: Convert to intel_ctx_t
>   tests/prime_busy: Convert to intel_ctx_t
>   tests/prime_vgem: Convert to intel_ctx_t
>   tests/gem_exec_whisper: Convert to intel_ctx_t
>   tests/i915/gem_ctx_exec: Stop cloning contexts in close_race
>   tests/i915/gem_ctx_exec: Convert to intel_ctx_t
>   tests/i915/gem_exec_suspend: Convert to intel_ctx_t
>   tests/i915/gem_sync: Convert to intel_ctx_t
>   tests/i915/gem_userptr_blits: Convert to intel_ctx_t
>   tests/i915/gem_wait: Convert to intel_ctx_t
>   tests/i915/gem_request_retire: Convert to intel_ctx_t
>   tests/i915/gem_ctx_shared: Convert to intel_ctx_t
>   tests/i915/gem_ctx_shared: Stop cloning contexts
>   tests/i915/gem_create: Convert to intel_ctx_t
>   tests/i915/gem_ctx_switch: Convert to intel_ctx_t
>   tests/i915/gem_exec_parallel: Convert to intel_ctx_t
>   tests/i915/gem_exec_latency: Convert to intel_ctx_t
>   tests/i915/gem_watchdog: Convert to intel_ctx_t
>   tests/i915/gem_shrink: Convert to intel_ctx_t
>   tests/i915/gem_exec_params: Convert to intel_ctx_t
>   tests/i915/gem_exec_gttfill: Convert to intel_ctx_t
>   tests/i915/gem_exec_capture: Convert to intel_ctx_t
>   tests/i915/gem_exec_create: Convert to intel_ctx_t
>   tests/i915/gem_exec_await: Convert to intel_ctx_t
>   tests/i915/gem_ctx_persistence: Drop the clone subtest
>   tests/i915/gem_ctx_persistence: Drop the engine replace subtests
>   tests/i915/gem_ctx_persistence: Convert to intel_ctx_t
>   tests/i915/module_load: Convert to intel_ctx_t
>   tests/i915/pm_rc6_residency: Convert to intel_ctx_t
>   tests/i915/gem_cs_tlb: Convert to intel_ctx_t
>   tests/core_hotplug: Convert to intel_ctx_t
>   tests/i915/gem_exec_balancer: Stop cloning engines
>   tests/i915/gem_exec_balancer: Don't reset engines on a context
>   tests/i915/gem_exec_balancer: Stop munging ctx0 engines
>   tests/i915/gem_exec_endless: Stop munging ctx0 engines
>   lib/i915: Use for_each_physical_ring for submission tests
>   tests/i915/gem_ctx_engines: Rework execute-one*
>   tests/i915/gem_ctx_engines: Use better engine iteration
>   tests/i915/gem_ctx_engines: Drop the idempotent subtest
>   tests/i915/gem_ctx_create: Convert benchmarks to intel_ctx_t
>   lib/i915/gem_context: Delete all the context clone/copy stuff
>   tests/i915/gem_ctx_engines: Delete the libapi subtest
>   lib/igt_dummyload: Stop supporting ALL_ENGINES without an intel_ctx_t
>   lib/i915/gem_engine_topology: Delete the old physical engine iterators
>
>  lib/i915/gem_context.c             | 206 ++-----
>  lib/i915/gem_context.h             |  19 +-
>  lib/i915/gem_engine_topology.c     | 142 +++--
>  lib/i915/gem_engine_topology.h     |  29 +-
>  lib/i915/gem_submission.c          |  13 +-
>  lib/igt_dummyload.c                |  13 +-
>  lib/igt_dummyload.h                |   6 +-
>  lib/igt_gt.c                       |   2 +-
>  lib/intel_ctx.c                    | 177 ++++++
>  lib/intel_ctx.h                    | 112 ++++
>  lib/meson.build                    |   1 +
>  tests/amdgpu/amd_prime.c           |  10 +-
>  tests/core_hotunplug.c             |   6 +-
>  tests/i915/gem_busy.c              |  77 +--
>  tests/i915/gem_create.c            |  14 +-
>  tests/i915/gem_cs_tlb.c            |  10 +-
>  tests/i915/gem_ctx_clone.c         | 450 ---------------
>  tests/i915/gem_ctx_create.c        |  76 +--
>  tests/i915/gem_ctx_engines.c       | 239 ++------
>  tests/i915/gem_ctx_exec.c          |  19 +-
>  tests/i915/gem_ctx_isolation.c     | 112 ++--
>  tests/i915/gem_ctx_param.c         |  33 --
>  tests/i915/gem_ctx_persistence.c   | 435 ++++----------
>  tests/i915/gem_ctx_ringsize.c      | 345 ------------
>  tests/i915/gem_ctx_shared.c        | 335 ++++++-----
>  tests/i915/gem_ctx_switch.c        | 115 ++--
>  tests/i915/gem_eio.c               |   2 +-
>  tests/i915/gem_exec_async.c        |  32 +-
>  tests/i915/gem_exec_await.c        |  20 +-
>  tests/i915/gem_exec_balancer.c     | 293 ++++------
>  tests/i915/gem_exec_basic.c        |   7 +-
>  tests/i915/gem_exec_capture.c      |  30 +-
>  tests/i915/gem_exec_create.c       |   9 +-
>  tests/i915/gem_exec_endless.c      |  14 +-
>  tests/i915/gem_exec_fair.c         | 112 ++--
>  tests/i915/gem_exec_fence.c        | 302 +++++-----
>  tests/i915/gem_exec_gttfill.c      |  15 +-
>  tests/i915/gem_exec_latency.c      | 118 ++--
>  tests/i915/gem_exec_nop.c          | 156 ++---
>  tests/i915/gem_exec_parallel.c     |  29 +-
>  tests/i915/gem_exec_params.c       |   4 +-
>  tests/i915/gem_exec_reloc.c        | 102 ++--
>  tests/i915/gem_exec_schedule.c     | 876 +++++++++++++++--------------
>  tests/i915/gem_exec_store.c        |  36 +-
>  tests/i915/gem_exec_suspend.c      |  52 +-
>  tests/i915/gem_exec_whisper.c      |  83 ++-
>  tests/i915/gem_request_retire.c    |  17 +-
>  tests/i915/gem_ringfill.c          |  48 +-
>  tests/i915/gem_shrink.c            |  37 +-
>  tests/i915/gem_spin_batch.c        |  79 +--
>  tests/i915/gem_sync.c              | 159 +++---
>  tests/i915/gem_userptr_blits.c     |  25 +-
>  tests/i915/gem_vm_create.c         |   4 +-
>  tests/i915/gem_wait.c              |  20 +-
>  tests/i915/gem_watchdog.c          | 167 ++----
>  tests/i915/gem_workarounds.c       |   2 +-
>  tests/i915/i915_hangman.c          |  37 +-
>  tests/i915/i915_module_load.c      |   7 +-
>  tests/i915/i915_pm_rc6_residency.c |   7 +-
>  tests/i915/perf_pmu.c              | 226 ++++----
>  tests/i915/sysfs_clients.c         |  87 +--
>  tests/meson.build                  |   2 -
>  tests/prime_busy.c                 |  19 +-
>  tests/prime_vgem.c                 |  35 +-
>  64 files changed, 2785 insertions(+), 3481 deletions(-)
>  create mode 100644 lib/intel_ctx.c
>  create mode 100644 lib/intel_ctx.h
>  delete mode 100644 tests/i915/gem_ctx_clone.c
>  delete mode 100644 tests/i915/gem_ctx_ringsize.c
>
> --
> 2.31.1
>
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https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 00/74] Stop depending on context mutation

[Jason Ekstrand]

I'm trying to clean up some of our uAPI technical debt in i915.  One of the
biggest areas we have right now is context mutability.  There's no good
reason why things like the set of engines or the VM should be able to be
changed on the fly and no "real" userspace actually relies on this
functionality.  It does, however, make for a good excuse for tests and lots
of bug reports as things like swapping out the set of engines under load
break randomly.  The solution here is to stop allowing that behavior and
simplify the i915 internals.

In particular, we'd like to remove the following from the i915 API:

 1. I915_CONTEXT_CLONE_*.  These are only used by IGT and have never been
    used by any "real" userspace.

 2. Changing the VM or set of engines via SETPARAM after they've been
    "used" by an execbuf or similar.  This would effectively make those
    parameters create params rather than mutable state.  We can't drop
    setparam entirely for those because media does use it but we can
    enforce some rules.

 3. Unused (by non-IGT userspace) GETPARAM for things like engines.

As much as we'd love to do that, we have a bit of a problem in IGT.  The
way we handle multi-engine testing today relies heavily on this soon-to-be-
deprecated functionality.  In particular, the standard flow is usually
something like this:

    static void run_test1(int fd, uint32_t engine)
    {
        igt_spin_t *spin;

        ctx = = gem_context_clone_with_engines(fd, 0);
        __igt_spin_new(fd, ctx, .engine = engine);

        /* do some testing with ctx */

        igt_spin_free(fd, spin);
        gem_destroy_context(fd, ctx);
    }

    igt_main
    {
        struct intel_execution_engine2 *e;

        /* Usual fixture code */

        __for_each_physical_engine(fd, e)
            run_test1(fd, e->flags);

        __for_each_physical_engine(fd, e)
            run_test2(fd, e->flags);
    }

Let's walk through what this does:

 1. __for_each_physical_engine calls intel_init_engine_list() which resets
    the set of engines on ctx0 to the full set of engines available as per
    the engine query.  On older kernels/hardware where we don't have the
    engines query, it leaves the set alone.

 2. intel_init_engine_list() also returns a set of engines for iteration
    and __for_each_physical_engine() sets up a for loop to walk the set.

 3. gem_context_clone_with_engines() creates a new context using
    I915_CONTEXT_CONTEXT_CLONE_ENGINES (not used by anything other than
    IGT) to ask that the newly created context has the same set of engines
    as ctx0.  Remember we changed that at the start of loop iteration!

 4. When the context is passed to __igt_spin_new(), it calls
    gem_context_lookup_engine which does a GETPARAM to introspet the set of
    engines on the context and figure out the engine class.

If you've been keeping track, this trivial and extremely common example
uses every single one of these soon-to-be-deprecated APIs even though the
test author may be completely obvious to it.  It also means that getting
rid of IGT's use of them is going to require some fairly deep surgery.

The approach proposed and partially implemented here is to add a new
wrapper struct intel_ctx_t which wraps a GEM context handle as well as the
full set of parameters used to create it, represented by intel_ctx_cfg_t.
We can then use the context anywhere we would regularly use a context, we
just have to do ctx->id.  If we want to clone it, we can do so by re-using
the create parameters by calling intel_ctx_create(fd, &old_ctx->cfg);

Along with the above rework (which got long, sorry) I've got a few other
patches in here which delete tests which exist expressly to test APIs that
are on the chopping block.

--Jason


Cc: Daniel Vetter <daniel@ffwll.ch>

Jason Ekstrand (74):
  tests/i915: Drop gem_ctx_ringsize
  tests/i915/gem_exec_balancer: Drop the ringsize subtest
  tests/i915/gem_exec_endless: Stop setting the ring size
  tests/i915/gem_ctx_param: Drop the zeromap subtests
  tests/i915: Drop gem_ctx_clone
  lib/i915/gem_engine_topology: Expose the __query_engines helper
  lib/i915/gem_context: Add gem_context_create_ext helpers
  lib: Add an intel_ctx wrapper struct and helpers (v2)
  lib/i915/gem_engine_topology: Rework query_engine_list()
  lib/i915/gem_engine_topology: Factor out static engine listing
  lib/i915/gem_engine_topology: Add an iterator which doesn't munge
    contexts
  lib/i915/gem_engine_topology: Add an iterator for intel_ctx_t
  tests/i915/gem_exec_basic: Convert to intel_ctx_t
  lib/igt_spin: Rename igt_spin_factory::ctx to ctx_id
  lib/igt_spin: Support intel_ctx_t
  tests/i915/gem_exec_fence: Move the engine data into
    inter_engine_context
  tests/i915/gem_exec_fence: Convert to intel_ctx_t
  tests/i915/gem_exec_schedule: Convert to intel_ctx_t
  tests/i915/perf_pmu: Convert to intel_ctx_t
  tests/i915/gem_exec_nop: Convert to intel_ctx_t
  tests/i915/gem_exec_reloc: Convert to intel_ctx_t
  tests/i915/gem_busy: Convert to intel_ctx_t
  tests/i915/gem_ctx_isolation: Convert to intel_ctx_t
  tests/i915/gem_exec_async: Convert to intel_ctx_t
  tests/i915/sysfs_clients: Convert to intel_ctx_t
  tests/i915/gem_exec_fair: Convert to intel_ctx_t
  tests/i915/gem_spin_batch: Convert to intel_ctx_t
  tests/i915/gem_exec_store: Convert to intel_ctx_t
  tests/amdgpu/amd_prime: Convert to intel_ctx_t
  tests/i915/i915_hangman: Convert to intel_ctx_t
  tests/i915/gem_ringfill: Convert to intel_ctx_t
  tests/prime_busy: Convert to intel_ctx_t
  tests/prime_vgem: Convert to intel_ctx_t
  tests/gem_exec_whisper: Convert to intel_ctx_t
  tests/i915/gem_ctx_exec: Stop cloning contexts in close_race
  tests/i915/gem_ctx_exec: Convert to intel_ctx_t
  tests/i915/gem_exec_suspend: Convert to intel_ctx_t
  tests/i915/gem_sync: Convert to intel_ctx_t
  tests/i915/gem_userptr_blits: Convert to intel_ctx_t
  tests/i915/gem_wait: Convert to intel_ctx_t
  tests/i915/gem_request_retire: Convert to intel_ctx_t
  tests/i915/gem_ctx_shared: Convert to intel_ctx_t
  tests/i915/gem_ctx_shared: Stop cloning contexts
  tests/i915/gem_create: Convert to intel_ctx_t
  tests/i915/gem_ctx_switch: Convert to intel_ctx_t
  tests/i915/gem_exec_parallel: Convert to intel_ctx_t
  tests/i915/gem_exec_latency: Convert to intel_ctx_t
  tests/i915/gem_watchdog: Convert to intel_ctx_t
  tests/i915/gem_shrink: Convert to intel_ctx_t
  tests/i915/gem_exec_params: Convert to intel_ctx_t
  tests/i915/gem_exec_gttfill: Convert to intel_ctx_t
  tests/i915/gem_exec_capture: Convert to intel_ctx_t
  tests/i915/gem_exec_create: Convert to intel_ctx_t
  tests/i915/gem_exec_await: Convert to intel_ctx_t
  tests/i915/gem_ctx_persistence: Drop the clone subtest
  tests/i915/gem_ctx_persistence: Drop the engine replace subtests
  tests/i915/gem_ctx_persistence: Convert to intel_ctx_t
  tests/i915/module_load: Convert to intel_ctx_t
  tests/i915/pm_rc6_residency: Convert to intel_ctx_t
  tests/i915/gem_cs_tlb: Convert to intel_ctx_t
  tests/core_hotplug: Convert to intel_ctx_t
  tests/i915/gem_exec_balancer: Stop cloning engines
  tests/i915/gem_exec_balancer: Don't reset engines on a context
  tests/i915/gem_exec_balancer: Stop munging ctx0 engines
  tests/i915/gem_exec_endless: Stop munging ctx0 engines
  lib/i915: Use for_each_physical_ring for submission tests
  tests/i915/gem_ctx_engines: Rework execute-one*
  tests/i915/gem_ctx_engines: Use better engine iteration
  tests/i915/gem_ctx_engines: Drop the idempotent subtest
  tests/i915/gem_ctx_create: Convert benchmarks to intel_ctx_t
  lib/i915/gem_context: Delete all the context clone/copy stuff
  tests/i915/gem_ctx_engines: Delete the libapi subtest
  lib/igt_dummyload: Stop supporting ALL_ENGINES without an intel_ctx_t
  lib/i915/gem_engine_topology: Delete the old physical engine iterators

 lib/i915/gem_context.c             | 206 ++-----
 lib/i915/gem_context.h             |  19 +-
 lib/i915/gem_engine_topology.c     | 142 +++--
 lib/i915/gem_engine_topology.h     |  29 +-
 lib/i915/gem_submission.c          |  13 +-
 lib/igt_dummyload.c                |  13 +-
 lib/igt_dummyload.h                |   6 +-
 lib/igt_gt.c                       |   2 +-
 lib/intel_ctx.c                    | 177 ++++++
 lib/intel_ctx.h                    | 112 ++++
 lib/meson.build                    |   1 +
 tests/amdgpu/amd_prime.c           |  10 +-
 tests/core_hotunplug.c             |   6 +-
 tests/i915/gem_busy.c              |  77 +--
 tests/i915/gem_create.c            |  14 +-
 tests/i915/gem_cs_tlb.c            |  10 +-
 tests/i915/gem_ctx_clone.c         | 450 ---------------
 tests/i915/gem_ctx_create.c        |  76 +--
 tests/i915/gem_ctx_engines.c       | 239 ++------
 tests/i915/gem_ctx_exec.c          |  19 +-
 tests/i915/gem_ctx_isolation.c     | 112 ++--
 tests/i915/gem_ctx_param.c         |  33 --
 tests/i915/gem_ctx_persistence.c   | 435 ++++----------
 tests/i915/gem_ctx_ringsize.c      | 345 ------------
 tests/i915/gem_ctx_shared.c        | 335 ++++++-----
 tests/i915/gem_ctx_switch.c        | 115 ++--
 tests/i915/gem_eio.c               |   2 +-
 tests/i915/gem_exec_async.c        |  32 +-
 tests/i915/gem_exec_await.c        |  20 +-
 tests/i915/gem_exec_balancer.c     | 293 ++++------
 tests/i915/gem_exec_basic.c        |   7 +-
 tests/i915/gem_exec_capture.c      |  30 +-
 tests/i915/gem_exec_create.c       |   9 +-
 tests/i915/gem_exec_endless.c      |  14 +-
 tests/i915/gem_exec_fair.c         | 112 ++--
 tests/i915/gem_exec_fence.c        | 302 +++++-----
 tests/i915/gem_exec_gttfill.c      |  15 +-
 tests/i915/gem_exec_latency.c      | 118 ++--
 tests/i915/gem_exec_nop.c          | 156 ++---
 tests/i915/gem_exec_parallel.c     |  29 +-
 tests/i915/gem_exec_params.c       |   4 +-
 tests/i915/gem_exec_reloc.c        | 102 ++--
 tests/i915/gem_exec_schedule.c     | 876 +++++++++++++++--------------
 tests/i915/gem_exec_store.c        |  36 +-
 tests/i915/gem_exec_suspend.c      |  52 +-
 tests/i915/gem_exec_whisper.c      |  83 ++-
 tests/i915/gem_request_retire.c    |  17 +-
 tests/i915/gem_ringfill.c          |  48 +-
 tests/i915/gem_shrink.c            |  37 +-
 tests/i915/gem_spin_batch.c        |  79 +--
 tests/i915/gem_sync.c              | 159 +++---
 tests/i915/gem_userptr_blits.c     |  25 +-
 tests/i915/gem_vm_create.c         |   4 +-
 tests/i915/gem_wait.c              |  20 +-
 tests/i915/gem_watchdog.c          | 167 ++----
 tests/i915/gem_workarounds.c       |   2 +-
 tests/i915/i915_hangman.c          |  37 +-
 tests/i915/i915_module_load.c      |   7 +-
 tests/i915/i915_pm_rc6_residency.c |   7 +-
 tests/i915/perf_pmu.c              | 226 ++++----
 tests/i915/sysfs_clients.c         |  87 +--
 tests/meson.build                  |   2 -
 tests/prime_busy.c                 |  19 +-
 tests/prime_vgem.c                 |  35 +-
 64 files changed, 2785 insertions(+), 3481 deletions(-)
 create mode 100644 lib/intel_ctx.c
 create mode 100644 lib/intel_ctx.h
 delete mode 100644 tests/i915/gem_ctx_clone.c
 delete mode 100644 tests/i915/gem_ctx_ringsize.c

-- 
2.31.1

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