From: Flavio de Castro Alves Filho <flavio.alves@domain.hid>
To: xenomai@xenomai.org
Subject: Re: [Xenomai-help] Porting I-Pipe for new ARM board
Date: Fri, 8 Jan 2010 17:42:52 -0200 [thread overview]
Message-ID: <4303dd241001081142q37797dcjb25fd9103f7e497e@domain.hid> (raw)
In-Reply-To: <4B478825.9000006@domain.hid>
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Of course :-)
As I don't know the best way to send it, I attached the files.
I hope everything is in there. I'm sorry if you find some ugly commented
debug code.
2010/1/8 Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>
> Flavio de Castro Alves Filho wrote:
> > Not this time :-(
> >
> > I increased the value, but it didn't work.
> >
> > I was thinking here. The problem related in the first message of this
> thread
> > is exactly the same problem that I am having:
> >
> > http://www.mail-archive.com/xenomai@xenomai.org
>
> The answer is here:
> http://www.mail-archive.com/xenomai@xenomai.org
>
> Sergey copied the PXA hardware timer support (a free-running counter
> with a match register) instead of writing the code for his real hardware
> timer (a decrementer). This could not work.
>
> So, now, the only thing I can suggest you is to show us your code.
>
> --
> Gilles.
>
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[-- Attachment #2: gpio.c --]
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/*
* TI DaVinci GPIO Support
*
* Copyright (c) 2006-2007 David Brownell
* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <mach/cpu.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <asm/mach/irq.h>
#include <asm/ipipe.h>
static DEFINE_SPINLOCK(gpio_lock);
struct davinci_gpio {
struct gpio_chip chip;
struct gpio_controller *__iomem regs;
};
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
static unsigned __initdata ngpio;
/* create a non-inlined version */
static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio)
{
return __gpio_to_controller(gpio);
}
/*--------------------------------------------------------------------------*/
/*
* board setup code *MUST* set PINMUX0 and PINMUX1 as
* needed, and enable the GPIO clock.
*/
static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
u32 temp;
spin_lock(&gpio_lock);
temp = __raw_readl(&g->dir);
temp |= (1 << offset);
__raw_writel(temp, &g->dir);
spin_unlock(&gpio_lock);
return 0;
}
/*
* Read the pin's value (works even if it's set up as output);
* returns zero/nonzero.
*
* Note that changes are synched to the GPIO clock, so reading values back
* right after you've set them may give old values.
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
return (1 << offset) & __raw_readl(&g->in_data);
}
static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
u32 temp;
u32 mask = 1 << offset;
spin_lock(&gpio_lock);
temp = __raw_readl(&g->dir);
temp &= ~mask;
__raw_writel(mask, value ? &g->set_data : &g->clr_data);
__raw_writel(temp, &g->dir);
spin_unlock(&gpio_lock);
return 0;
}
/*
* Assuming the pin is muxed as a gpio output, set its output value.
*/
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
struct gpio_controller *__iomem g = d->regs;
__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}
static int __init davinci_gpio_setup(void)
{
int i, base;
/* The gpio banks conceptually expose a segmented bitmap,
* and "ngpio" is one more than the largest zero-based
* bit index that's valid.
*/
if (cpu_is_davinci_dm355()) { /* or dm335() */
ngpio = 104;
} else if (cpu_is_davinci_dm644x()) { /* or dm337() */
ngpio = 71;
} else if (cpu_is_davinci_dm646x()) {
/* NOTE: each bank has several "reserved" bits,
* unusable as GPIOs. Only 33 of the GPIO numbers
* are usable, and we're not rejecting the others.
*/
ngpio = 43;
} else if (cpu_is_da830()) { /* or da830 */
ngpio = 128;
} else if (cpu_is_da850()) {
ngpio = 144;
} else {
/* if cpu_is_davinci_dm643x() ngpio = 111 */
pr_err("GPIO setup: how many GPIOs?\n");
return -EINVAL;
}
if (WARN_ON(DAVINCI_N_GPIO < ngpio))
ngpio = DAVINCI_N_GPIO;
for (i = 0, base = 0; base < ngpio; i++, base += 32) {
chips[i].chip.label = "DaVinci";
chips[i].chip.direction_input = davinci_direction_in;
chips[i].chip.get = davinci_gpio_get;
chips[i].chip.direction_output = davinci_direction_out;
chips[i].chip.set = davinci_gpio_set;
chips[i].chip.base = base;
chips[i].chip.ngpio = ngpio - base;
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
chips[i].regs = gpio2controller(base);
gpiochip_add(&chips[i].chip);
}
return 0;
}
pure_initcall(davinci_gpio_setup);
/*--------------------------------------------------------------------------*/
/*
* We expect irqs will normally be set up as input pins, but they can also be
* used as output pins ... which is convenient for testing.
*
* NOTE: The first few GPIOs also have direct INTC hookups in addition
* to their GPIOBNK0 irq, with a bit less overhead but less flexibility
* on triggering (e.g. no edge options). We don't try to use those.
*
* All those INTC hookups (direct, plus several IRQ banks) can also
* serve as EDMA event triggers.
*/
static void gpio_irq_disable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
u32 mask = __gpio_mask(irq_to_gpio(irq));
__raw_writel(mask, &g->clr_falling);
__raw_writel(mask, &g->clr_rising);
}
static void gpio_irq_enable(unsigned irq)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
u32 mask = __gpio_mask(irq_to_gpio(irq));
if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
__raw_writel(mask, &g->set_falling);
if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
__raw_writel(mask, &g->set_rising);
}
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
u32 mask = __gpio_mask(irq_to_gpio(irq));
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL;
irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
irq_desc[irq].status |= trigger;
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
? &g->set_falling : &g->clr_falling);
__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
? &g->set_rising : &g->clr_rising);
return 0;
}
static struct irq_chip gpio_irqchip = {
.name = "GPIO",
.enable = gpio_irq_enable,
.disable = gpio_irq_disable,
.set_type = gpio_irq_type,
};
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
u32 mask = 0xffff;
/* we only care about one bank */
if (irq & 1)
mask <<= 16;
/* temporarily mask (level sensitive) parent IRQ */
desc->chip->ack(irq);
while (1) {
u32 status;
int n;
int res;
/* ack any irqs */
status = __raw_readl(&g->intstat) & mask;
if (!status)
break;
__raw_writel(status, &g->intstat);
if (irq & 1)
status >>= 16;
/* now demux them to the right lowlevel handler */
n = (int)get_irq_data(irq);
while (status) {
res = ffs(status);
n += res;
generic_handle_irq(n - 1);
status >>= res;
}
}
desc->chip->unmask(irq);
/* now it may re-trigger */
}
#ifdef CONFIG_IPIPE
/* Flavio Alves: for debugging */
extern void printascii(const char *);
void __ipipe_mach_demux_irq(unsigned irq, struct pt_regs *regs)
{
struct gpio_controller *__iomem g = get_irq_chip_data(irq);
struct irq_desc *desc;
u32 mask = 0xffff;
//printascii("1__ipipe_mach_demux_irq\n");
/* we only care about one bank */
if (irq & 1)
mask <<= 16;
desc = &irq_desc[irq];
/* temporarily mask (level sensitive) parent IRQ */
desc->chip->ack(irq);
while (1) {
u32 status;
int n;
int res;
/* ack any irqs */
status = __raw_readl(&g->intstat) & mask;
if (!status)
break;
__raw_writel(status, &g->intstat);
if (irq & 1)
status >>= 16;
/* now demux them to the right lowlevel handler */
n = (int)get_irq_data(irq);
while (status) {
res = ffs(status);
n += res;
__ipipe_handle_irq((n-1),regs);
status >>= res;
}
}
desc->chip->unmask(irq);
/* now it may re-trigger */
}
#endif /* CONFIG_IPIPE */
/*
* NOTE: for suspend/resume, probably best to make a platform_device with
* suspend_late/resume_resume calls hooking into results of the set_wake()
* calls ... so if no gpios are wakeup events the clock can be disabled,
* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
* (dm6446) can be set appropriately for GPIOV33 pins.
*/
static int __init davinci_gpio_irq_setup(void)
{
unsigned gpio, irq, bank;
unsigned bank_irq;
struct clk *clk;
u32 binten = 0;
if (cpu_is_davinci_dm355()) { /* or dm335() */
bank_irq = IRQ_DM355_GPIOBNK0;
} else if (cpu_is_davinci_dm644x()) {
bank_irq = IRQ_GPIOBNK0;
} else if (cpu_is_davinci_dm646x()) {
bank_irq = IRQ_DM646X_GPIOBNK0;
} else if (cpu_is_da8xx()) {
bank_irq = IRQ_DA8XX_GPIO0;
} else {
printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
return -EINVAL;
}
clk = clk_get(NULL, "gpio");
if (IS_ERR(clk)) {
printk(KERN_ERR "Error %ld getting gpio clock?\n",
PTR_ERR(clk));
return PTR_ERR(clk);
}
clk_enable(clk);
for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
gpio < ngpio;
bank++, bank_irq++) {
struct gpio_controller *__iomem g = gpio2controller(gpio);
unsigned i;
__raw_writel(~0, &g->clr_falling);
__raw_writel(~0, &g->clr_rising);
/* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler);
set_irq_chip_data(bank_irq, g);
set_irq_data(bank_irq, (void *)irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
set_irq_chip(irq, &gpio_irqchip);
set_irq_chip_data(irq, g);
set_irq_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID);
}
binten |= BIT(bank);
}
/* BINTEN -- per-bank interrupt enable. genirq would also let these
* bits be set/cleared dynamically.
*/
__raw_writel(binten, (void *__iomem)
IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
return 0;
}
arch_initcall(davinci_gpio_irq_setup);
[-- Attachment #3: irq.c --]
[-- Type: text/x-csrc, Size: 14712 bytes --]
/*
* Interrupt handler for DaVinci boards.
*
* Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <asm/io.h>
#include <asm/mach/irq.h>
#define IRQ_BIT(irq) ((irq) & 0x1f)
#define FIQ_REG0_OFFSET 0x0000
#define FIQ_REG1_OFFSET 0x0004
#define IRQ_REG0_OFFSET 0x0008
#define IRQ_REG1_OFFSET 0x000C
#define IRQ_ENT_REG0_OFFSET 0x0018
#define IRQ_ENT_REG1_OFFSET 0x001C
#define IRQ_INCTL_REG_OFFSET 0x0020
#define IRQ_EABASE_REG_OFFSET 0x0024
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
const u8 *davinci_def_priorities;
#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
static inline unsigned int davinci_irq_readl(int offset)
{
return __raw_readl(INTC_BASE + offset);
}
static inline void davinci_irq_writel(unsigned long value, int offset)
{
__raw_writel(value, INTC_BASE + offset);
}
/* Disable interrupt */
static void davinci_mask_irq(unsigned int irq)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(irq);
if (irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l &= ~mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l &= ~mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
}
/* Enable interrupt */
static void davinci_unmask_irq(unsigned int irq)
{
unsigned int mask;
u32 l;
mask = 1 << IRQ_BIT(irq);
if (irq > 31) {
l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
} else {
l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
l |= mask;
davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
}
}
/* EOI interrupt */
static void davinci_ack_irq(unsigned int irq)
{
unsigned int mask;
mask = 1 << IRQ_BIT(irq);
if (irq > 31)
davinci_irq_writel(mask, IRQ_REG1_OFFSET);
else
davinci_irq_writel(mask, IRQ_REG0_OFFSET);
}
static struct irq_chip davinci_irq_chip_0 = {
.name = "AINTC",
.ack = davinci_ack_irq,
.mask = davinci_mask_irq,
#ifdef CONFIG_IPIPE
.mask_ack = davinci_mask_irq,
#endif /* CONFIG_IPIPE */
.unmask = davinci_unmask_irq,
};
#ifdef CONFIG_IPIPE
static const u8 da850_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
[IRQ_DA8XX_COMMTX] = 7,
[IRQ_DA8XX_COMMRX] = 7,
[IRQ_DA8XX_NINT] = 7,
[IRQ_DA8XX_EVTOUT0] = 7,
[IRQ_DA8XX_EVTOUT1] = 7,
[IRQ_DA8XX_EVTOUT2] = 7,
[IRQ_DA8XX_EVTOUT3] = 7,
[IRQ_DA8XX_EVTOUT4] = 7,
[IRQ_DA8XX_EVTOUT5] = 7,
[IRQ_DA8XX_EVTOUT6] = 7,
[IRQ_DA8XX_EVTOUT7] = 7,
[IRQ_DA8XX_CCINT0] = 7,
[IRQ_DA8XX_CCERRINT] = 7,
[IRQ_DA8XX_TCERRINT0] = 7,
[IRQ_DA8XX_AEMIFINT] = 7,
[IRQ_DA8XX_I2CINT0] = 5,
[IRQ_DA8XX_MMCSDINT0] = 5,
[IRQ_DA8XX_MMCSDINT1] = 5,
[IRQ_DA8XX_ALLINT0] = 5,
[IRQ_DA8XX_RTC] = 4,
[IRQ_DA8XX_SPINT0] = 5,
[IRQ_DA8XX_TINT12_0] = 2,
[IRQ_DA8XX_TINT34_0] = 5,
[IRQ_DA8XX_TINT12_1] = 5,
[IRQ_DA8XX_TINT34_1] = 5,
[IRQ_DA8XX_UARTINT0] = 5,
[IRQ_DA8XX_KEYMGRINT] = 7,
[IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
[IRQ_DA8XX_CHIPINT0] = 7,
[IRQ_DA8XX_CHIPINT1] = 7,
[IRQ_DA8XX_CHIPINT2] = 7,
[IRQ_DA8XX_CHIPINT3] = 7,
[IRQ_DA8XX_TCERRINT1] = 7,
[IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C0_RX_PULSE] = 7,
[IRQ_DA8XX_C0_TX_PULSE] = 7,
[IRQ_DA8XX_C0_MISC_PULSE] = 7,
[IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C1_RX_PULSE] = 7,
[IRQ_DA8XX_C1_TX_PULSE] = 7,
[IRQ_DA8XX_C1_MISC_PULSE] = 7,
[IRQ_DA8XX_MEMERR] = 5,
[IRQ_DA8XX_GPIO0] = 6,
[IRQ_DA8XX_GPIO1] = 6,
[IRQ_DA8XX_GPIO2] = 6,
[IRQ_DA8XX_GPIO3] = 6,
[IRQ_DA8XX_GPIO4] = 6,
[IRQ_DA8XX_GPIO5] = 6,
[IRQ_DA8XX_GPIO6] = 6,
[IRQ_DA8XX_GPIO7] = 6,
[IRQ_DA8XX_GPIO8] = 6,
[IRQ_DA8XX_I2CINT1] = 5,
[IRQ_DA8XX_LCDINT] = 5,
[IRQ_DA8XX_UARTINT1] = 5,
[IRQ_DA8XX_MCASPINT] = 5,
[IRQ_DA8XX_ALLINT1] = 5,
[IRQ_DA8XX_SPINT1] = 5,
[IRQ_DA8XX_UHPI_INT1] = 5,
[IRQ_DA8XX_USB_INT] = 5,
[IRQ_DA8XX_IRQN] = 5,
[IRQ_DA8XX_RWAKEUP] = 5,
[IRQ_DA8XX_UARTINT2] = 5,
[IRQ_DA8XX_DFTSSINT] = 5,
[IRQ_DA8XX_EHRPWM0] = 7,
[IRQ_DA8XX_EHRPWM0TZ] = 7,
[IRQ_DA8XX_EHRPWM1] = 7,
[IRQ_DA8XX_EHRPWM1TZ] = 7,
[IRQ_DA850_SATAINT] = 5,
[IRQ_DA850_TINT12_2] = 5,
[IRQ_DA8XX_ECAP0] = 7,
[IRQ_DA8XX_ECAP1] = 7,
[IRQ_DA8XX_ECAP2] = 7,
[IRQ_DA850_MMCSDINT0_1] = 5,
[IRQ_DA850_MMCSDINT1_1] = 5,
[IRQ_DA850_T12CMPINT0_2] = 7,
[IRQ_DA850_T12CMPINT1_2] = 7,
[IRQ_DA850_T12CMPINT2_2] = 7,
[IRQ_DA850_T12CMPINT3_2] = 7,
[IRQ_DA850_T12CMPINT4_2] = 7,
[IRQ_DA850_T12CMPINT5_2] = 7,
[IRQ_DA850_T12CMPINT6_2] = 7,
[IRQ_DA850_T12CMPINT7_2] = 7,
[IRQ_DA850_T12CMPINT0_3] = 7,
[IRQ_DA850_T12CMPINT1_3] = 7,
[IRQ_DA850_T12CMPINT2_3] = 7,
[IRQ_DA850_T12CMPINT3_3] = 7,
[IRQ_DA850_T12CMPINT4_3] = 7,
[IRQ_DA850_T12CMPINT5_3] = 7,
[IRQ_DA850_T12CMPINT6_3] = 7,
[IRQ_DA850_T12CMPINT7_3] = 7,
[IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
[IRQ_DA850_RPIINT] = 7,
[IRQ_DA850_VPIFINT] = 7,
[IRQ_DA850_CCINT1] = 7,
[IRQ_DA850_CCERRINT1] = 7,
[IRQ_DA850_TCERRINT2] = 7,
[IRQ_DA850_TINT12_3] = 5,
[IRQ_DA850_MCBSP0RINT] = 5,
[IRQ_DA850_MCBSP0XINT] = 5,
[IRQ_DA850_MCBSP1RINT] = 5,
[IRQ_DA850_MCBSP1XINT] = 5
};
#endif /* CONFIG_IPIPE */
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
[IRQ_VDINT0] = 2,
[IRQ_VDINT1] = 6,
[IRQ_VDINT2] = 6,
[IRQ_HISTINT] = 6,
[IRQ_H3AINT] = 6,
[IRQ_PRVUINT] = 6,
[IRQ_RSZINT] = 6,
[7] = 7,
[IRQ_VENCINT] = 6,
[IRQ_ASQINT] = 6,
[IRQ_IMXINT] = 6,
[IRQ_VLCDINT] = 6,
[IRQ_USBINT] = 4,
[IRQ_EMACINT] = 4,
[14] = 7,
[15] = 7,
[IRQ_CCINT0] = 5, /* dma */
[IRQ_CCERRINT] = 5, /* dma */
[IRQ_TCERRINT0] = 5, /* dma */
[IRQ_TCERRINT] = 5, /* dma */
[IRQ_PSCIN] = 7,
[21] = 7,
[IRQ_IDE] = 4,
[23] = 7,
[IRQ_MBXINT] = 7,
[IRQ_MBRINT] = 7,
[IRQ_MMCINT] = 7,
[IRQ_SDIOINT] = 7,
[28] = 7,
[IRQ_DDRINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_VLQINT] = 4,
[IRQ_TINT0_TINT12] = 2, /* clockevent */
[IRQ_TINT0_TINT34] = 2, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */
[IRQ_PWMINT0] = 7,
[IRQ_PWMINT1] = 7,
[IRQ_PWMINT2] = 7,
[IRQ_I2C] = 3,
[IRQ_UARTINT0] = 3,
[IRQ_UARTINT1] = 3,
[IRQ_UARTINT2] = 3,
[IRQ_SPINT0] = 3,
[IRQ_SPINT1] = 3,
[45] = 7,
[IRQ_DSP2ARM0] = 4,
[IRQ_DSP2ARM1] = 4,
[IRQ_GPIO0] = 7,
[IRQ_GPIO1] = 7,
[IRQ_GPIO2] = 7,
[IRQ_GPIO3] = 7,
[IRQ_GPIO4] = 7,
[IRQ_GPIO5] = 7,
[IRQ_GPIO6] = 7,
[IRQ_GPIO7] = 7,
[IRQ_GPIOBNK0] = 7,
[IRQ_GPIOBNK1] = 7,
[IRQ_GPIOBNK2] = 7,
[IRQ_GPIOBNK3] = 7,
[IRQ_GPIOBNK4] = 7,
[IRQ_COMMTX] = 7,
[IRQ_COMMRX] = 7,
[IRQ_EMUINT] = 7,
};
static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_VP_VERTINT0] = 7,
[IRQ_DM646X_VP_VERTINT1] = 7,
[IRQ_DM646X_VP_VERTINT2] = 7,
[IRQ_DM646X_VP_VERTINT3] = 7,
[IRQ_DM646X_VP_ERRINT] = 7,
[IRQ_DM646X_RESERVED_1] = 7,
[IRQ_DM646X_RESERVED_2] = 7,
[IRQ_DM646X_WDINT] = 7,
[IRQ_DM646X_CRGENINT0] = 7,
[IRQ_DM646X_CRGENINT1] = 7,
[IRQ_DM646X_TSIFINT0] = 7,
[IRQ_DM646X_TSIFINT1] = 7,
[IRQ_DM646X_VDCEINT] = 7,
[IRQ_DM646X_USBINT] = 7,
[IRQ_DM646X_USBDMAINT] = 7,
[IRQ_DM646X_PCIINT] = 7,
[IRQ_CCINT0] = 7, /* dma */
[IRQ_CCERRINT] = 7, /* dma */
[IRQ_TCERRINT0] = 7, /* dma */
[IRQ_TCERRINT] = 7, /* dma */
[IRQ_DM646X_TCERRINT2] = 7,
[IRQ_DM646X_TCERRINT3] = 7,
[IRQ_DM646X_IDE] = 7,
[IRQ_DM646X_HPIINT] = 7,
[IRQ_DM646X_EMACRXTHINT] = 7,
[IRQ_DM646X_EMACRXINT] = 7,
[IRQ_DM646X_EMACTXINT] = 7,
[IRQ_DM646X_EMACMISCINT] = 7,
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */
[IRQ_PWMINT0] = 7,
[IRQ_PWMINT1] = 7,
[IRQ_DM646X_VLQINT] = 7,
[IRQ_I2C] = 7,
[IRQ_UARTINT0] = 7,
[IRQ_UARTINT1] = 7,
[IRQ_DM646X_UARTINT2] = 7,
[IRQ_DM646X_SPINT0] = 7,
[IRQ_DM646X_SPINT1] = 7,
[IRQ_DM646X_DSP2ARMINT] = 7,
[IRQ_DM646X_RESERVED_4] = 7,
[IRQ_DM646X_PSCINT] = 7,
[IRQ_DM646X_GPIO0] = 7,
[IRQ_DM646X_GPIO1] = 7,
[IRQ_DM646X_GPIO2] = 7,
[IRQ_DM646X_GPIO3] = 7,
[IRQ_DM646X_GPIO4] = 7,
[IRQ_DM646X_GPIO5] = 7,
[IRQ_DM646X_GPIO6] = 7,
[IRQ_DM646X_GPIO7] = 7,
[IRQ_DM646X_GPIOBNK0] = 7,
[IRQ_DM646X_GPIOBNK1] = 7,
[IRQ_DM646X_GPIOBNK2] = 7,
[IRQ_DM646X_DDRINT] = 7,
[IRQ_DM646X_AEMIFINT] = 7,
[IRQ_COMMTX] = 7,
[IRQ_COMMRX] = 7,
[IRQ_EMUINT] = 7,
};
static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM355_CCDC_VDINT0] = 2,
[IRQ_DM355_CCDC_VDINT1] = 6,
[IRQ_DM355_CCDC_VDINT2] = 6,
[IRQ_DM355_IPIPE_HST] = 6,
[IRQ_DM355_H3AINT] = 6,
[IRQ_DM355_IPIPE_SDR] = 6,
[IRQ_DM355_IPIPEIFINT] = 6,
[IRQ_DM355_OSDINT] = 7,
[IRQ_DM355_VENCINT] = 6,
[IRQ_ASQINT] = 6,
[IRQ_IMXINT] = 6,
[IRQ_USBINT] = 4,
[IRQ_DM355_RTOINT] = 4,
[IRQ_DM355_UARTINT2] = 7,
[IRQ_DM355_TINT6] = 7,
[IRQ_CCINT0] = 5, /* dma */
[IRQ_CCERRINT] = 5, /* dma */
[IRQ_TCERRINT0] = 5, /* dma */
[IRQ_TCERRINT] = 5, /* dma */
[IRQ_DM355_SPINT2_1] = 7,
[IRQ_DM355_TINT7] = 4,
[IRQ_DM355_SDIOINT0] = 7,
[IRQ_MBXINT] = 7,
[IRQ_MBRINT] = 7,
[IRQ_MMCINT] = 7,
[IRQ_DM355_MMCINT1] = 7,
[IRQ_DM355_PWMINT3] = 7,
[IRQ_DDRINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_DM355_SDIOINT1] = 4,
[IRQ_TINT0_TINT12] = 2, /* clockevent */
[IRQ_TINT0_TINT34] = 2, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */
[IRQ_PWMINT0] = 7,
[IRQ_PWMINT1] = 7,
[IRQ_PWMINT2] = 7,
[IRQ_I2C] = 3,
[IRQ_UARTINT0] = 3,
[IRQ_UARTINT1] = 3,
[IRQ_DM355_SPINT0_0] = 3,
[IRQ_DM355_SPINT0_1] = 3,
[IRQ_DM355_GPIO0] = 3,
[IRQ_DM355_GPIO1] = 7,
[IRQ_DM355_GPIO2] = 4,
[IRQ_DM355_GPIO3] = 4,
[IRQ_DM355_GPIO4] = 7,
[IRQ_DM355_GPIO5] = 7,
[IRQ_DM355_GPIO6] = 7,
[IRQ_DM355_GPIO7] = 7,
[IRQ_DM355_GPIO8] = 7,
[IRQ_DM355_GPIO9] = 7,
[IRQ_DM355_GPIOBNK0] = 7,
[IRQ_DM355_GPIOBNK1] = 7,
[IRQ_DM355_GPIOBNK2] = 7,
[IRQ_DM355_GPIOBNK3] = 7,
[IRQ_DM355_GPIOBNK4] = 7,
[IRQ_DM355_GPIOBNK5] = 7,
[IRQ_DM355_GPIOBNK6] = 7,
[IRQ_COMMTX] = 7,
[IRQ_COMMRX] = 7,
[IRQ_EMUINT] = 7,
};
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
unsigned i;
if (cpu_is_davinci_dm644x())
davinci_def_priorities = dm644x_default_priorities;
else if (cpu_is_davinci_dm646x())
davinci_def_priorities = dm646x_default_priorities;
else if (cpu_is_davinci_dm355())
davinci_def_priorities = dm355_default_priorities;
#ifdef CONFIG_IPIPE
else if (cpu_is_da850())
davinci_def_priorities = da850_default_priorities;
#endif /* CONFIG_IPIPE */
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
/* Disable all interrupts */
davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
/* Interrupts disabled immediately, IRQ entry reflects all */
davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
/* we don't use the hardware vector table, just its entry addresses */
davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
pri |= (*davinci_def_priorities & 0x07) << j;
davinci_irq_writel(pri, i);
}
/* set up genirq dispatch for ARM INTC */
for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
set_irq_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
#ifndef CONFIG_IPIPE
if (i != IRQ_TINT1_TINT34)
set_irq_handler(i, handle_edge_irq);
else
#endif /* CONFIG IPIPE */
set_irq_handler(i, handle_level_irq);
}
}
[-- Attachment #4: time.c --]
[-- Type: text/x-csrc, Size: 18565 bytes --]
/*
* DaVinci timer subsystem
*
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/device.h>
#include <mach/da8xx.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/errno.h>
#include <mach/io.h>
#include <mach/cpu.h>
#include "clock.h"
#ifdef CONFIG_IPIPE
#ifdef CONFIG_NO_IDLE_HZ
#error "dynamic tick timer not yet supported with IPIPE"
#endif /* CONFIG_NO_IDLE_HZ */
#endif /* CONFIG_IPIPE */
static struct clock_event_device clockevent_davinci;
static unsigned int davinci_clock_tick_rate;
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
#define DA8XX_TIMER64P0_BASE 0x01C20000
#define DA8XX_TIMER64P1_BASE 0x01C21000
enum {
T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS,
};
#define IS_TIMER1(id) (id & 0x2)
#define IS_TIMER0(id) (!IS_TIMER1(id))
#define IS_TIMER_TOP(id) ((id & 0x1))
#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
static int default_timer_irqs[NUM_TIMERS] = {
IRQ_TINT0_TINT12,
IRQ_TINT0_TINT34,
IRQ_TINT1_TINT12,
IRQ_TINT1_TINT34,
};
static int da8xx_timer_irqs[NUM_TIMERS] = {
IRQ_DA8XX_TINT12_0,
IRQ_DA8XX_TINT34_0,
IRQ_DA8XX_TINT12_1,
IRQ_DA8XX_TINT34_1
};
/* Compare registers are only available to the bottom timer 0 */
static int da830_cmp_irqs[NUM_TIMERS] = {
IRQ_DA830_T12CMPINT0_0,
};
static int tid_system;
static int tid_freerun;
#ifdef CONFIG_IPIPE
int __ipipe_mach_timerint = IRQ_DA8XX_TINT12_0;
int __ipipe_mach_timerstolen = 0;
unsigned int __ipipe_mach_ticks_per_jiffy = LATCH;
static int davinci_timer_initialized;
union tsc_reg {
#ifdef __BIG_ENDIAN
struct {
unsigned long high;
unsigned long low;
};
#else /* __LITTLE_ENDIAN */
struct {
unsigned long low;
unsigned long high;
};
#endif /* __LITTLE_ENDIAN */
unsigned long long full;
};
#endif /* CONFIG_IPIPE */
/*
* This driver configures the 2 64-bit count-up timers as 4 independent
* 32-bit count-up timers used as follows:
*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
#define TID_CLOCKEVENT T0_BOT
#define TID_CLOCKSOURCE T0_TOP
/* Timer register offsets */
#define PID12 0x0
#define TIM12 0x10
#define TIM34 0x14
#define PRD12 0x18
#define PRD34 0x1c
#define TCR 0x20
#define TGCR 0x24
#define WDTCR 0x28
#define CMP12(n) (0x60 + ((n) << 2))
#define INTCTLSTAT 0x44
/* Timer register bitfields */
#define TCR_ENAMODE_DISABLE 0x0
#define TCR_ENAMODE_ONESHOT 0x1
#define TCR_ENAMODE_PERIODIC 0x2
#define TCR_ENAMODE_MASK 0x3
#define TGCR_TIMMODE_SHIFT 2
#define TGCR_TIMMODE_64BIT_GP 0x0
#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
#define TGCR_TIMMODE_64BIT_WDOG 0x2
#define TGCR_TIMMODE_32BIT_CHAINED 0x3
#define TGCR_TIM12RS_SHIFT 0
#define TGCR_TIM34RS_SHIFT 1
#define TGCR_RESET 0x0
#define TGCR_UNRESET 0x1
#define TGCR_RESET_MASK 0x3
#define WDTCR_WDEN_SHIFT 14
#define WDTCR_WDEN_DISABLE 0x0
#define WDTCR_WDEN_ENABLE 0x1
#define WDTCR_WDKEY_SHIFT 16
#define WDTCR_WDKEY_SEQ0 0xa5c6
#define WDTCR_WDKEY_SEQ1 0xda7e
struct timer_s {
char *name;
unsigned int id;
unsigned long period;
unsigned long opts;
void __iomem *base;
unsigned long tim_off;
unsigned long prd_off;
unsigned long cmp_off;
unsigned long enamode_shift;
struct irqaction irqaction;
struct irqaction cmpaction;
};
/* values for 'opts' field of struct timer_s */
#define TIMER_OPTS_DISABLED 0x00
#define TIMER_OPTS_ONESHOT 0x01
#define TIMER_OPTS_PERIODIC 0x02
/* Flags to be set when it is necessary to clear the */
/* status register for timer interrupts */
#define TIMER12_CLEAR_PRDINT 0x02
#define TIMER12_CLEAR_EVTINT 0x04
#ifdef CONFIG_IPIPE
#ifdef CONFIG_SMP
static union tsc_reg tsc[NR_CPUS];
void __ipipe_mach_get_tscinfo(struct __ipipe_tscinfo *info)
{
info->type = IPIPE_TSC_TYPE_NONE;
}
#else /* !CONFIG_SMP */
static union tsc_reg *tsc;
void __ipipe_mach_get_tscinfo(struct __ipipe_tscinfo *info)
{
info->type = IPIPE_TSC_TYPE_FREERUNNING;
info->u.fr.counter = (unsigned *)(DAVINCI_TIMER0_BASE + TIM12);
info->u.fr.mask = 0xffffffff;
info->u.fr.tsc = &tsc->full;
}
#endif /* !CONFIG_SMP */
void __ipipe_mach_acktimer(void)
{
void __iomem *base = IO_ADDRESS(DAVINCI_TIMER0_BASE);
unsigned long status;
status = __raw_readl(base + INTCTLSTAT);
status |= (TIMER12_CLEAR_PRDINT | TIMER12_CLEAR_EVTINT);
__raw_writel(status,base+INTCTLSTAT);
}
static void ipipe_mach_update_tsc(void)
{
union tsc_reg *local_tsc;
unsigned long stamp, flags;
void __iomem *base = IO_ADDRESS(DAVINCI_TIMER0_BASE);
local_irq_save_hw(flags);
local_tsc = &tsc[ipipe_processor_id()];
stamp = __raw_readl(base + TIM12);
if (unlikely(stamp < local_tsc->low))
/* 32 bit counter wrapped, increment high word. */
local_tsc->high++;
local_tsc->low = stamp;
local_irq_restore_hw(flags);
}
notrace unsigned long long __ipipe_mach_get_tsc(void)
{
if (likely(davinci_timer_initialized)) {
union tsc_reg *local_tsc, result;
unsigned long stamp;
void __iomem *base = IO_ADDRESS(DAVINCI_TIMER0_BASE);
local_tsc = &tsc[ipipe_processor_id()];
__asm__("ldmia %1, %M0\n":
"=r"(result.full): "r"(local_tsc), "m"(*local_tsc));
barrier();
stamp = __raw_readl(base + TIM12);
if (unlikely(stamp < result.low))
result.high++;
result.low = stamp;
return result.full;
}
return 0;
}
EXPORT_SYMBOL(__ipipe_mach_get_tsc);
/*
* Reprogram the timer
*/
void __ipipe_mach_set_dec(unsigned long delay)
{
unsigned long flags;
unsigned int value;
void __iomem *base = IO_ADDRESS(DAVINCI_TIMER0_BASE);
if (delay > 20) {
local_irq_save_hw(flags);
value = __raw_readl(base + TIM12) + delay;
__raw_writel(value,base + CMP12(0));
local_irq_restore_hw(flags);
} else {
ipipe_trigger_irq(IRQ_DA8XX_TINT12_0);
}
}
EXPORT_SYMBOL(__ipipe_mach_set_dec);
unsigned long __ipipe_mach_get_dec(void)
{
unsigned long value;
void __iomem *base = IO_ADDRESS(DAVINCI_TIMER0_BASE);
value = __raw_readl(base + CMP12(0));
value -= __raw_readl(base + TIM12);
return value;
}
int __ipipe_check_tickdev(const char *devname)
{
return !strcmp(devname, clockevent_davinci.name);
}
#endif /* CONFIG_IPIPE */
static int timer32_config(struct timer_s *t)
{
u32 tcr = __raw_readl(t->base + TCR);
/* disable timer */
tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
__raw_writel(tcr, t->base + TCR);
/* reset counter to zero, set new period */
__raw_writel(0, t->base + t->tim_off);
__raw_writel(t->period, t->base + t->prd_off);
if (t->cmp_off)
__raw_writel(t->period, t->base + t->cmp_off);
/* Set enable mode */
if (t->opts & TIMER_OPTS_ONESHOT) {
tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
} else if (t->opts & TIMER_OPTS_PERIODIC) {
tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
}
__raw_writel(tcr, t->base + TCR);
return 0;
}
static inline u32 timer32_read(struct timer_s *t)
{
return __raw_readl(t->base + t->tim_off);
}
/* Flavio Alves: for debugging */
extern void printascii(const char *);
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_davinci;
// printascii("entrei\n");
#ifdef CONFIG_IPIPE
ipipe_mach_update_tsc();
#endif /* CONFIG_IPIPE */
evt->event_handler(evt);
return IRQ_HANDLED;
}
/* called when 32-bit counter wraps */
static irqreturn_t freerun_interrupt(int irq, void *dev_id)
{
return IRQ_HANDLED;
}
static irqreturn_t cmp_interrupt(int irq, void *dev_id)
{
struct timer_s *t = dev_id;
struct clock_event_device *evt = &clockevent_davinci;
/* We have to emulate the periodic mode for the clockevents layer */
if (t->opts & TIMER_OPTS_PERIODIC) {
unsigned long tim, cmp = __raw_readl(t->base + t->cmp_off);
cmp += t->period;
__raw_writel(cmp, t->base + t->cmp_off);
/*
* The interrupts do happen to be disabled by the kernel for
* a long periods of time, thus the timer can go far ahead of
* the last set compare value...
*/
tim = __raw_readl(t->base + t->tim_off);
if (time_after(tim, cmp))
__raw_writel(tim + t->period, t->base + t->cmp_off);
}
clockevent_davinci.event_handler(evt);
return IRQ_HANDLED;
}
static struct timer_s davinci_system_timer = {
.name = "clockevent",
.opts = TIMER_OPTS_DISABLED,
.irqaction = {
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = timer_interrupt,
}
};
static struct timer_s davinci_freerun_timer = {
.name = "free-run counter",
.period = ~0,
.opts = TIMER_OPTS_PERIODIC,
.irqaction = {
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = freerun_interrupt,
},
.cmpaction = {
.name = "timer compare reg 0",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = cmp_interrupt,
}
};
static struct timer_s *timers[NUM_TIMERS];
static void __init timer_init(int num_timers, u32 *phys_bases,
int *timer_irqs, int *cmp_irqs)
{
int i;
/* Global init of each 64-bit timer as a whole */
for(i=0; i<num_timers; i++) {
u32 tgcr;
void __iomem *base = IO_ADDRESS(phys_bases[i]);
/* Disabled, Internal clock source */
__raw_writel(0, base + TCR);
/* reset both timers, no pre-scaler for timer34 */
tgcr = 0;
__raw_writel(tgcr, base + TGCR);
/* Set both timers to unchained 32-bit */
tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
__raw_writel(tgcr, base + TGCR);
/* Unreset timers */
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
__raw_writel(tgcr, base + TGCR);
/* Init both counters to zero */
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
}
/* Init of each timer as a 32-bit timer */
for (i=0; i< NUM_TIMERS; i++) {
struct timer_s *t = timers[i];
u32 phys_base;
if (t && t->name) {
t->id = i;
phys_base = phys_bases[i >> 1];
t->base = IO_ADDRESS(phys_base);
if (IS_TIMER_BOT(t->id)) {
t->enamode_shift = 6;
t->tim_off = TIM12;
t->prd_off = PRD12;
/* Check the compare register IRQ */
if (t->cmpaction.handler != NULL &&
cmp_irqs != NULL && cmp_irqs[t->id]) {
t->cmp_off = CMP12(0);
t->cmpaction.dev_id = (void *)t;
setup_irq(cmp_irqs[t->id],
&t->cmpaction);
}
} else {
t->enamode_shift = 22;
t->tim_off = TIM34;
t->prd_off = PRD34;
}
/* Register interrupt */
t->irqaction.name = t->name;
t->irqaction.dev_id = (void *)t;
if (t->irqaction.handler != NULL) {
setup_irq(timer_irqs[t->id], &t->irqaction);
}
timer32_config(timers[i]);
}
}
#ifdef CONFIG_IPIPE
#ifndef CONFIG_SMP
tsc = (union tsc_reg *)__ipipe_tsc_area;
barrier();
#endif /* CONFIG_SMP */
davinci_timer_initialized = 1;
#endif /* CONFIG_IPIPE */
}
/*
* clocksource
*/
static cycle_t read_cycles(void)
{
struct timer_s *t;
if (tid_freerun == -1) {
t = timers[tid_system];
}
else {
t = timers[tid_freerun];
}
return (cycles_t)timer32_read(t);
}
static struct clocksource clocksource_davinci = {
.name = "timer0_1",
.rating = 300,
.read = read_cycles,
.mask = CLOCKSOURCE_MASK(32),
.shift = 24,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/*
* clockevent
*/
static int davinci_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct timer_s *t = timers[tid_system];
t->period = cycles;
/*
* We need not (and must not) disable the timer and reprogram
* its mode/period when using the compare register...
*/
if (t->cmp_off)
__raw_writel(__raw_readl(t->base + t->tim_off) + cycles,
t->base + t->cmp_off);
else
timer32_config(t);
return 0;
}
static void davinci_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
struct timer_s *t = timers[tid_system];
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
t->period = davinci_clock_tick_rate / (HZ);
t->opts = TIMER_OPTS_PERIODIC;
if (t->cmp_off)
davinci_set_next_event(davinci_clock_tick_rate / HZ,
evt);
else
timer32_config(t);
break;
case CLOCK_EVT_MODE_ONESHOT:
t->opts = TIMER_OPTS_ONESHOT;
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
t->opts = TIMER_OPTS_DISABLED;
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device clockevent_davinci = {
.name = "timer0_0",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_next_event = davinci_set_next_event,
.set_mode = davinci_set_mode,
};
static u32 davinci_bases[] = { DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE };
static u32 da8xx_bases[] = { DA8XX_TIMER64P0_BASE, DA8XX_TIMER64P1_BASE };
static void __init davinci_timer_init(void)
{
int num_timers;
int *timer_irqs = NULL, *cmp_irqs = NULL;
u32 *bases;
struct clk *timer_clk;
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
timer_clk = clk_get(NULL, "timer0");
BUG_ON(IS_ERR(timer_clk));
clk_enable(timer_clk);
num_timers = 2;
bases = davinci_bases;
timer_irqs = default_timer_irqs;
/*
* DA850 does not support compare IRQs for bottom two timers.
* It has 4 timers, so assume using compare registers is not
* really a necessity.
*/
if (cpu_is_da830())
cmp_irqs = da830_cmp_irqs;
if (cpu_is_da8xx()) {
/*
* Configure the 2 64-bit timer as 4 32-bit timers with
* following assignments.
*
* T0_BOT: Timer 0, bottom: free run counter and system clock.
* T0_TOP: Timer 0, top: Reserve for DSP
* T1_BOT: Timer 1, watch dog timer.
*/
tid_system = T0_BOT;
bases = da8xx_bases;
timer_irqs = da8xx_timer_irqs;
/* timer interrupt using compare reg so free-run not needed */
if (cmp_irqs != NULL)
tid_freerun = T0_BOT;
else
tid_freerun = T0_TOP;
} else if (cpu_is_davinci_dm646x()) {
/*
* Configure the 2 64-bit timer as 4 32-bit timers with
* following assignments.
*
* T0_BOT: Timer 0, bottom: AV Sync
* T0_TOP: Timer 0, top: free-running counter,
* used for cycle counter
* T1_BOT: Timer 1, bottom: reserved for DSP
* T1_TOP: Timer 1, top : Linux system tick
*/
tid_system = T1_TOP;
tid_freerun = T0_TOP;
} else if (cpu_is_davinci_dm644x()) {
/*
* Configure the 2 64-bit timer as 4 32-bit timers with
* following assignments.
*
* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
* T0_TOP: Timer 0, top : clocksource for generic timekeeping
* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
* T1_TOP: Timer 1, top : <unused>
*/
tid_system = T0_BOT;
tid_freerun = T0_TOP;
}
if (tid_system != -1)
timers[tid_system] = &davinci_system_timer;
if (tid_freerun != -1)
timers[tid_freerun] = &davinci_freerun_timer;
/* init timer hw */
timer_init(num_timers, bases, timer_irqs, cmp_irqs);
davinci_clock_tick_rate = clk_get_rate(timer_clk);
clk_put(timer_clk);
/* setup clocksource */
clocksource_davinci.mult =
clocksource_khz2mult(davinci_clock_tick_rate/1000,
clocksource_davinci.shift);
if (clocksource_register(&clocksource_davinci))
printk(err, clocksource_davinci.name);
/* setup clockevent */
clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
clockevent_davinci.shift);
clockevent_davinci.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
clockevent_davinci.min_delta_ns =
clockevent_delta2ns(1, &clockevent_davinci);
clockevent_davinci.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_davinci);
}
struct sys_timer davinci_timer = {
.init = davinci_timer_init,
};
/* reset board using watchdog timer */
void davinci_watchdog_reset(void) {
u32 tgcr, wdtcr;
void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
struct device dev;
struct clk *wd_clk;
dev_set_name(&dev, "watchdog");
wd_clk = clk_get(&dev, NULL);
if (WARN_ON(IS_ERR(wd_clk)))
return;
clk_enable(wd_clk);
if (cpu_is_da8xx())
base = IO_ADDRESS(DA8XX_TIMER64P1_BASE);
/* disable, internal clock source */
__raw_writel(0, base + TCR);
/* reset timer, set mode to 64-bit watchdog, and unreset */
tgcr = 0;
__raw_writel(tgcr, base + TGCR);
tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
__raw_writel(tgcr, base + TGCR);
/* clear counter and period regs */
__raw_writel(0, base + TIM12);
__raw_writel(0, base + TIM34);
__raw_writel(0, base + PRD12);
__raw_writel(0, base + PRD34);
/* enable */
wdtcr = __raw_readl(base + WDTCR);
wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
__raw_writel(wdtcr, base + WDTCR);
/* put watchdog in pre-active state */
wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
__raw_writel(wdtcr, base + WDTCR);
/* put watchdog in active state */
wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
__raw_writel(wdtcr, base + WDTCR);
/* write an invalid value to the WDKEY field to trigger
* a watchdog reset */
wdtcr = 0x00004000;
__raw_writel(wdtcr, base + WDTCR);
}
#ifdef CONFIG_IPIPE
void __ipipe_mach_release_timer(void)
{
davinci_set_mode(clockevent_davinci.mode, &clockevent_davinci);
if (clockevent_davinci.mode == CLOCK_EVT_MODE_ONESHOT)
davinci_set_next_event(LATCH, &clockevent_davinci);
}
EXPORT_SYMBOL(__ipipe_mach_release_timer);
#endif /* CONFIG_IPIPE */
[-- Attachment #5: irqs.h --]
[-- Type: text/x-chdr, Size: 13101 bytes --]
/*
* DaVinci interrupt controller definitions
*
* Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
/* Base address */
#define DAVINCI_ARM_INTC_BASE 0x01C48000
/* Interrupt lines */
#define IRQ_VDINT0 0
#define IRQ_VDINT1 1
#define IRQ_VDINT2 2
#define IRQ_HISTINT 3
#define IRQ_H3AINT 4
#define IRQ_PRVUINT 5
#define IRQ_RSZINT 6
#define IRQ_VFOCINT 7
#define IRQ_VENCINT 8
#define IRQ_ASQINT 9
#define IRQ_IMXINT 10
#define IRQ_VLCDINT 11
#define IRQ_USBINT 12
#define IRQ_EMACINT 13
#define IRQ_CCINT0 16
#define IRQ_CCERRINT 17
#define IRQ_TCERRINT0 18
#define IRQ_TCERRINT 19
#define IRQ_PSCIN 20
#define IRQ_IDE 22
#define IRQ_HPIINT 23
#define IRQ_MBXINT 24
#define IRQ_MBRINT 25
#define IRQ_MMCINT 26
#define IRQ_SDIOINT 27
#define IRQ_MSINT 28
#define IRQ_DDRINT 29
#define IRQ_AEMIFINT 30
#define IRQ_VLQINT 31
#define IRQ_TINT0_TINT12 32
#define IRQ_TINT0_TINT34 33
#define IRQ_TINT1_TINT12 34
#define IRQ_TINT1_TINT34 35
#define IRQ_PWMINT0 36
#define IRQ_PWMINT1 37
#define IRQ_PWMINT2 38
#define IRQ_I2C 39
#define IRQ_UARTINT0 40
#define IRQ_UARTINT1 41
#define IRQ_UARTINT2 42
#define IRQ_SPINT0 43
#define IRQ_SPINT1 44
#define IRQ_DSP2ARM0 46
#define IRQ_DSP2ARM1 47
#define IRQ_GPIO0 48
#define IRQ_GPIO1 49
#define IRQ_GPIO2 50
#define IRQ_GPIO3 51
#define IRQ_GPIO4 52
#define IRQ_GPIO5 53
#define IRQ_GPIO6 54
#define IRQ_GPIO7 55
#define IRQ_GPIOBNK0 56
#define IRQ_GPIOBNK1 57
#define IRQ_GPIOBNK2 58
#define IRQ_GPIOBNK3 59
#define IRQ_GPIOBNK4 60
#define IRQ_COMMTX 61
#define IRQ_COMMRX 62
#define IRQ_EMUINT 63
/* da850 currently has the most irqs (101) */
#define DAVINCI_N_AINTC_IRQ 101
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
/* DaVinci DM6467-specific Interrupts */
#define IRQ_DM646X_VP_VERTINT0 0
#define IRQ_DM646X_VP_VERTINT1 1
#define IRQ_DM646X_VP_VERTINT2 2
#define IRQ_DM646X_VP_VERTINT3 3
#define IRQ_DM646X_VP_ERRINT 4
#define IRQ_DM646X_RESERVED_1 5
#define IRQ_DM646X_RESERVED_2 6
#define IRQ_DM646X_WDINT 7
#define IRQ_DM646X_CRGENINT0 8
#define IRQ_DM646X_CRGENINT1 9
#define IRQ_DM646X_TSIFINT0 10
#define IRQ_DM646X_TSIFINT1 11
#define IRQ_DM646X_VDCEINT 12
#define IRQ_DM646X_USBINT 13
#define IRQ_DM646X_USBDMAINT 14
#define IRQ_DM646X_PCIINT 15
#define IRQ_DM646X_TCERRINT2 20
#define IRQ_DM646X_TCERRINT3 21
#define IRQ_DM646X_IDE 22
#define IRQ_DM646X_HPIINT 23
#define IRQ_DM646X_EMACRXTHINT 24
#define IRQ_DM646X_EMACRXINT 25
#define IRQ_DM646X_EMACTXINT 26
#define IRQ_DM646X_EMACMISCINT 27
#define IRQ_DM646X_MCASP0TXINT 28
#define IRQ_DM646X_MCASP0RXINT 29
#define IRQ_DM646X_RESERVED_3 31
#define IRQ_DM646X_MCASP1TXINT 32
#define IRQ_DM646X_VLQINT 38
#define IRQ_DM646X_UARTINT2 42
#define IRQ_DM646X_SPINT0 43
#define IRQ_DM646X_SPINT1 44
#define IRQ_DM646X_DSP2ARMINT 45
#define IRQ_DM646X_RESERVED_4 46
#define IRQ_DM646X_PSCINT 47
#define IRQ_DM646X_GPIO0 48
#define IRQ_DM646X_GPIO1 49
#define IRQ_DM646X_GPIO2 50
#define IRQ_DM646X_GPIO3 51
#define IRQ_DM646X_GPIO4 52
#define IRQ_DM646X_GPIO5 53
#define IRQ_DM646X_GPIO6 54
#define IRQ_DM646X_GPIO7 55
#define IRQ_DM646X_GPIOBNK0 56
#define IRQ_DM646X_GPIOBNK1 57
#define IRQ_DM646X_GPIOBNK2 58
#define IRQ_DM646X_DDRINT 59
#define IRQ_DM646X_AEMIFINT 60
/* DaVinci DM355-specific Interrupts */
#define IRQ_DM355_CCDC_VDINT0 0
#define IRQ_DM355_CCDC_VDINT1 1
#define IRQ_DM355_CCDC_VDINT2 2
#define IRQ_DM355_IPIPE_HST 3
#define IRQ_DM355_H3AINT 4
#define IRQ_DM355_IPIPE_SDR 5
#define IRQ_DM355_IPIPEIFINT 6
#define IRQ_DM355_OSDINT 7
#define IRQ_DM355_VENCINT 8
#define IRQ_DM355_IMCOPINT 11
#define IRQ_DM355_RTOINT 13
#define IRQ_DM355_TINT4 13
#define IRQ_DM355_TINT2_TINT12 13
#define IRQ_DM355_UARTINT2 14
#define IRQ_DM355_TINT5 14
#define IRQ_DM355_TINT2_TINT34 14
#define IRQ_DM355_TINT6 15
#define IRQ_DM355_TINT3_TINT12 15
#define IRQ_DM355_SPINT1_0 17
#define IRQ_DM355_SPINT1_1 18
#define IRQ_DM355_SPINT2_0 19
#define IRQ_DM355_SPINT2_1 21
#define IRQ_DM355_TINT7 22
#define IRQ_DM355_TINT3_TINT34 22
#define IRQ_DM355_SDIOINT0 23
#define IRQ_DM355_MMCINT0 26
#define IRQ_DM355_MSINT 26
#define IRQ_DM355_MMCINT1 27
#define IRQ_DM355_PWMINT3 28
#define IRQ_DM355_SDIOINT1 31
#define IRQ_DM355_SPINT0_0 42
#define IRQ_DM355_SPINT0_1 43
#define IRQ_DM355_GPIO0 44
#define IRQ_DM355_GPIO1 45
#define IRQ_DM355_GPIO2 46
#define IRQ_DM355_GPIO3 47
#define IRQ_DM355_GPIO4 48
#define IRQ_DM355_GPIO5 49
#define IRQ_DM355_GPIO6 50
#define IRQ_DM355_GPIO7 51
#define IRQ_DM355_GPIO8 52
#define IRQ_DM355_GPIO9 53
#define IRQ_DM355_GPIOBNK0 54
#define IRQ_DM355_GPIOBNK1 55
#define IRQ_DM355_GPIOBNK2 56
#define IRQ_DM355_GPIOBNK3 57
#define IRQ_DM355_GPIOBNK4 58
#define IRQ_DM355_GPIOBNK5 59
#define IRQ_DM355_GPIOBNK6 60
/* Interrupts common to DA830 and DA850*/
#define IRQ_DA8XX_COMMTX 0
#define IRQ_DA8XX_COMMRX 1
#define IRQ_DA8XX_NINT 2
#define IRQ_DA8XX_EVTOUT0 3
#define IRQ_DA8XX_EVTOUT1 4
#define IRQ_DA8XX_EVTOUT2 5
#define IRQ_DA8XX_EVTOUT3 6
#define IRQ_DA8XX_EVTOUT4 7
#define IRQ_DA8XX_EVTOUT5 8
#define IRQ_DA8XX_EVTOUT6 9
#define IRQ_DA8XX_EVTOUT7 10
#define IRQ_DA8XX_CCINT0 11
#define IRQ_DA8XX_CCERRINT 12
#define IRQ_DA8XX_TCERRINT0 13
#define IRQ_DA8XX_AEMIFINT 14
#define IRQ_DA8XX_I2CINT0 15
#define IRQ_DA8XX_MMCSDINT0 16
#define IRQ_DA8XX_MMCSDINT1 17
#define IRQ_DA8XX_ALLINT0 18
#define IRQ_DA8XX_RTC 19
#define IRQ_DA8XX_SPINT0 20
#define IRQ_DA8XX_TINT12_0 21
#define IRQ_DA8XX_TINT34_0 22
#define IRQ_DA8XX_TINT12_1 23
#define IRQ_DA8XX_TINT34_1 24
#define IRQ_DA8XX_UARTINT0 25
#define IRQ_DA8XX_KEYMGRINT 26
#define IRQ_DA8XX_SECINT 26
#define IRQ_DA8XX_SECKEYERR 26
#define IRQ_DA8XX_CHIPINT0 28
#define IRQ_DA8XX_CHIPINT1 29
#define IRQ_DA8XX_CHIPINT2 30
#define IRQ_DA8XX_CHIPINT3 31
#define IRQ_DA8XX_TCERRINT1 32
#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33
#define IRQ_DA8XX_C0_RX_PULSE 34
#define IRQ_DA8XX_C0_TX_PULSE 35
#define IRQ_DA8XX_C0_MISC_PULSE 36
#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37
#define IRQ_DA8XX_C1_RX_PULSE 38
#define IRQ_DA8XX_C1_TX_PULSE 39
#define IRQ_DA8XX_C1_MISC_PULSE 40
#define IRQ_DA8XX_MEMERR 41
#define IRQ_DA8XX_GPIO0 42
#define IRQ_DA8XX_GPIO1 43
#define IRQ_DA8XX_GPIO2 44
#define IRQ_DA8XX_GPIO3 45
#define IRQ_DA8XX_GPIO4 46
#define IRQ_DA8XX_GPIO5 47
#define IRQ_DA8XX_GPIO6 48
#define IRQ_DA8XX_GPIO7 49
#define IRQ_DA8XX_GPIO8 50
#define IRQ_DA8XX_I2CINT1 51
#define IRQ_DA8XX_LCDINT 52
#define IRQ_DA8XX_UARTINT1 53
#define IRQ_DA8XX_MCASPINT 54
#define IRQ_DA8XX_ALLINT1 55
#define IRQ_DA8XX_SPINT1 56
#define IRQ_DA8XX_UHPI_INT1 57
#define IRQ_DA8XX_USB_INT 58
#define IRQ_DA8XX_IRQN 59
#define IRQ_DA8XX_RWAKEUP 60
#define IRQ_DA8XX_UARTINT2 61
#define IRQ_DA8XX_DFTSSINT 62
#define IRQ_DA8XX_EHRPWM0 63
#define IRQ_DA8XX_EHRPWM0TZ 64
#define IRQ_DA8XX_EHRPWM1 65
#define IRQ_DA8XX_EHRPWM1TZ 66
#define IRQ_DA8XX_ECAP0 69
#define IRQ_DA8XX_ECAP1 70
#define IRQ_DA8XX_ECAP2 71
#define IRQ_DA8XX_ARMCLKSTOPREQ 90
/* DA830 specific interrupts */
#define IRQ_DA830_MPUERR 27
#define IRQ_DA830_IOPUERR 27
#define IRQ_DA830_BOOTCFGERR 27
#define IRQ_DA830_EHRPWM2 67
#define IRQ_DA830_EHRPWM2TZ 68
#define IRQ_DA830_EQEP0 72
#define IRQ_DA830_EQEP1 73
#define IRQ_DA830_T12CMPINT0_0 74
#define IRQ_DA830_T12CMPINT1_0 75
#define IRQ_DA830_T12CMPINT2_0 76
#define IRQ_DA830_T12CMPINT3_0 77
#define IRQ_DA830_T12CMPINT4_0 78
#define IRQ_DA830_T12CMPINT5_0 79
#define IRQ_DA830_T12CMPINT6_0 80
#define IRQ_DA830_T12CMPINT7_0 81
#define IRQ_DA830_T12CMPINT0_1 82
#define IRQ_DA830_T12CMPINT1_1 83
#define IRQ_DA830_T12CMPINT2_1 84
#define IRQ_DA830_T12CMPINT3_1 85
#define IRQ_DA830_T12CMPINT4_1 86
#define IRQ_DA830_T12CMPINT5_1 87
#define IRQ_DA830_T12CMPINT6_1 88
#define IRQ_DA830_T12CMPINT7_1 89
/* DA850 speicific interrupts */
#define IRQ_DA850_MPUADDRERR0 27
#define IRQ_DA850_MPUPROTERR0 27
#define IRQ_DA850_IOPUADDRERR0 27
#define IRQ_DA850_IOPUPROTERR0 27
#define IRQ_DA850_IOPUADDRERR1 27
#define IRQ_DA850_IOPUPROTERR1 27
#define IRQ_DA850_IOPUADDRERR2 27
#define IRQ_DA850_IOPUPROTERR2 27
#define IRQ_DA850_BOOTCFG_ADDR_ERR 27
#define IRQ_DA850_BOOTCFG_PROT_ERR 27
#define IRQ_DA850_MPUADDRERR1 27
#define IRQ_DA850_MPUPROTERR1 27
#define IRQ_DA850_IOPUADDRERR3 27
#define IRQ_DA850_IOPUPROTERR3 27
#define IRQ_DA850_IOPUADDRERR4 27
#define IRQ_DA850_IOPUPROTERR4 27
#define IRQ_DA850_IOPUADDRERR5 27
#define IRQ_DA850_IOPUPROTERR5 27
#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27
#define IRQ_DA850_SATAINT 67
#define IRQ_DA850_TINT12_2 68
#define IRQ_DA850_TINT34_2 68
#define IRQ_DA850_TINTALL_2 68
#define IRQ_DA850_MMCSDINT0_1 72
#define IRQ_DA850_MMCSDINT1_1 73
#define IRQ_DA850_T12CMPINT0_2 74
#define IRQ_DA850_T12CMPINT1_2 75
#define IRQ_DA850_T12CMPINT2_2 76
#define IRQ_DA850_T12CMPINT3_2 77
#define IRQ_DA850_T12CMPINT4_2 78
#define IRQ_DA850_T12CMPINT5_2 79
#define IRQ_DA850_T12CMPINT6_2 80
#define IRQ_DA850_T12CMPINT7_2 81
#define IRQ_DA850_T12CMPINT0_3 82
#define IRQ_DA850_T12CMPINT1_3 83
#define IRQ_DA850_T12CMPINT2_3 84
#define IRQ_DA850_T12CMPINT3_3 85
#define IRQ_DA850_T12CMPINT4_3 86
#define IRQ_DA850_T12CMPINT5_3 87
#define IRQ_DA850_T12CMPINT6_3 88
#define IRQ_DA850_T12CMPINT7_3 89
#define IRQ_DA850_RPIINT 91
#define IRQ_DA850_VPIFINT 92
#define IRQ_DA850_CCINT1 93
#define IRQ_DA850_CCERRINT1 94
#define IRQ_DA850_TCERRINT2 95
#define IRQ_DA850_TINT12_3 96
#define IRQ_DA850_TINT34_3 96
#define IRQ_DA850_TINTALL_3 96
#define IRQ_DA850_MCBSP0RINT 97
#define IRQ_DA850_MCBSP0XINT 98
#define IRQ_DA850_MCBSP1RINT 99
#define IRQ_DA850_MCBSP1XINT 100
#ifdef CONFIG_IPIPE
#if 0
#define __ipipe_mach_irq_mux_p(irq) \
((unsigned) (irq - IRQ_DA8XX_GPIO0) \
<= (IRQ_DA8XX_GPIO7 - IRQ_DA8XX_GPIO0))
#endif
#define __ipipe_mach_irq_mux_p(irq) \
((irq) == IRQ_DA8XX_GPIO0 \
|| (irq) == IRQ_DA8XX_GPIO1 \
|| (irq) == IRQ_DA8XX_GPIO2 \
|| (irq) == IRQ_DA8XX_GPIO3 \
|| (irq) == IRQ_DA8XX_GPIO4 \
|| (irq) == IRQ_DA8XX_GPIO5 \
|| (irq) == IRQ_DA8XX_GPIO6 \
|| (irq) == IRQ_DA8XX_GPIO7)
#endif /* CONFIG_IPIPE */
#endif /* __ASM_ARCH_IRQS_H */
next prev parent reply other threads:[~2010-01-08 19:42 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-03 15:00 [Xenomai-help] Porting I-Pipe for new ARM board Wael Showair
2009-11-03 15:13 ` Gilles Chanteperdrix
2009-11-03 15:45 ` Didenko Sergey
2009-11-03 15:48 ` Gilles Chanteperdrix
2009-11-04 6:58 ` Wael Showair
2009-11-04 10:54 ` Gilles Chanteperdrix
2009-11-06 9:08 ` Wael Showair
2009-11-06 9:39 ` Sergey Didenko
2009-11-06 10:22 ` Gilles Chanteperdrix
2009-12-15 19:37 ` Олександр Лаврущенко
2009-12-15 20:34 ` Gilles Chanteperdrix
[not found] ` <20091215213210.19d5b6a5@domain.hid>
2009-12-16 1:15 ` Sergey Didenko
2009-12-31 12:52 ` Flavio de Castro Alves Filho
2009-12-31 15:41 ` Gilles Chanteperdrix
2010-01-04 22:14 ` Flavio Alves
2010-01-04 22:22 ` Gilles Chanteperdrix
2010-01-06 10:56 ` Flavio Alves
2010-01-06 11:01 ` Gilles Chanteperdrix
2010-01-06 11:38 ` Flavio de Castro Alves Filho
2010-01-06 14:01 ` Gilles Chanteperdrix
2010-01-06 19:16 ` Flavio de Castro Alves Filho
2010-01-06 19:23 ` Gilles Chanteperdrix
2010-01-08 14:11 ` Flavio de Castro Alves Filho
2010-01-08 14:35 ` Gilles Chanteperdrix
2010-01-08 14:58 ` Flavio de Castro Alves Filho
2010-01-08 15:36 ` Gilles Chanteperdrix
2010-01-08 17:43 ` Flavio de Castro Alves Filho
2010-01-08 18:02 ` Flavio de Castro Alves Filho
2010-01-08 18:08 ` Gilles Chanteperdrix
2010-01-08 19:27 ` Flavio de Castro Alves Filho
2010-01-08 19:31 ` Gilles Chanteperdrix
2010-01-08 19:42 ` Flavio de Castro Alves Filho [this message]
2010-01-08 19:45 ` Gilles Chanteperdrix
2010-01-08 21:54 ` Flavio de Castro Alves Filho
2010-01-08 22:26 ` Gilles Chanteperdrix
2010-01-13 8:50 ` Flavio de Castro Alves Filho
2010-01-13 10:05 ` Gilles Chanteperdrix
2010-01-08 19:32 ` Gilles Chanteperdrix
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