* [U-Boot] [PATCH 00/13] add support for rk3066 platform.
@ 2017-06-06 18:48 Paweł Jarosz
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
` (12 more replies)
0 siblings, 13 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:48 UTC (permalink / raw)
To: u-boot
This patch serie adds support for Rockchip RK3066 processor.
Paweł Jarosz (13):
rockchip: rk3066: add grf header file
rockchip: rk3066: add rk3066 pinctrl driver
rockchip: rk3066: add sysreset driver
rockchip: rk3066: add clock driver for rk3066 soc
rockchip: rk3066: add rk3066 platform devicetree file
rockchip: rk3066: add core support
rockchip: rk3066: add mk808 board files
rockchip: mmc: support rk3066 mmc
rockchip: dts: set fifo mode as default for mmc
rockchip: rk3066: add sdram driver
rockchip: serial: support rockchip rk3066
armv7: support rk3066 early back to bootrom in start.S
rockchip: rk3066: add sdram init code for tpl
arch/arm/cpu/armv7/start.S | 13 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3066a-mk808.dts | 172 ++++
arch/arm/dts/rk3066a.dtsi | 699 +++++++++++++++++
arch/arm/dts/rk3xxx.dtsi | 3 +
arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 +++++
arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 +++++++++++++++
arch/arm/mach-rockchip/Kconfig | 16 +
arch/arm/mach-rockchip/Makefile | 4 +
arch/arm/mach-rockchip/rk3066-board-spl.c | 173 ++++
arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 ++
arch/arm/mach-rockchip/rk3066-board.c | 180 +++++
arch/arm/mach-rockchip/rk3066/Kconfig | 34 +
arch/arm/mach-rockchip/rk3066/Makefile | 13 +
arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +
arch/arm/mach-rockchip/rk3066/sdram_init.c | 995 ++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++
board/rikomagic/mk808_rk3066/Kconfig | 15 +
board/rikomagic/mk808_rk3066/MAINTAINERS | 6 +
board/rikomagic/mk808_rk3066/Makefile | 7 +
board/rikomagic/mk808_rk3066/mk808_rk3066.c | 10 +
configs/mk808-rk3066_defconfig | 54 ++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3066.c | 586 ++++++++++++++
drivers/mmc/rockchip_dw_mmc.c | 31 +-
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3066.c | 342 ++++++++
drivers/serial/serial_rockchip.c | 19 +-
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3066.c | 62 ++
include/configs/mk808_rk3066.h | 15 +
include/configs/rk3066_common.h | 125 +++
35 files changed, 4643 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/rk3066a-mk808.dts
create mode 100644 arch/arm/dts/rk3066a.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
create mode 100644 board/rikomagic/mk808_rk3066/Makefile
create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
create mode 100644 configs/mk808-rk3066_defconfig
create mode 100644 drivers/clk/rockchip/clk_rk3066.c
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c
create mode 100644 drivers/sysreset/sysreset_rk3066.c
create mode 100644 include/configs/mk808_rk3066.h
create mode 100644 include/configs/rk3066_common.h
--
2.7.4
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
@ 2017-06-06 18:48 ` Paweł Jarosz
2017-06-06 21:09 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,01/13] " Philipp Tomsich
2017-06-06 18:49 ` [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver Paweł Jarosz
` (11 subsequent siblings)
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:48 UTC (permalink / raw)
To: u-boot
grf is needed by various drivers for rk3066 soc.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++
1 file changed, 621 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
new file mode 100644
index 0000000..96b4ca6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3066_H
+#define _ASM_ARCH_GRF_RK3066_H
+
+struct rk3066_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3066_grf {
+ struct rk3066_grf_gpio_lh gpio_dir[7];
+ struct rk3066_grf_gpio_lh gpio_do[7];
+ struct rk3066_grf_gpio_lh gpio_en[7];
+
+ u32 gpio0a_iomux;
+ u32 gpio0b_iomux;
+ u32 gpio0c_iomux;
+ u32 gpio0d_iomux;
+
+ u32 gpio1a_iomux;
+ u32 gpio1b_iomux;
+ u32 gpio1c_iomux;
+ u32 gpio1d_iomux;
+
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+ u32 gpio2c_iomux;
+ u32 gpio2d_iomux;
+
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+ u32 gpio3c_iomux;
+ u32 gpio3d_iomux;
+
+ u32 gpio4a_iomux;
+ u32 gpio4b_iomux;
+ u32 gpio4c_iomux;
+ u32 gpio4d_iomux;
+
+ u32 reserved0[5];
+
+ u32 gpio6b_iomux;
+
+ u32 reserved1[2];
+
+ struct rk3066_grf_gpio_lh gpio_pull[7];
+
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+
+ u32 soc_status0;
+
+ u32 dmac1_con[3];
+ u32 dmac2_con[4];
+
+ u32 uoc0_con[3];
+ u32 uoc1_con[4];
+ u32 ddrc_con;
+ u32 ddrc_stat;
+
+ u32 reserved2[10];
+
+ u32 os_reg[4];
+};
+check_member(rk3066_grf, os_reg[3], 0x01d4);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 1,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_HOST_DRV_VBUS,
+
+ GPIO0A5_SHIFT = 10,
+ GPIO0A5_MASK = 1,
+ GPIO0A5_GPIO = 0,
+ GPIO0A5_OTG_DRV_VBUS,
+
+ GPIO0A4_SHIFT = 8,
+ GPIO0A4_MASK = 1,
+ GPIO0A4_GPIO = 0,
+ GPIO0A4_PWM1,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 1,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_PWM0
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D7_SHIFT = 14,
+ GPIO0D7_MASK = 1,
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_PWM3,
+
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 1,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_PWM2
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 3,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_UART1_RTS_N,
+ GPIO1A7_SPI0_TXD,
+
+ GPIO1A6_SHIFT = 12,
+ GPIO1A6_MASK = 3,
+ GPIO1A6_GPIO = 0,
+ GPIO1A6_UART1_CTS_N,
+ GPIO1A6_SPI0_RXD,
+
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 3,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_UART1_SOUT,
+ GPIO1A5_SPI0_CLK,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 3,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_UART1_SIN,
+ GPIO1A4_SPI0_CSN0,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_UART0_RTS_N,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 1,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_UART0_CTS_N,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 1,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_UART0_SOUT,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 1,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_UART0_SIN
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 1,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART2_SOUT,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 1,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_UART2_SIN
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_LCDC1_DATA23,
+ GPIO2C7_SPI1_CSN1,
+ GPIO2C7_HSADC_DATA4,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 3,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_LCDC1_DATA22,
+ GPIO2C6_SPI1_RXD,
+ GPIO2C6_HSADC_DATA3,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 3,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_LCDC1_DATA21,
+ GPIO2C5_SPI1_TXD,
+ GPIO2C5_HSADC_DATA2,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 3,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_LCDC1_DATA20,
+ GPIO2C4_SPI1_CSN0,
+ GPIO2C4_HSADC_DATA1,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_LCDC1_DATA19,
+ GPIO2C3_SPI1_CLK,
+ GPIO2C3_HSADC_DATA0
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D7_SHIFT = 14,
+ GPIO2D7_MASK = 1,
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_I2C1_SCL,
+
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 1,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_I2C1_SDA,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 1,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_I2C0_SCL,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 1,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_I2C0_SDA
+
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 1,
+ GPIO3A7_GPIO = 0,
+ GPIO3A7_SDMMC0_WRITE_PRT,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 1,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_SDMMC0_RSTN_OUT,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 1,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_I2C4_SCL,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 1,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_I2C4_SDA,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 1,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_I2C3_SCL,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 1,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_I2C3_SDA,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 1,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_I2C2_SCL,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 1,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_I2C2_SDA,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+ GPIO3B7_SHIFT = 14,
+ GPIO3B7_MASK = 1,
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_SDMMC0_WRITE_PRT,
+
+ GPIO3B6_SHIFT = 12,
+ GPIO3B6_MASK = 1,
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_SDMMC0_DETECT_N,
+
+ GPIO3B5_SHIFT = 10,
+ GPIO3B5_MASK = 1,
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_SDMMC0_DATA3,
+
+ GPIO3B4_SHIFT = 8,
+ GPIO3B4_MASK = 1,
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_SDMMC0_DATA2,
+
+ GPIO3B3_SHIFT = 6,
+ GPIO3B3_MASK = 1,
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_SDMMC0_DATA1,
+
+ GPIO3B2_SHIFT = 4,
+ GPIO3B2_MASK = 1,
+ GPIO3B2_GPIO = 0,
+ GPIO3B2_SDMMC0_DATA0,
+
+ GPIO3B1_SHIFT = 2,
+ GPIO3B1_MASK = 1,
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_SDMMC0_CMD,
+
+ GPIO3B0_SHIFT = 0,
+ GPIO3B0_MASK = 1,
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_SDMMC0_CLKOUT
+
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 1,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_SDMMC1_WRITE_PRT,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 1,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_SDMMC1_DETECT_N,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 1,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_SDMMC1_CLKOUT,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 1,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_SDMMC1_DATA3,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 1,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_SDMMC1_DATA2,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 1,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_SDMMC1_DATA1,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 1,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_SDMMC1_DATA0,
+
+ GPIO3C0_SHIFT = 0,
+ GPIO3C0_MASK = 1,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_SMMC1_CMD
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D7_SHIFT = 14,
+ GPIO3D7_MASK = 3,
+ GPIO3D7_GPIO = 0,
+ GPIO3D7_FLASH_DQS,
+ GPIO3D7_EMMC_CLKOUT,
+
+ GPIO3D6_SHIFT = 12,
+ GPIO3D6_MASK = 1,
+ GPIO3D6_GPIO = 0,
+ GPIO3D6_UART3_RTS_N,
+
+ GPIO3D5_SHIFT = 10,
+ GPIO3D5_MASK = 1,
+ GPIO3D5_GPIO = 0,
+ GPIO3D5_UART3_CTS_N,
+
+ GPIO3D4_SHIFT = 8,
+ GPIO3D4_MASK = 1,
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_UART3_SOUT,
+
+ GPIO3D3_SHIFT = 6,
+ GPIO3D3_MASK = 1,
+ GPIO3D3_GPIO = 0,
+ GPIO3D3_UART3_SIN,
+
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 1,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_SDMMC1_INT_N,
+
+ GPIO3D1_SHIFT = 2,
+ GPIO3D1_MASK = 1,
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_SDMMC1_BACKEND_PWR,
+
+ GPIO3D0_SHIFT = 0,
+ GPIO3D0_MASK = 1,
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_SDMMC1_PWR_EN
+
+};
+
+/* GRF_GPIO4A_IOMUX */
+enum {
+ GPIO4A7_SHIFT = 14,
+ GPIO4A7_MASK = 1,
+ GPIO4A7_GPIO = 0,
+ GPIO4A7_FLASH_DATA15,
+
+ GPIO4A6_SHIFT = 12,
+ GPIO4A6_MASK = 1,
+ GPIO4A6_GPIO = 0,
+ GPIO4A6_FLASH_DATA14,
+
+ GPIO4A5_SHIFT = 10,
+ GPIO4A5_MASK = 1,
+ GPIO4A5_GPIO = 0,
+ GPIO4A5_FLASH_DATA13,
+
+ GPIO4A4_SHIFT = 8,
+ GPIO4A4_MASK = 1,
+ GPIO4A4_GPIO = 0,
+ GPIO4A4_FLASH_DATA12,
+
+ GPIO4A3_SHIFT = 6,
+ GPIO4A3_MASK = 1,
+ GPIO4A3_GPIO = 0,
+ GPIO4A3_FLASH_DATA11,
+
+ GPIO4A2_SHIFT = 4,
+ GPIO4A2_MASK = 1,
+ GPIO4A2_GPIO = 0,
+ GPIO4A2_FLASH_DATA10,
+
+ GPIO4A1_SHIFT = 2,
+ GPIO4A1_MASK = 1,
+ GPIO4A1_GPIO = 0,
+ GPIO4A1_FLASH_DATA9,
+
+ GPIO4A0_SHIFT = 0,
+ GPIO4A0_MASK = 1,
+ GPIO4A0_GPIO = 0,
+ GPIO4A0_FLASH_DATA8
+
+};
+
+/* GRF_GPIO4B_IOMUX */
+enum {
+ GPIO4B7_SHIFT = 14,
+ GPIO4B7_MASK = 1,
+ GPIO4B7_GPIO = 0,
+ GPIO4B7_SPI0_CSN1,
+
+ GPIO4B6_SHIFT = 12,
+ GPIO4B6_MASK = 1,
+ GPIO4B6_GPIO = 0,
+ GPIO4B6_FLASH_CSN7,
+
+ GPIO4B5_SHIFT = 10,
+ GPIO4B5_MASK = 1,
+ GPIO4B5_GPIO = 0,
+ GPIO4B5_FLASH_CSN6,
+
+ GPIO4B4_SHIFT = 8,
+ GPIO4B4_MASK = 1,
+ GPIO4B4_GPIO = 0,
+ GPIO4B4_FLASH_CSN5,
+
+ GPIO4B3_SHIFT = 6,
+ GPIO4B3_MASK = 1,
+ GPIO4B3_GPIO = 0,
+ GPIO4B3_FLASH_CSN4,
+
+ GPIO4B2_SHIFT = 4,
+ GPIO4B2_MASK = 3,
+ GPIO4B2_GPIO = 0,
+ GPIO4B2_FLASH_CSN3,
+ GPIO4B2_EMMC_RSTN_OUT,
+
+ GPIO4B1_SHIFT = 2,
+ GPIO4B1_MASK = 3,
+ GPIO4B1_GPIO = 0,
+ GPIO4B1_FLASH_CSN2,
+ GPIO4B1_EMMC_CMD,
+
+ GPIO4B0_SHIFT = 0,
+ GPIO4B0_MASK = 1,
+ GPIO4B0_GPIO = 0,
+ GPIO4B0_FLASH_CSN1
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ SMC_MUX_CON_SHIFT = 13,
+ SMC_MUX_CON_MASK = 1,
+
+ NOC_REMAP_SHIFT = 12,
+ NOC_REMAP_MASK = 1,
+
+ EMMC_FLASH_SEL_SHIFT = 11,
+ EMMC_FLASH_SEL_MASK = 1,
+
+ TZPC_REVISION_SHIFT = 7,
+ TZPC_REVISION_MASK = 0xf,
+
+ L2CACHE_ACC_SHIFT = 5,
+ L2CACHE_ACC_MASK = 3,
+
+ L2RD_WAIT_SHIFT = 3,
+ L2RD_WAIT_MASK = 3,
+
+ IMEMRD_WAIT_SHIFT = 1,
+ IMEMRD_WAIT_MASK = 3,
+
+ SOC_REMAP_SHIFT = 0,
+ SOC_REMAP_MASK = 1,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+ RKI2C4_SEL_SHIFT = 15,
+ RKI2C4_SEL_MASK = 1,
+
+ RKI2C3_SEL_SHIFT = 14,
+ RKI2C3_SEL_MASK = 1,
+
+ RKI2C2_SEL_SHIFT = 13,
+ RKI2C2_SEL_MASK = 1,
+
+ RKI2C1_SEL_SHIFT = 12,
+ RKI2C1_SEL_MASK = 1,
+
+ RKI2C0_SEL_SHIFT = 11,
+ RKI2C0_SEL_MASK = 1,
+
+ VCODEC_SEL_SHIFT = 10,
+ VCODEC_SEL_MASK = 1,
+
+ PERI_EMEM_PAUSE_SHIFT = 9,
+ PERI_EMEM_PAUSE_MASK = 1,
+
+ PERI_USB_PAUSE_SHIFT = 8,
+ PERI_USB_PAUSE_MASK = 1,
+
+ SMC_MUX_MODE_0_SHIFT = 6,
+ SMC_MUX_MODE_0_MASK = 1,
+
+ SMC_SRAM_MW_0_SHIFT = 4,
+ SMC_SRAM_MW_0_MASK = 3,
+
+ SMC_REMAP_0_SHIFT = 3,
+ SMC_REMAP_0_MASK = 1,
+
+ SMC_A_GT_M0_SYNC_SHIFT = 2,
+ SMC_A_GT_M0_SYNC_MASK = 1,
+
+ EMAC_SPEED_SHIFT = 1,
+ EMAC_SPEEC_MASK = 1,
+
+ EMAC_MODE_SHIFT = 0,
+ EMAC_MODE_MASK = 1,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+
+ MSCH4_MAINDDR3_SHIFT = 7,
+ MSCH4_MAINDDR3_MASK = 1,
+ MSCH4_MAINDDR3_DDR3 = 1,
+
+ EMAC_NEWRCV_EN_SHIFT = 6,
+ EMAC_NEWRCV_EN_MASK = 1,
+
+ SW_ADDR15_EN_SHIFT = 5,
+ SW_ADDR15_EN_MASK = 1,
+
+ SW_ADDR16_EN_SHIFT = 4,
+ SW_ADDR16_EN_MASK = 1,
+
+ SW_ADDR17_EN_SHIFT = 3,
+ SW_ADDR17_EN_MASK = 1,
+
+ BANK2_TO_RANK_EN_SHIFT = 2,
+ BANK2_TO_RANK_EN_MASK = 1,
+
+ RANK_TO_ROW15_EN_SHIFT = 1,
+ RANK_TO_ROW15_EN_MASK = 1,
+
+ UPCTL_C_ACTIVE_IN_SHIFT = 0,
+ UPCTL_C_ACTIVE_IN_MASK = 1,
+ UPCTL_C_ACTIVE_IN_MAY = 0,
+ UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+ DTO_LB_SHIFT = 11,
+ DTO_LB_MASK = 3,
+
+ DTO_TE_SHIFT = 9,
+ DTO_TE_MASK = 3,
+
+ DTO_PDR_SHIFT = 7,
+ DTO_PDR_MASK = 3,
+
+ DTO_PDD_SHIFT = 5,
+ DTO_PDD_MASK = 3,
+
+ DTO_IOM_SHIFT = 3,
+ DTO_IOM_MASK = 3,
+
+ DTO_OE_SHIFT = 1,
+ DTO_OE_MASK = 3,
+
+ ATO_AE_SHIFT = 0,
+ ATO_AE_MASK = 1,
+};
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
@ 2017-06-06 18:49 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
` (10 subsequent siblings)
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:49 UTC (permalink / raw)
To: u-boot
Add driver supporting pin multiplexing on rk3066 platform.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk3066.c | 342 ++++++++++++++++++++++++++++++
3 files changed, 352 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f6616c5..992de5b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -167,6 +167,15 @@ config PINCTRL_ROCKCHIP_RK3036
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_ROCKCHIP_RK3066
+ bool "Rockchip rk3066 pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3066 SoCs. The driver is
+ controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config PINCTRL_ROCKCHIP_RK3188
bool "Rockchip rk3188 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index 69eef4c..6e4b4be 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3066) += pinctrl_rk3066.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3066.c b/drivers/pinctrl/rockchip/pinctrl_rk3066.c
new file mode 100644
index 0000000..596ddb7
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3066.c
@@ -0,0 +1,342 @@
+/*
+ * Pinctrl driver for Rockchip 3066 SoCs
+ * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3066_pinctrl_priv {
+ struct rk3066_grf *grf;
+};
+
+static void pinctrl_rk3066_pwm_config(struct rk3066_grf *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A3_MASK << GPIO0A3_SHIFT,
+ GPIO0A3_PWM0 << GPIO0A3_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A4_MASK << GPIO0A4_SHIFT,
+ GPIO0A4_PWM1 << GPIO0A4_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK << GPIO0D6_SHIFT,
+ GPIO0D6_PWM2 << GPIO0D6_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D7_MASK << GPIO0D7_SHIFT,
+ GPIO0D7_PWM3 << GPIO0D7_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3066_i2c_config(struct rk3066_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D4_MASK << GPIO2D4_SHIFT |
+ GPIO2D5_MASK << GPIO2D5_SHIFT,
+ GPIO2D4_I2C0_SDA << GPIO2D4_SHIFT |
+ GPIO2D5_I2C0_SCL << GPIO2D5_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
+ 1 << RKI2C0_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D6_MASK << GPIO2D6_SHIFT |
+ GPIO2D7_MASK << GPIO2D7_SHIFT,
+ GPIO2D6_I2C1_SDA << GPIO2D6_SHIFT |
+ GPIO2D7_I2C1_SCL << GPIO2D7_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
+ 1 << RKI2C1_SEL_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GPIO3A1_MASK << GPIO3A1_SHIFT |
+ GPIO3A0_MASK << GPIO3A0_SHIFT,
+ GPIO3A1_I2C2_SCL << GPIO3A1_SHIFT |
+ GPIO3A0_I2C2_SDA << GPIO3A0_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
+ 1 << RKI2C2_SEL_SHIFT);
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GPIO3A3_MASK << GPIO3A3_SHIFT |
+ GPIO3A2_SHIFT << GPIO3A2_SHIFT,
+ GPIO3A3_I2C3_SCL << GPIO3A3_SHIFT |
+ GPIO3A2_I2C3_SDA << GPIO3A2_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
+ 1 << RKI2C3_SEL_SHIFT);
+ case PERIPH_ID_I2C4:
+ rk_clrsetreg(&grf->gpio3a_iomux,
+ GPIO3A5_MASK << GPIO3A5_SHIFT |
+ GPIO3A4_MASK << GPIO3A4_SHIFT,
+ GPIO3A5_I2C4_SCL << GPIO3A5_SHIFT |
+ GPIO3A4_I2C4_SDA << GPIO3A4_SHIFT);
+ rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
+ 1 << RKI2C4_SEL_SHIFT);
+ break;
+ }
+}
+
+static void pinctrl_rk3066_spi_config(struct rk3066_grf *grf, int spi_id, int cs)
+{
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A7_MASK << GPIO1A7_SHIFT |
+ GPIO1A6_MASK << GPIO1A6_SHIFT |
+ GPIO1A5_MASK << GPIO1A5_SHIFT,
+ GPIO1A7_SPI0_TXD << GPIO1A7_SHIFT |
+ GPIO1A6_SPI0_RXD << GPIO1A6_SHIFT |
+ GPIO1A5_SPI0_CLK << GPIO1A5_SHIFT);
+ if(cs == 0)
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A4_MASK << GPIO1A4_SHIFT,
+ GPIO1A4_SPI0_CSN0 << GPIO1A4_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio4b_iomux,
+ GPIO4B7_MASK << GPIO4B7_SHIFT,
+ GPIO4B7_SPI0_CSN1 << GPIO4B7_SHIFT);
+ break;
+ case PERIPH_ID_SPI1:
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C5_MASK << GPIO2C5_SHIFT |
+ GPIO2C6_MASK << GPIO2C6_SHIFT |
+ GPIO2C3_MASK << GPIO2C3_SHIFT,
+ GPIO2C5_SPI1_TXD << GPIO2C5_SHIFT |
+ GPIO2C6_SPI1_RXD << GPIO2C6_SHIFT |
+ GPIO2C3_SPI1_CLK << GPIO2C3_SHIFT);
+ if(cs == 0)
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C4_MASK << GPIO2C4_SHIFT,
+ GPIO2C4_SPI1_CSN0 << GPIO2C4_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C7_MASK << GPIO2C7_SHIFT,
+ GPIO2C7_SPI1_CSN1 << GPIO2C7_SHIFT);
+ break;
+ }
+}
+
+static void pinctrl_rk3066_uart_config(struct rk3066_grf *grf, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART0:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A2_MASK << GPIO1A2_SHIFT |
+ GPIO1A3_MASK << GPIO1A3_SHIFT |
+ GPIO1A0_MASK << GPIO1A0_SHIFT |
+ GPIO1A1_MASK << GPIO1A1_SHIFT,
+ GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
+ GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
+ GPIO1A0_UART0_SIN << GPIO1A0_SHIFT |
+ GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT);
+ break;
+ case PERIPH_ID_UART1:
+ rk_clrsetreg(&grf->gpio1a_iomux,
+ GPIO1A7_MASK << GPIO1A7_SHIFT |
+ GPIO1A6_MASK << GPIO1A6_SHIFT |
+ GPIO1A5_MASK << GPIO1A5_SHIFT |
+ GPIO1A4_MASK << GPIO1A4_SHIFT,
+ GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
+ GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
+ GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
+ GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
+ break;
+ case PERIPH_ID_UART2:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK << GPIO1B1_SHIFT |
+ GPIO1B0_MASK << GPIO1B0_SHIFT,
+ GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+ GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+ break;
+ case PERIPH_ID_UART3:
+ rk_clrsetreg(&grf->gpio3d_iomux,
+ GPIO3D6_MASK << GPIO3D6_SHIFT |
+ GPIO3D5_MASK << GPIO3D5_SHIFT |
+ GPIO3D4_MASK << GPIO3D4_SHIFT |
+ GPIO3D3_MASK << GPIO3D3_SHIFT,
+ GPIO3D6_UART3_RTS_N << GPIO3D6_SHIFT |
+ GPIO3D5_UART3_CTS_N << GPIO3D5_SHIFT |
+ GPIO3D4_UART3_SOUT << GPIO3D4_SHIFT |
+ GPIO3D3_UART3_SIN << GPIO3D3_SHIFT);
+ break;
+ }
+}
+
+static void pinctrl_rk3066_sdmmc_config(struct rk3066_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->soc_con0,
+ EMMC_FLASH_SEL_MASK << EMMC_FLASH_SEL_SHIFT,
+ 1 << EMMC_FLASH_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio3d_iomux,
+ GPIO3D7_MASK << GPIO3D7_SHIFT,
+ GPIO3D7_EMMC_CLKOUT << GPIO3D7_SHIFT);
+ rk_clrsetreg(&grf->gpio4b_iomux,
+ GPIO4B2_MASK << GPIO4B2_SHIFT |
+ GPIO4B1_MASK << GPIO4B1_SHIFT,
+ GPIO4B2_EMMC_RSTN_OUT << GPIO4B2_SHIFT |
+ GPIO4B1_EMMC_CMD << GPIO4B1_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio3b_iomux, 0xffff,
+ GPIO3B7_SDMMC0_WRITE_PRT << GPIO3B7_SHIFT |
+ GPIO3B6_SDMMC0_DETECT_N << GPIO3B6_SHIFT |
+ GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT |
+ GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT |
+ GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT |
+ GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT |
+ GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT |
+ GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT);
+ break;
+ }
+}
+
+static int rk3066_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3066_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ pinctrl_rk3066_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ pinctrl_rk3066_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ pinctrl_rk3066_spi_config(priv->grf, func, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ pinctrl_rk3066_uart_config(priv->grf, func);
+ break;
+ case PERIPH_ID_EMMC:
+ case PERIPH_ID_SDCARD:
+ pinctrl_rk3066_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3066_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 23:
+ return PERIPH_ID_SDCARD;
+ case 25:
+ return PERIPH_ID_EMMC;
+ case 34:
+ return PERIPH_ID_UART0;
+ case 35:
+ return PERIPH_ID_UART1;
+ case 36:
+ return PERIPH_ID_UART2;
+ case 37:
+ return PERIPH_ID_UART3;
+ case 38:
+ return PERIPH_ID_SPI0;
+ case 39:
+ return PERIPH_ID_SPI1;
+ case 40:
+ return PERIPH_ID_I2C0;
+ case 41:
+ return PERIPH_ID_I2C1;
+ case 42:
+ return PERIPH_ID_I2C2;
+ case 43:
+ return PERIPH_ID_I2C3;
+ case 30:
+ return PERIPH_ID_PWM0;
+ }
+#endif
+ return -ENOENT;
+}
+
+static int rk3066_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3066_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk3066_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3066_pinctrl_ops = {
+ .set_state_simple = rk3066_pinctrl_set_state_simple,
+ .request = rk3066_pinctrl_request,
+ .get_periph_id = rk3066_pinctrl_get_periph_id,
+};
+
+static int rk3066_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3066_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ return 0;
+}
+
+static const struct udevice_id rk3066_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3066a-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
+ .name = "rockchip_rk3066a_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3066_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3066_pinctrl_priv),
+ .ops = &rk3066_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rk3066_pinctrl_probe,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
2017-06-06 18:49 ` [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver Paweł Jarosz
@ 2017-06-06 18:49 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:50 ` [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc Paweł Jarosz
` (9 subsequent siblings)
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:49 UTC (permalink / raw)
To: u-boot
Add support for system reset for rk3066 socs.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3066.c | 62 ++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk3066.c
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index b683811..d138278 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
endif
+obj-$(CONFIG_ROCKCHIP_RK3066) += sysreset_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
diff --git a/drivers/sysreset/sysreset_rk3066.c b/drivers/sysreset/sysreset_rk3066.c
new file mode 100644
index 0000000..79f9e4f
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk3066.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3066_cru *cru = rockchip_get_cru();
+ struct rk3066_grf *grf;
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+
+ switch (type) {
+ case SYSRESET_WARM:
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(grf))
+ return -EPROTONOSUPPORT;
+ /*
+ * warm-reset keeps the remap value,
+ * so make sure it's disabled.
+ */
+ rk_clrsetreg(&grf->soc_con0,
+ NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+ 0 << NOC_REMAP_SHIFT);
+
+ rk_clrreg(&cru->cru_mode_con, 0xffff);
+ writel(0xeca8, &cru->cru_glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ rk_clrreg(&cru->cru_mode_con, 0xffff);
+ writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3066_sysreset = {
+ .request = rk3066_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3066) = {
+ .name = "rk3066_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3066_sysreset,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (2 preceding siblings ...)
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
@ 2017-06-06 18:50 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
` (8 subsequent siblings)
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:50 UTC (permalink / raw)
To: u-boot
Add clock driver for rk3066 platform.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 ++++++++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3066.c | 586 ++++++++++++++++++++++++
3 files changed, 776 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
create mode 100644 drivers/clk/rockchip/clk_rk3066.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
new file mode 100644
index 0000000..4badd4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3066_H
+#define _ASM_ARCH_CRU_RK3066_H
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ (1416 * 1000000)
+#define APLL_SAFE_HZ (600 * 1000000)
+#define GPLL_HZ (594 * 1000000)
+#define CPLL_HZ (384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ 297000000
+#define CPU_HCLK_HZ 148500000
+#define CPU_PCLK_HZ 74250000
+#define CPU_H2P_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3066_clk_priv {
+ struct rk3066_grf *grf;
+ struct rk3066_cru *cru;
+ ulong rate;
+ bool has_bwadj;
+};
+
+struct rk3066_cru {
+ struct rk3066_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[4];
+ u32 cru_mode_con;
+ u32 cru_clksel_con[35];
+ u32 cru_clkgate_con[10];
+ u32 reserved1[2];
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 reserved2[2];
+ u32 cru_softrst_con[9];
+ u32 cru_misc_con;
+ u32 reserved3[2];
+ u32 cru_glb_cnt_th;
+};
+check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+ /* a9_core_div: core = core_src / (a9_core_div + 1) */
+ A9_CORE_DIV_SHIFT = 9,
+ A9_CORE_DIV_MASK = 0x1f,
+ CORE_PLL_SHIFT = 8,
+ CORE_PLL_MASK = 1,
+ CORE_PLL_SELECT_APLL = 0,
+ CORE_PLL_SELECT_GPLL,
+
+ /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+ CORE_PERI_DIV_SHIFT = 6,
+ CORE_PERI_DIV_MASK = 3,
+
+ /* aclk_cpu pll selection */
+ CPU_ACLK_PLL_SHIFT = 5,
+ CPU_ACLK_PLL_MASK = 1,
+ CPU_ACLK_PLL_SELECT_APLL = 0,
+ CPU_ACLK_PLL_SELECT_GPLL,
+
+ /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+ A9_CPU_DIV_SHIFT = 0,
+ A9_CPU_DIV_MASK = 0x1f,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+ /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+ AHB2APB_DIV_SHIFT = 14,
+ AHB2APB_DIV_MASK = 3,
+
+ /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+ CPU_PCLK_DIV_SHIFT = 12,
+ CPU_PCLK_DIV_MASK = 3,
+
+ /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+ CPU_HCLK_DIV_SHIFT = 8,
+ CPU_HCLK_DIV_MASK = 3,
+
+ /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+ CORE_ACLK_DIV_SHIFT = 3,
+ CORE_ACLK_DIV_MASK = 7,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+ PERI_SEL_PLL_MASK = 1,
+ PERI_SEL_PLL_SHIFT = 15,
+ PERI_SEL_CPLL = 0,
+ PERI_SEL_GPLL,
+
+ /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_PCLK_DIV_MASK = 3,
+
+ /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_HCLK_DIV_MASK = 3,
+
+ /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+ PERI_ACLK_DIV_SHIFT = 0,
+ PERI_ACLK_DIV_MASK = 0x1f,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ UART_PLL_SHIFT = 15,
+ UART_PLL_MASK = 1,
+ UART_PLL_SELECT_GENERAL = 0,
+ UART_PLL_SELECT_CODEC,
+
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f,
+
+ SDIO_DIV_SHIFT = 0,
+ SDIO_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ SPI1_DIV_SHIFT = 8,
+ SPI1_DIV_MASK = 0x7f,
+
+ SPI0_DIV_SHIFT = 0,
+ SPI0_DIV_MASK = 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_MASK = 3,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORMAL,
+ GPLL_MODE_DEEP,
+
+ CPLL_MODE_SHIFT = 8,
+ CPLL_MODE_MASK = 3,
+ CPLL_MODE_SLOW = 0,
+ CPLL_MODE_NORMAL,
+ CPLL_MODE_DEEP,
+
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_MASK = 3,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORMAL,
+ DPLL_MODE_DEEP,
+
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_MASK = 3,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORMAL,
+ APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+ CLKR_SHIFT = 8,
+ CLKR_MASK = 0x3f,
+
+ CLKOD_SHIFT = 0,
+ CLKOD_MASK = 0x3f,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+ CLKF_SHIFT = 0,
+ CLKF_MASK = 0x1fff,
+};
+
+#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 1091a76..9302c48 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
new file mode 100644
index 0000000..967cd6b
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/hardware.h>
+#include <dt-bindings/clock/rk3066a-cru.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum rk3066_clk_type {
+ RK3066_CRU,
+ RK3066A_CRU,
+};
+
+struct rk3066_clk_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3066a_cru dtd;
+#endif
+};
+
+struct pll_div {
+ u32 nr;
+ u32 nf;
+ u32 no;
+};
+
+enum {
+ VCO_MAX_HZ = 1416U * 1000000,
+ VCO_MIN_HZ = 300 * 1000000,
+ OUTPUT_MAX_HZ = 1416U * 1000000,
+ OUTPUT_MIN_HZ = 30 * 1000000,
+ FREF_MAX_HZ = 1416U * 1000000,
+ FREF_MIN_HZ = 30 * 1000,
+};
+
+enum {
+ /* PLL CON0 */
+ PLL_OD_MASK = 0x0f,
+
+ /* PLL CON1 */
+ PLL_NF_MASK = 0x1fff,
+
+ /* PLL CON2 */
+ PLL_BWADJ_MASK = 0x0fff,
+
+ /* PLL CON3 */
+ PLL_RESET_SHIFT = 5,
+
+ /* GRF_SOC_STATUS0 */
+ SOCSTS_DPLL_LOCK = 1 << 4,
+ SOCSTS_APLL_LOCK = 1 << 5,
+ SOCSTS_CPLL_LOCK = 1 << 6,
+ SOCSTS_GPLL_LOCK = 1 << 7,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _nr, _no) {\
+ .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
+ _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
+ (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
+ "divisors on line " __stringify(__LINE__));
+
+/* Keep divisors as low as possible to reduce jitter and power usage */
+#ifdef CONFIG_SPL_BUILD
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
+static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+#endif
+
+static int rkclk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div, bool has_bwadj)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3066_pll *pll = &cru->pll[pll_id];
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
+ uint output_hz = vco_hz / div->no;
+
+ debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
+ (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
+ (div->no == 1 || !(div->no % 2)));
+
+ /* enter reset */
+ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
+ ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
+ rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
+
+ if (has_bwadj)
+ rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
+ udelay(10);
+
+ /* return from reset */
+ rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ return 0;
+}
+
+static int rkclk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf,
+ unsigned int hz, bool has_bwadj)
+{
+ static const struct pll_div dpll_cfg[] = {
+ {.nf = 25, .nr = 2, .no = 1},
+ {.nf = 400, .nr = 9, .no = 2},
+ {.nf = 500, .nr = 9, .no = 2},
+ {.nf = 100, .nr = 3, .no = 1},
+ };
+ int cfg;
+
+ switch (hz) {
+ case 300000000:
+ cfg = 0;
+ break;
+ case 533000000: /* actually 533.3P MHz */
+ cfg = 1;
+ break;
+ case 666000000: /* actually 666.6P MHz */
+ cfg = 2;
+ break;
+ case 800000000:
+ cfg = 3;
+ break;
+ default:
+ debug("Unsupported SDRAM frequency");
+ return -EINVAL;
+ }
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+
+ rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
+
+ /* wait for pll lock */
+ while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
+ udelay(1);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
+
+ return 0;
+}
+
+static int rkclk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf,
+ unsigned int hz, bool has_bwadj)
+{
+ static const struct pll_div apll_cfg[] = {
+ {.nf = 50, .nr = 1, .no = 2},
+ {.nf = 59, .nr = 1, .no = 1},
+ };
+ int div_core_peri, div_aclk_core, cfg;
+
+ /*
+ * We support two possible frequencies, the safe 600MHz
+ * which will work with default pmic settings and will
+ * be set to get away from the 24MHz default and
+ * the maximum of 1.416Ghz, which boards can set if they
+ * were able to get pmic support for it.
+ */
+ switch (hz) {
+ case APLL_SAFE_HZ:
+ cfg = 0;
+ div_core_peri = 1;
+ div_aclk_core = 3;
+ break;
+ case APLL_HZ:
+ cfg = 1;
+ div_core_peri = 2;
+ div_aclk_core = 3;
+ break;
+ default:
+ debug("Unsupported ARMCLK frequency");
+ return -EINVAL;
+ }
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
+ APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+ rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
+
+ /* waiting for pll lock */
+ while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
+ udelay(1);
+
+ /* Set divider for peripherals attached to the cpu core. */
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
+ div_core_peri << CORE_PERI_DIV_SHIFT);
+
+ /* set up dependent divisor for aclk_core */
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
+ div_aclk_core << CORE_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
+ APLL_MODE_NORMAL << APLL_MODE_SHIFT);
+
+ return hz;
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3066_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ uint32_t nr, no, nf;
+ uint32_t con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3066_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+ GPLL_MODE_SHIFT
+ };
+ uint shift;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ switch ((con >> shift) & APLL_MODE_MASK) {
+ case APLL_MODE_SLOW:
+ return OSC_HZ;
+ case APLL_MODE_NORMAL:
+ /* normal mode */
+ con = readl(&pll->con0);
+ no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
+ nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
+ con = readl(&pll->con1);
+ nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
+
+ return (24 * nf / (nr * no)) * 1000000;
+ case APLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+ int periph)
+{
+ uint div;
+ u32 con;
+
+ switch (periph) {
+ case HCLK_EMMC:
+ con = readl(&cru->cru_clksel_con[12]);
+ div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
+ break;
+ case HCLK_SDMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
+ break;
+ case HCLK_SDIO:
+ con = readl(&cru->cru_clksel_con[12]);
+ div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+ int periph, uint freq)
+{
+ int src_clk_div;
+
+ debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+ src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ assert(src_clk_div <= 0x3f);
+
+ switch (periph) {
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_DIV_MASK << EMMC_DIV_SHIFT,
+ src_clk_div << EMMC_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_DIV_MASK << MMC0_DIV_SHIFT,
+ src_clk_div << MMC0_DIV_SHIFT);
+ break;
+ case HCLK_SDIO:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ SDIO_DIV_MASK << SDIO_DIV_SHIFT,
+ src_clk_div << SDIO_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, gclk_rate, periph);
+}
+
+static ulong rockchip_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate,
+ int periph)
+{
+ uint div;
+ u32 con;
+
+ switch (periph) {
+ case SCLK_SPI0:
+ con = readl(&cru->cru_clksel_con[25]);
+ div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
+ break;
+ case SCLK_SPI1:
+ con = readl(&cru->cru_clksel_con[25]);
+ div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(gclk_rate, div);
+}
+
+static ulong rockchip_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate,
+ int periph, uint freq)
+{
+ int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+
+ switch (periph) {
+ case SCLK_SPI0:
+ assert(src_clk_div <= SPI0_DIV_MASK);
+ rk_clrsetreg(&cru->cru_clksel_con[25],
+ SPI0_DIV_MASK << SPI0_DIV_SHIFT,
+ src_clk_div << SPI0_DIV_SHIFT);
+ break;
+ case SCLK_SPI1:
+ assert(src_clk_div <= SPI1_DIV_MASK);
+ rk_clrsetreg(&cru->cru_clksel_con[25],
+ SPI1_DIV_MASK << SPI1_DIV_SHIFT,
+ src_clk_div << SPI1_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_spi_get_clk(cru, gclk_rate, periph);
+}
+#ifdef CONFIG_SPL_BUILD
+static void rkclk_init(struct rk3066_cru *cru, struct rk3066_grf *grf,
+ bool has_bwadj)
+{
+ u32 aclk_div, hclk_div, pclk_div, h2p_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
+ rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
+
+ /* waiting for pll lock */
+ while ((readl(&grf->soc_status0) &
+ (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
+ (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
+ udelay(1);
+
+ /*
+ * cpu clock pll source selection and
+ * reparent aclk_cpu_pre from apll to gpll
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
+ assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
+ A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
+ CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
+ aclk_div << A9_CPU_DIV_SHIFT);
+
+ hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
+ assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
+ pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
+ assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
+ h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
+ assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
+ CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
+ CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
+ h2p_div << AHB2APB_DIV_SHIFT |
+ pclk_div << CPU_PCLK_DIV_SHIFT |
+ hclk_div << CPU_HCLK_DIV_SHIFT);
+
+ /*
+ * peri clock pll source selection and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (hclk_div < 0x4));
+
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && (pclk_div < 0x4));
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
+ PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
+ PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
+ PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+ GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
+ CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
+
+ rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
+}
+#endif
+
+static ulong rk3066_clk_get_rate(struct clk *clk)
+{
+ struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case 1 ... 4:
+ new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
+ break;
+ case HCLK_EMMC:
+ case HCLK_SDMMC:
+ case HCLK_SDIO:
+ new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
+ clk->id);
+ break;
+ case SCLK_SPI0:
+ case SCLK_SPI1:
+ new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
+ clk->id);
+ break;
+ case PCLK_I2C0:
+ case PCLK_I2C1:
+ case PCLK_I2C2:
+ case PCLK_I2C3:
+ case PCLK_I2C4:
+ return gclk_rate;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3066_cru *cru = priv->cru;
+ ulong new_rate;
+
+ switch (clk->id) {
+ case PLL_APLL:
+ new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
+ priv->has_bwadj);
+ break;
+ case CLK_DDR:
+ new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
+ priv->has_bwadj);
+ break;
+ case HCLK_EMMC:
+ case HCLK_SDMMC:
+ case HCLK_SDIO:
+ new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
+ clk->id, rate);
+ break;
+ case SCLK_SPI0:
+ case SCLK_SPI1:
+ new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
+ clk->id, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk3066_clk_ops = {
+ .get_rate = rk3066_clk_get_rate,
+ .set_rate = rk3066_clk_set_rate,
+};
+
+static int rk3066_clk_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3066_cru *)devfdt_get_addr(dev);
+#endif
+
+ return 0;
+}
+
+static int rk3066_clk_probe(struct udevice *dev)
+{
+ struct rk3066_clk_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+
+#ifdef CONFIG_SPL_BUILD
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3066_clk_plat *plat = dev_get_platdata(dev);
+
+ priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
+#endif
+
+ rkclk_init(priv->cru, priv->grf, 1);
+#endif
+
+ return 0;
+}
+
+static int rk3066_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk3066_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No rk3066 reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+static const struct udevice_id rk3066_clk_ids[] = {
+ { .compatible = "rockchip,rk3066a-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
+ .name = "rockchip_rk3066a_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3066_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3066_clk_priv),
+ .platdata_auto_alloc_size = sizeof(struct rk3066_clk_plat),
+ .ops = &rk3066_clk_ops,
+ .bind = rk3066_clk_bind,
+ .ofdata_to_platdata = rk3066_clk_ofdata_to_platdata,
+ .probe = rk3066_clk_probe,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (3 preceding siblings ...)
2017-06-06 18:50 ` [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc Paweł Jarosz
@ 2017-06-06 18:50 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
` (7 subsequent siblings)
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:50 UTC (permalink / raw)
To: u-boot
rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
watchdog and uart
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/dts/rk3066a.dtsi | 699 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 699 insertions(+)
create mode 100644 arch/arm/dts/rk3066a.dtsi
diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi
new file mode 100644
index 0000000..ad3c3b5
--- /dev/null
+++ b/arch/arm/dts/rk3066a.dtsi
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3066a-cru.h>
+#include "rk3xxx.dtsi"
+
+/ {
+ compatible = "rockchip,rk3066a";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3066-smp";
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+ operating-points = <
+ /* kHz uV */
+ 1416000 1300000
+ 1200000 1175000
+ 1008000 1125000
+ 816000 1125000
+ 600000 1100000
+ 504000 1100000
+ 312000 1075000
+ >;
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0x1>;
+ };
+ };
+
+ sram: sram at 10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x10000>;
+
+ smp-sram at 0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x0 0x50>;
+ };
+ };
+
+ i2s0: i2s at 10118000 {
+ compatible = "rockchip,rk3066-i2s";
+ reg = <0x10118000 0x2000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_bus>;
+ dmas = <&dmac1_s 4>, <&dmac1_s 5>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+ rockchip,playback-channels = <8>;
+ rockchip,capture-channels = <2>;
+ status = "disabled";
+ };
+
+ i2s1: i2s at 1011a000 {
+ compatible = "rockchip,rk3066-i2s";
+ reg = <0x1011a000 0x2000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_bus>;
+ dmas = <&dmac1_s 6>, <&dmac1_s 7>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "disabled";
+ };
+
+ i2s2: i2s at 1011c000 {
+ compatible = "rockchip,rk3066-i2s";
+ reg = <0x1011c000 0x2000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2_bus>;
+ dmas = <&dmac1_s 9>, <&dmac1_s 10>;
+ dma-names = "tx", "rx";
+ clock-names = "i2s_hclk", "i2s_clk";
+ clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
+ rockchip,playback-channels = <2>;
+ rockchip,capture-channels = <2>;
+ status = "disabled";
+ };
+
+ cru: clock-controller at 20000000 {
+ compatible = "rockchip,rk3066a-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ u-boot,dm-spl;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+ <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>;
+ assigned-clock-rates = <400000000>, <594000000>,
+ <300000000>, <150000000>,
+ <75000000>, <300000000>,
+ <150000000>, <75000000>;
+ };
+
+ timer at 2000e000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x2000e000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
+ clock-names = "timer", "pclk";
+ };
+
+ efuse: efuse at 20010000 {
+ compatible = "rockchip,rk3066a-efuse";
+ reg = <0x20010000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE>;
+ clock-names = "pclk_efuse";
+
+ cpu_leakage: cpu_leakage at 17 {
+ reg = <0x17 0x1>;
+ };
+ };
+
+ timer at 20038000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x20038000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
+ clock-names = "timer", "pclk";
+ };
+
+ timer at 2003a000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x2003a000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
+ clock-names = "timer", "pclk";
+ };
+
+ tsadc: tsadc at 20060000 {
+ compatible = "rockchip,rk3066-tsadc";
+ reg = <0x20060000 0x100>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ resets = <&cru SRST_TSADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ usbphy: phy {
+ compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy at 17c {
+ #phy-cells = <0>;
+ reg = <0x17c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ };
+
+ usbphy1: usb-phy at 188 {
+ #phy-cells = <0>;
+ reg = <0x188>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3066a-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ u-boot,dm-spl;
+
+ gpio0: gpio0 at 20034000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20034000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at 2003c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at 2003e000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2003e000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3 at 20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4 at 20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio6 at 2000a000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2000a000 0x100>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO6>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_default: pcfg_pull_default {
+ bias-pull-pin-default;
+ };
+
+ pcfg_pull_none: pcfg_pull_none {
+ bias-disable;
+ };
+
+ emac {
+ emac_xfer: emac-xfer {
+ rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
+ <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
+ <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
+ <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
+ <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
+ <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
+ <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
+ <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
+ };
+
+ emac_mdio: emac-mdio {
+ rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
+ <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
+ };
+
+ emmc_rst: emmc-rst {
+ rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
+ };
+
+ /*
+ * The data pins are shared between nandc and emmc and
+ * not accessible through pinctrl. Also they should've
+ * been already set correctly by firmware, as
+ * flash/emmc is the boot-device.
+ */
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
+ <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c4 {
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
+ <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0_out: pwm0-out {
+ rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_out: pwm1-out {
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_out: pwm2-out {
+ rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_out: pwm3-out {
+ rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_clk: spi0-clk {
+ rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi0_cs0: spi0-cs0 {
+ rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi0_tx: spi0-tx {
+ rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi0_rx: spi0-rx {
+ rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi0_cs1: spi0-cs1 {
+ rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ spi1 {
+ spi1_clk: spi1-clk {
+ rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi1_cs0: spi1-cs0 {
+ rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi1_rx: spi1-rx {
+ rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi1_tx: spi1-tx {
+ rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ spi1_cs1: spi1-cs1 {
+ rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ /* no rts / cts for uart2 */
+ };
+
+ uart3 {
+ uart3_xfer: uart3-xfer {
+ rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart3_cts: uart3-cts {
+ rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ uart3_rts: uart3-rts {
+ rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ sd0 {
+ sd0_clk: sd0-clk {
+ rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd0_cmd: sd0-cmd {
+ rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd0_cd: sd0-cd {
+ rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd0_wp: sd0-wp {
+ rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd0_bus1: sd0-bus-width1 {
+ rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ sd1 {
+ sd1_clk: sd1-clk {
+ rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd1_cd: sd1-cd {
+ rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd1_wp: sd1-wp {
+ rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ i2s0 {
+ i2s0_bus: i2s0-bus {
+ rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+
+ i2s2 {
+ i2s2_bus: i2s2-bus {
+ rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
+ <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
+ };
+ };
+ };
+};
+
+&grf {
+ compatible = "rockchip,rk3066-grf", "syscon";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer>;
+};
+
+&mmc0 {
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <5000000 50000000>;
+ dmas = <&dmac2 1>;
+ dma-names = "rx-tx";
+ max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
+ u-boot,dm-spl;
+};
+
+&mmc1 {
+ dmas = <&dmac2 3>;
+ dma-names = "rx-tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
+};
+
+&emmc {
+ dmas = <&dmac2 4>;
+ dma-names = "rx-tx";
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_out>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_out>;
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_out>;
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_out>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+};
+
+&uart0 {
+ compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
+ dmas = <&dmac1_s 0>, <&dmac1_s 1>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+};
+
+&uart1 {
+ compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
+ dmas = <&dmac1_s 2>, <&dmac1_s 3>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+};
+
+&uart2 {
+ compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
+ dmas = <&dmac2 6>, <&dmac2 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+};
+
+&uart3 {
+ compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
+ dmas = <&dmac2 8>, <&dmac2 9>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_xfer>;
+};
+
+&wdt {
+ compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
+};
+
+&emac {
+ compatible = "rockchip,rk3066-emac";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (4 preceding siblings ...)
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
@ 2017-06-06 18:50 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (3 more replies)
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
` (6 subsequent siblings)
12 siblings, 4 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:50 UTC (permalink / raw)
To: u-boot
Add core skeleton for rk3066
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/mach-rockchip/Kconfig | 16 +++
arch/arm/mach-rockchip/Makefile | 4 +
arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
arch/arm/mach-rockchip/rk3066-board.c | 180 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
include/configs/rk3066_common.h | 125 ++++++++++++++++++
10 files changed, 677 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
create mode 100644 include/configs/rk3066_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 6be2ab5..ad35e0a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK3066
+ bool "Support Rockchip RK3066"
+ select CPU_V7
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select SPL
+ select TPL
+ select BOARD_LATE_INIT
+ select ROCKCHIP_BROM_HELPER
+ help
+ The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
@@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
default y if !ROCKCHIP_SPL_BACK_TO_BROM
source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3066/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 327b267..1ebba0c 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -7,15 +7,18 @@
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
@@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
+obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c b/arch/arm/mach-rockchip/rk3066-board-spl.c
new file mode 100644
index 0000000..6f7bfb0
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <led.h>
+#include <malloc.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/timer.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <power/regulator.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ const char *bootdev;
+ int node;
+ int ret;
+
+ bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
+ debug("Boot device %s\n", bootdev);
+ if (!bootdev)
+ goto fallback;
+
+ node = fdt_path_offset(blob, bootdev);
+ if (node < 0) {
+ debug("node=%d\n", node);
+ goto fallback;
+ }
+ ret = device_get_global_by_of_offset(node, &dev);
+ if (ret) {
+ debug("device@node %s/%d not found: %d\n", bootdev, node,
+ ret);
+ goto fallback;
+ }
+ debug("Found device %s\n", dev->name);
+ switch (device_get_uclass_id(dev)) {
+ case UCLASS_SPI_FLASH:
+ return BOOT_DEVICE_SPI;
+ case UCLASS_MMC:
+ return BOOT_DEVICE_MMC1;
+ default:
+ debug("Booting from device uclass '%s' not supported\n",
+ dev_get_uclass_name(dev));
+ }
+
+fallback:
+#endif
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_FS;
+}
+
+static int setup_arm_clock(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ret;
+
+ clk.id = CLK_ARM;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_set_rate(&clk, 600000000);
+
+ clk_free(&clk);
+ return ret;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *pinctrl, *dev;
+ int ret;
+
+ debug_uart_init();
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Enable Timer0 */
+ rk_clrsetreg(CONFIG_SYS_TIMER_BASE + 0x8, 0x1, 0x1);
+
+ ret = rockchip_get_clk(&dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("Pinctrl init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+
+ setup_arm_clock();
+}
+
+void spl_board_init(void)
+{
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+ if (ret) {
+ debug("%s: Failed to set up SD card\n", __func__);
+ goto err;
+ }
+#endif
+
+ /* Enable debug UART */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+ if (ret) {
+ debug("%s: Failed to set up console UART\n", __func__);
+ goto err;
+ }
+
+ preloader_console_init();
+
+ return;
+
+err:
+ printf("spl_board_init: Error %d\n", ret);
+
+ /* No way to report error here */
+ hang();
+}
diff --git a/arch/arm/mach-rockchip/rk3066-board-tpl.c b/arch/arm/mach-rockchip/rk3066-board-tpl.c
new file mode 100644
index 0000000..d517a33
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066-board-tpl.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/ddr_rk3188.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/pmu_rk3188.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RK3066_TIMER_CONTROL 0x8
+#define GRF_BASE 0x20008000
+
+void board_init_f(ulong dummy)
+{
+ /* Enable early UART on the RK3066 */
+
+ struct rk3066_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK << GPIO1B1_SHIFT |
+ GPIO1B0_MASK << GPIO1B0_SHIFT,
+ GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+ GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+
+ debug_uart_init();
+
+ printch('T');
+ printch('P');
+ printch('L');
+ printch('\n');
+
+ /* Enable Timer0 */
+ rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1, 0x1);
+
+ sdram_initialise();
+
+ back_to_bootrom();
+}
diff --git a/arch/arm/mach-rockchip/rk3066-board.c b/arch/arm/mach-rockchip/rk3066-board.c
new file mode 100644
index 0000000..3d92253
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066-board.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ struct rk3066_grf *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(grf)) {
+ error("grf syscon returned %ld\n", PTR_ERR(grf));
+ } else {
+ /* enable noc remap to mimic legacy loaders */
+ rk_clrsetreg(&grf->soc_con0,
+ NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+ NOC_REMAP_MASK << NOC_REMAP_SHIFT);
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
+ struct udevice *pinctrl;
+ int ret;
+
+ /*
+ * We need to implement sdcard iomux here for the further
+ * initialization, otherwise, it'll hit sdcard command sending
+ * timeout exception.
+ */
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+ if (ret) {
+ debug("%s: Failed to set up SD card\n", __func__);
+ goto err;
+ }
+
+ return 0;
+err:
+ printf("board_init: Error %d\n", ret);
+
+ /* No way to report error here */
+ hang();
+
+ return -1;
+#else
+ return 0;
+#endif
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get DRAM size: %d\n", ret);
+ return ret;
+ }
+ debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+int print_cpuinfo (void)
+{
+ printf("CPU: Rockchip RK3066\n");
+ return 0;
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3066_otg_data = {
+ .rx_fifo_sz = 275,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 256,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node, phy_node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+ u32 grf_phy_offset;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3066-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3066-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ node = fdtdec_lookup_phandle(blob, node, "phys");
+ if (node <= 0) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ phy_node = fdt_parent_offset(blob, node);
+ if (phy_node <= 0) {
+ debug("Not found usb phy device\n");
+ return -ENODEV;
+ }
+
+ rk3066_otg_data.phy_of_node = phy_node;
+ grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3066-grf");
+ if (node <= 0) {
+ debug("Not found grf device\n");
+ return -ENODEV;
+ }
+ rk3066_otg_data.regs_phy = grf_phy_offset +
+ fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk3066_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
new file mode 100644
index 0000000..27d32fd
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/Kconfig
@@ -0,0 +1,34 @@
+if ROCKCHIP_RK3066
+
+config TARGET_MK808_RK3066
+ bool "MK808_RK3066"
+ help
+ MK808 is a tv stick with usb host and otg, microsd card slot, hdmi and wifi.
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config TPL_LIBCOMMON_SUPPORT
+ default y
+
+config TPL_LIBGENERIC_SUPPORT
+ default y
+
+config TPL_SERIAL_SUPPORT
+ default y
+
+source "board/rikomagic/mk808_rk3066/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
new file mode 100644
index 0000000..4cf5df2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_TPL_BUILD
+obj-y += clk_rk3066.o
+obj-y += syscon_rk3066.o
+else
+obj-y += sdram_init.o
+endif
diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
new file mode 100644
index 0000000..ae52902
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3066_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
new file mode 100644
index 0000000..57b2376
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3066_syscon_ids[] = {
+ { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
+ { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3066) = {
+ .name = "rk3066_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
+{
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3188_noc) = {
+ .name = "rockchip_rk3188_noc",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids,
+ .bind = rk3066_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_grf) = {
+ .name = "rockchip_rk3066_grf",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids + 1,
+ .bind = rk3066_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
+ .name = "rockchip_rk3066_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3066_syscon_ids + 2,
+ .bind = rk3066_syscon_bind_of_platdata,
+};
+#endif
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
new file mode 100644
index 0000000..7009616
--- /dev/null
+++ b/include/configs/rk3066_common.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3066_COMMON_H
+#define __CONFIG_RK3066_COMMON_H
+
+#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_MALLOC_LEN (64 << 20)
+#define CONFIG_SYS_CBSIZE 256
+
+#define CONFIG_SYS_TIMER_RATE 24000000
+#define CONFIG_SYS_TIMER_BASE 0x20038000
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_TEXT_BASE 0x60408000
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
+#define CONFIG_SYS_LOAD_ADDR 0x70800800
+
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_TEXT_BASE 0x10080C04
+#define CONFIG_SPL_STACK 0x1008FFFF
+/* tpl size max 32kb - 4byte RK30 header */
+#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
+#elif defined(CONFIG_SPL_BUILD)
+/* spl size max 200k */
+#define CONFIG_SPL_MAX_SIZE 0x32000
+#define CONFIG_SPL_TEXT_BASE 0x60000000
+#define CONFIG_SPL_STACK 0x1008FFFF
+#define CONFIG_SPL_STACK_R_ADDR 0x70000000
+#define CONFIG_SPL_STACK_R 1
+#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
+#define CONFIG_SPL_OF_CONTROL 1
+#define CONFIG_SPL_OF_PLATDATA 1
+#define CONFIG_SPL_FRAMEWORK 1
+#define CONFIG_SPL_CLK 1
+#define CONFIG_SPL_PINCTRL 1
+#define CONFIG_SPL_REGMAP 1
+#define CONFIG_SPL_SYSCON 1
+#define CONFIG_SPL_RAM 1
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
+#define CONFIG_SPL_MMC_SUPPORT 1
+#define CONFIG_ROCKCHIP_SERIAL 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_LIBDISK_SUPPORT 1
+#define CONFIG_SPL_EXT_SUPPORT 1
+#define CONFIG_SPL_FAT_SUPPORT 1
+#define CONFIG_SPL_DM 1
+#define CONFIG_SPL_GPIO_SUPPORT 1
+#define CONFIG_SPL_POWER_SUPPORT 1
+#endif
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
+#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_NR_DRAM_BANKS 1
+#define SDRAM_BANK_SIZE (1024UL << 20UL)
+
+#ifndef CONFIG_SPL_BUILD
+/* usb */
+#define CONFIG_USB
+#define CONFIG_DM_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB2_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM 0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60000000\0" \
+ "pxefile_addr_r=0x60100000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x6fffffff\0" \
+ "initrd_high=0x6fffffff\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#include <config_distro_defaults.h>
+#endif
+
+#define CONFIG_PREBOOT
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (5 preceding siblings ...)
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
@ 2017-06-06 18:51 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:51 ` [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc Paweł Jarosz
` (5 subsequent siblings)
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:51 UTC (permalink / raw)
To: u-boot
mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
nand onboard.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3066a-mk808.dts | 172 ++++++++++++++++++++++++++++
board/rikomagic/mk808_rk3066/Kconfig | 15 +++
board/rikomagic/mk808_rk3066/MAINTAINERS | 6 +
board/rikomagic/mk808_rk3066/Makefile | 7 ++
board/rikomagic/mk808_rk3066/mk808_rk3066.c | 10 ++
configs/mk808-rk3066_defconfig | 54 +++++++++
include/configs/mk808_rk3066.h | 15 +++
8 files changed, 280 insertions(+)
create mode 100644 arch/arm/dts/rk3066a-mk808.dts
create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
create mode 100644 board/rikomagic/mk808_rk3066/Makefile
create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
create mode 100644 configs/mk808-rk3066_defconfig
create mode 100644 include/configs/mk808_rk3066.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aceb29e..ac0a1d9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3036-sdk.dtb \
+ rk3066a-mk808.dtb \
rk3188-radxarock.dtb \
rk3288-evb.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts
new file mode 100644
index 0000000..536a31a
--- /dev/null
+++ b/arch/arm/dts/rk3066a-mk808.dts
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "rk3066a.dtsi"
+
+/ {
+ model = "Rikomagic MK808";
+ compatible = "rikomagic,mk808", "rockchip,rk3066a";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory at 60000000 {
+ reg = <0x60000000 0x40000000>;
+ device_type = "memory";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "mk808:blue:power";
+ gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&host_drv>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-name = "host-pwr";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_otg: usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&otg_drv>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-name = "vcc_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdmmc_pwr>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_wifi: sdio-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&wifi_pwr>;
+ pinctrl-names = "default";
+ regulator-name = "vcc_wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&dmc {
+ compatible = "rockchip,rk3066-dmc", "syscon";
+ rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+ 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+ 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+ 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+ 0x4 0x0>;
+ rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+ 0x220 0x40 0x0 0x0>;
+ rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ num-slots = <1>;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_wifi>;
+ status = "okay";
+};
+
+&pinctrl {
+ usb-host {
+ host_drv: host-drv {
+ rockchip,pins = <RK_GPIO0 6 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ usb-otg {
+ otg_drv: otg-drv {
+ rockchip,pins = <RK_GPIO0 5 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <RK_GPIO3 7 RK_FUNC_GPIO &pcfg_pull_default>;
+ };
+ };
+
+ sdio {
+ wifi_pwr: wifi-pwr {
+ rockchip,pins = <RK_GPIO3 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+&usb_host {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/board/rikomagic/mk808_rk3066/Kconfig b/board/rikomagic/mk808_rk3066/Kconfig
new file mode 100644
index 0000000..0da0a17
--- /dev/null
+++ b/board/rikomagic/mk808_rk3066/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MK808_RK3066
+
+config SYS_BOARD
+ default "mk808_rk3066"
+
+config SYS_VENDOR
+ default "rikomagic"
+
+config SYS_CONFIG_NAME
+ default "mk808_rk3066"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rikomagic/mk808_rk3066/MAINTAINERS b/board/rikomagic/mk808_rk3066/MAINTAINERS
new file mode 100644
index 0000000..65b5cbd
--- /dev/null
+++ b/board/rikomagic/mk808_rk3066/MAINTAINERS
@@ -0,0 +1,6 @@
+MK808
+M: Paweł Jarosz <paweljarosz3691@gmail.com>
+S: Maintained
+F: include/configs/mk808_rk3066.h
+F: configs/mk808-rk3066_defconfig
+F: board/rikomagic/mk808_rk3066
diff --git a/board/rikomagic/mk808_rk3066/Makefile b/board/rikomagic/mk808_rk3066/Makefile
new file mode 100644
index 0000000..ef5ba56
--- /dev/null
+++ b/board/rikomagic/mk808_rk3066/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Paweł‚ Jarosz <paweljarosz3691@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mk808_rk3066.o
diff --git a/board/rikomagic/mk808_rk3066/mk808_rk3066.c b/board/rikomagic/mk808_rk3066/mk808_rk3066.c
new file mode 100644
index 0000000..e5d66fe
--- /dev/null
+++ b/board/rikomagic/mk808_rk3066/mk808_rk3066.c
@@ -0,0 +1,10 @@
+/*
+ * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
diff --git a/configs/mk808-rk3066_defconfig b/configs/mk808-rk3066_defconfig
new file mode 100644
index 0000000..d241d05
--- /dev/null
+++ b/configs/mk808-rk3066_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3066=y
+CONFIG_TARGET_MK808_RK3066=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
+CONFIG_CMD_REGULATOR=y
+CONFIG_CLK=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_RAM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+CONFIG_SYS_NS16550=y
+CONFIG_BOOTDELAY=1
+CONFIG_CONSOLE_MUX=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_CMD_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_MMC=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_EFI_PARTITION is not set
+CONFIG_CMD_BOOTEFI is not set
+CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_EFI_LOADER is not set
+CONFIG_CMD_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GENERIC=y
+CONFIG_PINCTRL_ROCKCHIP_RK3066=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x20064000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+# CONFIG_TPL_DM_SERIAL is not set
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+# CONFIG_TPL_SERIAL_SUPPORT is not set
+
diff --git a/include/configs/mk808_rk3066.h b/include/configs/mk808_rk3066.h
new file mode 100644
index 0000000..974e328
--- /dev/null
+++ b/include/configs/mk808_rk3066.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+
+#include <configs/rk3066_common.h>
+
+#endif
+
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (6 preceding siblings ...)
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
@ 2017-06-06 18:51 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,08/13] " Philipp Tomsich
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
` (4 subsequent siblings)
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:51 UTC (permalink / raw)
To: u-boot
rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
internal dma support and max driver frequency.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
drivers/mmc/rockchip_dw_mmc.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 25a21e2..d94c395 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
struct rockchip_mmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
+
+#ifdef CONFIG_ROCKCHIP_RK3066
+ struct dtd_rockchip_rk2928_dw_mshc dtplat;
+#else
struct dtd_rockchip_rk3288_dw_mshc dtplat;
#endif
+
+#endif
struct mmc_config cfg;
struct mmc mmc;
};
@@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
+#ifdef CONFIG_ROCKCHIP_RK3066
+ struct dtd_rockchip_rk2928_dw_mshc *dtplat = &plat->dtplat;
+#else
struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
-
+#endif
host->name = dev->name;
host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
host->buswidth = dtplat->bus_width;
@@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
host->priv = dev;
host->dev_index = 0;
priv->fifo_depth = dtplat->fifo_depth;
+
+#ifdef CONFIG_ROCKCHIP_RK3066
+ priv->fifo_mode = 1;
+#else
priv->fifo_mode = 0;
+#endif
memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
@@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
}
static const struct udevice_id rockchip_dwmmc_ids[] = {
+ { .compatible = "rockchip,rk2928-dw-mshc" },
{ .compatible = "rockchip,rk3288-dw-mshc" },
{ }
};
+U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
+ .name = "rockchip_rk2928_dw_mshc",
+ .id = UCLASS_MMC,
+ .of_match = rockchip_dwmmc_ids,
+ .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+ .ops = &dm_dwmci_ops,
+ .bind = rockchip_dwmmc_bind,
+ .probe = rockchip_dwmmc_probe,
+ .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+};
+
U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
.name = "rockchip_rk3288_dw_mshc",
.id = UCLASS_MMC,
- .of_match = rockchip_dwmmc_ids,
+ .of_match = rockchip_dwmmc_ids + 1,
.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
.ops = &dm_dwmci_ops,
.bind = rockchip_dwmmc_bind,
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (7 preceding siblings ...)
2017-06-06 18:51 ` [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc Paweł Jarosz
@ 2017-06-06 18:52 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
` (3 subsequent siblings)
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:52 UTC (permalink / raw)
To: u-boot
rk3066 and rk3188 designware mmc ip doesn't support internal dma
transfer mode. So set fifo mode as default.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/dts/rk3xxx.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi
index 6d9e36d..4a32e27 100644
--- a/arch/arm/dts/rk3xxx.dtsi
+++ b/arch/arm/dts/rk3xxx.dtsi
@@ -192,6 +192,7 @@
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <256>;
+ fifo-mode;
status = "disabled";
};
@@ -202,6 +203,7 @@
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
clock-names = "biu", "ciu";
fifo-depth = <256>;
+ fifo-mode;
status = "disabled";
};
@@ -212,6 +214,7 @@
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <256>;
+ fifo-mode;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (8 preceding siblings ...)
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
@ 2017-06-06 18:52 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:53 ` [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066 Paweł Jarosz
` (2 subsequent siblings)
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:52 UTC (permalink / raw)
To: u-boot
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/mach-rockchip/rk3066/Makefile | 1 +
arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++
2 files changed, 112 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
index 4cf5df2..1d38518 100644
--- a/arch/arm/mach-rockchip/rk3066/Makefile
+++ b/arch/arm/mach-rockchip/rk3066/Makefile
@@ -6,6 +6,7 @@
ifndef CONFIG_TPL_BUILD
obj-y += clk_rk3066.o
+obj-y += sdram_rk3066.o
obj-y += syscon_rk3066.o
else
obj-y += sdram_init.o
diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
new file mode 100644
index 0000000..a713ac4
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Adapted from the very similar rk3288 ddr init.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <errno.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/ddr_rk3188.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/sdram.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dram_info {
+ struct ram_info info;
+ struct rk3188_pmu *pmu;
+};
+
+size_t sdram_size_mb(struct rk3188_pmu *pmu)
+{
+ u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+ size_t chipsize_mb = 0;
+ size_t size_mb = 0;
+ u32 ch;
+ u32 sys_reg = readl(&pmu->sys_reg[2]);
+ u32 chans;
+
+ chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
+
+ for (ch = 0; ch < chans; ch++) {
+ rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
+ SYS_REG_RANK_MASK);
+ col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+ bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+ cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
+ SYS_REG_CS0_ROW_MASK);
+ cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
+ SYS_REG_CS1_ROW_MASK);
+ bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+ SYS_REG_BW_MASK));
+ row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
+ SYS_REG_ROW_3_4_MASK;
+ chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+ if (rank > 1)
+ chipsize_mb += chipsize_mb >>
+ (cs0_row - cs1_row);
+ if (row_3_4)
+ chipsize_mb = chipsize_mb * 3 / 4;
+ size_mb += chipsize_mb;
+ }
+
+ /* there can be no more than 2gb of memory */
+ size_mb = min(size_mb, 0x80000000 >> 20);
+
+ return size_mb;
+}
+
+static int rk3066_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = sdram_size_mb(priv->pmu) << 20;
+
+ return 0;
+}
+
+static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3066_dmc_ops = {
+ .get_info = rk3066_dmc_get_info,
+};
+
+static const struct udevice_id rk3066_dmc_ids[] = {
+ { .compatible = "rockchip,rk3066-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3066) = {
+ .name = "rockchip_rk3066_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3066_dmc_ids,
+ .ops = &rk3066_dmc_ops,
+ .probe = rk3066_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (9 preceding siblings ...)
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
@ 2017-06-06 18:53 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
2017-06-06 18:53 ` [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl Paweł Jarosz
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:53 UTC (permalink / raw)
To: u-boot
update driver to support rk3066 serial
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
drivers/serial/serial_rockchip.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
index 734cee2..e7be2ea 100644
--- a/drivers/serial/serial_rockchip.c
+++ b/drivers/serial/serial_rockchip.c
@@ -12,7 +12,14 @@
#include <serial.h>
#include <asm/arch/clock.h>
-#if defined(CONFIG_ROCKCHIP_RK3188)
+
+#if defined(CONFIG_ROCKCHIP_RK3066)
+struct rockchip_uart_platdata {
+ struct dtd_rockchip_rk3066_uart dtplat;
+ struct ns16550_platdata plat;
+};
+struct dtd_rockchip_rk3066_uart *dtplat, s_dtplat;
+#elif defined(CONFIG_ROCKCHIP_RK3188)
struct rockchip_uart_platdata {
struct dtd_rockchip_rk3188_uart dtplat;
struct ns16550_platdata plat;
@@ -40,6 +47,16 @@ static int rockchip_serial_probe(struct udevice *dev)
return ns16550_serial_probe(dev);
}
+U_BOOT_DRIVER(rockchip_rk3066_uart) = {
+ .name = "rockchip_rk3066_uart",
+ .id = UCLASS_SERIAL,
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata),
+ .probe = rockchip_serial_probe,
+ .ops = &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
U_BOOT_DRIVER(rockchip_rk3188_uart) = {
.name = "rockchip_rk3188_uart",
.id = UCLASS_SERIAL,
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (10 preceding siblings ...)
2017-06-06 18:53 ` [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066 Paweł Jarosz
@ 2017-06-06 18:53 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
` (2 more replies)
2017-06-06 18:53 ` [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl Paweł Jarosz
12 siblings, 3 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:53 UTC (permalink / raw)
To: u-boot
Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
executes it. Then waits for back to bootrom and loads another 32KB to sram
which also executes. Sdram initialisation code needs to be in one of these two
steps. Then bootloader loads another ~200KB of data at offset 0x60000000
and jumps to it.
32KB of data is a little low for tpl + spl part and ~200KB data is to low for
u-boot part(for example to boot from mmc you need to disable usb support.
My solution to size problem is to move sdram initialisation code to tpl stage,
move spl part to third stage(reading 200KB data) and add support for loading
u-boot by spl from ext2/4, fat partitions.
But moving sdram initialisation code to tpl increases size of tpl above 1KB
(first boot stage). Solution to this is to add code which will be below 1KB
offset in tpl binary and do back to bootrom at very beginning of the tpl
execution.
Adding this few lines of code here meets these conditions.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/cpu/armv7/start.S | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f06fd28..73e03d9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -36,6 +36,19 @@
#endif
reset:
+
+#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
+ ldr r3, =0x10080900
+ ldr r0, [r3]
+ cmp r0, #1
+ movne r0, #1
+ strne r0, [r3]
+ beq out_of_bootrom
+ bx lr
+out_of_bootrom:
+ mov r0, #0
+ str r0, [r3]
+#endif
/* Allow the board to save important registers */
b save_boot_params
save_boot_params_ret:
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
` (11 preceding siblings ...)
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
@ 2017-06-06 18:53 ` Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
12 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-06 18:53 UTC (permalink / raw)
To: u-boot
Add sdram initialisation code which will be ussed by tpl first boot stage.
We need to implement sdram initialisation in tpl due to size issues on rk3066
platform.
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
arch/arm/mach-rockchip/rk3066/sdram_init.c | 995 ++++++++++++++++++++++++
2 files changed, 1000 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
index 3d7929f..74d11c6 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
@@ -10,6 +10,11 @@
#include <asm/arch/ddr_rk3288.h>
/*
+ * RK3066 Tpl memory init.
+ */
+void sdram_initialise(void);
+
+/*
* RK3188 Memory scheduler register map.
*/
struct rk3188_msch {
diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c b/arch/arm/mach-rockchip/rk3066/sdram_init.c
new file mode 100644
index 0000000..e7e506a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
@@ -0,0 +1,995 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Adapted from the very similar rk3288 ddr init.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <errno.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3066.h>
+#include <asm/arch/ddr_rk3188.h>
+#include <asm/arch/grf_rk3066.h>
+#include <asm/arch/pmu_rk3188.h>
+#include <asm/arch/sdram.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pll_div {
+ u32 nr;
+ u32 nf;
+ u32 no;
+};
+
+enum {
+ VCO_MAX_HZ = 1416U * 1000000,
+ VCO_MIN_HZ = 300 * 1000000,
+ OUTPUT_MAX_HZ = 1416U * 1000000,
+ OUTPUT_MIN_HZ = 30 * 1000000,
+ FREF_MAX_HZ = 1416U * 1000000,
+ FREF_MIN_HZ = 30 * 1000,
+};
+
+enum {
+ /* PLL CON0 */
+ PLL_OD_MASK = 0x0f,
+
+ /* PLL CON1 */
+ PLL_NF_MASK = 0x1fff,
+
+ /* PLL CON2 */
+ PLL_BWADJ_MASK = 0x0fff,
+
+ /* PLL CON3 */
+ PLL_RESET_SHIFT = 5,
+
+ /* GRF_SOC_STATUS0 */
+ SOCSTS_DPLL_LOCK = 1 << 4,
+ SOCSTS_APLL_LOCK = 1 << 5,
+ SOCSTS_CPLL_LOCK = 1 << 6,
+ SOCSTS_GPLL_LOCK = 1 << 7,
+};
+
+#define CRU_BASE 0x20000000
+#define GRF_BASE 0x20008000
+#define PMU_BASE 0x20004000
+#define PCTL_BASE 0x20020000
+#define PUBL_BASE 0x20040000
+#define NOC_BASE 0x10128000
+
+#define RK3066_PCTL_TIMING_DEFAULT { \
+ .togcnt1u = 0x12c, \
+ .tinit = 0xc8, \
+ .trsth = 0x1f4, \
+ .togcnt100n = 0x1e, \
+ .trefi = 0x4e, \
+ .tmrd = 0x4, \
+ .trfc = 0x69, \
+ .trp = 0x6, \
+ .trtw = 0x3, \
+ .tal = 0x0, \
+ .tcl = 0x6, \
+ .tcwl = 0x5, \
+ .tras = 0xc, \
+ .trc = 0x10, \
+ .trcd = 0x6, \
+ .trrd = 0x4, \
+ .trtp = 0x4, \
+ .twr = 0x5, \
+ .twtr = 0x4, \
+ .texsr = 0x200, \
+ .txp = 0x3, \
+ .txpdll = 0xa, \
+ .tzqcs = 0x40, \
+ .tzqcsi = 0x0, \
+ .tdqs = 0x1, \
+ .tcksre = 0x5, \
+ .tcksrx = 0x5, \
+ .tcke = 0x3, \
+ .tmod = 0xc, \
+ .trstl = 0x1e, \
+ .tzqcl = 0x100, \
+ .tmrr = 0x0, \
+ .tckesr = 0x4, \
+ .tdpd = 0x0 \
+}
+
+#define RK3066_PHY_TIMING_DEFAULT { \
+ .dtpr0 = 0x208c6690, \
+ .dtpr1 = 0x690878, \
+ .dtpr2 = 0x10022a00, \
+ .mr = { 0x220, 0x40, 0x0, 0x0 } \
+}
+
+#define RK3066_SDRAM_PARAMS_DEFAULT { \
+ .noc_timing = 0x24716310, \
+ .noc_activate = 0, \
+ .ddrconfig = 2, \
+ .ddr_freq = 300000000, \
+ .dramtype = 3, \
+ .stride = 9, \
+ .odt = 0 \
+}
+
+#ifndef RK3066_PCTL_TIMING
+#define RK3066_PCTL_TIMING RK3066_PCTL_TIMING_DEFAULT
+#endif
+
+#ifndef RK3066_PHY_TIMING
+#define RK3066_PHY_TIMING RK3066_PHY_TIMING_DEFAULT
+#endif
+
+#ifndef RK3066_SDRAM_PARAMS
+#define RK3066_SDRAM_PARAMS RK3066_SDRAM_PARAMS_DEFAULT
+#endif
+
+struct chan_info {
+ struct rk3288_ddr_pctl *pctl;
+ struct rk3288_ddr_publ *publ;
+ struct rk3188_msch *msch;
+};
+
+struct dram_info {
+ struct chan_info chan[1];
+ struct ram_info info;
+ struct rk3066_cru *cru;
+ struct rk3066_grf *grf;
+ struct rk3188_pmu *pmu;
+};
+
+struct rk3066_sdram_params {
+ struct rk3288_sdram_channel ch[2];
+ struct rk3288_sdram_pctl_timing pctl_timing;
+ struct rk3288_sdram_phy_timing phy_timing;
+ struct rk3288_base_params base;
+ int num_channels;
+ struct regmap *map;
+};
+
+const int ddrconf_table[] = {
+ /*
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ * row col,bw
+ */
+ 0,
+ ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+ ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+};
+
+#define TEST_PATTEN 0x5aa5f00f
+#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
+#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
+
+
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
+{
+ u32 phy_ctl_srstn_shift = 13;
+ u32 ctl_psrstn_shift = 11;
+ u32 ctl_srstn_shift = 10;
+ u32 phy_psrstn_shift = 9;
+ u32 phy_srstn_shift = 8;
+
+ rk_clrsetreg(&cru->cru_softrst_con[5],
+ 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
+ 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
+ 1 << phy_srstn_shift,
+ phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
+ ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
+ phy << phy_srstn_shift);
+}
+
+static void ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
+{
+ u32 phy_ctl_srstn_shift = 13;
+
+ rk_clrsetreg(&cru->cru_softrst_con[5],
+ 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
+}
+
+static void phy_pctrl_reset(struct rk3066_cru *cru,
+ struct rk3288_ddr_publ *publ,
+ int channel)
+{
+ int i;
+
+ ddr_reset(cru, channel, 1, 1);
+ udelay(1);
+ clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
+ for (i = 0; i < 4; i++)
+ clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+ udelay(10);
+ setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
+ for (i = 0; i < 4; i++)
+ setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
+
+ udelay(10);
+ ddr_reset(cru, channel, 1, 0);
+ udelay(10);
+ ddr_reset(cru, channel, 0, 0);
+ udelay(10);
+}
+
+static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
+ u32 freq)
+{
+ int i;
+
+ if (freq <= 250000000) {
+ if (freq <= 150000000)
+ clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+ else
+ setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+ setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
+ for (i = 0; i < 4; i++)
+ setbits_le32(&publ->datx8[i].dxdllcr,
+ DXDLLCR_DLLDIS);
+
+ setbits_le32(&publ->pir, PIR_DLLBYP);
+ } else {
+ clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
+ clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
+ for (i = 0; i < 4; i++) {
+ clrbits_le32(&publ->datx8[i].dxdllcr,
+ DXDLLCR_DLLDIS);
+ }
+
+ clrbits_le32(&publ->pir, PIR_DLLBYP);
+ }
+}
+
+static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
+{
+ writel(DFI_INIT_START, &pctl->dfistcfg0);
+ writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
+ &pctl->dfistcfg1);
+ writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+ writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+ &pctl->dfilpcfg0);
+
+ writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
+ writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
+ writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
+ writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
+ writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
+ writel(1, &pctl->dfitphyupdtype0);
+
+ /* cs0 and cs1 write odt enable */
+ writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
+ &pctl->dfiodtcfg);
+ /* odt write length */
+ writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+ /* phyupd and ctrlupd disabled */
+ writel(0, &pctl->dfiupdcfg);
+}
+
+static void ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel,
+ bool ddr3_mode)
+{
+ uint mask, val;
+
+ mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
+ val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
+ rk_clrsetreg(&grf->soc_con2, mask, val);
+}
+
+static void ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable)
+{
+ uint mask, val;
+
+ mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
+ val = enable << RANK_TO_ROW15_EN_SHIFT;
+ rk_clrsetreg(&grf->soc_con2, mask, val);
+}
+
+static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
+ struct rk3066_sdram_params *sdram_params,
+ struct rk3066_grf *grf)
+{
+ copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
+ sizeof(sdram_params->pctl_timing));
+ switch (sdram_params->base.dramtype) {
+ case DDR3:
+ if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
+ writel(sdram_params->pctl_timing.tcl - 3,
+ &pctl->dfitrddataen);
+ } else {
+ writel(sdram_params->pctl_timing.tcl - 2,
+ &pctl->dfitrddataen);
+ }
+ writel(sdram_params->pctl_timing.tcwl - 1,
+ &pctl->dfitphywrlat);
+ writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
+ DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
+ 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
+ &pctl->mcfg);
+ ddr_set_ddr3_mode(grf, channel, true);
+ break;
+ }
+
+ setbits_le32(&pctl->scfg, 1);
+}
+
+static void phy_cfg(const struct chan_info *chan, int channel,
+ struct rk3066_sdram_params *sdram_params)
+{
+ struct rk3288_ddr_publ *publ = chan->publ;
+ struct rk3188_msch *msch = chan->msch;
+ uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
+ u32 dinit2;
+ int i;
+
+ dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
+ /* DDR PHY Timing */
+ copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
+ sizeof(sdram_params->phy_timing));
+ writel(sdram_params->base.noc_timing, &msch->ddrtiming);
+ writel(0x3f, &msch->readlatency);
+ writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
+ DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
+ 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
+ writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
+ DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
+ &publ->ptr[1]);
+ writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
+ DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
+ &publ->ptr[2]);
+
+ switch (sdram_params->base.dramtype) {
+ case DDR3:
+ clrbits_le32(&publ->pgcr, 0x1f);
+ clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
+ DDRMD_DDR3 << DDRMD_SHIFT);
+ break;
+ }
+ if (sdram_params->base.odt) {
+ /*dynamic RTT enable */
+ for (i = 0; i < 4; i++)
+ setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
+ } else {
+ /*dynamic RTT disable */
+ for (i = 0; i < 4; i++)
+ clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
+ }
+}
+
+static void phy_init(struct rk3288_ddr_publ *publ)
+{
+ setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
+ | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
+ udelay(1);
+ while ((readl(&publ->pgsr) &
+ (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
+ (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
+ ;
+}
+
+static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
+ u32 cmd, u32 arg)
+{
+ writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
+ udelay(1);
+ while (readl(&pctl->mcmd) & START_CMD)
+ ;
+}
+
+static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
+ u32 rank, u32 cmd, u32 ma, u32 op)
+{
+ send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
+ (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
+}
+
+static void memory_init(struct rk3288_ddr_publ *publ,
+ u32 dramtype)
+{
+ setbits_le32(&publ->pir,
+ (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
+ | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
+ | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
+ udelay(1);
+ while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
+ != (PGSR_IDONE | PGSR_DLDONE))
+ ;
+}
+
+static void move_to_config_state(struct rk3288_ddr_publ *publ,
+ struct rk3288_ddr_pctl *pctl)
+{
+ unsigned int state;
+
+ while (1) {
+ state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK)
+ != ACCESS)
+ ;
+ /* wait DLL lock */
+ while ((readl(&publ->pgsr) & PGSR_DLDONE)
+ != PGSR_DLDONE)
+ ;
+ /*
+ * if at low power state,need wakeup first,
+ * and then enter the config, so
+ * fallthrough
+ */
+ case ACCESS:
+ /* fallthrough */
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ ;
+ break;
+ case CONFIG:
+ return;
+ default:
+ break;
+ }
+ }
+}
+
+static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
+ u32 n, struct rk3066_grf *grf)
+{
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+ struct rk3288_ddr_publ *publ = chan->publ;
+ struct rk3188_msch *msch = chan->msch;
+
+ if (n == 1) {
+ setbits_le32(&pctl->ppcfg, 1);
+ setbits_le32(&msch->ddrtiming, 1 << 31);
+ /* Data Byte disable*/
+ clrbits_le32(&publ->datx8[2].dxgcr, 1);
+ clrbits_le32(&publ->datx8[3].dxgcr, 1);
+ /* disable DLL */
+ setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
+ setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
+ } else {
+ clrbits_le32(&pctl->ppcfg, 1);
+ clrbits_le32(&msch->ddrtiming, 1 << 31);
+ /* Data Byte enable*/
+ setbits_le32(&publ->datx8[2].dxgcr, 1);
+ setbits_le32(&publ->datx8[3].dxgcr, 1);
+
+ /* enable DLL */
+ clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
+ clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
+ /* reset DLL */
+ clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
+ clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
+ udelay(10);
+ setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
+ setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
+ }
+ setbits_le32(&pctl->dfistcfg0, 1 << 2);
+}
+
+static int data_training(const struct chan_info *chan, int channel,
+ struct rk3066_sdram_params *sdram_params)
+{
+ unsigned int j;
+ int ret = 0;
+ u32 rank;
+ int i;
+ u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
+ struct rk3288_ddr_publ *publ = chan->publ;
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+
+ /* disable auto refresh */
+ writel(0, &pctl->trefi);
+
+ if (sdram_params->base.dramtype != LPDDR3)
+ setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
+ rank = sdram_params->ch[channel].rank | 1;
+ for (j = 0; j < ARRAY_SIZE(step); j++) {
+ /*
+ * trigger QSTRN and RVTRN
+ * clear DTDONE status
+ */
+ setbits_le32(&publ->pir, PIR_CLRSR);
+
+ /* trigger DTT */
+ setbits_le32(&publ->pir,
+ PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
+ PIR_CLRSR);
+ udelay(1);
+ /* wait echo byte DTDONE */
+ while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
+ != rank)
+ ;
+ while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
+ != rank)
+ ;
+ if (!(readl(&pctl->ppcfg) & 1)) {
+ while ((readl(&publ->datx8[2].dxgsr[0])
+ & rank) != rank)
+ ;
+ while ((readl(&publ->datx8[3].dxgsr[0])
+ & rank) != rank)
+ ;
+ }
+ if (readl(&publ->pgsr) &
+ (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
+ ret = -1;
+ break;
+ }
+ }
+ /* send some auto refresh to complement the lost while DTT */
+ for (i = 0; i < (rank > 1 ? 8 : 4); i++)
+ send_command(pctl, rank, REF_CMD, 0);
+
+ if (sdram_params->base.dramtype != LPDDR3)
+ clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
+
+ /* resume auto refresh */
+ writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
+
+ return ret;
+}
+
+static void move_to_access_state(const struct chan_info *chan)
+{
+ struct rk3288_ddr_publ *publ = chan->publ;
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+ unsigned int state;
+
+ while (1) {
+ state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
+ LP_TRIG_MASK) == 1)
+ return;
+
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+ ;
+ /* wait DLL lock */
+ while ((readl(&publ->pgsr) & PGSR_DLDONE)
+ != PGSR_DLDONE)
+ ;
+ break;
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ ;
+ /* fallthrough */
+ case CONFIG:
+ writel(GO_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
+ ;
+ break;
+ case ACCESS:
+ return;
+ default:
+ break;
+ }
+ }
+}
+
+static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
+ struct rk3066_sdram_params *sdram_params)
+{
+ struct rk3288_ddr_publ *publ = chan->publ;
+
+ if (sdram_params->ch[chnum].bk == 3)
+ clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
+ 1 << PDQ_SHIFT);
+ else
+ clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
+
+ writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
+}
+
+static void dram_all_config(const struct dram_info *dram,
+ struct rk3066_sdram_params *sdram_params)
+{
+ unsigned int chan;
+ u32 sys_reg = 0;
+
+ sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+ sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
+ for (chan = 0; chan < sdram_params->num_channels; chan++) {
+ const struct rk3288_sdram_channel *info =
+ &sdram_params->ch[chan];
+
+ sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
+ sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+ sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
+ sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
+ sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+ sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
+ sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
+ sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+ sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
+
+ dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
+ }
+ if (sdram_params->ch[0].rank == 2)
+ ddr_rank_2_row15en(dram->grf, 0);
+ else
+ ddr_rank_2_row15en(dram->grf, 1);
+
+ writel(sys_reg, &dram->pmu->sys_reg[2]);
+}
+
+static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
+ struct rk3066_sdram_params *sdram_params)
+{
+ int reg;
+ int need_trainig = 0;
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3288_ddr_publ *publ = chan->publ;
+
+ ddr_rank_2_row15en(dram->grf, 0);
+
+ if (data_training(chan, channel, sdram_params) < 0) {
+ reg = readl(&publ->datx8[0].dxgsr[0]);
+ /* Check the result for rank 0 */
+ if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
+ return -EIO;
+ }
+
+ /* Check the result for rank 1 */
+ if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
+ sdram_params->ch[channel].rank = 1;
+ clrsetbits_le32(&publ->pgcr, 0xF << 18,
+ sdram_params->ch[channel].rank << 18);
+ need_trainig = 1;
+ }
+ reg = readl(&publ->datx8[2].dxgsr[0]);
+ if (reg & (1 << 4)) {
+ sdram_params->ch[channel].bw = 1;
+ set_bandwidth_ratio(chan, channel,
+ sdram_params->ch[channel].bw,
+ dram->grf);
+ need_trainig = 1;
+ }
+ }
+ /* Assume the Die bit width are the same with the chip bit width */
+ sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
+
+ if (need_trainig &&
+ (data_training(chan, channel, sdram_params) < 0)) {
+ if (sdram_params->base.dramtype == LPDDR3) {
+ ddr_phy_ctl_reset(dram->cru, channel, 1);
+ udelay(10);
+ ddr_phy_ctl_reset(dram->cru, channel, 0);
+ udelay(10);
+ }
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/*
+ * Detect ram columns and rows.
+ * @dram: dram info struct
+ * @channel: channel number to handle
+ * @sdram_params: sdram parameters, function will fill in col and row values
+ *
+ * Returns 0 or negative on error.
+ */
+static int sdram_col_row_detect(struct dram_info *dram, int channel,
+ struct rk3066_sdram_params *sdram_params)
+{
+ int row, col;
+ unsigned int addr;
+ const struct chan_info *chan = &dram->chan[channel];
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+ struct rk3288_ddr_publ *publ = chan->publ;
+ int ret = 0;
+
+ /* Detect col */
+ for (col = 11; col >= 9; col--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE +
+ (1 << (col + sdram_params->ch[channel].bw - 1));
+ writel(TEST_PATTEN, addr);
+ if ((readl(addr) == TEST_PATTEN) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+ if (col == 8) {
+ ret = -EINVAL;
+ goto out;
+ } else {
+ sdram_params->ch[channel].col = col;
+ }
+
+ ddr_rank_2_row15en(dram->grf, 1);
+ move_to_config_state(publ, pctl);
+ writel(1, &chan->msch->ddrconf);
+ move_to_access_state(chan);
+ /* Detect row, max 15,min13 in rk3066*/
+ for (row = 16; row >= 13; row--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(TEST_PATTEN, addr);
+ if ((readl(addr) == TEST_PATTEN) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+ if (row == 12) {
+ ret = -EINVAL;
+ } else {
+ sdram_params->ch[channel].cs1_row = row;
+ sdram_params->ch[channel].row_3_4 = 0;
+ sdram_params->ch[channel].cs0_row = row;
+ }
+
+out:
+ return ret;
+}
+
+static int sdram_get_niu_config(struct rk3066_sdram_params *sdram_params)
+{
+ int i, tmp, size, ret = 0;
+
+ tmp = sdram_params->ch[0].col - 9;
+ tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
+ tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
+ size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
+ for (i = 0; i < size; i++)
+ if (tmp == ddrconf_table[i])
+ break;
+ if (i >= size) {
+ ret = -EINVAL;
+ } else {
+ sdram_params->base.ddrconfig = i;
+ }
+
+ return ret;
+}
+
+size_t sdram_size_mb(struct rk3188_pmu *pmu)
+{
+ u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+ size_t chipsize_mb = 0;
+ size_t size_mb = 0;
+ u32 ch;
+ u32 sys_reg = readl(&pmu->sys_reg[2]);
+ u32 chans;
+
+ chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
+
+ for (ch = 0; ch < chans; ch++) {
+ rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
+ SYS_REG_RANK_MASK);
+ col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+ bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+ cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
+ SYS_REG_CS0_ROW_MASK);
+ cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
+ SYS_REG_CS1_ROW_MASK);
+ bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+ SYS_REG_BW_MASK));
+ row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
+ SYS_REG_ROW_3_4_MASK;
+ chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+ if (rank > 1)
+ chipsize_mb += chipsize_mb >>
+ (cs0_row - cs1_row);
+ if (row_3_4)
+ chipsize_mb = chipsize_mb * 3 / 4;
+ size_mb += chipsize_mb;
+ }
+
+ /* there can be no more than 2gb of memory */
+ size_mb = min(size_mb, 0x80000000 >> 20);
+
+ return size_mb;
+}
+
+static int rkclk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div, bool has_bwadj)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3066_pll *pll = &cru->pll[pll_id];
+ /* All PLLs have same VCO and output frequency range restrictions. */
+
+ /* enter reset */
+ rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
+ ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
+ rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
+
+ if (has_bwadj)
+ rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
+ udelay(10);
+
+ /* return from reset */
+ rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
+
+ return 0;
+}
+
+static int rkclk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf,
+ unsigned int hz, bool has_bwadj)
+{
+ static const struct pll_div dpll_cfg[] = {
+ {.nf = 25, .nr = 2, .no = 1},
+ {.nf = 400, .nr = 9, .no = 2},
+ {.nf = 500, .nr = 9, .no = 2},
+ {.nf = 100, .nr = 3, .no = 1},
+ };
+ int cfg;
+
+ switch (hz) {
+ case 300000000:
+ cfg = 0;
+ break;
+ case 533000000: /* actually 533.3P MHz */
+ cfg = 1;
+ break;
+ case 666000000: /* actually 666.6P MHz */
+ cfg = 2;
+ break;
+ case 800000000:
+ cfg = 3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+
+ rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
+
+ /* wait for pll lock */
+ while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
+ udelay(1);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
+
+ return 0;
+}
+
+void sdram_initialise(void)
+{
+ struct dram_info dram;
+ struct rk3066_sdram_params sdram_params = {
+ .pctl_timing = RK3066_PCTL_TIMING,
+ .phy_timing = RK3066_PHY_TIMING,
+ .base = RK3066_SDRAM_PARAMS
+ };
+ int channel = 0;
+ int zqcr;
+ int ret;
+
+ dram.cru = (void *)CRU_BASE;
+ dram.grf = (void *)GRF_BASE;
+ dram.pmu = (void *)PMU_BASE;
+ dram.chan[0].pctl = (void *)PCTL_BASE;
+ dram.chan[0].publ = (void *)PUBL_BASE;
+ dram.chan[0].msch = (void *)NOC_BASE;
+ dram.info.base = CONFIG_SYS_SDRAM_BASE;
+ dram.info.size = sdram_size_mb(dram.pmu) << 20;
+ sdram_params.num_channels = 1;
+
+ if ((sdram_params.base.dramtype == DDR3 &&
+ sdram_params.base.ddr_freq > 800000000)) {
+ return;
+ }
+
+ rkclk_configure_ddr(dram.cru, dram.grf, sdram_params.base.ddr_freq, 1);
+
+ const struct chan_info *chan = &dram.chan[channel];
+ struct rk3288_ddr_pctl *pctl = chan->pctl;
+ struct rk3288_ddr_publ *publ = chan->publ;
+
+ phy_pctrl_reset(dram.cru, publ, channel);
+ phy_dll_bypass_set(publ, sdram_params.base.ddr_freq);
+
+ dfi_cfg(pctl, sdram_params.base.dramtype);
+
+ pctl_cfg(channel, pctl, &sdram_params, dram.grf);
+
+ phy_cfg(chan, channel, &sdram_params);
+
+ phy_init(publ);
+
+ writel(POWER_UP_START, &pctl->powctl);
+ while (!(readl(&pctl->powstat) & POWER_UP_DONE))
+ ;
+
+ memory_init(publ, sdram_params.base.dramtype);
+ move_to_config_state(publ, pctl);
+
+ /* Using 32bit bus width for detect */
+ sdram_params.ch[channel].bw = 2;
+ set_bandwidth_ratio(chan, channel,
+ sdram_params.ch[channel].bw, dram.grf);
+ /*
+ * set cs, using n=3 for detect
+ * CS0, n=1
+ * CS1, n=2
+ * CS0 & CS1, n = 3
+ */
+ sdram_params.ch[channel].rank = 2,
+ clrsetbits_le32(&publ->pgcr, 0xF << 18,
+ (sdram_params.ch[channel].rank | 1) << 18);
+
+ /* DS=40ohm,ODT=155ohm */
+ zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
+ 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
+ 0x19 << PD_OUTPUT_SHIFT;
+ writel(zqcr, &publ->zq1cr[0]);
+ writel(zqcr, &publ->zq0cr[0]);
+
+ /* Detect the rank and bit-width with data-training */
+ writel(1, &chan->msch->ddrconf);
+ sdram_rank_bw_detect(&dram, channel, &sdram_params);
+
+ if (sdram_params.base.dramtype == LPDDR3) {
+ u32 i;
+ writel(0, &pctl->mrrcfg0);
+ for (i = 0; i < 17; i++)
+ send_command_op(pctl, 1, MRR_CMD, i, 0);
+ }
+ writel(4, &chan->msch->ddrconf);
+ move_to_access_state(chan);
+ /* DDR3 and LPDDR3 are always 8 bank, no need detect */
+ sdram_params.ch[channel].bk = 3;
+ /* Detect Col and Row number*/
+ ret = sdram_col_row_detect(&dram, channel, &sdram_params);
+ if (ret)
+ goto error;
+
+ /* Find NIU DDR configuration */
+ ret = sdram_get_niu_config(&sdram_params);
+ if (ret)
+ goto error;
+
+ dram_all_config(&dram, &sdram_params);
+
+ return;
+error:
+ hang();
+}
+
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
@ 2017-06-06 21:09 ` Simon Glass
2017-06-07 15:07 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot,01/13] " Philipp Tomsich
1 sibling, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:09 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:48, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> grf is needed by various drivers for rk3066 soc.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++
> 1 file changed, 621 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
> new file mode 100644
> index 0000000..96b4ca6
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
> @@ -0,0 +1,621 @@
> +/*
> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef _ASM_ARCH_GRF_RK3066_H
> +#define _ASM_ARCH_GRF_RK3066_H
> +
> +struct rk3066_grf_gpio_lh {
> + u32 l;
> + u32 h;
> +};
> +
> +struct rk3066_grf {
> + struct rk3066_grf_gpio_lh gpio_dir[7];
> + struct rk3066_grf_gpio_lh gpio_do[7];
> + struct rk3066_grf_gpio_lh gpio_en[7];
> +
> + u32 gpio0a_iomux;
> + u32 gpio0b_iomux;
> + u32 gpio0c_iomux;
> + u32 gpio0d_iomux;
> +
> + u32 gpio1a_iomux;
> + u32 gpio1b_iomux;
> + u32 gpio1c_iomux;
> + u32 gpio1d_iomux;
> +
> + u32 gpio2a_iomux;
> + u32 gpio2b_iomux;
> + u32 gpio2c_iomux;
> + u32 gpio2d_iomux;
> +
> + u32 gpio3a_iomux;
> + u32 gpio3b_iomux;
> + u32 gpio3c_iomux;
> + u32 gpio3d_iomux;
> +
> + u32 gpio4a_iomux;
> + u32 gpio4b_iomux;
> + u32 gpio4c_iomux;
> + u32 gpio4d_iomux;
> +
> + u32 reserved0[5];
> +
> + u32 gpio6b_iomux;
> +
> + u32 reserved1[2];
> +
> + struct rk3066_grf_gpio_lh gpio_pull[7];
> +
> + u32 soc_con0;
> + u32 soc_con1;
> + u32 soc_con2;
> +
> + u32 soc_status0;
> +
> + u32 dmac1_con[3];
> + u32 dmac2_con[4];
> +
> + u32 uoc0_con[3];
> + u32 uoc1_con[4];
> + u32 ddrc_con;
> + u32 ddrc_stat;
> +
> + u32 reserved2[10];
> +
> + u32 os_reg[4];
> +};
> +check_member(rk3066_grf, os_reg[3], 0x01d4);
> +
> +/* GRF_GPIO0A_IOMUX */
> +enum {
> + GPIO0A6_SHIFT = 12,
> + GPIO0A6_MASK = 1,
Can you please use shifted masks for these values?
GPIO0A6_MASK = 1 << GPIO0A6_SHIFT,
> + GPIO0A6_GPIO = 0,
> + GPIO0A6_HOST_DRV_VBUS,
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver
2017-06-06 18:49 ` [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:49, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Add driver supporting pin multiplexing on rk3066 platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3066.c | 342 ++++++++++++++++++++++++++++++
> 3 files changed, 352 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c
Can you please update the masks here as per the previous comment on grf?
Otherwise looks good.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,03/13] " Philipp Tomsich
2017-07-04 17:41 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:49, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Add support for system reset for rk3066 socs.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3066.c | 62 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 63 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_rk3066.c
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc
2017-06-06 18:50 ` [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Add clock driver for rk3066 platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 ++++++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3066.c | 586 ++++++++++++++++++++++++
> 3 files changed, 776 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
> create mode 100644 drivers/clk/rockchip/clk_rk3066.c
Again please can you update the masks?
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 15:12 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
> watchdog and uart
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/dts/rk3066a.dtsi | 699 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 699 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a.dtsi
How come this file has 'a' on the end?
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 15:22 ` Paweł Jarosz
2017-06-07 6:37 ` Andy Yan
` (2 subsequent siblings)
3 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/mach-rockchip/Kconfig | 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
> arch/arm/mach-rockchip/rk3066-board.c | 180 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
> arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
> arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
> arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
> include/configs/rk3066_common.h | 125 ++++++++++++++++++
> 10 files changed, 677 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> create mode 100644 include/configs/rk3066_common.h
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 6be2ab5..ad35e0a 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3066
> + bool "Support Rockchip RK3066"
> + select CPU_V7
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL
> + select TPL
> + select BOARD_LATE_INIT
> + select ROCKCHIP_BROM_HELPER
> + help
> + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
> + including NEON and GPU, Mali-400 graphics, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
> +
> config ROCKCHIP_RK3188
> bool "Support Rockchip RK3188"
> select CPU_V7
> @@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
> default y if !ROCKCHIP_SPL_BACK_TO_BROM
>
> source "arch/arm/mach-rockchip/rk3036/Kconfig"
> +source "arch/arm/mach-rockchip/rk3066/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 327b267..1ebba0c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -7,15 +7,18 @@
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>
> ifdef CONFIG_TPL_BUILD
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> @@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
> endif
>
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c b/arch/arm/mach-rockchip/rk3066-board-spl.c
> new file mode 100644
> index 0000000..6f7bfb0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
> @@ -0,0 +1,173 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <led.h>
> +#include <malloc.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/timer.h>
> +#include <dm/pinctrl.h>
> +#include <dm/root.h>
> +#include <dm/test.h>
> +#include <dm/util.h>
> +#include <power/regulator.h>
> +#include <syscon.h>
That should go below spi.h
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u32 spl_boot_device(void)
> +{
This function seems to be common. Can you please (in a separate patch)
move it into a separate shared file and delete all the copies?
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + const void *blob = gd->fdt_blob;
> + struct udevice *dev;
> + const char *bootdev;
> + int node;
> + int ret;
> +
> + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
> + debug("Boot device %s\n", bootdev);
> + if (!bootdev)
> + goto fallback;
> +
> + node = fdt_path_offset(blob, bootdev);
> + if (node < 0) {
> + debug("node=%d\n", node);
> + goto fallback;
> + }
> + ret = device_get_global_by_of_offset(node, &dev);
> + if (ret) {
> + debug("device at node %s/%d not found: %d\n", bootdev, node,
> + ret);
> + goto fallback;
> + }
> + debug("Found device %s\n", dev->name);
> + switch (device_get_uclass_id(dev)) {
> + case UCLASS_SPI_FLASH:
> + return BOOT_DEVICE_SPI;
> + case UCLASS_MMC:
> + return BOOT_DEVICE_MMC1;
> + default:
> + debug("Booting from device uclass '%s' not supported\n",
> + dev_get_uclass_name(dev));
> + }
> +
> +fallback:
> +#endif
> + return BOOT_DEVICE_MMC1;
> +}
> +
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> + return MMCSD_MODE_FS;
> +}
> +
> +static int setup_arm_clock(void)
> +{
> + struct udevice *dev;
> + struct clk clk;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ret;
> +
> + clk.id = CLK_ARM;
> + ret = clk_request(dev, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_set_rate(&clk, 600000000);
> +
> + clk_free(&clk);
> + return ret;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *pinctrl, *dev;
> + int ret;
> +
> + debug_uart_init();
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + 0x8, 0x1, 0x1);
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret) {
> + debug("CLK init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("Pinctrl init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return;
> + }
> +
> + setup_arm_clock();
> +}
> +
> +void spl_board_init(void)
> +{
> + struct udevice *pinctrl;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +#endif
> +
> + /* Enable debug UART */
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
> + if (ret) {
> + debug("%s: Failed to set up console UART\n", __func__);
> + goto err;
> + }
> +
> + preloader_console_init();
> +
> + return;
> +
> +err:
> + printf("spl_board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board-tpl.c b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> new file mode 100644
> index 0000000..d517a33
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> @@ -0,0 +1,46 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define RK3066_TIMER_CONTROL 0x8
> +#define GRF_BASE 0x20008000
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Enable early UART on the RK3066 */
> +
> + struct rk3066_grf * const grf = (void *)GRF_BASE;
> +
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK << GPIO1B1_SHIFT |
> + GPIO1B0_MASK << GPIO1B0_SHIFT,
> + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
> + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
> +
> + debug_uart_init();
> +
> + printch('T');
> + printch('P');
> + printch('L');
> + printch('\n');
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1, 0x1);
> +
> + sdram_initialise();
How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
> +
> + back_to_bootrom();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board.c b/arch/arm/mach-rockchip/rk3066-board.c
> new file mode 100644
> index 0000000..3d92253
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board.c
> @@ -0,0 +1,180 @@
> +/*
> + * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/boot_mode.h>
> +#include <asm/gpio.h>
> +#include <dm/pinctrl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_late_init(void)
> +{
> + struct rk3066_grf *grf;
> +
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(grf)) {
> + error("grf syscon returned %ld\n", PTR_ERR(grf));
debug() might be better here. Also please return the error so that it halts.
> + } else {
Then drop this else because you will have returned by now.
> + /* enable noc remap to mimic legacy loaders */
> + rk_clrsetreg(&grf->soc_con0,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT);
> + }
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
> + struct udevice *pinctrl;
> + int ret;
> +
> + /*
> + * We need to implement sdcard iomux here for the further
> + * initialization, otherwise, it'll hit sdcard command sending
> + * timeout exception.
> + */
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +
> + return 0;
> +err:
> + printf("board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +
> + return -1;
> +#else
> + return 0;
> +#endif
> +}
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> + ret = ram_get_info(dev, &ram);
> + if (ret) {
> + debug("Cannot get DRAM size: %d\n", ret);
> + return ret;
> + }
> + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +#endif
> +
> +int print_cpuinfo (void)
> +{
> + printf("CPU: Rockchip RK3066\n");
> + return 0;
> +}
> +
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rk3066_otg_data = {
> + .rx_fifo_sz = 275,
> + .np_tx_fifo_sz = 16,
> + .tx_fifo_sz = 256,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + int node, phy_node;
> + const char *mode;
> + bool matched = false;
> + const void *blob = gd->fdt_blob;
> + u32 grf_phy_offset;
> +
> + /* find the usb_otg node */
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-usb");
Can you please use live tree functions? You'll need to add a separate
patch to add this (see ofnode_path() for something simliar). Perhaps
call it ofnode_by_compatible()?
Ideally we should turn this into a driver so you can use dev_read_...
functions. But that can come later.
> +
> + while (node > 0) {
> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
This becomes ofnode_read_string()
> + if (mode && strcmp(mode, "otg") == 0) {
> + matched = true;
> + break;
> + }
> +
> + node = fdt_node_offset_by_compatible(blob, node,
> + "rockchip,rk3066-usb")
> + }
> + if (!matched) {
> + debug("Not found usb_otg device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
ofnode_get_addr
> +
> + node = fdtdec_lookup_phandle(blob, node, "phys");
etc.
> + if (node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + phy_node = fdt_parent_offset(blob, node);
> + if (phy_node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + rk3066_otg_data.phy_of_node = phy_node;
> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
> +
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-grf");
> + if (node <= 0) {
> + debug("Not found grf device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_phy = grf_phy_offset +
> + fdtdec_get_addr(blob, node, "reg");
> +
> + return dwc2_udc_probe(&rk3066_otg_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
> new file mode 100644
> index 0000000..27d32fd
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Kconfig
> @@ -0,0 +1,34 @@
> +if ROCKCHIP_RK3066
> +
> +config TARGET_MK808_RK3066
> + bool "MK808_RK3066"
> + help
> + MK808 is a tv stick with usb host and otg, microsd card slot, hdmi and wifi.
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x0800
> +
> +config SPL_LIBCOMMON_SUPPORT
You should be able to add these as 'imply' options now (to the
ROCKCHIP_RK3066 config)
> + default y
> +
> +config SPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config SPL_SERIAL_SUPPORT
> + default y
> +
> +config TPL_LIBCOMMON_SUPPORT
> + default y
> +
> +config TPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config TPL_SERIAL_SUPPORT
> + default y
> +
> +source "board/rikomagic/mk808_rk3066/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
> new file mode 100644
> index 0000000..4cf5df2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +ifndef CONFIG_TPL_BUILD
> +obj-y += clk_rk3066.o
> +obj-y += syscon_rk3066.o
> +else
> +obj-y += sdram_init.o
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> new file mode 100644
> index 0000000..ae52902
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2016 Google, Inc
> + * Written by Simon Glass <sjg@chromium.org>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3066_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> new file mode 100644
> index 0000000..57b2376
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> @@ -0,0 +1,54 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +
> +static const struct udevice_id rk3066_syscon_ids[] = {
> + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
> + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3066) = {
> + .name = "rk3066_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> +};
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
> +{
> + dev->driver_data = dev->driver->of_match->data;
> + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(rockchip_rk3188_noc) = {
> + .name = "rockchip_rk3188_noc",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_grf) = {
> + .name = "rockchip_rk3066_grf",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 1,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
> + .name = "rockchip_rk3066_pmu",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 2,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +#endif
> diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
> new file mode 100644
> index 0000000..7009616
> --- /dev/null
> +++ b/include/configs/rk3066_common.h
> @@ -0,0 +1,125 @@
> +/*
> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_RK3066_COMMON_H
> +#define __CONFIG_RK3066_COMMON_H
> +
> +#include <asm/arch/hardware.h>
> +#include "rockchip-common.h"
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_MALLOC_LEN (64 << 20)
> +#define CONFIG_SYS_CBSIZE 256
> +
> +#define CONFIG_SYS_TIMER_RATE 24000000
> +#define CONFIG_SYS_TIMER_BASE 0x20038000
> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> +
> +#define CONFIG_SPL_BOARD_INIT
> +
> +#define CONFIG_SYS_TEXT_BASE 0x60408000
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
> +#define CONFIG_SYS_LOAD_ADDR 0x70800800
> +
> +#ifdef CONFIG_TPL_BUILD
> +#define CONFIG_SPL_TEXT_BASE 0x10080C04
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +/* tpl size max 32kb - 4byte RK30 header */
> +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
> +#elif defined(CONFIG_SPL_BUILD)
> +/* spl size max 200k */
> +#define CONFIG_SPL_MAX_SIZE 0x32000
> +#define CONFIG_SPL_TEXT_BASE 0x60000000
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +#define CONFIG_SPL_STACK_R_ADDR 0x70000000
> +#define CONFIG_SPL_STACK_R 1
> +#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
> +#define CONFIG_SPL_OF_CONTROL 1
> +#define CONFIG_SPL_OF_PLATDATA 1
> +#define CONFIG_SPL_FRAMEWORK 1
> +#define CONFIG_SPL_CLK 1
> +#define CONFIG_SPL_PINCTRL 1
> +#define CONFIG_SPL_REGMAP 1
Many of these should be set in Kconfig or the defconfig file.
> +#define CONFIG_SPL_SYSCON 1
> +#define CONFIG_SPL_RAM 1
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
> +#define CONFIG_SPL_MMC_SUPPORT 1
> +#define CONFIG_ROCKCHIP_SERIAL 1
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SPL_LIBDISK_SUPPORT 1
> +#define CONFIG_SPL_EXT_SUPPORT 1
> +#define CONFIG_SPL_FAT_SUPPORT 1
> +#define CONFIG_SPL_DM 1
> +#define CONFIG_SPL_GPIO_SUPPORT 1
> +#define CONFIG_SPL_POWER_SUPPORT 1
> +#endif
> +
> +#define CONFIG_SYS_NS16550_MEM32
> +
> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
> +
> +/* MMC/SD IP block */
> +#define CONFIG_BOUNCE_BUFFER
> +
> +#define CONFIG_CMD_CACHE
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define SDRAM_BANK_SIZE (1024UL << 20UL)
> +
> +#ifndef CONFIG_SPL_BUILD
> +/* usb */
> +#define CONFIG_USB
> +#define CONFIG_DM_USB
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_DWC2
> +
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_DWC2_OTG
> +#define CONFIG_ROCKCHIP_USB2_PHY
> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
> +
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_CMD_USB_MASS_STORAGE
> +
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
> +#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
> +
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x60000000\0" \
> + "pxefile_addr_r=0x60100000\0" \
> + "fdt_addr_r=0x61f00000\0" \
> + "kernel_addr_r=0x62000000\0" \
> + "ramdisk_addr_r=0x64000000\0"
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x6fffffff\0" \
> + "initrd_high=0x6fffffff\0" \
> + "partitions=" PARTS_DEFAULT \
> + ENV_MEM_LAYOUT_SETTINGS \
> + ROCKCHIP_DEVICE_SETTINGS \
> + BOOTENV
> +
> +#include <config_distro_defaults.h>
> +#endif
> +
> +#define CONFIG_PREBOOT
> +
> +#endif
> --
> 2.7.4
>
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc
2017-06-06 18:51 ` [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 3:23 ` Kever Yang
2017-06-25 23:23 ` [U-Boot] [U-Boot,08/13] " Philipp Tomsich
1 sibling, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:51, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
> internal dma support and max driver frequency.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/mmc/rockchip_dw_mmc.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 25a21e2..d94c395 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
>
> struct rockchip_mmc_plat {
> #if CONFIG_IS_ENABLED(OF_PLATDATA)
> +
> +#ifdef CONFIG_ROCKCHIP_RK3066
> + struct dtd_rockchip_rk2928_dw_mshc dtplat;
> +#else
> struct dtd_rockchip_rk3288_dw_mshc dtplat;
> #endif
> +
> +#endif
> struct mmc_config cfg;
> struct mmc mmc;
> };
> @@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
> int ret;
>
> #if CONFIG_IS_ENABLED(OF_PLATDATA)
> +#ifdef CONFIG_ROCKCHIP_RK3066
> + struct dtd_rockchip_rk2928_dw_mshc *dtplat = &plat->dtplat;
> +#else
> struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
> -
> +#endif
I am not keen on this - it will get ugly. Can you please do this:
Create a new driver for rk3288 which just has the platdata stuff,
rockchip_dwmmc_ofdata_to_platdata() and the U_BOOT_DRIVER().
Everything else should remain in this file.
Then in a new patch, create a driver for rk3066 which uses the same
common elements from rockchip_dw_mmc.c
> host->name = dev->name;
> host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
> host->buswidth = dtplat->bus_width;
> @@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
> host->priv = dev;
> host->dev_index = 0;
> priv->fifo_depth = dtplat->fifo_depth;
> +
> +#ifdef CONFIG_ROCKCHIP_RK3066
> + priv->fifo_mode = 1;
> +#else
> priv->fifo_mode = 0;
> +#endif
What about the fifo_mode property in the DT?
If you have to hard-code this you should use a .data parameter in
rockchip_dwmmc_ids (e.g. RK2928, RK3288) and use that to determine the
mode. But hopefully the DT is enough.
For OF_PLATDATA however I suggest you have a different probe() which
either sets up this value and then calls rockchip_dwmmc_probe(), or
add it as a parameter to rockchip_dwmmc_probe().
> memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
>
> ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
> @@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
> }
>
> static const struct udevice_id rockchip_dwmmc_ids[] = {
> + { .compatible = "rockchip,rk2928-dw-mshc" },
> { .compatible = "rockchip,rk3288-dw-mshc" },
> { }
> };
>
> +U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
> + .name = "rockchip_rk2928_dw_mshc",
> + .id = UCLASS_MMC,
> + .of_match = rockchip_dwmmc_ids,
> + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
> + .ops = &dm_dwmci_ops,
> + .bind = rockchip_dwmmc_bind,
> + .probe = rockchip_dwmmc_probe,
> + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
> + .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
> +};
> +
> U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
> .name = "rockchip_rk3288_dw_mshc",
> .id = UCLASS_MMC,
> - .of_match = rockchip_dwmmc_ids,
I think you ne
> .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
> .ops = &dm_dwmci_ops,
> .bind = rockchip_dwmmc_bind,
> --
> 2.7.4
>
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:51, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
> nand onboard.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3066a-mk808.dts | 172 ++++++++++++++++++++++++++++
> board/rikomagic/mk808_rk3066/Kconfig | 15 +++
> board/rikomagic/mk808_rk3066/MAINTAINERS | 6 +
> board/rikomagic/mk808_rk3066/Makefile | 7 ++
> board/rikomagic/mk808_rk3066/mk808_rk3066.c | 10 ++
> configs/mk808-rk3066_defconfig | 54 +++++++++
> include/configs/mk808_rk3066.h | 15 +++
> 8 files changed, 280 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a-mk808.dts
> create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
> create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
> create mode 100644 board/rikomagic/mk808_rk3066/Makefile
> create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
> create mode 100644 configs/mk808-rk3066_defconfig
> create mode 100644 include/configs/mk808_rk3066.h
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 3:14 ` Kever Yang
2017-06-25 23:23 ` [U-Boot] [U-Boot,10/13] " Philipp Tomsich
2017-07-04 16:18 ` Philipp Tomsich
2 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:52, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
Commit message?
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/mach-rockchip/rk3066/Makefile | 1 +
> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++
> 2 files changed, 112 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>
Acked-by: Simon Glass <sjg@chromium.org>
> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
> index 4cf5df2..1d38518 100644
> --- a/arch/arm/mach-rockchip/rk3066/Makefile
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -6,6 +6,7 @@
>
> ifndef CONFIG_TPL_BUILD
> obj-y += clk_rk3066.o
> +obj-y += sdram_rk3066.o
> obj-y += syscon_rk3066.o
> else
> obj-y += sdram_init.o
> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> new file mode 100644
> index 0000000..a713ac4
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> @@ -0,0 +1,111 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Adapted from the very similar rk3288 ddr init.
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-structs.h>
> +#include <errno.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <linux/err.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> + struct ram_info info;
> + struct rk3188_pmu *pmu;
> +};
> +
> +size_t sdram_size_mb(struct rk3188_pmu *pmu)
I wonder if most of this could go in a common function, or are the
registers / offsets different?
> +{
> + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
> + size_t chipsize_mb = 0;
> + size_t size_mb = 0;
> + u32 ch;
> + u32 sys_reg = readl(&pmu->sys_reg[2]);
> + u32 chans;
> +
> + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
> +
> + for (ch = 0; ch < chans; ch++) {
> + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
> + SYS_REG_RANK_MASK);
> + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
> + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
> + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
> + SYS_REG_CS0_ROW_MASK);
> + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
> + SYS_REG_CS1_ROW_MASK);
> + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
> + SYS_REG_BW_MASK));
> + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
> + SYS_REG_ROW_3_4_MASK;
> + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
> +
> + if (rank > 1)
> + chipsize_mb += chipsize_mb >>
> + (cs0_row - cs1_row);
> + if (row_3_4)
> + chipsize_mb = chipsize_mb * 3 / 4;
> + size_mb += chipsize_mb;
> + }
> +
> + /* there can be no more than 2gb of memory */
> + size_mb = min(size_mb, 0x80000000 >> 20);
> +
> + return size_mb;
> +}
> +
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066
2017-06-06 18:53 ` [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066 Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> update driver to support rk3066 serial
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/serial/serial_rockchip.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
Similar comments here to the mmc driver.
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 15:37 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 16:20 ` Philipp Tomsich
2 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> executes it. Then waits for back to bootrom and loads another 32KB to sram
> which also executes. Sdram initialisation code needs to be in one of these two
> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
> and jumps to it.
>
> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
> u-boot part(for example to boot from mmc you need to disable usb support.
>
> My solution to size problem is to move sdram initialisation code to tpl stage,
> move spl part to third stage(reading 200KB data) and add support for loading
> u-boot by spl from ext2/4, fat partitions.
>
> But moving sdram initialisation code to tpl increases size of tpl above 1KB
> (first boot stage). Solution to this is to add code which will be below 1KB
> offset in tpl binary and do back to bootrom at very beginning of the tpl
> execution.
So do you mean that TPL starts and then loads more of itself? Why not
put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
not clear why.
>
> Adding this few lines of code here meets these conditions.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/cpu/armv7/start.S | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index f06fd28..73e03d9 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -36,6 +36,19 @@
> #endif
>
> reset:
> +
> +#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
> + ldr r3, =0x10080900
> + ldr r0, [r3]
> + cmp r0, #1
> + movne r0, #1
> + strne r0, [r3]
> + beq out_of_bootrom
> + bx lr
> +out_of_bootrom:
> + mov r0, #0
> + str r0, [r3]
> +#endif
> /* Allow the board to save important registers */
> b save_boot_params
> save_boot_params_ret:
> --
> 2.7.4
>
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 16:41 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 12:52, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> rk3066 and rk3188 designware mmc ip doesn't support internal dma
> transfer mode. So set fifo mode as default.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/dts/rk3xxx.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-06 18:53 ` [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl Paweł Jarosz
@ 2017-06-06 21:10 ` Simon Glass
2017-06-07 15:44 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
1 sibling, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-06 21:10 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Add sdram initialisation code which will be ussed by tpl first boot stage.
> We need to implement sdram initialisation in tpl due to size issues on rk3066
> platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995 ++++++++++++++++++++++++
> 2 files changed, 1000 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> index 3d7929f..74d11c6 100644
> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
> @@ -10,6 +10,11 @@
> #include <asm/arch/ddr_rk3288.h>
>
> /*
> + * RK3066 Tpl memory init.
> + */
> +void sdram_initialise(void);
> +
> +/*
> * RK3188 Memory scheduler register map.
> */
> struct rk3188_msch {
> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c b/arch/arm/mach-rockchip/rk3066/sdram_init.c
> new file mode 100644
> index 0000000..e7e506a
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
> @@ -0,0 +1,995 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Adapted from the very similar rk3288 ddr init.
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <errno.h>
> +#include <ram.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <linux/err.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct pll_div {
> + u32 nr;
> + u32 nf;
> + u32 no;
> +};
> +
> +enum {
> + VCO_MAX_HZ = 1416U * 1000000,
> + VCO_MIN_HZ = 300 * 1000000,
> + OUTPUT_MAX_HZ = 1416U * 1000000,
> + OUTPUT_MIN_HZ = 30 * 1000000,
> + FREF_MAX_HZ = 1416U * 1000000,
> + FREF_MIN_HZ = 30 * 1000,
> +};
> +
> +enum {
> + /* PLL CON0 */
> + PLL_OD_MASK = 0x0f,
> +
> + /* PLL CON1 */
> + PLL_NF_MASK = 0x1fff,
> +
> + /* PLL CON2 */
> + PLL_BWADJ_MASK = 0x0fff,
> +
> + /* PLL CON3 */
> + PLL_RESET_SHIFT = 5,
> +
> + /* GRF_SOC_STATUS0 */
> + SOCSTS_DPLL_LOCK = 1 << 4,
> + SOCSTS_APLL_LOCK = 1 << 5,
> + SOCSTS_CPLL_LOCK = 1 << 6,
> + SOCSTS_GPLL_LOCK = 1 << 7,
> +};
> +
> +#define CRU_BASE 0x20000000
> +#define GRF_BASE 0x20008000
> +#define PMU_BASE 0x20004000
> +#define PCTL_BASE 0x20020000
> +#define PUBL_BASE 0x20040000
> +#define NOC_BASE 0x10128000
I'm assume we cannot use the DT / syscon because of space constraints?
> +
> +#define RK3066_PCTL_TIMING_DEFAULT { \
Do you need this? Why not just put these values below and avoid the indirection?
> + .togcnt1u = 0x12c, \
> + .tinit = 0xc8, \
> + .trsth = 0x1f4, \
> + .togcnt100n = 0x1e, \
> + .trefi = 0x4e, \
> + .tmrd = 0x4, \
> + .trfc = 0x69, \
> + .trp = 0x6, \
> + .trtw = 0x3, \
> + .tal = 0x0, \
> + .tcl = 0x6, \
> + .tcwl = 0x5, \
> + .tras = 0xc, \
> + .trc = 0x10, \
> + .trcd = 0x6, \
> + .trrd = 0x4, \
> + .trtp = 0x4, \
> + .twr = 0x5, \
> + .twtr = 0x4, \
> + .texsr = 0x200, \
> + .txp = 0x3, \
> + .txpdll = 0xa, \
> + .tzqcs = 0x40, \
> + .tzqcsi = 0x0, \
> + .tdqs = 0x1, \
> + .tcksre = 0x5, \
> + .tcksrx = 0x5, \
> + .tcke = 0x3, \
> + .tmod = 0xc, \
> + .trstl = 0x1e, \
> + .tzqcl = 0x100, \
> + .tmrr = 0x0, \
> + .tckesr = 0x4, \
> + .tdpd = 0x0 \
> +}
> +
> +#define RK3066_PHY_TIMING_DEFAULT { \
> + .dtpr0 = 0x208c6690, \
> + .dtpr1 = 0x690878, \
> + .dtpr2 = 0x10022a00, \
> + .mr = { 0x220, 0x40, 0x0, 0x0 } \
> +}
> +
> +#define RK3066_SDRAM_PARAMS_DEFAULT { \
> + .noc_timing = 0x24716310, \
> + .noc_activate = 0, \
> + .ddrconfig = 2, \
> + .ddr_freq = 300000000, \
> + .dramtype = 3, \
> + .stride = 9, \
> + .odt = 0 \
> +}
> +
> +#ifndef RK3066_PCTL_TIMING
> +#define RK3066_PCTL_TIMING RK3066_PCTL_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_PHY_TIMING
> +#define RK3066_PHY_TIMING RK3066_PHY_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_SDRAM_PARAMS
> +#define RK3066_SDRAM_PARAMS RK3066_SDRAM_PARAMS_DEFAULT
> +#endif
> +
> +struct chan_info {
> + struct rk3288_ddr_pctl *pctl;
> + struct rk3288_ddr_publ *publ;
> + struct rk3188_msch *msch;
> +};
> +
> +struct dram_info {
> + struct chan_info chan[1];
> + struct ram_info info;
> + struct rk3066_cru *cru;
> + struct rk3066_grf *grf;
> + struct rk3188_pmu *pmu;
> +};
> +
> +struct rk3066_sdram_params {
> + struct rk3288_sdram_channel ch[2];
> + struct rk3288_sdram_pctl_timing pctl_timing;
> + struct rk3288_sdram_phy_timing phy_timing;
> + struct rk3288_base_params base;
> + int num_channels;
> + struct regmap *map;
> +};
> +
> +const int ddrconf_table[] = {
> + /*
> + * [5:4] row(13+n)
> + * [1:0] col(9+n), assume bw=2
> + * row col,bw
> + */
> + 0,
> + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
You can drop the ()
> + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
> + ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
> + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
> + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
> + ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
> + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
> + ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
> + 0,
> + 0,
> + 0,
> + 0,
> + 0,
> + 0,
> + 0,
> +};
> +
> +#define TEST_PATTEN 0x5aa5f00f
> +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
> +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
> +
> +
> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++) {
> + writel(*src, dest);
> + src++;
> + dest++;
> + }
> +}
> +
> +static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
> +{
> + u32 phy_ctl_srstn_shift = 13;
> + u32 ctl_psrstn_shift = 11;
> + u32 ctl_srstn_shift = 10;
> + u32 phy_psrstn_shift = 9;
> + u32 phy_srstn_shift = 8;
> +
> + rk_clrsetreg(&cru->cru_softrst_con[5],
> + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
> + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
> + 1 << phy_srstn_shift,
> + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
> + ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
> + phy << phy_srstn_shift);
> +}
> +
How similar is this to rk3288? Could we put common code in a separate file?
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 3:14 ` Kever Yang
0 siblings, 0 replies; 86+ messages in thread
From: Kever Yang @ 2017-06-07 3:14 UTC (permalink / raw)
To: u-boot
Simon, Pawel,
On 06/07/2017 05:10 AM, Simon Glass wrote:
> On 6 June 2017 at 12:52, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
> Commit message?
>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> arch/arm/mach-rockchip/rk3066/Makefile | 1 +
>> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++
>> 2 files changed, 112 insertions(+)
>> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>>
> Acked-by: Simon Glass <sjg@chromium.org>
>
>> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
>> index 4cf5df2..1d38518 100644
>> --- a/arch/arm/mach-rockchip/rk3066/Makefile
>> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
>> @@ -6,6 +6,7 @@
>>
>> ifndef CONFIG_TPL_BUILD
>> obj-y += clk_rk3066.o
>> +obj-y += sdram_rk3066.o
>> obj-y += syscon_rk3066.o
>> else
>> obj-y += sdram_init.o
>> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>> new file mode 100644
>> index 0000000..a713ac4
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>> @@ -0,0 +1,111 @@
>> +/*
>> + * (C) Copyright 2015 Google, Inc
>> + * Copyright 2014 Rockchip Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Adapted from the very similar rk3288 ddr init.
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <dt-structs.h>
>> +#include <errno.h>
>> +#include <ram.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3066.h>
>> +#include <asm/arch/ddr_rk3188.h>
>> +#include <asm/arch/grf_rk3066.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +#include <asm/arch/sdram.h>
>> +#include <linux/err.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct dram_info {
>> + struct ram_info info;
>> + struct rk3188_pmu *pmu;
>> +};
>> +
>> +size_t sdram_size_mb(struct rk3188_pmu *pmu)
> I wonder if most of this could go in a common function, or are the
> registers / offsets different?
The definition of sys_reg for all the Rockchip SoC are the same, the only
difference may be some chip have dual channel while others only have one,
but the definition is not conflict.
The dram driver for rk3066, rk3188 and rk3288 are very similar.
Thanks,
- Kever
>
>> +{
>> + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
>> + size_t chipsize_mb = 0;
>> + size_t size_mb = 0;
>> + u32 ch;
>> + u32 sys_reg = readl(&pmu->sys_reg[2]);
>> + u32 chans;
>> +
>> + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
>> +
>> + for (ch = 0; ch < chans; ch++) {
>> + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
>> + SYS_REG_RANK_MASK);
>> + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
>> + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
>> + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
>> + SYS_REG_CS0_ROW_MASK);
>> + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
>> + SYS_REG_CS1_ROW_MASK);
>> + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
>> + SYS_REG_BW_MASK));
>> + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
>> + SYS_REG_ROW_3_4_MASK;
>> + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
>> +
>> + if (rank > 1)
>> + chipsize_mb += chipsize_mb >>
>> + (cs0_row - cs1_row);
>> + if (row_3_4)
>> + chipsize_mb = chipsize_mb * 3 / 4;
>> + size_mb += chipsize_mb;
>> + }
>> +
>> + /* there can be no more than 2gb of memory */
>> + size_mb = min(size_mb, 0x80000000 >> 20);
>> +
>> + return size_mb;
>> +}
>> +
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 3:23 ` Kever Yang
2017-06-08 3:30 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Kever Yang @ 2017-06-07 3:23 UTC (permalink / raw)
To: u-boot
Simon,
On 06/07/2017 05:10 AM, Simon Glass wrote:
> Hi Pawel,
>
> On 6 June 2017 at 12:51, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
>> internal dma support and max driver frequency.
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> drivers/mmc/rockchip_dw_mmc.c | 31 +++++++++++++++++++++++++++++--
>> 1 file changed, 29 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
>> index 25a21e2..d94c395 100644
>> --- a/drivers/mmc/rockchip_dw_mmc.c
>> +++ b/drivers/mmc/rockchip_dw_mmc.c
>> @@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>
>> struct rockchip_mmc_plat {
>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +
>> +#ifdef CONFIG_ROCKCHIP_RK3066
>> + struct dtd_rockchip_rk2928_dw_mshc dtplat;
>> +#else
>> struct dtd_rockchip_rk3288_dw_mshc dtplat;
>> #endif
>> +
>> +#endif
>> struct mmc_config cfg;
>> struct mmc mmc;
>> };
>> @@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>> int ret;
>>
>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +#ifdef CONFIG_ROCKCHIP_RK3066
>> + struct dtd_rockchip_rk2928_dw_mshc *dtplat = &plat->dtplat;
>> +#else
>> struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
>> -
>> +#endif
> I am not keen on this - it will get ugly. Can you please do this:
>
> Create a new driver for rk3288 which just has the platdata stuff,
> rockchip_dwmmc_ofdata_to_platdata() and the U_BOOT_DRIVER().
> Everything else should remain in this file.
>
> Then in a new patch, create a driver for rk3066 which uses the same
> common elements from rockchip_dw_mmc.c
I think I have discuss this with you online or offline for many times,
when OF_PLATADATA enabled, the dts is pre-compile by dtoc and then
there is structure like 'dtd_rockchip_rk2928_dw_mshc' which is from the dts
node compatible name, I propose to use the last compatible name in dtoc
instead of the first one, then we can get the same structure name and used
in drivers.
I still not enable the dwmmc when OF_PLATDATA enabled on rk3399 because
of the same reason.
I think we should fix this from the root cause, but not make different
driver
for different SoCs.
Thanks,
- Kever
>
>> host->name = dev->name;
>> host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
>> host->buswidth = dtplat->bus_width;
>> @@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>> host->priv = dev;
>> host->dev_index = 0;
>> priv->fifo_depth = dtplat->fifo_depth;
>> +
>> +#ifdef CONFIG_ROCKCHIP_RK3066
>> + priv->fifo_mode = 1;
>> +#else
>> priv->fifo_mode = 0;
>> +#endif
> What about the fifo_mode property in the DT?
>
> If you have to hard-code this you should use a .data parameter in
> rockchip_dwmmc_ids (e.g. RK2928, RK3288) and use that to determine the
> mode. But hopefully the DT is enough.
>
> For OF_PLATDATA however I suggest you have a different probe() which
> either sets up this value and then calls rockchip_dwmmc_probe(), or
> add it as a parameter to rockchip_dwmmc_probe().
>
>> memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
>>
>> ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
>> @@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
>> }
>>
>> static const struct udevice_id rockchip_dwmmc_ids[] = {
>> + { .compatible = "rockchip,rk2928-dw-mshc" },
>> { .compatible = "rockchip,rk3288-dw-mshc" },
>> { }
>> };
>>
>> +U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
>> + .name = "rockchip_rk2928_dw_mshc",
>> + .id = UCLASS_MMC,
>> + .of_match = rockchip_dwmmc_ids,
>> + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
>> + .ops = &dm_dwmci_ops,
>> + .bind = rockchip_dwmmc_bind,
>> + .probe = rockchip_dwmmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
>> + .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
>> +};
>> +
>> U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
>> .name = "rockchip_rk3288_dw_mshc",
>> .id = UCLASS_MMC,
>> - .of_match = rockchip_dwmmc_ids,
> I think you ne
>> .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
>> .ops = &dm_dwmci_ops,
>> .bind = rockchip_dwmmc_bind,
>> --
>> 2.7.4
>>
> Regards,
> Simon
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 6:37 ` Andy Yan
2017-06-25 23:23 ` [U-Boot] [U-Boot,06/13] " Philipp Tomsich
2017-07-04 17:35 ` Philipp Tomsich
3 siblings, 0 replies; 86+ messages in thread
From: Andy Yan @ 2017-06-07 6:37 UTC (permalink / raw)
To: u-boot
Hi Pawel:
2017-06-07 2:50 GMT+08:00 Paweł Jarosz <paweljarosz3691@gmail.com>:
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/mach-rockchip/Kconfig | 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173
> +++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
> arch/arm/mach-rockchip/rk3066-board.c | 180
> ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
> arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
> arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
> arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
> include/configs/rk3066_common.h | 125 ++++++++++++++++++
> 10 files changed, 677 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> create mode 100644 include/configs/rk3066_common.h
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/
> Kconfig
> index 6be2ab5..ad35e0a 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3066
> + bool "Support Rockchip RK3066"
> + select CPU_V7
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL
> + select TPL
> + select BOARD_LATE_INIT
> + select ROCKCHIP_BROM_HELPER
> + help
> + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
>
RK3066 is dual-core Cortex-A9
> + including NEON and GPU, Mali-400 graphics, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
> +
> config ROCKCHIP_RK3188
> bool "Support Rockchip RK3188"
> select CPU_V7
> @@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
> default y if !ROCKCHIP_SPL_BACK_TO_BROM
>
> source "arch/arm/mach-rockchip/rk3036/Kconfig"
> +source "arch/arm/mach-rockchip/rk3066/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/
> Makefile
> index 327b267..1ebba0c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -7,15 +7,18 @@
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>
> ifdef CONFIG_TPL_BUILD
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> @@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
> endif
>
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c
> b/arch/arm/mach-rockchip/rk3066-board-spl.c
> new file mode 100644
> index 0000000..6f7bfb0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
> @@ -0,0 +1,173 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <led.h>
> +#include <malloc.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/timer.h>
> +#include <dm/pinctrl.h>
> +#include <dm/root.h>
> +#include <dm/test.h>
> +#include <dm/util.h>
> +#include <power/regulator.h>
> +#include <syscon.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u32 spl_boot_device(void)
> +{
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + const void *blob = gd->fdt_blob;
> + struct udevice *dev;
> + const char *bootdev;
> + int node;
> + int ret;
> +
> + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
> + debug("Boot device %s\n", bootdev);
> + if (!bootdev)
> + goto fallback;
> +
> + node = fdt_path_offset(blob, bootdev);
> + if (node < 0) {
> + debug("node=%d\n", node);
> + goto fallback;
> + }
> + ret = device_get_global_by_of_offset(node, &dev);
> + if (ret) {
> + debug("device at node %s/%d not found: %d\n", bootdev,
> node,
> + ret);
> + goto fallback;
> + }
> + debug("Found device %s\n", dev->name);
> + switch (device_get_uclass_id(dev)) {
> + case UCLASS_SPI_FLASH:
> + return BOOT_DEVICE_SPI;
> + case UCLASS_MMC:
> + return BOOT_DEVICE_MMC1;
> + default:
> + debug("Booting from device uclass '%s' not supported\n",
> + dev_get_uclass_name(dev));
> + }
> +
> +fallback:
> +#endif
> + return BOOT_DEVICE_MMC1;
> +}
> +
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> + return MMCSD_MODE_FS;
> +}
> +
> +static int setup_arm_clock(void)
> +{
> + struct udevice *dev;
> + struct clk clk;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ret;
> +
> + clk.id = CLK_ARM;
> + ret = clk_request(dev, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_set_rate(&clk, 600000000);
> +
> + clk_free(&clk);
> + return ret;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *pinctrl, *dev;
> + int ret;
> +
> + debug_uart_init();
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + 0x8, 0x1, 0x1);
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret) {
> + debug("CLK init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("Pinctrl init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return;
> + }
> +
> + setup_arm_clock();
> +}
> +
> +void spl_board_init(void)
> +{
> + struct udevice *pinctrl;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +#endif
> +
> + /* Enable debug UART */
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
> + if (ret) {
> + debug("%s: Failed to set up console UART\n", __func__);
> + goto err;
> + }
> +
> + preloader_console_init();
> +
> + return;
> +
> +err:
> + printf("spl_board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board-tpl.c
> b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> new file mode 100644
> index 0000000..d517a33
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> @@ -0,0 +1,46 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define RK3066_TIMER_CONTROL 0x8
> +#define GRF_BASE 0x20008000
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Enable early UART on the RK3066 */
> +
> + struct rk3066_grf * const grf = (void *)GRF_BASE;
> +
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK << GPIO1B1_SHIFT |
> + GPIO1B0_MASK << GPIO1B0_SHIFT,
> + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
> + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
> +
> + debug_uart_init();
> +
> + printch('T');
> + printch('P');
> + printch('L');
> + printch('\n');
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1,
> 0x1);
> +
> + sdram_initialise();
> +
> + back_to_bootrom();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board.c
> b/arch/arm/mach-rockchip/rk3066-board.c
> new file mode 100644
> index 0000000..3d92253
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board.c
> @@ -0,0 +1,180 @@
> +/*
> + * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/boot_mode.h>
> +#include <asm/gpio.h>
> +#include <dm/pinctrl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_late_init(void)
> +{
> + struct rk3066_grf *grf;
> +
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(grf)) {
> + error("grf syscon returned %ld\n", PTR_ERR(grf));
> + } else {
> + /* enable noc remap to mimic legacy loaders */
> + rk_clrsetreg(&grf->soc_con0,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT);
> + }
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
> + struct udevice *pinctrl;
> + int ret;
> +
> + /*
> + * We need to implement sdcard iomux here for the further
> + * initialization, otherwise, it'll hit sdcard command sending
> + * timeout exception.
> + */
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +
> + return 0;
> +err:
> + printf("board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +
> + return -1;
> +#else
> + return 0;
> +#endif
> +}
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> + ret = ram_get_info(dev, &ram);
> + if (ret) {
> + debug("Cannot get DRAM size: %d\n", ret);
> + return ret;
> + }
> + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +#endif
> +
> +int print_cpuinfo (void)
> +{
> + printf("CPU: Rockchip RK3066\n");
> + return 0;
> +}
> +
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rk3066_otg_data = {
> + .rx_fifo_sz = 275,
> + .np_tx_fifo_sz = 16,
> + .tx_fifo_sz = 256,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + int node, phy_node;
> + const char *mode;
> + bool matched = false;
> + const void *blob = gd->fdt_blob;
> + u32 grf_phy_offset;
> +
> + /* find the usb_otg node */
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-usb");
> +
> + while (node > 0) {
> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
> + if (mode && strcmp(mode, "otg") == 0) {
> + matched = true;
> + break;
> + }
> +
> + node = fdt_node_offset_by_compatible(blob, node,
> + "rockchip,rk3066-usb");
> + }
> + if (!matched) {
> + debug("Not found usb_otg device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> + node = fdtdec_lookup_phandle(blob, node, "phys");
> + if (node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + phy_node = fdt_parent_offset(blob, node);
> + if (phy_node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + rk3066_otg_data.phy_of_node = phy_node;
> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
> +
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-grf");
> + if (node <= 0) {
> + debug("Not found grf device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_phy = grf_phy_offset +
> + fdtdec_get_addr(blob, node, "reg");
> +
> + return dwc2_udc_probe(&rk3066_otg_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig
> b/arch/arm/mach-rockchip/rk3066/Kconfig
> new file mode 100644
> index 0000000..27d32fd
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Kconfig
> @@ -0,0 +1,34 @@
> +if ROCKCHIP_RK3066
> +
> +config TARGET_MK808_RK3066
> + bool "MK808_RK3066"
> + help
> + MK808 is a tv stick with usb host and otg, microsd card slot,
> hdmi and wifi.
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x0800
> +
> +config SPL_LIBCOMMON_SUPPORT
> + default y
> +
> +config SPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config SPL_SERIAL_SUPPORT
> + default y
> +
> +config TPL_LIBCOMMON_SUPPORT
> + default y
> +
> +config TPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config TPL_SERIAL_SUPPORT
> + default y
> +
> +source "board/rikomagic/mk808_rk3066/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile
> b/arch/arm/mach-rockchip/rk3066/Makefile
> new file mode 100644
> index 0000000..4cf5df2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +ifndef CONFIG_TPL_BUILD
> +obj-y += clk_rk3066.o
> +obj-y += syscon_rk3066.o
> +else
> +obj-y += sdram_init.o
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> new file mode 100644
> index 0000000..ae52902
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2016 Google, Inc
> + * Written by Simon Glass <sjg@chromium.org>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3066_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> new file mode 100644
> index 0000000..57b2376
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> @@ -0,0 +1,54 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +
> +static const struct udevice_id rk3066_syscon_ids[] = {
> + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC
> },
> + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF
> },
> + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU
> },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3066) = {
> + .name = "rk3066_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> +};
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
> +{
> + dev->driver_data = dev->driver->of_match->data;
> + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(rockchip_rk3188_noc) = {
> + .name = "rockchip_rk3188_noc",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_grf) = {
> + .name = "rockchip_rk3066_grf",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 1,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
> + .name = "rockchip_rk3066_pmu",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 2,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +#endif
> diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_
> common.h
> new file mode 100644
> index 0000000..7009616
> --- /dev/null
> +++ b/include/configs/rk3066_common.h
> @@ -0,0 +1,125 @@
> +/*
> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_RK3066_COMMON_H
> +#define __CONFIG_RK3066_COMMON_H
> +
> +#include <asm/arch/hardware.h>
> +#include "rockchip-common.h"
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_MALLOC_LEN (64 << 20)
> +#define CONFIG_SYS_CBSIZE 256
> +
> +#define CONFIG_SYS_TIMER_RATE 24000000
> +#define CONFIG_SYS_TIMER_BASE 0x20038000
> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> +
> +#define CONFIG_SPL_BOARD_INIT
> +
> +#define CONFIG_SYS_TEXT_BASE 0x60408000
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
> +#define CONFIG_SYS_LOAD_ADDR 0x70800800
> +
> +#ifdef CONFIG_TPL_BUILD
> +#define CONFIG_SPL_TEXT_BASE 0x10080C04
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +/* tpl size max 32kb - 4byte RK30 header */
> +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
> +#elif defined(CONFIG_SPL_BUILD)
> +/* spl size max 200k */
> +#define CONFIG_SPL_MAX_SIZE 0x32000
> +#define CONFIG_SPL_TEXT_BASE 0x60000000
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +#define CONFIG_SPL_STACK_R_ADDR 0x70000000
> +#define CONFIG_SPL_STACK_R 1
> +#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
> +#define CONFIG_SPL_OF_CONTROL 1
> +#define CONFIG_SPL_OF_PLATDATA 1
> +#define CONFIG_SPL_FRAMEWORK 1
> +#define CONFIG_SPL_CLK 1
> +#define CONFIG_SPL_PINCTRL 1
> +#define CONFIG_SPL_REGMAP 1
> +#define CONFIG_SPL_SYSCON 1
> +#define CONFIG_SPL_RAM 1
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
> +#define CONFIG_SPL_MMC_SUPPORT 1
> +#define CONFIG_ROCKCHIP_SERIAL 1
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SPL_LIBDISK_SUPPORT 1
> +#define CONFIG_SPL_EXT_SUPPORT 1
> +#define CONFIG_SPL_FAT_SUPPORT 1
> +#define CONFIG_SPL_DM 1
> +#define CONFIG_SPL_GPIO_SUPPORT 1
> +#define CONFIG_SPL_POWER_SUPPORT 1
> +#endif
> +
> +#define CONFIG_SYS_NS16550_MEM32
> +
> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
> +
> +/* MMC/SD IP block */
> +#define CONFIG_BOUNCE_BUFFER
> +
> +#define CONFIG_CMD_CACHE
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define SDRAM_BANK_SIZE (1024UL << 20UL)
> +
> +#ifndef CONFIG_SPL_BUILD
> +/* usb */
> +#define CONFIG_USB
> +#define CONFIG_DM_USB
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_DWC2
> +
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_DWC2_OTG
> +#define CONFIG_ROCKCHIP_USB2_PHY
> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
> +
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_CMD_USB_MASS_STORAGE
> +
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
> +#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
> +
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x60000000\0" \
> + "pxefile_addr_r=0x60100000\0" \
> + "fdt_addr_r=0x61f00000\0" \
> + "kernel_addr_r=0x62000000\0" \
> + "ramdisk_addr_r=0x64000000\0"
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x6fffffff\0" \
> + "initrd_high=0x6fffffff\0" \
> + "partitions=" PARTS_DEFAULT \
> + ENV_MEM_LAYOUT_SETTINGS \
> + ROCKCHIP_DEVICE_SETTINGS \
> + BOOTENV
> +
> +#include <config_distro_defaults.h>
> +#endif
> +
> +#define CONFIG_PREBOOT
> +
> +#endif
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file
2017-06-06 21:09 ` Simon Glass
@ 2017-06-07 15:07 ` Paweł Jarosz
0 siblings, 0 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-07 15:07 UTC (permalink / raw)
To: u-boot
Hi Simon
W dniu 06.06.2017 o 23:09, Simon Glass pisze:
> Hi Pawel,
>
> On 6 June 2017 at 12:48, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> grf is needed by various drivers for rk3066 soc.
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++
>> 1 file changed, 621 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>> new file mode 100644
>> index 0000000..96b4ca6
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>> @@ -0,0 +1,621 @@
>> +/*
>> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef _ASM_ARCH_GRF_RK3066_H
>> +#define _ASM_ARCH_GRF_RK3066_H
>> +
>> +struct rk3066_grf_gpio_lh {
>> + u32 l;
>> + u32 h;
>> +};
>> +
>> +struct rk3066_grf {
>> + struct rk3066_grf_gpio_lh gpio_dir[7];
>> + struct rk3066_grf_gpio_lh gpio_do[7];
>> + struct rk3066_grf_gpio_lh gpio_en[7];
>> +
>> + u32 gpio0a_iomux;
>> + u32 gpio0b_iomux;
>> + u32 gpio0c_iomux;
>> + u32 gpio0d_iomux;
>> +
>> + u32 gpio1a_iomux;
>> + u32 gpio1b_iomux;
>> + u32 gpio1c_iomux;
>> + u32 gpio1d_iomux;
>> +
>> + u32 gpio2a_iomux;
>> + u32 gpio2b_iomux;
>> + u32 gpio2c_iomux;
>> + u32 gpio2d_iomux;
>> +
>> + u32 gpio3a_iomux;
>> + u32 gpio3b_iomux;
>> + u32 gpio3c_iomux;
>> + u32 gpio3d_iomux;
>> +
>> + u32 gpio4a_iomux;
>> + u32 gpio4b_iomux;
>> + u32 gpio4c_iomux;
>> + u32 gpio4d_iomux;
>> +
>> + u32 reserved0[5];
>> +
>> + u32 gpio6b_iomux;
>> +
>> + u32 reserved1[2];
>> +
>> + struct rk3066_grf_gpio_lh gpio_pull[7];
>> +
>> + u32 soc_con0;
>> + u32 soc_con1;
>> + u32 soc_con2;
>> +
>> + u32 soc_status0;
>> +
>> + u32 dmac1_con[3];
>> + u32 dmac2_con[4];
>> +
>> + u32 uoc0_con[3];
>> + u32 uoc1_con[4];
>> + u32 ddrc_con;
>> + u32 ddrc_stat;
>> +
>> + u32 reserved2[10];
>> +
>> + u32 os_reg[4];
>> +};
>> +check_member(rk3066_grf, os_reg[3], 0x01d4);
>> +
>> +/* GRF_GPIO0A_IOMUX */
>> +enum {
>> + GPIO0A6_SHIFT = 12,
>> + GPIO0A6_MASK = 1,
> Can you please use shifted masks for these values?
>
> GPIO0A6_MASK = 1 << GPIO0A6_SHIFT,
I will do that in the next version.
Regards
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 15:12 ` Paweł Jarosz
2017-06-08 12:41 ` Heiko Stübner
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-07 15:12 UTC (permalink / raw)
To: u-boot
Hi Simon,
W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> Hi Pawel,
>
> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
>> watchdog and uart
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> arch/arm/dts/rk3066a.dtsi | 699 ++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 699 insertions(+)
>> create mode 100644 arch/arm/dts/rk3066a.dtsi
> How come this file has 'a' on the end?
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Not sure why ... as there is no rk3066a named chip (acording to
datasheet) but there is rk3066b.
I have copied linux source without renaming it.
Regards
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 15:22 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-07 15:22 UTC (permalink / raw)
To: u-boot
Hi Simon
W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> Hi Pawel,
>
> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> +#include <dm/test.h>
>> +#include <dm/util.h>
>> +#include <power/regulator.h>
>> +#include <syscon.h>
> That should go below spi.h
>
Ok
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +u32 spl_boot_device(void)
>> +{
> This function seems to be common. Can you please (in a separate patch)
> move it into a separate shared file and delete all the copies?
Ok
>
>> +
>> + sdram_initialise();
> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>
Due to size issues i needed to move spl load to sdram (not sram) and
sdram settings
should be done by code executed in SRAM or you get to hang a board.
>> +
>> + back_to_bootrom();
>> +}
>> diff --git a/arch/arm/mach-rockchip/rk3066-board.c b/arch/arm/mach-rockchip/rk3066-board.c
>> new file mode 100644
>> index 0000000..3d92253
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066-board.c
>> @@ -0,0 +1,180 @@
>> +/*
>> + * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <ram.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/grf_rk3066.h>
>> +#include <asm/arch/periph.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +#include <asm/arch/boot_mode.h>
>> +#include <asm/gpio.h>
>> +#include <dm/pinctrl.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_late_init(void)
>> +{
>> + struct rk3066_grf *grf;
>> +
>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> + if (IS_ERR(grf)) {
>> + error("grf syscon returned %ld\n", PTR_ERR(grf));
> debug() might be better here. Also please return the error so that it halts.
Ok
>> + } else {
> Then drop this else because you will have returned by now.
Ok
>> + /* enable noc remap to mimic legacy loaders */
>> + rk_clrsetreg(&grf->soc_con0,
>> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
>> + NOC_REMAP_MASK << NOC_REMAP_SHIFT);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
>> + struct udevice *pinctrl;
>> + int ret;
>> +
>> + /*
>> + * We need to implement sdcard iomux here for the further
>> + * initialization, otherwise, it'll hit sdcard command sending
>> + * timeout exception.
>> + */
>> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> + if (ret) {
>> + debug("%s: Cannot find pinctrl device\n", __func__);
>> + goto err;
>> + }
>> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
>> + if (ret) {
>> + debug("%s: Failed to set up SD card\n", __func__);
>> + goto err;
>> + }
>> +
>> + return 0;
>> +err:
>> + printf("board_init: Error %d\n", ret);
>> +
>> + /* No way to report error here */
>> + hang();
>> +
>> + return -1;
>> +#else
>> + return 0;
>> +#endif
>> +}
>> +
>> +int dram_init(void)
>> +{
>> + struct ram_info ram;
>> + struct udevice *dev;
>> + int ret;
>> +
>> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (ret) {
>> + debug("DRAM init failed: %d\n", ret);
>> + return ret;
>> + }
>> + ret = ram_get_info(dev, &ram);
>> + if (ret) {
>> + debug("Cannot get DRAM size: %d\n", ret);
>> + return ret;
>> + }
>> + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
>> + gd->ram_size = ram.size;
>> +
>> + return 0;
>> +}
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +void enable_caches(void)
>> +{
>> + /* Enable D-cache. I-cache is already enabled in start.S */
>> + dcache_enable();
>> +}
>> +#endif
>> +
>> +int print_cpuinfo (void)
>> +{
>> + printf("CPU: Rockchip RK3066\n");
>> + return 0;
>> +}
>> +
>> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>> +#include <usb.h>
>> +#include <usb/dwc2_udc.h>
>> +
>> +static struct dwc2_plat_otg_data rk3066_otg_data = {
>> + .rx_fifo_sz = 275,
>> + .np_tx_fifo_sz = 16,
>> + .tx_fifo_sz = 256,
>> +};
>> +
>> +int board_usb_init(int index, enum usb_init_type init)
>> +{
>> + int node, phy_node;
>> + const char *mode;
>> + bool matched = false;
>> + const void *blob = gd->fdt_blob;
>> + u32 grf_phy_offset;
>> +
>> + /* find the usb_otg node */
>> + node = fdt_node_offset_by_compatible(blob, -1,
>> + "rockchip,rk3066-usb");
> Can you please use live tree functions? You'll need to add a separate
> patch to add this (see ofnode_path() for something simliar). Perhaps
> call it ofnode_by_compatible()?
>
> Ideally we should turn this into a driver so you can use dev_read_...
> functions. But that can come later.
>
>> +
>> + while (node > 0) {
>> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
> This becomes ofnode_read_string()
>
>> + if (mode && strcmp(mode, "otg") == 0) {
>> + matched = true;
>> + break;
>> + }
>> +
>> + node = fdt_node_offset_by_compatible(blob, node,
>> + "rockchip,rk3066-usb")
>> + }
>> + if (!matched) {
>> + debug("Not found usb_otg device\n");
>> + return -ENODEV;
>> + }
>> + rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> ofnode_get_addr
>
>> +
>> + node = fdtdec_lookup_phandle(blob, node, "phys");
> etc.
>
>> + if (node <= 0) {
>> + debug("Not found usb phy device\n");
>> + return -ENODEV;
>> + }
>> +
>> + phy_node = fdt_parent_offset(blob, node);
>> + if (phy_node <= 0) {
>> + debug("Not found usb phy device\n");
>> + return -ENODEV;
>> + }
>> +
>> + rk3066_otg_data.phy_of_node = phy_node;
>> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
>> +
>> + node = fdt_node_offset_by_compatible(blob, -1,
>> + "rockchip,rk3066-grf");
>> + if (node <= 0) {
>> + debug("Not found grf device\n");
>> + return -ENODEV;
>> + }
>> + rk3066_otg_data.regs_phy = grf_phy_offset +
>> + fdtdec_get_addr(blob, node, "reg");
>> +
>> + return dwc2_udc_probe(&rk3066_otg_data);
>> +}
>> +
>> +int board_usb_cleanup(int index, enum usb_init_type init)
>> +{
>> + return 0;
>> +}
>> +#endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
>> new file mode 100644
>> index 0000000..27d32fd
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/Kconfig
>> @@ -0,0 +1,34 @@
>> +if ROCKCHIP_RK3066
>> +
>> +config TARGET_MK808_RK3066
>> + bool "MK808_RK3066"
>> + help
>> + MK808 is a tv stick with usb host and otg, microsd card slot, hdmi and wifi.
>> +
>> +config SYS_SOC
>> + default "rockchip"
>> +
>> +config SYS_MALLOC_F_LEN
>> + default 0x0800
>> +
>> +config SPL_LIBCOMMON_SUPPORT
> You should be able to add these as 'imply' options now (to the
> ROCKCHIP_RK3066 config)
>
What do you mean by 'imply' options?
>> + default y
>> +
>> +config SPL_LIBGENERIC_SUPPORT
>> + default y
>> +
>> +config SPL_SERIAL_SUPPORT
>> + default y
>> +
>> +config TPL_LIBCOMMON_SUPPORT
>> + default y
>> +
>> +config TPL_LIBGENERIC_SUPPORT
>> + default y
>> +
>> +config TPL_SERIAL_SUPPORT
>> + default y
>> +
>> +source "board/rikomagic/mk808_rk3066/Kconfig"
>> +
>> +endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
>> new file mode 100644
>> index 0000000..4cf5df2
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
>> @@ -0,0 +1,12 @@
>> +#
>> +# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +ifndef CONFIG_TPL_BUILD
>> +obj-y += clk_rk3066.o
>> +obj-y += syscon_rk3066.o
>> +else
>> +obj-y += sdram_init.o
>> +endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> new file mode 100644
>> index 0000000..ae52902
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> @@ -0,0 +1,33 @@
>> +/*
>> + * Copyright (C) 2016 Google, Inc
>> + * Written by Simon Glass <sjg@chromium.org>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <syscon.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3066.h>
>> +
>> +int rockchip_get_clk(struct udevice **devp)
>> +{
>> + return uclass_get_device_by_driver(UCLASS_CLK,
>> + DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
>> +}
>> +
>> +void *rockchip_get_cru(void)
>> +{
>> + struct rk3066_clk_priv *priv;
>> + struct udevice *dev;
>> + int ret;
>> +
>> + ret = rockchip_get_clk(&dev);
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> + priv = dev_get_priv(dev);
>> +
>> + return priv->cru;
>> +}
>> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> new file mode 100644
>> index 0000000..57b2376
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> @@ -0,0 +1,54 @@
>> +/*
>> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <syscon.h>
>> +#include <asm/arch/clock.h>
>> +
>> +static const struct udevice_id rk3066_syscon_ids[] = {
>> + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
>> + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
>> + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(syscon_rk3066) = {
>> + .name = "rk3066_syscon",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids,
>> +};
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
>> +{
>> + dev->driver_data = dev->driver->of_match->data;
>> + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
>> +
>> + return 0;
>> +}
>> +
>> +U_BOOT_DRIVER(rockchip_rk3188_noc) = {
>> + .name = "rockchip_rk3188_noc",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3066_grf) = {
>> + .name = "rockchip_rk3066_grf",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids + 1,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
>> + .name = "rockchip_rk3066_pmu",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids + 2,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +#endif
>> diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
>> new file mode 100644
>> index 0000000..7009616
>> --- /dev/null
>> +++ b/include/configs/rk3066_common.h
>> @@ -0,0 +1,125 @@
>> +/*
>> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_RK3066_COMMON_H
>> +#define __CONFIG_RK3066_COMMON_H
>> +
>> +#include <asm/arch/hardware.h>
>> +#include "rockchip-common.h"
>> +
>> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>> +#define CONFIG_ENV_IS_NOWHERE
>> +#define CONFIG_ENV_SIZE 0x2000
>> +#define CONFIG_SYS_MAXARGS 16
>> +#define CONFIG_BAUDRATE 115200
>> +#define CONFIG_SYS_MALLOC_LEN (64 << 20)
>> +#define CONFIG_SYS_CBSIZE 256
>> +
>> +#define CONFIG_SYS_TIMER_RATE 24000000
>> +#define CONFIG_SYS_TIMER_BASE 0x20038000
>> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
>> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
>> +
>> +#define CONFIG_SPL_BOARD_INIT
>> +
>> +#define CONFIG_SYS_TEXT_BASE 0x60408000
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
>> +#define CONFIG_SYS_LOAD_ADDR 0x70800800
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> +#define CONFIG_SPL_TEXT_BASE 0x10080C04
>> +#define CONFIG_SPL_STACK 0x1008FFFF
>> +/* tpl size max 32kb - 4byte RK30 header */
>> +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
>> +#elif defined(CONFIG_SPL_BUILD)
>> +/* spl size max 200k */
>> +#define CONFIG_SPL_MAX_SIZE 0x32000
>> +#define CONFIG_SPL_TEXT_BASE 0x60000000
>> +#define CONFIG_SPL_STACK 0x1008FFFF
>> +#define CONFIG_SPL_STACK_R_ADDR 0x70000000
>> +#define CONFIG_SPL_STACK_R 1
>> +#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
>> +#define CONFIG_SPL_OF_CONTROL 1
>> +#define CONFIG_SPL_OF_PLATDATA 1
>> +#define CONFIG_SPL_FRAMEWORK 1
>> +#define CONFIG_SPL_CLK 1
>> +#define CONFIG_SPL_PINCTRL 1
>> +#define CONFIG_SPL_REGMAP 1
> Many of these should be set in Kconfig or the defconfig file.
>
Yes but some have gave me tpl build issues that's why i did that here
>> +#define CONFIG_SPL_SYSCON 1
>> +#define CONFIG_SPL_RAM 1
>> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
>> +#define CONFIG_SPL_MMC_SUPPORT 1
>> +#define CONFIG_ROCKCHIP_SERIAL 1
>> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
>> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
>> +#define CONFIG_SPL_LIBDISK_SUPPORT 1
>> +#define CONFIG_SPL_EXT_SUPPORT 1
>> +#define CONFIG_SPL_FAT_SUPPORT 1
>> +#define CONFIG_SPL_DM 1
>> +#define CONFIG_SPL_GPIO_SUPPORT 1
>> +#define CONFIG_SPL_POWER_SUPPORT 1
>> +#endif
>> +
>> +#define CONFIG_SYS_NS16550_MEM32
>> +
>> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
>> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
>> +
>> +/* MMC/SD IP block */
>> +#define CONFIG_BOUNCE_BUFFER
>> +
>> +#define CONFIG_CMD_CACHE
>> +
>> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +#define SDRAM_BANK_SIZE (1024UL << 20UL)
>> +
>> +#ifndef CONFIG_SPL_BUILD
>> +/* usb */
>> +#define CONFIG_USB
>> +#define CONFIG_DM_USB
>> +#define CONFIG_USB_STORAGE
>> +#define CONFIG_CMD_USB
>> +#define CONFIG_USB_DWC2
>> +
>> +#define CONFIG_USB_GADGET
>> +#define CONFIG_USB_GADGET_DUALSPEED
>> +#define CONFIG_USB_GADGET_DWC2_OTG
>> +#define CONFIG_ROCKCHIP_USB2_PHY
>> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
>> +
>> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
>> +#define CONFIG_CMD_USB_MASS_STORAGE
>> +
>> +#define CONFIG_USB_GADGET_DOWNLOAD
>> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
>> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
>> +#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
>> +
>> +#define ENV_MEM_LAYOUT_SETTINGS \
>> + "scriptaddr=0x60000000\0" \
>> + "pxefile_addr_r=0x60100000\0" \
>> + "fdt_addr_r=0x61f00000\0" \
>> + "kernel_addr_r=0x62000000\0" \
>> + "ramdisk_addr_r=0x64000000\0"
>> +
>> +#include <config_distro_bootcmd.h>
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "fdt_high=0x6fffffff\0" \
>> + "initrd_high=0x6fffffff\0" \
>> + "partitions=" PARTS_DEFAULT \
>> + ENV_MEM_LAYOUT_SETTINGS \
>> + ROCKCHIP_DEVICE_SETTINGS \
>> + BOOTENV
>> +
>> +#include <config_distro_defaults.h>
>> +#endif
>> +
>> +#define CONFIG_PREBOOT
>> +
>> +#endif
>> --
>> 2.7.4
>>
> Regards,
> Simon
Regards,
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 15:37 ` Paweł Jarosz
2017-06-09 11:46 ` Heiko Stuebner
2017-06-09 12:27 ` Simon Glass
0 siblings, 2 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-07 15:37 UTC (permalink / raw)
To: u-boot
Hi Simon,
W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> Hi Pawel,
>
> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
>> executes it. Then waits for back to bootrom and loads another 32KB to sram
>> which also executes. Sdram initialisation code needs to be in one of these two
>> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
>> and jumps to it.
>>
>> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
>> u-boot part(for example to boot from mmc you need to disable usb support.
>>
>> My solution to size problem is to move sdram initialisation code to tpl stage,
>> move spl part to third stage(reading 200KB data) and add support for loading
>> u-boot by spl from ext2/4, fat partitions.
>>
>> But moving sdram initialisation code to tpl increases size of tpl above 1KB
>> (first boot stage). Solution to this is to add code which will be below 1KB
>> offset in tpl binary and do back to bootrom at very beginning of the tpl
>> execution.
> So do you mean that TPL starts and then loads more of itself? Why not
> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
> not clear why.
Ad.1 No. Tpl starts and at the first execution returns to bootrom.
Bootrom then loads
rest of the tpl (31KB) and executes it for a second time.
Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
mmc. To load u-boot from
mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
support) i moved SPL to sdram.
Code executed in sdram can't mess with sdram settings because it will
hang the board. Sdram setup
needs to be done by code in SRAM (tpl).
>> Adding this few lines of code here meets these conditions.
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> arch/arm/cpu/armv7/start.S | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
>> index f06fd28..73e03d9 100644
>> --- a/arch/arm/cpu/armv7/start.S
>> +++ b/arch/arm/cpu/armv7/start.S
>> @@ -36,6 +36,19 @@
>> #endif
>>
>> reset:
>> +
>> +#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
>> + ldr r3, =0x10080900
>> + ldr r0, [r3]
>> + cmp r0, #1
>> + movne r0, #1
>> + strne r0, [r3]
>> + beq out_of_bootrom
>> + bx lr
>> +out_of_bootrom:
>> + mov r0, #0
>> + str r0, [r3]
>> +#endif
>> /* Allow the board to save important registers */
>> b save_boot_params
>> save_boot_params_ret:
>> --
>> 2.7.4
>>
> Regards,
> Simon
Regards,
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-06 21:10 ` Simon Glass
@ 2017-06-07 15:44 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-07 15:44 UTC (permalink / raw)
To: u-boot
Hi Simon,
W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> Hi Pawel,
>
> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> Add sdram initialisation code which will be ussed by tpl first boot stage.
>> We need to implement sdram initialisation in tpl due to size issues on rk3066
>> platform.
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> ---
>> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
>> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995 ++++++++++++++++++++++++
>> 2 files changed, 1000 insertions(+)
>> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>> index 3d7929f..74d11c6 100644
>> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>> @@ -10,6 +10,11 @@
>> #include <asm/arch/ddr_rk3288.h>
>>
>> /*
>> + * RK3066 Tpl memory init.
>> + */
>> +void sdram_initialise(void);
>> +
>> +/*
>> * RK3188 Memory scheduler register map.
>> */
>> struct rk3188_msch {
>> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>> new file mode 100644
>> index 0000000..e7e506a
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>> @@ -0,0 +1,995 @@
>> +/*
>> + * (C) Copyright 2015 Google, Inc
>> + * Copyright 2014 Rockchip Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Adapted from the very similar rk3288 ddr init.
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <errno.h>
>> +#include <ram.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3066.h>
>> +#include <asm/arch/ddr_rk3188.h>
>> +#include <asm/arch/grf_rk3066.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +#include <asm/arch/sdram.h>
>> +#include <linux/err.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct pll_div {
>> + u32 nr;
>> + u32 nf;
>> + u32 no;
>> +};
>> +
>> +enum {
>> + VCO_MAX_HZ = 1416U * 1000000,
>> + VCO_MIN_HZ = 300 * 1000000,
>> + OUTPUT_MAX_HZ = 1416U * 1000000,
>> + OUTPUT_MIN_HZ = 30 * 1000000,
>> + FREF_MAX_HZ = 1416U * 1000000,
>> + FREF_MIN_HZ = 30 * 1000,
>> +};
>> +
>> +enum {
>> + /* PLL CON0 */
>> + PLL_OD_MASK = 0x0f,
>> +
>> + /* PLL CON1 */
>> + PLL_NF_MASK = 0x1fff,
>> +
>> + /* PLL CON2 */
>> + PLL_BWADJ_MASK = 0x0fff,
>> +
>> + /* PLL CON3 */
>> + PLL_RESET_SHIFT = 5,
>> +
>> + /* GRF_SOC_STATUS0 */
>> + SOCSTS_DPLL_LOCK = 1 << 4,
>> + SOCSTS_APLL_LOCK = 1 << 5,
>> + SOCSTS_CPLL_LOCK = 1 << 6,
>> + SOCSTS_GPLL_LOCK = 1 << 7,
>> +};
>> +
>> +#define CRU_BASE 0x20000000
>> +#define GRF_BASE 0x20008000
>> +#define PMU_BASE 0x20004000
>> +#define PCTL_BASE 0x20020000
>> +#define PUBL_BASE 0x20040000
>> +#define NOC_BASE 0x10128000
> I'm assume we cannot use the DT / syscon because of space constraints?
Correct.
>> +
>> +#define RK3066_PCTL_TIMING_DEFAULT { \
> Do you need this? Why not just put these values below and avoid the indirection?
Some board may need this in the future as sdram timings are not universal.
Default timings are dumped from rockchip proprietary loader.
Look here:
> +#ifndef RK3066_PCTL_TIMING
> +#define RK3066_PCTL_TIMING RK3066_PCTL_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_PHY_TIMING
> +#define RK3066_PHY_TIMING RK3066_PHY_TIMING_DEFAULT
> +#endif
> +
> +#ifndef RK3066_SDRAM_PARAMS
> +#define RK3066_SDRAM_PARAMS RK3066_SDRAM_PARAMS_DEFAULT
> +#endif
> +
> +struct chan_info {
> + struct rk3288_ddr_pctl *pctl;
> + struct rk3288_ddr_publ *publ;
> + struct rk3188_msch *msch;
> +};
> +
> +struct dram_info {
> + struct chan_info chan[1];
> + struct ram_info info;
> + struct rk3066_cru *cru;
> + struct rk3066_grf *grf;
> + struct rk3188_pmu *pmu;
> +};
> +
> +struct rk3066_sdram_params {
> + struct rk3288_sdram_channel ch[2];
> + struct rk3288_sdram_pctl_timing pctl_timing;
> + struct rk3288_sdram_phy_timing phy_timing;
> + struct rk3288_base_params base;
> + int num_channels;
> + struct regmap *map;
> +};
> +
> +const int ddrconf_table[] = {
> + /*
> + * [5:4] row(13+n)
> + * [1:0] col(9+n), assume bw=2
> + * row col,bw
> + */
> + 0,
> + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
> You can drop the ()
Ok
>> + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
>> + ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
>> + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
>> + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
>> + ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
>> + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
>> + ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
>> + 0,
>> + 0,
>> + 0,
>> + 0,
>> + 0,
>> + 0,
>> + 0,
>> +};
>> +
>> +#define TEST_PATTEN 0x5aa5f00f
>> +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
>> +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
>> +
>> +
>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n / sizeof(u32); i++) {
>> + writel(*src, dest);
>> + src++;
>> + dest++;
>> + }
>> +}
>> +
>> +static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
>> +{
>> + u32 phy_ctl_srstn_shift = 13;
>> + u32 ctl_psrstn_shift = 11;
>> + u32 ctl_srstn_shift = 10;
>> + u32 phy_psrstn_shift = 9;
>> + u32 phy_srstn_shift = 8;
>> +
>> + rk_clrsetreg(&cru->cru_softrst_con[5],
>> + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
>> + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
>> + 1 << phy_srstn_shift,
>> + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
>> + ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
>> + phy << phy_srstn_shift);
>> +}
>> +
> How similar is this to rk3288? Could we put common code in a separate file?
Not sure how similar is it to rk3288. CRU, GRF, PMU differ a little
between socs.
Also i needed to add few adjustments to make it build and run with tpl.
> Regards,
> Simon
Regards
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc
2017-06-07 3:23 ` Kever Yang
@ 2017-06-08 3:30 ` Simon Glass
0 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-08 3:30 UTC (permalink / raw)
To: u-boot
Hi Kever,
On 6 June 2017 at 21:23, Kever Yang <kever.yang@rock-chips.com> wrote:
> Simon,
>
>
>
> On 06/07/2017 05:10 AM, Simon Glass wrote:
>>
>> Hi Pawel,
>>
>> On 6 June 2017 at 12:51, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
>>> internal dma support and max driver frequency.
>>>
>>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>>> ---
>>> drivers/mmc/rockchip_dw_mmc.c | 31 +++++++++++++++++++++++++++++--
>>> 1 file changed, 29 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/rockchip_dw_mmc.c
>>> b/drivers/mmc/rockchip_dw_mmc.c
>>> index 25a21e2..d94c395 100644
>>> --- a/drivers/mmc/rockchip_dw_mmc.c
>>> +++ b/drivers/mmc/rockchip_dw_mmc.c
>>> @@ -22,8 +22,14 @@ DECLARE_GLOBAL_DATA_PTR;
>>>
>>> struct rockchip_mmc_plat {
>>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> +
>>> +#ifdef CONFIG_ROCKCHIP_RK3066
>>> + struct dtd_rockchip_rk2928_dw_mshc dtplat;
>>> +#else
>>> struct dtd_rockchip_rk3288_dw_mshc dtplat;
>>> #endif
>>> +
>>> +#endif
>>> struct mmc_config cfg;
>>> struct mmc mmc;
>>> };
>>> @@ -109,8 +115,11 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>>> int ret;
>>>
>>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> +#ifdef CONFIG_ROCKCHIP_RK3066
>>> + struct dtd_rockchip_rk2928_dw_mshc *dtplat = &plat->dtplat;
>>> +#else
>>> struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
>>> -
>>> +#endif
>>
>> I am not keen on this - it will get ugly. Can you please do this:
>>
>> Create a new driver for rk3288 which just has the platdata stuff,
>> rockchip_dwmmc_ofdata_to_platdata() and the U_BOOT_DRIVER().
>> Everything else should remain in this file.
>>
>> Then in a new patch, create a driver for rk3066 which uses the same
>> common elements from rockchip_dw_mmc.c
>
>
> I think I have discuss this with you online or offline for many times,
> when OF_PLATADATA enabled, the dts is pre-compile by dtoc and then
> there is structure like 'dtd_rockchip_rk2928_dw_mshc' which is from the dts
> node compatible name, I propose to use the last compatible name in dtoc
> instead of the first one, then we can get the same structure name and used
> in drivers.
>
> I still not enable the dwmmc when OF_PLATDATA enabled on rk3399 because
> of the same reason.
>
> I think we should fix this from the root cause, but not make different
> driver
> for different SoCs.
OK, well if you think that will work it is fine with me. I will take a
look at the change.
Regards,
Simon
>
> Thanks,
> - Kever
>>
>>
>>> host->name = dev->name;
>>> host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
>>> host->buswidth = dtplat->bus_width;
>>> @@ -118,7 +127,12 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>>> host->priv = dev;
>>> host->dev_index = 0;
>>> priv->fifo_depth = dtplat->fifo_depth;
>>> +
>>> +#ifdef CONFIG_ROCKCHIP_RK3066
>>> + priv->fifo_mode = 1;
>>> +#else
>>> priv->fifo_mode = 0;
>>> +#endif
>>
>> What about the fifo_mode property in the DT?
>>
>> If you have to hard-code this you should use a .data parameter in
>> rockchip_dwmmc_ids (e.g. RK2928, RK3288) and use that to determine the
>> mode. But hopefully the DT is enough.
>>
>> For OF_PLATDATA however I suggest you have a different probe() which
>> either sets up this value and then calls rockchip_dwmmc_probe(), or
>> add it as a parameter to rockchip_dwmmc_probe().
>>
>>> memcpy(priv->minmax, dtplat->clock_freq_min_max,
>>> sizeof(priv->minmax));
>>>
>>> ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks,
>>> &priv->clk);
>>> @@ -162,14 +176,27 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
>>> }
>>>
>>> static const struct udevice_id rockchip_dwmmc_ids[] = {
>>> + { .compatible = "rockchip,rk2928-dw-mshc" },
>>> { .compatible = "rockchip,rk3288-dw-mshc" },
>>> { }
>>> };
>>>
>>> +U_BOOT_DRIVER(rockchip_rk2928_dw_mshc) = {
>>> + .name = "rockchip_rk2928_dw_mshc",
>>> + .id = UCLASS_MMC,
>>> + .of_match = rockchip_dwmmc_ids,
>>> + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
>>> + .ops = &dm_dwmci_ops,
>>> + .bind = rockchip_dwmmc_bind,
>>> + .probe = rockchip_dwmmc_probe,
>>> + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
>>> + .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
>>> +};
>>> +
>>> U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
>>> .name = "rockchip_rk3288_dw_mshc",
>>> .id = UCLASS_MMC,
>>> - .of_match = rockchip_dwmmc_ids,
>>
>> I think you ne
>>>
>>> .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
>>> .ops = &dm_dwmci_ops,
>>> .bind = rockchip_dwmmc_bind,
>>> --
>>> 2.7.4
>>>
>> Regards,
>> Simon
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot at lists.denx.de
>> https://lists.denx.de/listinfo/u-boot
>
>
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-07 15:12 ` Paweł Jarosz
@ 2017-06-08 12:41 ` Heiko Stübner
0 siblings, 0 replies; 86+ messages in thread
From: Heiko Stübner @ 2017-06-08 12:41 UTC (permalink / raw)
To: u-boot
Am Mittwoch, 7. Juni 2017, 17:12:24 CEST schrieb Paweł Jarosz:
> Hi Simon,
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> > Hi Pawel,
> >
> > On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> >> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
> >> watchdog and uart
> >>
> >> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> >> ---
> >>
> >> arch/arm/dts/rk3066a.dtsi | 699
> >> ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 699
> >> insertions(+)
> >> create mode 100644 arch/arm/dts/rk3066a.dtsi
> >
> > How come this file has 'a' on the end?
> >
> > Reviewed-by: Simon Glass <sjg@chromium.org>
>
> Not sure why ... as there is no rk3066a named chip (acording to
> datasheet) but there is rk3066b.
> I have copied linux source without renaming it.
actually there are "only" rk3066a and rk3066b ... only the rk3066a often
just gets called rk3066. If you look in device schematics you always find
the rk3066a naming.
Also, so far I haven't seen any rk3066b yet, therefore we have no support
for it at all.
Heiko
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-07 15:37 ` Paweł Jarosz
@ 2017-06-09 11:46 ` Heiko Stuebner
2017-06-09 12:31 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
1 sibling, 1 reply; 86+ messages in thread
From: Heiko Stuebner @ 2017-06-09 11:46 UTC (permalink / raw)
To: u-boot
Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
> Hi Simon,
>
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
> > Hi Pawel,
> >
> > On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> >> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> >> executes it. Then waits for back to bootrom and loads another 32KB to sram
> >> which also executes. Sdram initialisation code needs to be in one of these two
> >> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
> >> and jumps to it.
> >>
> >> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
> >> u-boot part(for example to boot from mmc you need to disable usb support.
> >>
> >> My solution to size problem is to move sdram initialisation code to tpl stage,
> >> move spl part to third stage(reading 200KB data) and add support for loading
> >> u-boot by spl from ext2/4, fat partitions.
> >>
> >> But moving sdram initialisation code to tpl increases size of tpl above 1KB
> >> (first boot stage). Solution to this is to add code which will be below 1KB
> >> offset in tpl binary and do back to bootrom at very beginning of the tpl
> >> execution.
> > So do you mean that TPL starts and then loads more of itself? Why not
> > put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
> > not clear why.
> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
> Bootrom then loads
> rest of the tpl (31KB) and executes it for a second time.
>
> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
> mmc. To load u-boot from
> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
> support) i moved SPL to sdram.
> Code executed in sdram can't mess with sdram settings because it will
> hang the board. Sdram setup
> needs to be done by code in SRAM (tpl).
At least the rk3288-Firefly was able to also have mmc stack in the SPL in
the past, without requiring the back_to_bootrom at all. So question would
be why this doesn't fit anymore, or on the rk3066 specifically.
Also, it seems like I got my hands on a preliminary (linux/mtd) nand driver
(rk3228 but cursory glance at the registers suggests that it may actually
work on previous socs down to the rk3066 as well) and it may be possible
to adapt that for uboot, therefore making the spl able to also load the
full u-boot from without needing back_to_bootrom.
Heiko
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-07 15:22 ` Paweł Jarosz
@ 2017-06-09 12:27 ` Simon Glass
2017-06-09 13:03 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-09 12:27 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Hi Simon
>
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>
>> Hi Pawel,
>>
>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> +#include <dm/test.h>
>>> +#include <dm/util.h>
>>> +#include <power/regulator.h>
>>> +#include <syscon.h>
>>
>> That should go below spi.h
>>
> Ok
>>>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +u32 spl_boot_device(void)
>>> +{
>>
>> This function seems to be common. Can you please (in a separate patch)
>> move it into a separate shared file and delete all the copies?
>
> Ok
>>
>>
>>> +
>>> + sdram_initialise();
>>
>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>
> Due to size issues i needed to move spl load to sdram (not sram) and sdram
> settings
> should be done by code executed in SRAM or you get to hang a board.
What is the size limit on SRAM?
[...]
>>> +config SYS_SOC
>>> + default "rockchip"
>>> +
>>> +config SYS_MALLOC_F_LEN
>>> + default 0x0800
>>> +
>>> +config SPL_LIBCOMMON_SUPPORT
>>
>> You should be able to add these as 'imply' options now (to the
>> ROCKCHIP_RK3066 config)
>>
> What do you mean by 'imply' options?
Things like:
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SPL
imply SPL_LIBCOMMON_SUPPORT
Either select or imply cause that option to be enabled.
>>> +#define CONFIG_SPL_FRAMEWORK 1
>>> +#define CONFIG_SPL_CLK 1
>>> +#define CONFIG_SPL_PINCTRL 1
>>> +#define CONFIG_SPL_REGMAP 1
>>
>> Many of these should be set in Kconfig or the defconfig file.
>>
> Yes but some have gave me tpl build issues that's why i did that here
We need to figure out if TPL is really needed. E.g. I don't think
kylin_rk3036 needs it. It produces an SPL that is about 4KB.
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-07 15:37 ` Paweł Jarosz
2017-06-09 11:46 ` Heiko Stuebner
@ 2017-06-09 12:27 ` Simon Glass
2017-06-09 13:11 ` Paweł Jarosz
1 sibling, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-09 12:27 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 7 June 2017 at 09:37, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Hi Simon,
>
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>
>> Hi Pawel,
>>
>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>> sram
>>> which also executes. Sdram initialisation code needs to be in one of
>>> these two
>>> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
>>> and jumps to it.
>>>
>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to low
>>> for
>>> u-boot part(for example to boot from mmc you need to disable usb support.
>>>
>>> My solution to size problem is to move sdram initialisation code to tpl
>>> stage,
>>> move spl part to third stage(reading 200KB data) and add support for
>>> loading
>>> u-boot by spl from ext2/4, fat partitions.
>>>
>>> But moving sdram initialisation code to tpl increases size of tpl above
>>> 1KB
>>> (first boot stage). Solution to this is to add code which will be below
>>> 1KB
>>> offset in tpl binary and do back to bootrom at very beginning of the tpl
>>> execution.
>>
>> So do you mean that TPL starts and then loads more of itself? Why not
>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>> not clear why.
>
> Ad.1 No. Tpl starts and at the first execution returns to bootrom. Bootrom
> then loads
> rest of the tpl (31KB) and executes it for a second time.
So can we do this trick with SPL and drop TPL?
>
> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to mmc.
> To load u-boot from
> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc support) i
> moved SPL to sdram.
> Code executed in sdram can't mess with sdram settings because it will hang
> the board. Sdram setup
> needs to be done by code in SRAM (tpl).
You should be able to fit MMC and SDRAM into 32KB. E.g. I can build
firefly-rk3288 that way as Heiko mentions
>
>>> Adding this few lines of code here meets these conditions.
>>>
>>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>>> ---
>>> arch/arm/cpu/armv7/start.S | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
>>> index f06fd28..73e03d9 100644
>>> --- a/arch/arm/cpu/armv7/start.S
>>> +++ b/arch/arm/cpu/armv7/start.S
>>> @@ -36,6 +36,19 @@
>>> #endif
>>>
>>> reset:
>>> +
>>> +#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
>>> + ldr r3, =0x10080900
>>> + ldr r0, [r3]
>>> + cmp r0, #1
>>> + movne r0, #1
>>> + strne r0, [r3]
>>> + beq out_of_bootrom
>>> + bx lr
>>> +out_of_bootrom:
>>> + mov r0, #0
>>> + str r0, [r3]
>>> +#endif
>>> /* Allow the board to save important registers */
>>> b save_boot_params
>>> save_boot_params_ret:
>>> --
>>> 2.7.4
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-07 15:44 ` Paweł Jarosz
@ 2017-06-09 12:27 ` Simon Glass
2017-06-09 13:15 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-09 12:27 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 7 June 2017 at 09:44, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Hi Simon,
>
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>
>> Hi Pawel,
>>
>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Add sdram initialisation code which will be ussed by tpl first boot
>>> stage.
>>> We need to implement sdram initialisation in tpl due to size issues on
>>> rk3066
>>> platform.
>>>
>>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>>> ---
>>> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
>>> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995
>>> ++++++++++++++++++++++++
>>> 2 files changed, 1000 insertions(+)
>>> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>> b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>> index 3d7929f..74d11c6 100644
>>> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>> @@ -10,6 +10,11 @@
>>> #include <asm/arch/ddr_rk3288.h>
>>>
>>> /*
>>> + * RK3066 Tpl memory init.
>>> + */
>>> +void sdram_initialise(void);
>>> +
>>> +/*
>>> * RK3188 Memory scheduler register map.
>>> */
>>> struct rk3188_msch {
>>> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>> b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>> new file mode 100644
>>> index 0000000..e7e506a
>>> --- /dev/null
>>> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>> @@ -0,0 +1,995 @@
>>> +/*
>>> + * (C) Copyright 2015 Google, Inc
>>> + * Copyright 2014 Rockchip Inc.
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0
>>> + *
>>> + * Adapted from the very similar rk3288 ddr init.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <clk.h>
>>> +#include <errno.h>
>>> +#include <ram.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/cru_rk3066.h>
>>> +#include <asm/arch/ddr_rk3188.h>
>>> +#include <asm/arch/grf_rk3066.h>
>>> +#include <asm/arch/pmu_rk3188.h>
>>> +#include <asm/arch/sdram.h>
>>> +#include <linux/err.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +struct pll_div {
>>> + u32 nr;
>>> + u32 nf;
>>> + u32 no;
>>> +};
>>> +
>>> +enum {
>>> + VCO_MAX_HZ = 1416U * 1000000,
>>> + VCO_MIN_HZ = 300 * 1000000,
>>> + OUTPUT_MAX_HZ = 1416U * 1000000,
>>> + OUTPUT_MIN_HZ = 30 * 1000000,
>>> + FREF_MAX_HZ = 1416U * 1000000,
>>> + FREF_MIN_HZ = 30 * 1000,
>>> +};
>>> +
>>> +enum {
>>> + /* PLL CON0 */
>>> + PLL_OD_MASK = 0x0f,
>>> +
>>> + /* PLL CON1 */
>>> + PLL_NF_MASK = 0x1fff,
>>> +
>>> + /* PLL CON2 */
>>> + PLL_BWADJ_MASK = 0x0fff,
>>> +
>>> + /* PLL CON3 */
>>> + PLL_RESET_SHIFT = 5,
>>> +
>>> + /* GRF_SOC_STATUS0 */
>>> + SOCSTS_DPLL_LOCK = 1 << 4,
>>> + SOCSTS_APLL_LOCK = 1 << 5,
>>> + SOCSTS_CPLL_LOCK = 1 << 6,
>>> + SOCSTS_GPLL_LOCK = 1 << 7,
>>> +};
>>> +
>>> +#define CRU_BASE 0x20000000
>>> +#define GRF_BASE 0x20008000
>>> +#define PMU_BASE 0x20004000
>>> +#define PCTL_BASE 0x20020000
>>> +#define PUBL_BASE 0x20040000
>>> +#define NOC_BASE 0x10128000
>>
>> I'm assume we cannot use the DT / syscon because of space constraints?
>
> Correct.
>>>
>>> +
>>> +#define RK3066_PCTL_TIMING_DEFAULT { \
>>
>> Do you need this? Why not just put these values below and avoid the
>> indirection?
>
> Some board may need this in the future as sdram timings are not universal.
> Default timings are dumped from rockchip proprietary loader.
> Look here:
In that case these should go in the device tree like with other Rockchip boards.
[...]
>>
>> How similar is this to rk3288? Could we put common code in a separate
>> file?
>
> Not sure how similar is it to rk3288. CRU, GRF, PMU differ a little between
> socs.
Where did you get the code from? I want to avoid duplicate code and
factor out the differences if we can.
> Also i needed to add few adjustments to make it build and run with tpl.
I am still hoping we can drop TPL.
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-09 11:46 ` Heiko Stuebner
@ 2017-06-09 12:31 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-09 12:31 UTC (permalink / raw)
To: u-boot
W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>> Hi Simon,
>>
>>
>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>> Hi Pawel,
>>>
>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
>>>> executes it. Then waits for back to bootrom and loads another 32KB to sram
>>>> which also executes. Sdram initialisation code needs to be in one of these two
>>>> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
>>>> and jumps to it.
>>>>
>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
>>>> u-boot part(for example to boot from mmc you need to disable usb support.
>>>>
>>>> My solution to size problem is to move sdram initialisation code to tpl stage,
>>>> move spl part to third stage(reading 200KB data) and add support for loading
>>>> u-boot by spl from ext2/4, fat partitions.
>>>>
>>>> But moving sdram initialisation code to tpl increases size of tpl above 1KB
>>>> (first boot stage). Solution to this is to add code which will be below 1KB
>>>> offset in tpl binary and do back to bootrom at very beginning of the tpl
>>>> execution.
>>> So do you mean that TPL starts and then loads more of itself? Why not
>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>> not clear why.
>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>> Bootrom then loads
>> rest of the tpl (31KB) and executes it for a second time.
>>
>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>> mmc. To load u-boot from
>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>> support) i moved SPL to sdram.
>> Code executed in sdram can't mess with sdram settings because it will
>> hang the board. Sdram setup
>> needs to be done by code in SRAM (tpl).
> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
> the past, without requiring the back_to_bootrom at all. So question would
> be why this doesn't fit anymore, or on the rk3066 specifically.
>
> Also, it seems like I got my hands on a preliminary (linux/mtd) nand driver
> (rk3228 but cursory glance at the registers suggests that it may actually
> work on previous socs down to the rk3066 as well) and it may be possible
> to adapt that for uboot, therefore making the spl able to also load the
> full u-boot from without needing back_to_bootrom.
>
>
> Heiko
I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
for tpl)size limit.
One (or two i didn't check how much) back to bootrom is required on
rk3066. If not done bootrom stays in weird state and halts on bringup
secondary cpu in kernel. So it's rk3066 specific.
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-09 12:27 ` Simon Glass
@ 2017-06-09 13:03 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-09 13:03 UTC (permalink / raw)
To: u-boot
W dniu 09.06.2017 o 14:27, Simon Glass pisze:
> Hi Pawel,
>
> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> Hi Simon
>>
>>
>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>> Hi Pawel,
>>>
>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> +#include <dm/test.h>
>>>> +#include <dm/util.h>
>>>> +#include <power/regulator.h>
>>>> +#include <syscon.h>
>>> That should go below spi.h
>>>
>> Ok
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +u32 spl_boot_device(void)
>>>> +{
>>> This function seems to be common. Can you please (in a separate patch)
>>> move it into a separate shared file and delete all the copies?
>> Ok
>>>
>>>> +
>>>> + sdram_initialise();
>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>
>> Due to size issues i needed to move spl load to sdram (not sram) and sdram
>> settings
>> should be done by code executed in SRAM or you get to hang a board.
> What is the size limit on SRAM?
RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
> [...]
>
>>>> +config SYS_SOC
>>>> + default "rockchip"
>>>> +
>>>> +config SYS_MALLOC_F_LEN
>>>> + default 0x0800
>>>> +
>>>> +config SPL_LIBCOMMON_SUPPORT
>>> You should be able to add these as 'imply' options now (to the
>>> ROCKCHIP_RK3066 config)
>>>
>> What do you mean by 'imply' options?
> Things like:
>
> config ROCKCHIP_RK3288
> bool "Support Rockchip RK3288"
> select CPU_V7
> select SPL_BOARD_INIT if SPL
> select SUPPORT_SPL
> select SPL
> imply SPL_LIBCOMMON_SUPPORT
>
> Either select or imply cause that option to be enabled.
>
>>>> +#define CONFIG_SPL_FRAMEWORK 1
>>>> +#define CONFIG_SPL_CLK 1
>>>> +#define CONFIG_SPL_PINCTRL 1
>>>> +#define CONFIG_SPL_REGMAP 1
>>> Many of these should be set in Kconfig or the defconfig file.
>>>
>> Yes but some have gave me tpl build issues that's why i did that here
> We need to figure out if TPL is really needed. E.g. I don't think
> kylin_rk3036 needs it. It produces an SPL that is about 4KB.
RK3036 has a different bootrom load process so we shouldn't compare
those two.
Better is to compare RK3066 and RK3188 as those are similiar(RK3188 is
without 200KB limit i think)
Paweł
> Regards,
> Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-09 12:27 ` Simon Glass
@ 2017-06-09 13:11 ` Paweł Jarosz
0 siblings, 0 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-09 13:11 UTC (permalink / raw)
To: u-boot
W dniu 09.06.2017 o 14:27, Simon Glass pisze:
> So can we do this trick with SPL and drop TPL?
I think it's better to leave tpl build as it is.
>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to mmc.
>> To load u-boot from
>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc support) i
>> moved SPL to sdram.
>> Code executed in sdram can't mess with sdram settings because it will hang
>> the board. Sdram setup
>> needs to be done by code in SRAM (tpl).
> You should be able to fit MMC and SDRAM into 32KB. E.g. I can build
> firefly-rk3288 that way as Heiko mentions
>
Maybe i could drop some configs and fit in 32KB SPL but not with very
convenient for users configs for loading u-boot from partition and not
offset in mmc :-).
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-09 12:27 ` Simon Glass
@ 2017-06-09 13:15 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-09 13:15 UTC (permalink / raw)
To: u-boot
W dniu 09.06.2017 o 14:27, Simon Glass pisze:
> Hi Pawel,
>
> On 7 June 2017 at 09:44, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> Hi Simon,
>>
>>
>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>
>>> Hi Pawel,
>>>
>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> Add sdram initialisation code which will be ussed by tpl first boot
>>>> stage.
>>>> We need to implement sdram initialisation in tpl due to size issues on
>>>> rk3066
>>>> platform.
>>>>
>>>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>>>> ---
>>>> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
>>>> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995
>>>> ++++++++++++++++++++++++
>>>> 2 files changed, 1000 insertions(+)
>>>> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>>
>>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>> b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>> index 3d7929f..74d11c6 100644
>>>> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>> @@ -10,6 +10,11 @@
>>>> #include <asm/arch/ddr_rk3288.h>
>>>>
>>>> /*
>>>> + * RK3066 Tpl memory init.
>>>> + */
>>>> +void sdram_initialise(void);
>>>> +
>>>> +/*
>>>> * RK3188 Memory scheduler register map.
>>>> */
>>>> struct rk3188_msch {
>>>> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>> b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>> new file mode 100644
>>>> index 0000000..e7e506a
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>> @@ -0,0 +1,995 @@
>>>> +/*
>>>> + * (C) Copyright 2015 Google, Inc
>>>> + * Copyright 2014 Rockchip Inc.
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0
>>>> + *
>>>> + * Adapted from the very similar rk3288 ddr init.
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <clk.h>
>>>> +#include <errno.h>
>>>> +#include <ram.h>
>>>> +#include <asm/io.h>
>>>> +#include <asm/arch/clock.h>
>>>> +#include <asm/arch/cru_rk3066.h>
>>>> +#include <asm/arch/ddr_rk3188.h>
>>>> +#include <asm/arch/grf_rk3066.h>
>>>> +#include <asm/arch/pmu_rk3188.h>
>>>> +#include <asm/arch/sdram.h>
>>>> +#include <linux/err.h>
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +struct pll_div {
>>>> + u32 nr;
>>>> + u32 nf;
>>>> + u32 no;
>>>> +};
>>>> +
>>>> +enum {
>>>> + VCO_MAX_HZ = 1416U * 1000000,
>>>> + VCO_MIN_HZ = 300 * 1000000,
>>>> + OUTPUT_MAX_HZ = 1416U * 1000000,
>>>> + OUTPUT_MIN_HZ = 30 * 1000000,
>>>> + FREF_MAX_HZ = 1416U * 1000000,
>>>> + FREF_MIN_HZ = 30 * 1000,
>>>> +};
>>>> +
>>>> +enum {
>>>> + /* PLL CON0 */
>>>> + PLL_OD_MASK = 0x0f,
>>>> +
>>>> + /* PLL CON1 */
>>>> + PLL_NF_MASK = 0x1fff,
>>>> +
>>>> + /* PLL CON2 */
>>>> + PLL_BWADJ_MASK = 0x0fff,
>>>> +
>>>> + /* PLL CON3 */
>>>> + PLL_RESET_SHIFT = 5,
>>>> +
>>>> + /* GRF_SOC_STATUS0 */
>>>> + SOCSTS_DPLL_LOCK = 1 << 4,
>>>> + SOCSTS_APLL_LOCK = 1 << 5,
>>>> + SOCSTS_CPLL_LOCK = 1 << 6,
>>>> + SOCSTS_GPLL_LOCK = 1 << 7,
>>>> +};
>>>> +
>>>> +#define CRU_BASE 0x20000000
>>>> +#define GRF_BASE 0x20008000
>>>> +#define PMU_BASE 0x20004000
>>>> +#define PCTL_BASE 0x20020000
>>>> +#define PUBL_BASE 0x20040000
>>>> +#define NOC_BASE 0x10128000
>>> I'm assume we cannot use the DT / syscon because of space constraints?
>> Correct.
>>>> +
>>>> +#define RK3066_PCTL_TIMING_DEFAULT { \
>>> Do you need this? Why not just put these values below and avoid the
>>> indirection?
>> Some board may need this in the future as sdram timings are not universal.
>> Default timings are dumped from rockchip proprietary loader.
>> Look here:
> In that case these should go in the device tree like with other Rockchip boards.
> [...]
It's tpl build. Is device tree supported in tpl?
>>> How similar is this to rk3288? Could we put common code in a separate
>>> file?
>> Not sure how similar is it to rk3288. CRU, GRF, PMU differ a little between
>> socs.
> Where did you get the code from? I want to avoid duplicate code and
> factor out the differences if we can.
It's adjusted code from rk3188 sdram driver.
>> Also i needed to add few adjustments to make it build and run with tpl.
> I am still hoping we can drop TPL.
>
> Regards,
> Simon
Regards
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-09 13:03 ` Paweł Jarosz
@ 2017-06-12 23:50 ` Simon Glass
2017-06-14 12:15 ` Kever Yang
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-12 23:50 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 9 June 2017 at 07:03, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
>
> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>
>> Hi Pawel,
>>
>> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Hi Simon
>>>
>>>
>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>> +#include <dm/test.h>
>>>>> +#include <dm/util.h>
>>>>> +#include <power/regulator.h>
>>>>> +#include <syscon.h>
>>>>
>>>> That should go below spi.h
>>>>
>>> Ok
>>>>>
>>>>> +
>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>> +
>>>>> +u32 spl_boot_device(void)
>>>>> +{
>>>>
>>>> This function seems to be common. Can you please (in a separate patch)
>>>> move it into a separate shared file and delete all the copies?
>>>
>>> Ok
>>>>
>>>>
>>>>> +
>>>>> + sdram_initialise();
>>>>
>>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>>
>>> Due to size issues i needed to move spl load to sdram (not sram) and
>>> sdram
>>> settings
>>> should be done by code executed in SRAM or you get to hang a board.
>>
>> What is the size limit on SRAM?
>
>
> RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
That is not a very low limit. RK3288 uses SPL (and not TPL) and it has
the same limit. Can we not just drop the use of TPL?
>
>> [...]
>>
>>>>> +config SYS_SOC
>>>>> + default "rockchip"
>>>>> +
>>>>> +config SYS_MALLOC_F_LEN
>>>>> + default 0x0800
>>>>> +
>>>>> +config SPL_LIBCOMMON_SUPPORT
>>>>
>>>> You should be able to add these as 'imply' options now (to the
>>>> ROCKCHIP_RK3066 config)
>>>>
>>> What do you mean by 'imply' options?
>>
>> Things like:
>>
>> config ROCKCHIP_RK3288
>> bool "Support Rockchip RK3288"
>> select CPU_V7
>> select SPL_BOARD_INIT if SPL
>> select SUPPORT_SPL
>> select SPL
>> imply SPL_LIBCOMMON_SUPPORT
>>
>> Either select or imply cause that option to be enabled.
>>
>>>>> +#define CONFIG_SPL_FRAMEWORK 1
>>>>> +#define CONFIG_SPL_CLK 1
>>>>> +#define CONFIG_SPL_PINCTRL 1
>>>>> +#define CONFIG_SPL_REGMAP 1
>>>>
>>>> Many of these should be set in Kconfig or the defconfig file.
>>>>
>>> Yes but some have gave me tpl build issues that's why i did that here
>>
>> We need to figure out if TPL is really needed. E.g. I don't think
>> kylin_rk3036 needs it. It produces an SPL that is about 4KB.
>
>
> RK3036 has a different bootrom load process so we shouldn't compare those
> two.
> Better is to compare RK3066 and RK3188 as those are similiar(RK3188 is
> without 200KB limit i think)
OK, still I don't understand why SPL cannot work.
>
> Paweł
>>
>> Regards,
>> Simon
>
>
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-09 12:31 ` Paweł Jarosz
@ 2017-06-12 23:50 ` Simon Glass
2017-06-14 11:06 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-12 23:50 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
>
> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>
>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>
>>> Hi Simon,
>>>
>>>
>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>> and
>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>> sram
>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>> these two
>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>> 0x60000000
>>>>> and jumps to it.
>>>>>
>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>> low for
>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>> support.
>>>>>
>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>> stage,
>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>> loading
>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>
>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>> 1KB
>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>> 1KB
>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>> tpl
>>>>> execution.
>>>>
>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>> not clear why.
>>>
>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>> Bootrom then loads
>>> rest of the tpl (31KB) and executes it for a second time.
>>>
>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>> mmc. To load u-boot from
>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>> support) i moved SPL to sdram.
>>> Code executed in sdram can't mess with sdram settings because it will
>>> hang the board. Sdram setup
>>> needs to be done by code in SRAM (tpl).
>>
>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>> the past, without requiring the back_to_bootrom at all. So question would
>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>
>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>> driver
>> (rk3228 but cursory glance at the registers suggests that it may actually
>> work on previous socs down to the rk3066 as well) and it may be possible
>> to adapt that for uboot, therefore making the spl able to also load the
>> full u-boot from without needing back_to_bootrom.
>>
>>
>> Heiko
>
> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb for
> tpl)size limit.
> One (or two i didn't check how much) back to bootrom is required on rk3066.
> If not done bootrom stays in weird state and halts on bringup secondary cpu
> in kernel. So it's rk3066 specific.
What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
init and MMC stack. Are you building with Thumb 2?
If you are on irc we could try to clear this up more quicky (I am sjg1)
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-09 13:15 ` Paweł Jarosz
@ 2017-06-12 23:50 ` Simon Glass
0 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-12 23:50 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 9 June 2017 at 07:15, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
>
> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>
>> Hi Pawel,
>>
>> On 7 June 2017 at 09:44, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Hi Simon,
>>>
>>>
>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>
>>>> Hi Pawel,
>>>>
>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>> Add sdram initialisation code which will be ussed by tpl first boot
>>>>> stage.
>>>>> We need to implement sdram initialisation in tpl due to size issues on
>>>>> rk3066
>>>>> platform.
>>>>>
>>>>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>> ---
>>>>> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
>>>>> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995
>>>>> ++++++++++++++++++++++++
>>>>> 2 files changed, 1000 insertions(+)
>>>>> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>>>
>>>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>>> b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>>> index 3d7929f..74d11c6 100644
>>>>> --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
>>>>> @@ -10,6 +10,11 @@
>>>>> #include <asm/arch/ddr_rk3288.h>
>>>>>
>>>>> /*
>>>>> + * RK3066 Tpl memory init.
>>>>> + */
>>>>> +void sdram_initialise(void);
>>>>> +
>>>>> +/*
>>>>> * RK3188 Memory scheduler register map.
>>>>> */
>>>>> struct rk3188_msch {
>>>>> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>>> b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>>> new file mode 100644
>>>>> index 0000000..e7e506a
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-rockchip/rk3066/sdram_init.c
>>>>> @@ -0,0 +1,995 @@
>>>>> +/*
>>>>> + * (C) Copyright 2015 Google, Inc
>>>>> + * Copyright 2014 Rockchip Inc.
>>>>> + *
>>>>> + * SPDX-License-Identifier: GPL-2.0
>>>>> + *
>>>>> + * Adapted from the very similar rk3288 ddr init.
>>>>> + */
>>>>> +
>>>>> +#include <common.h>
>>>>> +#include <clk.h>
>>>>> +#include <errno.h>
>>>>> +#include <ram.h>
>>>>> +#include <asm/io.h>
>>>>> +#include <asm/arch/clock.h>
>>>>> +#include <asm/arch/cru_rk3066.h>
>>>>> +#include <asm/arch/ddr_rk3188.h>
>>>>> +#include <asm/arch/grf_rk3066.h>
>>>>> +#include <asm/arch/pmu_rk3188.h>
>>>>> +#include <asm/arch/sdram.h>
>>>>> +#include <linux/err.h>
>>>>> +
>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>> +
>>>>> +struct pll_div {
>>>>> + u32 nr;
>>>>> + u32 nf;
>>>>> + u32 no;
>>>>> +};
>>>>> +
>>>>> +enum {
>>>>> + VCO_MAX_HZ = 1416U * 1000000,
>>>>> + VCO_MIN_HZ = 300 * 1000000,
>>>>> + OUTPUT_MAX_HZ = 1416U * 1000000,
>>>>> + OUTPUT_MIN_HZ = 30 * 1000000,
>>>>> + FREF_MAX_HZ = 1416U * 1000000,
>>>>> + FREF_MIN_HZ = 30 * 1000,
>>>>> +};
>>>>> +
>>>>> +enum {
>>>>> + /* PLL CON0 */
>>>>> + PLL_OD_MASK = 0x0f,
>>>>> +
>>>>> + /* PLL CON1 */
>>>>> + PLL_NF_MASK = 0x1fff,
>>>>> +
>>>>> + /* PLL CON2 */
>>>>> + PLL_BWADJ_MASK = 0x0fff,
>>>>> +
>>>>> + /* PLL CON3 */
>>>>> + PLL_RESET_SHIFT = 5,
>>>>> +
>>>>> + /* GRF_SOC_STATUS0 */
>>>>> + SOCSTS_DPLL_LOCK = 1 << 4,
>>>>> + SOCSTS_APLL_LOCK = 1 << 5,
>>>>> + SOCSTS_CPLL_LOCK = 1 << 6,
>>>>> + SOCSTS_GPLL_LOCK = 1 << 7,
>>>>> +};
>>>>> +
>>>>> +#define CRU_BASE 0x20000000
>>>>> +#define GRF_BASE 0x20008000
>>>>> +#define PMU_BASE 0x20004000
>>>>> +#define PCTL_BASE 0x20020000
>>>>> +#define PUBL_BASE 0x20040000
>>>>> +#define NOC_BASE 0x10128000
>>>>
>>>> I'm assume we cannot use the DT / syscon because of space constraints?
>>>
>>> Correct.
>>>>>
>>>>> +
>>>>> +#define RK3066_PCTL_TIMING_DEFAULT { \
>>>>
>>>> Do you need this? Why not just put these values below and avoid the
>>>> indirection?
>>>
>>> Some board may need this in the future as sdram timings are not
>>> universal.
>>> Default timings are dumped from rockchip proprietary loader.
>>> Look here:
>>
>> In that case these should go in the device tree like with other Rockchip
>> boards.
>> [...]
>
>
> It's tpl build. Is device tree supported in tpl?
Well maybe, but you only use TPL if things are really tight, so I
wouldn't recommend it.
>
>>>> How similar is this to rk3288? Could we put common code in a separate
>>>> file?
>>>
>>> Not sure how similar is it to rk3288. CRU, GRF, PMU differ a little
>>> between
>>> socs.
>>
>> Where did you get the code from? I want to avoid duplicate code and
>> factor out the differences if we can.
>
>
> It's adjusted code from rk3188 sdram driver.
>
>>> Also i needed to add few adjustments to make it build and run with tpl.
>>
>> I am still hoping we can drop TPL.
>>
>> Regards,
>> Simon
>
>
> Regards
> Paweł
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-12 23:50 ` Simon Glass
@ 2017-06-14 11:06 ` Simon Glass
2017-06-15 7:15 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-14 11:06 UTC (permalink / raw)
To: u-boot
+Philippe
Hi Pawel,
On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
> Hi Pawel,
>
> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>>
>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>
>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>
>>>> Hi Simon,
>>>>
>>>>
>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>>
>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>> and
>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>> sram
>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>> these two
>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>> 0x60000000
>>>>>> and jumps to it.
>>>>>>
>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>> low for
>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>> support.
>>>>>>
>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>> stage,
>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>> loading
>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>
>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>> 1KB
>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>> 1KB
>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>> tpl
>>>>>> execution.
>>>>>
>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>> not clear why.
>>>>
>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>> Bootrom then loads
>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>
>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>> mmc. To load u-boot from
>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>> support) i moved SPL to sdram.
>>>> Code executed in sdram can't mess with sdram settings because it will
>>>> hang the board. Sdram setup
>>>> needs to be done by code in SRAM (tpl).
>>>
>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>>> the past, without requiring the back_to_bootrom at all. So question would
>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>
>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>> driver
>>> (rk3228 but cursory glance at the registers suggests that it may actually
>>> work on previous socs down to the rk3066 as well) and it may be possible
>>> to adapt that for uboot, therefore making the spl able to also load the
>>> full u-boot from without needing back_to_bootrom.
>>>
>>>
>>> Heiko
>>
>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb for
>> tpl)size limit.
>> One (or two i didn't check how much) back to bootrom is required on rk3066.
>> If not done bootrom stays in weird state and halts on bringup secondary cpu
>> in kernel. So it's rk3066 specific.
>
> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
> init and MMC stack. Are you building with Thumb 2?
>
> If you are on irc we could try to clear this up more quicky (I am sjg1)
To summarise where I think we got to:
- move DRAM init into SPL
- either have a very small TPL which just returns to boot ROM, or
adjust start.S to return to the boot room early in SPL to load the
other 31KB
Can you please post to the mailing list with your thoughts on this so
that others (including rockchip) can chime in? I think either will
work but I think others will have an opinion.
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-12 23:50 ` Simon Glass
@ 2017-06-14 12:15 ` Kever Yang
2017-06-15 14:57 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Kever Yang @ 2017-06-14 12:15 UTC (permalink / raw)
To: u-boot
Simon,
On 06/13/2017 07:50 AM, Simon Glass wrote:
> Hi Pawel,
>
> On 9 June 2017 at 07:03, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>>
>>> Hi Pawel,
>>>
>>> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> Hi Simon
>>>>
>>>>
>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>> Hi Pawel,
>>>>>
>>>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>> +#include <dm/test.h>
>>>>>> +#include <dm/util.h>
>>>>>> +#include <power/regulator.h>
>>>>>> +#include <syscon.h>
>>>>> That should go below spi.h
>>>>>
>>>> Ok
>>>>>> +
>>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>>> +
>>>>>> +u32 spl_boot_device(void)
>>>>>> +{
>>>>> This function seems to be common. Can you please (in a separate patch)
>>>>> move it into a separate shared file and delete all the copies?
>>>> Ok
>>>>>
>>>>>> +
>>>>>> + sdram_initialise();
>>>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>>>
>>>> Due to size issues i needed to move spl load to sdram (not sram) and
>>>> sdram
>>>> settings
>>>> should be done by code executed in SRAM or you get to hang a board.
>>> What is the size limit on SRAM?
>>
>> RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
> That is not a very low limit. RK3288 uses SPL (and not TPL) and it has
> the same limit. Can we not just drop the use of TPL?
I don't think rk3066 can drop TPL, because the bootrom for rk3066 is
very much like rk3188:
- bootrom read 1KB and run it, in purpose of get higher frequency;
- back to bootrom;
- bootrom continue read 31KB most and run it;
- back to bootrom if needed;
- boot rom read and run loader like uboot.
Thanks,
- Kever
>
>>> [...]
>>>
>>>>>> +config SYS_SOC
>>>>>> + default "rockchip"
>>>>>> +
>>>>>> +config SYS_MALLOC_F_LEN
>>>>>> + default 0x0800
>>>>>> +
>>>>>> +config SPL_LIBCOMMON_SUPPORT
>>>>> You should be able to add these as 'imply' options now (to the
>>>>> ROCKCHIP_RK3066 config)
>>>>>
>>>> What do you mean by 'imply' options?
>>> Things like:
>>>
>>> config ROCKCHIP_RK3288
>>> bool "Support Rockchip RK3288"
>>> select CPU_V7
>>> select SPL_BOARD_INIT if SPL
>>> select SUPPORT_SPL
>>> select SPL
>>> imply SPL_LIBCOMMON_SUPPORT
>>>
>>> Either select or imply cause that option to be enabled.
>>>
>>>>>> +#define CONFIG_SPL_FRAMEWORK 1
>>>>>> +#define CONFIG_SPL_CLK 1
>>>>>> +#define CONFIG_SPL_PINCTRL 1
>>>>>> +#define CONFIG_SPL_REGMAP 1
>>>>> Many of these should be set in Kconfig or the defconfig file.
>>>>>
>>>> Yes but some have gave me tpl build issues that's why i did that here
>>> We need to figure out if TPL is really needed. E.g. I don't think
>>> kylin_rk3036 needs it. It produces an SPL that is about 4KB.
>>
>> RK3036 has a different bootrom load process so we shouldn't compare those
>> two.
>> Better is to compare RK3066 and RK3188 as those are similiar(RK3188 is
>> without 200KB limit i think)
> OK, still I don't understand why SPL cannot work.
>
>> Paweł
>>> Regards,
>>> Simon
>>
> Regards,
> Simon
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-14 11:06 ` Simon Glass
@ 2017-06-15 7:15 ` Paweł Jarosz
2017-06-15 14:50 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-15 7:15 UTC (permalink / raw)
To: u-boot
Hi Simon
W dniu 14.06.2017 o 13:06, Simon Glass pisze:
> +Philippe
>
> Hi Pawel,
>
> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>> Hi Pawel,
>>
>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>
>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>> Hi Simon,
>>>>>
>>>>>
>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>>> and
>>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>>> sram
>>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>>> these two
>>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>>> 0x60000000
>>>>>>> and jumps to it.
>>>>>>>
>>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>>> low for
>>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>>> support.
>>>>>>>
>>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>>> stage,
>>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>>> loading
>>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>>
>>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>>> 1KB
>>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>>> 1KB
>>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>>> tpl
>>>>>>> execution.
>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>> not clear why.
>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>> Bootrom then loads
>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>
>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>> mmc. To load u-boot from
>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>> support) i moved SPL to sdram.
>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>> hang the board. Sdram setup
>>>>> needs to be done by code in SRAM (tpl).
>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>>>> the past, without requiring the back_to_bootrom at all. So question would
>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>
>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>> driver
>>>> (rk3228 but cursory glance at the registers suggests that it may actually
>>>> work on previous socs down to the rk3066 as well) and it may be possible
>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>> full u-boot from without needing back_to_bootrom.
>>>>
>>>>
>>>> Heiko
>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb for
>>> tpl)size limit.
>>> One (or two i didn't check how much) back to bootrom is required on rk3066.
>>> If not done bootrom stays in weird state and halts on bringup secondary cpu
>>> in kernel. So it's rk3066 specific.
>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>> init and MMC stack. Are you building with Thumb 2?
>>
>> If you are on irc we could try to clear this up more quicky (I am sjg1)
> To summarise where I think we got to:
>
> - move DRAM init into SPL
> - either have a very small TPL which just returns to boot ROM, or
> adjust start.S to return to the boot room early in SPL to load the
> other 31KB
>
> Can you please post to the mailing list with your thoughts on this so
> that others (including rockchip) can chime in? I think either will
> work but I think others will have an opinion.
>
> Regards,
> Simon
About moving dram init to spl i agree.
I think early back to bootrom in start.S is a good solution as it would
give me 1KB more space for spl and i could drop hacks like jumping to
spl in tpl board file. But I would like to hear the opinion of other
people on this.
Also i got a nandc driver from Heiko and i would like to adopt it for
u-boot in the next version. Is it ok?
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 7:15 ` Paweł Jarosz
@ 2017-06-15 14:50 ` Simon Glass
2017-06-15 15:42 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-15 14:50 UTC (permalink / raw)
To: u-boot
+ Some other rockchip people
Hi Pawel,
On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Hi Simon
>
>
> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>
> +Philippe
>
> Hi Pawel,
>
> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Pawel,
>
> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>
> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>
> Hi Simon,
>
>
> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>
> Hi Pawel,
>
> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
> and
> executes it. Then waits for back to bootrom and loads another 32KB to
> sram
> which also executes. Sdram initialisation code needs to be in one of
> these two
> steps. Then bootloader loads another ~200KB of data at offset
> 0x60000000
> and jumps to it.
>
> 32KB of data is a little low for tpl + spl part and ~200KB data is to
> low for
> u-boot part(for example to boot from mmc you need to disable usb
> support.
>
> My solution to size problem is to move sdram initialisation code to tpl
> stage,
> move spl part to third stage(reading 200KB data) and add support for
> loading
> u-boot by spl from ext2/4, fat partitions.
>
> But moving sdram initialisation code to tpl increases size of tpl above
> 1KB
> (first boot stage). Solution to this is to add code which will be below
> 1KB
> offset in tpl binary and do back to bootrom at very beginning of the
> tpl
> execution.
>
> So do you mean that TPL starts and then loads more of itself? Why not
> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
> not clear why.
>
> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
> Bootrom then loads
> rest of the tpl (31KB) and executes it for a second time.
>
> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
> mmc. To load u-boot from
> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
> support) i moved SPL to sdram.
> Code executed in sdram can't mess with sdram settings because it will
> hang the board. Sdram setup
> needs to be done by code in SRAM (tpl).
>
> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
> the past, without requiring the back_to_bootrom at all. So question would
> be why this doesn't fit anymore, or on the rk3066 specifically.
>
> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
> driver
> (rk3228 but cursory glance at the registers suggests that it may actually
> work on previous socs down to the rk3066 as well) and it may be possible
> to adapt that for uboot, therefore making the spl able to also load the
> full u-boot from without needing back_to_bootrom.
>
>
> Heiko
>
> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb for
> tpl)size limit.
> One (or two i didn't check how much) back to bootrom is required on rk3066.
> If not done bootrom stays in weird state and halts on bringup secondary cpu
> in kernel. So it's rk3066 specific.
>
> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
> init and MMC stack. Are you building with Thumb 2?
>
> If you are on irc we could try to clear this up more quicky (I am sjg1)
>
> To summarise where I think we got to:
>
> - move DRAM init into SPL
> - either have a very small TPL which just returns to boot ROM, or
> adjust start.S to return to the boot room early in SPL to load the
> other 31KB
>
> Can you please post to the mailing list with your thoughts on this so
> that others (including rockchip) can chime in? I think either will
> work but I think others will have an opinion.
>
> Regards,
> Simon
>
>
> About moving dram init to spl i agree.
>
> I think early back to bootrom in start.S is a good solution as it would give
> me 1KB more space for spl and i could drop hacks like jumping to spl in tpl
> board file. But I would like to hear the opinion of other people on this.
So with this solution there would be no TPL needed? It sounds
reasonable to me. I'd like to hear other opinions also.
>
> Also i got a nandc driver from Heiko and i would like to adopt it for u-boot
> in the next version. Is it ok?
Sounds good.
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-14 12:15 ` Kever Yang
@ 2017-06-15 14:57 ` Simon Glass
2017-06-15 15:41 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-15 14:57 UTC (permalink / raw)
To: u-boot
+Philipp
Hi Kever,
On 14 June 2017 at 06:15, Kever Yang <kever.yang@rock-chips.com> wrote:
> Simon,
>
>
>
> On 06/13/2017 07:50 AM, Simon Glass wrote:
>>
>> Hi Pawel,
>>
>> On 9 June 2017 at 07:03, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>>
>>> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>>>
>>>> Hi Pawel,
>>>>
>>>> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>> Hi Simon
>>>>>
>>>>>
>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>> wrote:
>>>>>>>
>>>>>>> +#include <dm/test.h>
>>>>>>> +#include <dm/util.h>
>>>>>>> +#include <power/regulator.h>
>>>>>>> +#include <syscon.h>
>>>>>>
>>>>>> That should go below spi.h
>>>>>>
>>>>> Ok
>>>>>>>
>>>>>>> +
>>>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>>>> +
>>>>>>> +u32 spl_boot_device(void)
>>>>>>> +{
>>>>>>
>>>>>> This function seems to be common. Can you please (in a separate patch)
>>>>>> move it into a separate shared file and delete all the copies?
>>>>>
>>>>> Ok
>>>>>>
>>>>>>
>>>>>>> +
>>>>>>> + sdram_initialise();
>>>>>>
>>>>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>>>>
>>>>> Due to size issues i needed to move spl load to sdram (not sram) and
>>>>> sdram
>>>>> settings
>>>>> should be done by code executed in SRAM or you get to hang a board.
>>>>
>>>> What is the size limit on SRAM?
>>>
>>>
>>> RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
>>
>> That is not a very low limit. RK3288 uses SPL (and not TPL) and it has
>> the same limit. Can we not just drop the use of TPL?
>
>
> I don't think rk3066 can drop TPL, because the bootrom for rk3066 is
> very much like rk3188:
> - bootrom read 1KB and run it, in purpose of get higher frequency;
> - back to bootrom;
> - bootrom continue read 31KB most and run it;
> - back to bootrom if needed;
> - boot rom read and run loader like uboot.
OK then it sounds like we will need TPL. Is that right Pawel?
>
> Thanks,
> - Kever
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-15 14:57 ` Simon Glass
@ 2017-06-15 15:41 ` Paweł Jarosz
2017-06-15 15:59 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-15 15:41 UTC (permalink / raw)
To: u-boot
Hi
W dniu 15.06.2017 o 16:57, Simon Glass pisze:
> +Philipp
>
> Hi Kever,
>
> On 14 June 2017 at 06:15, Kever Yang <kever.yang@rock-chips.com> wrote:
>> Simon,
>>
>>
>>
>> On 06/13/2017 07:50 AM, Simon Glass wrote:
>>> Hi Pawel,
>>>
>>> On 9 June 2017 at 07:03, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>
>>>> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>> Hi Simon
>>>>>>
>>>>>>
>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>> Hi Pawel,
>>>>>>>
>>>>>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>> wrote:
>>>>>>>> +#include <dm/test.h>
>>>>>>>> +#include <dm/util.h>
>>>>>>>> +#include <power/regulator.h>
>>>>>>>> +#include <syscon.h>
>>>>>>> That should go below spi.h
>>>>>>>
>>>>>> Ok
>>>>>>>> +
>>>>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>>>>> +
>>>>>>>> +u32 spl_boot_device(void)
>>>>>>>> +{
>>>>>>> This function seems to be common. Can you please (in a separate patch)
>>>>>>> move it into a separate shared file and delete all the copies?
>>>>>> Ok
>>>>>>>
>>>>>>>> +
>>>>>>>> + sdram_initialise();
>>>>>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>>>>>
>>>>>> Due to size issues i needed to move spl load to sdram (not sram) and
>>>>>> sdram
>>>>>> settings
>>>>>> should be done by code executed in SRAM or you get to hang a board.
>>>>> What is the size limit on SRAM?
>>>>
>>>> RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
>>> That is not a very low limit. RK3288 uses SPL (and not TPL) and it has
>>> the same limit. Can we not just drop the use of TPL?
>>
>> I don't think rk3066 can drop TPL, because the bootrom for rk3066 is
>> very much like rk3188:
>> - bootrom read 1KB and run it, in purpose of get higher frequency;
>> - back to bootrom;
>> - bootrom continue read 31KB most and run it;
>> - back to bootrom if needed;
>> - boot rom read and run loader like uboot.
> OK then it sounds like we will need TPL. Is that right Pawel?
>
We don't need tpl if i use early back to bootrom in start.S patch with
spl... but i didn't test it yet. If it will work i will drop the tpl. Is
that ok?
>> Thanks,
>> - Kever
Thanks
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 14:50 ` Simon Glass
@ 2017-06-15 15:42 ` Paweł Jarosz
2017-06-15 16:00 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-15 15:42 UTC (permalink / raw)
To: u-boot
W dniu 15.06.2017 o 16:50, Simon Glass pisze:
> + Some other rockchip people
>
> Hi Pawel,
>
> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>> Hi Simon
>>
>>
>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>
>> +Philippe
>>
>> Hi Pawel,
>>
>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>
>> Hi Pawel,
>>
>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>
>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>
>> Hi Simon,
>>
>>
>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>
>> Hi Pawel,
>>
>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>> and
>> executes it. Then waits for back to bootrom and loads another 32KB to
>> sram
>> which also executes. Sdram initialisation code needs to be in one of
>> these two
>> steps. Then bootloader loads another ~200KB of data at offset
>> 0x60000000
>> and jumps to it.
>>
>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>> low for
>> u-boot part(for example to boot from mmc you need to disable usb
>> support.
>>
>> My solution to size problem is to move sdram initialisation code to tpl
>> stage,
>> move spl part to third stage(reading 200KB data) and add support for
>> loading
>> u-boot by spl from ext2/4, fat partitions.
>>
>> But moving sdram initialisation code to tpl increases size of tpl above
>> 1KB
>> (first boot stage). Solution to this is to add code which will be below
>> 1KB
>> offset in tpl binary and do back to bootrom at very beginning of the
>> tpl
>> execution.
>>
>> So do you mean that TPL starts and then loads more of itself? Why not
>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>> not clear why.
>>
>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>> Bootrom then loads
>> rest of the tpl (31KB) and executes it for a second time.
>>
>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>> mmc. To load u-boot from
>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>> support) i moved SPL to sdram.
>> Code executed in sdram can't mess with sdram settings because it will
>> hang the board. Sdram setup
>> needs to be done by code in SRAM (tpl).
>>
>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>> the past, without requiring the back_to_bootrom at all. So question would
>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>
>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>> driver
>> (rk3228 but cursory glance at the registers suggests that it may actually
>> work on previous socs down to the rk3066 as well) and it may be possible
>> to adapt that for uboot, therefore making the spl able to also load the
>> full u-boot from without needing back_to_bootrom.
>>
>>
>> Heiko
>>
>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb for
>> tpl)size limit.
>> One (or two i didn't check how much) back to bootrom is required on rk3066.
>> If not done bootrom stays in weird state and halts on bringup secondary cpu
>> in kernel. So it's rk3066 specific.
>>
>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>> init and MMC stack. Are you building with Thumb 2?
>>
>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>
>> To summarise where I think we got to:
>>
>> - move DRAM init into SPL
>> - either have a very small TPL which just returns to boot ROM, or
>> adjust start.S to return to the boot room early in SPL to load the
>> other 31KB
>>
>> Can you please post to the mailing list with your thoughts on this so
>> that others (including rockchip) can chime in? I think either will
>> work but I think others will have an opinion.
>>
>> Regards,
>> Simon
>>
>>
>> About moving dram init to spl i agree.
>>
>> I think early back to bootrom in start.S is a good solution as it would give
>> me 1KB more space for spl and i could drop hacks like jumping to spl in tpl
>> board file. But I would like to hear the opinion of other people on this.
> So with this solution there would be no TPL needed? It sounds
> reasonable to me. I'd like to hear other opinions also.
We don't need tpl if i use early back to bootrom in start.S patch with
spl... but i didn't test it yet. If it will work i will drop the tpl. Is
that ok?
>> Also i got a nandc driver from Heiko and i would like to adopt it for u-boot
>> in the next version. Is it ok?
> Sounds good.
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support
2017-06-15 15:41 ` Paweł Jarosz
@ 2017-06-15 15:59 ` Simon Glass
0 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-06-15 15:59 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 15 June 2017 at 09:41, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
> Hi
>
>
> W dniu 15.06.2017 o 16:57, Simon Glass pisze:
>
>> +Philipp
>>
>> Hi Kever,
>>
>> On 14 June 2017 at 06:15, Kever Yang <kever.yang@rock-chips.com> wrote:
>>>
>>> Simon,
>>>
>>>
>>>
>>> On 06/13/2017 07:50 AM, Simon Glass wrote:
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 9 June 2017 at 07:03, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>>
>>>>> W dniu 09.06.2017 o 14:27, Simon Glass pisze:
>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 7 June 2017 at 09:22, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>> wrote:
>>>>>>>
>>>>>>> Hi Simon
>>>>>>>
>>>>>>>
>>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>>>
>>>>>>>> Hi Pawel,
>>>>>>>>
>>>>>>>> On 6 June 2017 at 12:50, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>> +#include <dm/test.h>
>>>>>>>>> +#include <dm/util.h>
>>>>>>>>> +#include <power/regulator.h>
>>>>>>>>> +#include <syscon.h>
>>>>>>>>
>>>>>>>> That should go below spi.h
>>>>>>>>
>>>>>>> Ok
>>>>>>>>>
>>>>>>>>> +
>>>>>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>>>>>> +
>>>>>>>>> +u32 spl_boot_device(void)
>>>>>>>>> +{
>>>>>>>>
>>>>>>>> This function seems to be common. Can you please (in a separate
>>>>>>>> patch)
>>>>>>>> move it into a separate shared file and delete all the copies?
>>>>>>>
>>>>>>> Ok
>>>>>>>>
>>>>>>>>
>>>>>>>>> +
>>>>>>>>> + sdram_initialise();
>>>>>>>>
>>>>>>>> How come TPL is setting up the DRAM? Shouldn't that be done in SPL?
>>>>>>>>
>>>>>>> Due to size issues i needed to move spl load to sdram (not sram) and
>>>>>>> sdram
>>>>>>> settings
>>>>>>> should be done by code executed in SRAM or you get to hang a board.
>>>>>>
>>>>>> What is the size limit on SRAM?
>>>>>
>>>>>
>>>>> RK3066 has 64KB SRAM but bootrom only reads 1KB + 31KB.
>>>>
>>>> That is not a very low limit. RK3288 uses SPL (and not TPL) and it has
>>>> the same limit. Can we not just drop the use of TPL?
>>>
>>>
>>> I don't think rk3066 can drop TPL, because the bootrom for rk3066 is
>>> very much like rk3188:
>>> - bootrom read 1KB and run it, in purpose of get higher frequency;
>>> - back to bootrom;
>>> - bootrom continue read 31KB most and run it;
>>> - back to bootrom if needed;
>>> - boot rom read and run loader like uboot.
>>
>> OK then it sounds like we will need TPL. Is that right Pawel?
>>
>
> We don't need tpl if i use early back to bootrom in start.S patch with
> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
> that ok?
It's OK with me. I don't know how the BROM re-enters SPL after the
first call into the 1KB region. Depending on how that works, it might
be too painful to use SPL only (e.g. if it jumps to a place in the
middle of SPL).
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 15:42 ` Paweł Jarosz
@ 2017-06-15 16:00 ` Simon Glass
2017-06-15 16:32 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-15 16:00 UTC (permalink / raw)
To: u-boot
(just repeating other thread for completeness)
On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
>
> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>
>> + Some other rockchip people
>>
>> Hi Pawel,
>>
>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Hi Simon
>>>
>>>
>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>
>>> +Philippe
>>>
>>> Hi Pawel,
>>>
>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>
>>> Hi Pawel,
>>>
>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>
>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>
>>> Hi Simon,
>>>
>>>
>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>
>>> Hi Pawel,
>>>
>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>> and
>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>> sram
>>> which also executes. Sdram initialisation code needs to be in one of
>>> these two
>>> steps. Then bootloader loads another ~200KB of data at offset
>>> 0x60000000
>>> and jumps to it.
>>>
>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>> low for
>>> u-boot part(for example to boot from mmc you need to disable usb
>>> support.
>>>
>>> My solution to size problem is to move sdram initialisation code to tpl
>>> stage,
>>> move spl part to third stage(reading 200KB data) and add support for
>>> loading
>>> u-boot by spl from ext2/4, fat partitions.
>>>
>>> But moving sdram initialisation code to tpl increases size of tpl above
>>> 1KB
>>> (first boot stage). Solution to this is to add code which will be below
>>> 1KB
>>> offset in tpl binary and do back to bootrom at very beginning of the
>>> tpl
>>> execution.
>>>
>>> So do you mean that TPL starts and then loads more of itself? Why not
>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>> not clear why.
>>>
>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>> Bootrom then loads
>>> rest of the tpl (31KB) and executes it for a second time.
>>>
>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>> mmc. To load u-boot from
>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>> support) i moved SPL to sdram.
>>> Code executed in sdram can't mess with sdram settings because it will
>>> hang the board. Sdram setup
>>> needs to be done by code in SRAM (tpl).
>>>
>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>>> the past, without requiring the back_to_bootrom at all. So question would
>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>
>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>> driver
>>> (rk3228 but cursory glance at the registers suggests that it may actually
>>> work on previous socs down to the rk3066 as well) and it may be possible
>>> to adapt that for uboot, therefore making the spl able to also load the
>>> full u-boot from without needing back_to_bootrom.
>>>
>>>
>>> Heiko
>>>
>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>> for
>>> tpl)size limit.
>>> One (or two i didn't check how much) back to bootrom is required on
>>> rk3066.
>>> If not done bootrom stays in weird state and halts on bringup secondary
>>> cpu
>>> in kernel. So it's rk3066 specific.
>>>
>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>> init and MMC stack. Are you building with Thumb 2?
>>>
>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>
>>> To summarise where I think we got to:
>>>
>>> - move DRAM init into SPL
>>> - either have a very small TPL which just returns to boot ROM, or
>>> adjust start.S to return to the boot room early in SPL to load the
>>> other 31KB
>>>
>>> Can you please post to the mailing list with your thoughts on this so
>>> that others (including rockchip) can chime in? I think either will
>>> work but I think others will have an opinion.
>>>
>>> Regards,
>>> Simon
>>>
>>>
>>> About moving dram init to spl i agree.
>>>
>>> I think early back to bootrom in start.S is a good solution as it would
>>> give
>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>> tpl
>>> board file. But I would like to hear the opinion of other people on this.
>>
>> So with this solution there would be no TPL needed? It sounds
>> reasonable to me. I'd like to hear other opinions also.
>
>
> We don't need tpl if i use early back to bootrom in start.S patch with
> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
> that ok?
It's OK with me. I don't know how the BROM re-enters SPL after the
first call into the 1KB region. Depending on how that works, it might
be too painful to use SPL only (e.g. if it jumps to a place in the
middle of SPL).
>
>
>>> Also i got a nandc driver from Heiko and i would like to adopt it for
>>> u-boot
>>> in the next version. Is it ok?
>>
>> Sounds good.
>>
>> Regards,
>> Simon
>
>
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 16:00 ` Simon Glass
@ 2017-06-15 16:32 ` Paweł Jarosz
2017-06-15 16:40 ` Simon Glass
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-06-15 16:32 UTC (permalink / raw)
To: u-boot
W dniu 15.06.2017 o 18:00, Simon Glass pisze:
> (just repeating other thread for completeness)
>
> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>
>>> + Some other rockchip people
>>>
>>> Hi Pawel,
>>>
>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> Hi Simon
>>>>
>>>>
>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>
>>>> +Philippe
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>
>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>
>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>
>>>> Hi Simon,
>>>>
>>>>
>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>
>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>> and
>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>> sram
>>>> which also executes. Sdram initialisation code needs to be in one of
>>>> these two
>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>> 0x60000000
>>>> and jumps to it.
>>>>
>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>> low for
>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>> support.
>>>>
>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>> stage,
>>>> move spl part to third stage(reading 200KB data) and add support for
>>>> loading
>>>> u-boot by spl from ext2/4, fat partitions.
>>>>
>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>> 1KB
>>>> (first boot stage). Solution to this is to add code which will be below
>>>> 1KB
>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>> tpl
>>>> execution.
>>>>
>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>> not clear why.
>>>>
>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>> Bootrom then loads
>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>
>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>> mmc. To load u-boot from
>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>> support) i moved SPL to sdram.
>>>> Code executed in sdram can't mess with sdram settings because it will
>>>> hang the board. Sdram setup
>>>> needs to be done by code in SRAM (tpl).
>>>>
>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL in
>>>> the past, without requiring the back_to_bootrom at all. So question would
>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>
>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>> driver
>>>> (rk3228 but cursory glance at the registers suggests that it may actually
>>>> work on previous socs down to the rk3066 as well) and it may be possible
>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>> full u-boot from without needing back_to_bootrom.
>>>>
>>>>
>>>> Heiko
>>>>
>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>> for
>>>> tpl)size limit.
>>>> One (or two i didn't check how much) back to bootrom is required on
>>>> rk3066.
>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>> cpu
>>>> in kernel. So it's rk3066 specific.
>>>>
>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>> init and MMC stack. Are you building with Thumb 2?
>>>>
>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>
>>>> To summarise where I think we got to:
>>>>
>>>> - move DRAM init into SPL
>>>> - either have a very small TPL which just returns to boot ROM, or
>>>> adjust start.S to return to the boot room early in SPL to load the
>>>> other 31KB
>>>>
>>>> Can you please post to the mailing list with your thoughts on this so
>>>> that others (including rockchip) can chime in? I think either will
>>>> work but I think others will have an opinion.
>>>>
>>>> Regards,
>>>> Simon
>>>>
>>>>
>>>> About moving dram init to spl i agree.
>>>>
>>>> I think early back to bootrom in start.S is a good solution as it would
>>>> give
>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>> tpl
>>>> board file. But I would like to hear the opinion of other people on this.
>>> So with this solution there would be no TPL needed? It sounds
>>> reasonable to me. I'd like to hear other opinions also.
>>
>> We don't need tpl if i use early back to bootrom in start.S patch with
>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>> that ok?
>
> It's OK with me. I don't know how the BROM re-enters SPL after the
> first call into the 1KB region. Depending on how that works, it might
> be too painful to use SPL only (e.g. if it jumps to a place in the
> middle of SPL).
BROM re-enters same address 0x10080C04 two times. First when it boots,
second after first back to brom. That is why i used counter at address
0x10080900 to count boot entries.
So it's not painful at all.
>>
>>>> Also i got a nandc driver from Heiko and i would like to adopt it for
>>>> u-boot
>>>> in the next version. Is it ok?
>>> Sounds good.
>>>
>>> Regards,
>>> Simon
>>
> Regards,
> Simon
Cheers
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 16:32 ` Paweł Jarosz
@ 2017-06-15 16:40 ` Simon Glass
2017-08-04 16:33 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Simon Glass @ 2017-06-15 16:40 UTC (permalink / raw)
To: u-boot
Hi Pawel,
On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
>
> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>
>> (just repeating other thread for completeness)
>>
>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>>
>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>
>>>> + Some other rockchip people
>>>>
>>>> Hi Pawel,
>>>>
>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>> wrote:
>>>>>
>>>>> Hi Simon
>>>>>
>>>>>
>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>
>>>>> +Philippe
>>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>> wrote:
>>>>>
>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>
>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>
>>>>> Hi Simon,
>>>>>
>>>>>
>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>> wrote:
>>>>>
>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>> and
>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>> sram
>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>> these two
>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>> 0x60000000
>>>>> and jumps to it.
>>>>>
>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>> low for
>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>> support.
>>>>>
>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>> stage,
>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>> loading
>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>
>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>> 1KB
>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>> 1KB
>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>> tpl
>>>>> execution.
>>>>>
>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>> not clear why.
>>>>>
>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>> Bootrom then loads
>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>
>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>> mmc. To load u-boot from
>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>> support) i moved SPL to sdram.
>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>> hang the board. Sdram setup
>>>>> needs to be done by code in SRAM (tpl).
>>>>>
>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>> in
>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>> would
>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>
>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>> driver
>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>> actually
>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>> possible
>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>> full u-boot from without needing back_to_bootrom.
>>>>>
>>>>>
>>>>> Heiko
>>>>>
>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>> for
>>>>> tpl)size limit.
>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>> rk3066.
>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>> cpu
>>>>> in kernel. So it's rk3066 specific.
>>>>>
>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>
>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>
>>>>> To summarise where I think we got to:
>>>>>
>>>>> - move DRAM init into SPL
>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>> other 31KB
>>>>>
>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>> that others (including rockchip) can chime in? I think either will
>>>>> work but I think others will have an opinion.
>>>>>
>>>>> Regards,
>>>>> Simon
>>>>>
>>>>>
>>>>> About moving dram init to spl i agree.
>>>>>
>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>> give
>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>> tpl
>>>>> board file. But I would like to hear the opinion of other people on
>>>>> this.
>>>>
>>>> So with this solution there would be no TPL needed? It sounds
>>>> reasonable to me. I'd like to hear other opinions also.
>>>
>>>
>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>> that ok?
>>
>>
>> It's OK with me. I don't know how the BROM re-enters SPL after the
>> first call into the 1KB region. Depending on how that works, it might
>> be too painful to use SPL only (e.g. if it jumps to a place in the
>> middle of SPL).
>
>
> BROM re-enters same address 0x10080C04 two times. First when it boots,
> second after first back to brom. That is why i used counter at address
> 0x10080900 to count boot entries.
> So it's not painful at all.
OK from my POV this seems good.
[..]
Regards,
Simon
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,01/13] rockchip: rk3066: add grf header file
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
2017-06-06 21:09 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> grf is needed by various drivers for rk3066 soc.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++
> 1 file changed, 621 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 02/13] rockchip: rk3066: add rk3066 pinctrl driver
2017-06-06 18:49 ` [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Add driver supporting pin multiplexing on rk3066 platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3066.c | 342 ++++++++++++++++++++++++++++++
> 3 files changed, 352 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,03/13] rockchip: rk3066: add sysreset driver
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 17:41 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Add support for system reset for rk3066 socs.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3066.c | 62 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 63 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_rk3066.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 04/13] rockchip: rk3066: add clock driver for rk3066 soc
2017-06-06 18:50 ` [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Add clock driver for rk3066 platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 ++++++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3066.c | 586 ++++++++++++++++++++++++
> 3 files changed, 776 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h
> create mode 100644 drivers/clk/rockchip/clk_rk3066.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,06/13] rockchip: rk3066: add core support
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 6:37 ` Andy Yan
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 17:35 ` Philipp Tomsich
3 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/mach-rockchip/Kconfig | 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
> arch/arm/mach-rockchip/rk3066-board.c | 180 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
> arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
> arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
> arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
> include/configs/rk3066_common.h | 125 ++++++++++++++++++
> 10 files changed, 677 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> create mode 100644 include/configs/rk3066_common.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
> watchdog and uart
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/dts/rk3066a.dtsi | 699 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 699 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a.dtsi
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,08/13] rockchip: mmc: support rk3066 mmc
2017-06-06 18:51 ` [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
> internal dma support and max driver frequency.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/mmc/rockchip_dw_mmc.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 07/13] rockchip: rk3066: add mk808 board files
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
> nand onboard.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3066a-mk808.dts | 172 ++++++++++++++++++++++++++++
> board/rikomagic/mk808_rk3066/Kconfig | 15 +++
> board/rikomagic/mk808_rk3066/MAINTAINERS | 6 +
> board/rikomagic/mk808_rk3066/Makefile | 7 ++
> board/rikomagic/mk808_rk3066/mk808_rk3066.c | 10 ++
> configs/mk808-rk3066_defconfig | 54 +++++++++
> include/configs/mk808_rk3066.h | 15 +++
> 8 files changed, 280 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a-mk808.dts
> create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
> create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
> create mode 100644 board/rikomagic/mk808_rk3066/Makefile
> create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
> create mode 100644 configs/mk808-rk3066_defconfig
> create mode 100644 include/configs/mk808_rk3066.h
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 09/13] rockchip: dts: set fifo mode as default for mmc
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 16:41 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> rk3066 and rk3188 designware mmc ip doesn't support internal dma
> transfer mode. So set fifo mode as default.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/dts/rk3xxx.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,10/13] rockchip: rk3066: add sdram driver
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 16:18 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/mach-rockchip/rk3066/Makefile | 1 +
> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++
> 2 files changed, 112 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
2017-07-04 16:20 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> executes it. Then waits for back to bootrom and loads another 32KB to sram
> which also executes. Sdram initialisation code needs to be in one of these two
> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
> and jumps to it.
>
> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
> u-boot part(for example to boot from mmc you need to disable usb support.
>
> My solution to size problem is to move sdram initialisation code to tpl stage,
> move spl part to third stage(reading 200KB data) and add support for loading
> u-boot by spl from ext2/4, fat partitions.
>
> But moving sdram initialisation code to tpl increases size of tpl above 1KB
> (first boot stage). Solution to this is to add code which will be below 1KB
> offset in tpl binary and do back to bootrom at very beginning of the tpl
> execution.
>
> Adding this few lines of code here meets these conditions.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/cpu/armv7/start.S | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 11/13] rockchip: serial: support rockchip rk3066
2017-06-06 18:53 ` [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066 Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> update driver to support rk3066 serial
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> drivers/serial/serial_rockchip.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 13/13] rockchip: rk3066: add sdram init code for tpl
2017-06-06 18:53 ` [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
@ 2017-06-25 23:23 ` Philipp Tomsich
1 sibling, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-06-25 23:23 UTC (permalink / raw)
To: u-boot
> Add sdram initialisation code which will be ussed by tpl first boot stage.
> We need to implement sdram initialisation in tpl due to size issues on rk3066
> platform.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> ---
> arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 5 +
> arch/arm/mach-rockchip/rk3066/sdram_init.c | 995 ++++++++++++++++++++++++
> 2 files changed, 1000 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_init.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,10/13] rockchip: rk3066: add sdram driver
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,10/13] " Philipp Tomsich
@ 2017-07-04 16:18 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 16:18 UTC (permalink / raw)
To: u-boot
On Tue, 6 Jun 2017, Paweł Jarosz wrote:
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/mach-rockchip/rk3066/Makefile | 1 +
> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++
> 2 files changed, 112 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
>
> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
> index 4cf5df2..1d38518 100644
> --- a/arch/arm/mach-rockchip/rk3066/Makefile
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -6,6 +6,7 @@
>
> ifndef CONFIG_TPL_BUILD
> obj-y += clk_rk3066.o
> +obj-y += sdram_rk3066.o
> obj-y += syscon_rk3066.o
> else
> obj-y += sdram_init.o
> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> new file mode 100644
> index 0000000..a713ac4
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c
> @@ -0,0 +1,111 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Copyright 2014 Rockchip Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + *
> + * Adapted from the very similar rk3288 ddr init.
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-structs.h>
> +#include <errno.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <linux/err.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> + struct ram_info info;
> + struct rk3188_pmu *pmu;
> +};
> +
> +size_t sdram_size_mb(struct rk3188_pmu *pmu)
> +{
> + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
> + size_t chipsize_mb = 0;
> + size_t size_mb = 0;
> + u32 ch;
> + u32 sys_reg = readl(&pmu->sys_reg[2]);
> + u32 chans;
> +
> + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
> +
> + for (ch = 0; ch < chans; ch++) {
> + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
> + SYS_REG_RANK_MASK);
> + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
> + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
> + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
> + SYS_REG_CS0_ROW_MASK);
> + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
> + SYS_REG_CS1_ROW_MASK);
> + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
> + SYS_REG_BW_MASK));
> + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
> + SYS_REG_ROW_3_4_MASK;
> + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
> +
> + if (rank > 1)
> + chipsize_mb += chipsize_mb >>
> + (cs0_row - cs1_row);
> + if (row_3_4)
> + chipsize_mb = chipsize_mb * 3 / 4;
> + size_mb += chipsize_mb;
> + }
> +
> + /* there can be no more than 2gb of memory */
> + size_mb = min(size_mb, 0x80000000 >> 20);
> +
> + return size_mb;
> +}
The common functions for these are already merged on u-boot-rockchip/next.
Please update your patchset to use these instead of duplicating here.
> +static int rk3066_dmc_probe(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
> +
> + priv->info.base = CONFIG_SYS_SDRAM_BASE;
> + priv->info.size = sdram_size_mb(priv->pmu) << 20;
> +
> + return 0;
> +}
> +
> +static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> +
> + return 0;
> +}
> +
> +static struct ram_ops rk3066_dmc_ops = {
> + .get_info = rk3066_dmc_get_info,
> +};
> +
> +static const struct udevice_id rk3066_dmc_ids[] = {
> + { .compatible = "rockchip,rk3066-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dmc_rk3066) = {
> + .name = "rockchip_rk3066_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3066_dmc_ids,
> + .ops = &rk3066_dmc_ops,
> + .probe = rk3066_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> +};
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2017-07-04 16:20 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 16:20 UTC (permalink / raw)
To: u-boot
On Tue, 6 Jun 2017, Paweł Jarosz wrote:
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> executes it. Then waits for back to bootrom and loads another 32KB to sram
> which also executes. Sdram initialisation code needs to be in one of these two
> steps. Then bootloader loads another ~200KB of data at offset 0x60000000
> and jumps to it.
>
> 32KB of data is a little low for tpl + spl part and ~200KB data is to low for
> u-boot part(for example to boot from mmc you need to disable usb support.
>
> My solution to size problem is to move sdram initialisation code to tpl stage,
> move spl part to third stage(reading 200KB data) and add support for loading
> u-boot by spl from ext2/4, fat partitions.
>
> But moving sdram initialisation code to tpl increases size of tpl above 1KB
> (first boot stage). Solution to this is to add code which will be below 1KB
> offset in tpl binary and do back to bootrom at very beginning of the tpl
> execution.
>
> Adding this few lines of code here meets these conditions.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/cpu/armv7/start.S | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index f06fd28..73e03d9 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arch/arm/cpu/armv7/start.S
> @@ -36,6 +36,19 @@
> #endif
>
> reset:
> +
> +#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
> + ldr r3, =0x10080900
> + ldr r0, [r3]
> + cmp r0, #1
> + movne r0, #1
> + strne r0, [r3]
> + beq out_of_bootrom
> + bx lr
> +out_of_bootrom:
> + mov r0, #0
> + str r0, [r3]
> +#endif
I don't like us adding device-specific code to armv7/start.S.
Can you try to handle this in the boot0 hook (device-specific) or somewhere
else (more suitable/chip-specific)?
> /* Allow the board to save important registers */
> b save_boot_params
> save_boot_params_ret:
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 09/13] rockchip: dts: set fifo mode as default for mmc
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2017-07-04 16:41 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 16:41 UTC (permalink / raw)
To: u-boot
This would be a change from the upstream DTSI file in Linux, which we
should try to avoid if possible.
Please handle this the same way as in Linux and fall back to fifo-mode
based on the transfer-mode bits [17:16] in HCON.
On Tue, 6 Jun 2017, Paweł Jarosz wrote:
> rk3066 and rk3188 designware mmc ip doesn't support internal dma
> transfer mode. So set fifo mode as default.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/dts/rk3xxx.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi
> index 6d9e36d..4a32e27 100644
> --- a/arch/arm/dts/rk3xxx.dtsi
> +++ b/arch/arm/dts/rk3xxx.dtsi
> @@ -192,6 +192,7 @@
> clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
> clock-names = "biu", "ciu";
> fifo-depth = <256>;
> + fifo-mode;
> status = "disabled";
> };
>
> @@ -202,6 +203,7 @@
> clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
> clock-names = "biu", "ciu";
> fifo-depth = <256>;
> + fifo-mode;
> status = "disabled";
> };
>
> @@ -212,6 +214,7 @@
> clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
> clock-names = "biu", "ciu";
> fifo-depth = <256>;
> + fifo-mode;
> status = "disabled";
> };
>
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,06/13] rockchip: rk3066: add core support
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
` (2 preceding siblings ...)
2017-06-25 23:23 ` [U-Boot] [U-Boot,06/13] " Philipp Tomsich
@ 2017-07-04 17:35 ` Philipp Tomsich
2017-08-09 19:54 ` Paweł Jarosz
3 siblings, 1 reply; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 17:35 UTC (permalink / raw)
To: u-boot
On Tue, 6 Jun 2017, Paweł Jarosz wrote:
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/mach-rockchip/Kconfig | 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
> arch/arm/mach-rockchip/rk3066-board.c | 180 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
> arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
> arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
> arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
> include/configs/rk3066_common.h | 125 ++++++++++++++++++
> 10 files changed, 677 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
> create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> create mode 100644 include/configs/rk3066_common.h
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 6be2ab5..ad35e0a 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3066
> + bool "Support Rockchip RK3066"
> + select CPU_V7
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL
> + select TPL
> + select BOARD_LATE_INIT
> + select ROCKCHIP_BROM_HELPER
> + help
> + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
> + including NEON and GPU, Mali-400 graphics, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
> +
> config ROCKCHIP_RK3188
> bool "Support Rockchip RK3188"
> select CPU_V7
> @@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
> default y if !ROCKCHIP_SPL_BACK_TO_BROM
>
> source "arch/arm/mach-rockchip/rk3036/Kconfig"
> +source "arch/arm/mach-rockchip/rk3066/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 327b267..1ebba0c 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -7,15 +7,18 @@
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>
> ifdef CONFIG_TPL_BUILD
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> @@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
> endif
>
> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c b/arch/arm/mach-rockchip/rk3066-board-spl.c
> new file mode 100644
> index 0000000..6f7bfb0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
> @@ -0,0 +1,173 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <led.h>
> +#include <malloc.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/timer.h>
> +#include <dm/pinctrl.h>
> +#include <dm/root.h>
> +#include <dm/test.h>
> +#include <dm/util.h>
> +#include <power/regulator.h>
> +#include <syscon.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u32 spl_boot_device(void)
> +{
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + const void *blob = gd->fdt_blob;
> + struct udevice *dev;
> + const char *bootdev;
> + int node;
> + int ret;
> +
> + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
> + debug("Boot device %s\n", bootdev);
> + if (!bootdev)
> + goto fallback;
> +
> + node = fdt_path_offset(blob, bootdev);
> + if (node < 0) {
> + debug("node=%d\n", node);
> + goto fallback;
> + }
> + ret = device_get_global_by_of_offset(node, &dev);
> + if (ret) {
> + debug("device at node %s/%d not found: %d\n", bootdev, node,
> + ret);
> + goto fallback;
> + }
> + debug("Found device %s\n", dev->name);
> + switch (device_get_uclass_id(dev)) {
> + case UCLASS_SPI_FLASH:
> + return BOOT_DEVICE_SPI;
> + case UCLASS_MMC:
> + return BOOT_DEVICE_MMC1;
> + default:
> + debug("Booting from device uclass '%s' not supported\n",
> + dev_get_uclass_name(dev));
> + }
> +
> +fallback:
> +#endif
> + return BOOT_DEVICE_MMC1;
> +}
> +
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> + return MMCSD_MODE_FS;
> +}
> +
> +static int setup_arm_clock(void)
> +{
> + struct udevice *dev;
> + struct clk clk;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ret;
> +
> + clk.id = CLK_ARM;
> + ret = clk_request(dev, &clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_set_rate(&clk, 600000000);
> +
> + clk_free(&clk);
> + return ret;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *pinctrl, *dev;
> + int ret;
> +
> + debug_uart_init();
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + 0x8, 0x1, 0x1);
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret) {
> + debug("CLK init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("Pinctrl init failed: %d\n", ret);
> + return;
> + }
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return;
> + }
> +
> + setup_arm_clock();
> +}
> +
> +void spl_board_init(void)
> +{
> + struct udevice *pinctrl;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> +
> +#ifdef CONFIG_SPL_MMC_SUPPORT
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +#endif
> +
> + /* Enable debug UART */
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
> + if (ret) {
> + debug("%s: Failed to set up console UART\n", __func__);
> + goto err;
> + }
> +
> + preloader_console_init();
> +
> + return;
> +
> +err:
> + printf("spl_board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board-tpl.c b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> new file mode 100644
> index 0000000..d517a33
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board-tpl.c
> @@ -0,0 +1,46 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/ddr_rk3188.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/pmu_rk3188.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define RK3066_TIMER_CONTROL 0x8
> +#define GRF_BASE 0x20008000
> +
> +void board_init_f(ulong dummy)
> +{
> + /* Enable early UART on the RK3066 */
> +
> + struct rk3066_grf * const grf = (void *)GRF_BASE;
> +
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK << GPIO1B1_SHIFT |
> + GPIO1B0_MASK << GPIO1B0_SHIFT,
> + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
> + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
> +
> + debug_uart_init();
> +
> + printch('T');
> + printch('P');
> + printch('L');
> + printch('\n');
Can you make this printascii("TPL\n")?
> +
> + /* Enable Timer0 */
> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1, 0x1);
> +
> + sdram_initialise();
> +
> + back_to_bootrom();
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066-board.c b/arch/arm/mach-rockchip/rk3066-board.c
> new file mode 100644
> index 0000000..3d92253
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066-board.c
> @@ -0,0 +1,180 @@
> +/*
> + * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/pmu_rk3188.h>
> +#include <asm/arch/boot_mode.h>
> +#include <asm/gpio.h>
> +#include <dm/pinctrl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int board_late_init(void)
> +{
> + struct rk3066_grf *grf;
> +
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(grf)) {
> + error("grf syscon returned %ld\n", PTR_ERR(grf));
> + } else {
> + /* enable noc remap to mimic legacy loaders */
> + rk_clrsetreg(&grf->soc_con0,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT);
> + }
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
> + struct udevice *pinctrl;
> + int ret;
> +
> + /*
> + * We need to implement sdcard iomux here for the further
> + * initialization, otherwise, it'll hit sdcard command sending
> + * timeout exception.
> + */
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret) {
> + debug("%s: Cannot find pinctrl device\n", __func__);
> + goto err;
> + }
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> + if (ret) {
> + debug("%s: Failed to set up SD card\n", __func__);
> + goto err;
> + }
> +
> + return 0;
> +err:
> + printf("board_init: Error %d\n", ret);
> +
> + /* No way to report error here */
> + hang();
> +
> + return -1;
> +#else
> + return 0;
> +#endif
> +}
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> + ret = ram_get_info(dev, &ram);
> + if (ret) {
> + debug("Cannot get DRAM size: %d\n", ret);
> + return ret;
> + }
> + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +#endif
> +
> +int print_cpuinfo (void)
> +{
> + printf("CPU: Rockchip RK3066\n");
> + return 0;
> +}
This should be implemented in a way that we can share this across all
the Rockchip boards.
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rk3066_otg_data = {
> + .rx_fifo_sz = 275,
> + .np_tx_fifo_sz = 16,
> + .tx_fifo_sz = 256,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + int node, phy_node;
> + const char *mode;
> + bool matched = false;
> + const void *blob = gd->fdt_blob;
> + u32 grf_phy_offset;
> +
> + /* find the usb_otg node */
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-usb");
> +
> + while (node > 0) {
> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
> + if (mode && strcmp(mode, "otg") == 0) {
> + matched = true;
> + break;
> + }
> +
> + node = fdt_node_offset_by_compatible(blob, node,
> + "rockchip,rk3066-usb");
> + }
> + if (!matched) {
> + debug("Not found usb_otg device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> + node = fdtdec_lookup_phandle(blob, node, "phys");
> + if (node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + phy_node = fdt_parent_offset(blob, node);
> + if (phy_node <= 0) {
> + debug("Not found usb phy device\n");
> + return -ENODEV;
> + }
> +
> + rk3066_otg_data.phy_of_node = phy_node;
> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
> +
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3066-grf");
> + if (node <= 0) {
> + debug("Not found grf device\n");
> + return -ENODEV;
> + }
> + rk3066_otg_data.regs_phy = grf_phy_offset +
> + fdtdec_get_addr(blob, node, "reg");
> +
> + return dwc2_udc_probe(&rk3066_otg_data);
> +}
This looks a lot like what we have in board/rockchip/evb_rk3328/evb-rk3328.c
(and possibly other places?). Can we deduplicate this for the various
boards/devices using the DWC2?
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
> new file mode 100644
> index 0000000..27d32fd
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Kconfig
> @@ -0,0 +1,34 @@
> +if ROCKCHIP_RK3066
> +
> +config TARGET_MK808_RK3066
> + bool "MK808_RK3066"
> + help
> + MK808 is a tv stick with usb host and otg, microsd card slot, hdmi and wifi.
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x0800
> +
> +config SPL_LIBCOMMON_SUPPORT
> + default y
> +
> +config SPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config SPL_SERIAL_SUPPORT
> + default y
> +
> +config TPL_LIBCOMMON_SUPPORT
> + default y
> +
> +config TPL_LIBGENERIC_SUPPORT
> + default y
> +
> +config TPL_SERIAL_SUPPORT
> + default y
> +
> +source "board/rikomagic/mk808_rk3066/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile
> new file mode 100644
> index 0000000..4cf5df2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +ifndef CONFIG_TPL_BUILD
> +obj-y += clk_rk3066.o
> +obj-y += syscon_rk3066.o
> +else
> +obj-y += sdram_init.o
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> new file mode 100644
> index 0000000..ae52902
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2016 Google, Inc
> + * Written by Simon Glass <sjg@chromium.org>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3066_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> new file mode 100644
> index 0000000..57b2376
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
> @@ -0,0 +1,54 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +
> +static const struct udevice_id rk3066_syscon_ids[] = {
> + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
> + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3066) = {
> + .name = "rk3066_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> +};
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
> +{
> + dev->driver_data = dev->driver->of_match->data;
> + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(rockchip_rk3188_noc) = {
> + .name = "rockchip_rk3188_noc",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_grf) = {
> + .name = "rockchip_rk3066_grf",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 1,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
> + .name = "rockchip_rk3066_pmu",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3066_syscon_ids + 2,
> + .bind = rk3066_syscon_bind_of_platdata,
> +};
> +#endif
> diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
> new file mode 100644
> index 0000000..7009616
> --- /dev/null
> +++ b/include/configs/rk3066_common.h
> @@ -0,0 +1,125 @@
> +/*
> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_RK3066_COMMON_H
> +#define __CONFIG_RK3066_COMMON_H
> +
> +#include <asm/arch/hardware.h>
> +#include "rockchip-common.h"
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_MALLOC_LEN (64 << 20)
> +#define CONFIG_SYS_CBSIZE 256
> +
> +#define CONFIG_SYS_TIMER_RATE 24000000
> +#define CONFIG_SYS_TIMER_BASE 0x20038000
> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> +
> +#define CONFIG_SPL_BOARD_INIT
> +
> +#define CONFIG_SYS_TEXT_BASE 0x60408000
> +
> +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
> +#define CONFIG_SYS_LOAD_ADDR 0x70800800
> +
> +#ifdef CONFIG_TPL_BUILD
> +#define CONFIG_SPL_TEXT_BASE 0x10080C04
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +/* tpl size max 32kb - 4byte RK30 header */
> +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
> +#elif defined(CONFIG_SPL_BUILD)
> +/* spl size max 200k */
> +#define CONFIG_SPL_MAX_SIZE 0x32000
> +#define CONFIG_SPL_TEXT_BASE 0x60000000
> +#define CONFIG_SPL_STACK 0x1008FFFF
> +#define CONFIG_SPL_STACK_R_ADDR 0x70000000
> +#define CONFIG_SPL_STACK_R 1
> +#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
> +#define CONFIG_SPL_OF_CONTROL 1
> +#define CONFIG_SPL_OF_PLATDATA 1
> +#define CONFIG_SPL_FRAMEWORK 1
> +#define CONFIG_SPL_CLK 1
> +#define CONFIG_SPL_PINCTRL 1
> +#define CONFIG_SPL_REGMAP 1
> +#define CONFIG_SPL_SYSCON 1
> +#define CONFIG_SPL_RAM 1
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
> +#define CONFIG_SPL_MMC_SUPPORT 1
> +#define CONFIG_ROCKCHIP_SERIAL 1
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SPL_LIBDISK_SUPPORT 1
> +#define CONFIG_SPL_EXT_SUPPORT 1
> +#define CONFIG_SPL_FAT_SUPPORT 1
> +#define CONFIG_SPL_DM 1
> +#define CONFIG_SPL_GPIO_SUPPORT 1
> +#define CONFIG_SPL_POWER_SUPPORT 1
Most of these should be in defconfig.
Please don't add any configurations via #define that can also go through
defconfig.
> +#endif
> +
> +#define CONFIG_SYS_NS16550_MEM32
> +
> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
Why do we have this ROCKCHIP_CHIP_TAG? I can't find any use of it across
our entire code-base.
> +/* MMC/SD IP block */
> +#define CONFIG_BOUNCE_BUFFER
> +
> +#define CONFIG_CMD_CACHE
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define SDRAM_BANK_SIZE (1024UL << 20UL)
> +
> +#ifndef CONFIG_SPL_BUILD
> +/* usb */
> +#define CONFIG_USB
> +#define CONFIG_DM_USB
> +#define CONFIG_USB_STORAGE
> +#define CONFIG_CMD_USB
> +#define CONFIG_USB_DWC2
Most of these should be in defconfig.
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_DWC2_OTG
> +#define CONFIG_ROCKCHIP_USB2_PHY
> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
> +
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_CMD_USB_MASS_STORAGE
> +
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
> +#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
Again: these should be in *_defconfig and not in the header-file.
Please check your entire header to make sure we don't add any definitions
here that could go through defconfig.
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x60000000\0" \
> + "pxefile_addr_r=0x60100000\0" \
> + "fdt_addr_r=0x61f00000\0" \
> + "kernel_addr_r=0x62000000\0" \
> + "ramdisk_addr_r=0x64000000\0"
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x6fffffff\0" \
> + "initrd_high=0x6fffffff\0" \
> + "partitions=" PARTS_DEFAULT \
> + ENV_MEM_LAYOUT_SETTINGS \
> + ROCKCHIP_DEVICE_SETTINGS \
> + BOOTENV
> +
> +#include <config_distro_defaults.h>
> +#endif
> +
> +#define CONFIG_PREBOOT
> +
> +#endif
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,03/13] rockchip: rk3066: add sysreset driver
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,03/13] " Philipp Tomsich
@ 2017-07-04 17:41 ` Philipp Tomsich
2017-07-07 3:59 ` Simon Glass
2 siblings, 1 reply; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 17:41 UTC (permalink / raw)
To: u-boot
Looks like we're ending up with a lot of sysreset_rk3***.o drivers here
that all have more or less the same logic in them. This one looks like a
verbatim copy of the RK3188 one...
Can we start deduplicating this and have rk3188/rk3066_sysreset_request
as a common function that is parameterised using register offsets from a
driver-data structure?
As a side-note: I think I need to do the same for the other ones (i.e.
RK32xx and RK33xx sysreset drivers that are basically copy-and-paste...)
for the next iteration.
On Tue, 6 Jun 2017, Paweł Jarosz wrote:
> Add support for system reset for rk3066 socs.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3066.c | 62 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 63 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_rk3066.c
>
> diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
> index b683811..d138278 100644
> --- a/drivers/sysreset/Makefile
> +++ b/drivers/sysreset/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
> ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o
> endif
> +obj-$(CONFIG_ROCKCHIP_RK3066) += sysreset_rk3066.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o
> diff --git a/drivers/sysreset/sysreset_rk3066.c b/drivers/sysreset/sysreset_rk3066.c
> new file mode 100644
> index 0000000..79f9e4f
> --- /dev/null
> +++ b/drivers/sysreset/sysreset_rk3066.c
> @@ -0,0 +1,62 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <sysreset.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3066.h>
> +#include <asm/arch/grf_rk3066.h>
> +#include <asm/arch/hardware.h>
> +#include <linux/err.h>
> +
> +int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type)
> +{
> + struct rk3066_cru *cru = rockchip_get_cru();
> + struct rk3066_grf *grf;
> +
> + if (IS_ERR(cru))
> + return PTR_ERR(cru);
> +
> + switch (type) {
> + case SYSRESET_WARM:
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(grf))
> + return -EPROTONOSUPPORT;
> + /*
> + * warm-reset keeps the remap value,
> + * so make sure it's disabled.
> + */
> + rk_clrsetreg(&grf->soc_con0,
> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
> + 0 << NOC_REMAP_SHIFT);
> +
> + rk_clrreg(&cru->cru_mode_con, 0xffff);
> + writel(0xeca8, &cru->cru_glb_srst_snd_value);
> + break;
> + case SYSRESET_COLD:
> + rk_clrreg(&cru->cru_mode_con, 0xffff);
> + writel(0xfdb9, &cru->cru_glb_srst_fst_value);
> + break;
> + default:
> + return -EPROTONOSUPPORT;
> + }
> +
> + return -EINPROGRESS;
> +}
> +
> +static struct sysreset_ops rk3066_sysreset = {
> + .request = rk3066_sysreset_request,
> +};
> +
> +U_BOOT_DRIVER(sysreset_rk3066) = {
> + .name = "rk3066_sysreset",
> + .id = UCLASS_SYSRESET,
> + .ops = &rk3066_sysreset,
> +};
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 05/13] rockchip: rk3066: add rk3066 platform devicetree file
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 17:43 UTC (permalink / raw)
To: u-boot
> rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi,
> watchdog and uart
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/dts/rk3066a.dtsi | 699 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 699 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a.dtsi
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot, 07/13] rockchip: rk3066: add mk808 board files
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2017-07-04 17:43 ` Philipp Tomsich
2 siblings, 0 replies; 86+ messages in thread
From: Philipp Tomsich @ 2017-07-04 17:43 UTC (permalink / raw)
To: u-boot
> mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
> nand onboard.
>
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3066a-mk808.dts | 172 ++++++++++++++++++++++++++++
> board/rikomagic/mk808_rk3066/Kconfig | 15 +++
> board/rikomagic/mk808_rk3066/MAINTAINERS | 6 +
> board/rikomagic/mk808_rk3066/Makefile | 7 ++
> board/rikomagic/mk808_rk3066/mk808_rk3066.c | 10 ++
> configs/mk808-rk3066_defconfig | 54 +++++++++
> include/configs/mk808_rk3066.h | 15 +++
> 8 files changed, 280 insertions(+)
> create mode 100644 arch/arm/dts/rk3066a-mk808.dts
> create mode 100644 board/rikomagic/mk808_rk3066/Kconfig
> create mode 100644 board/rikomagic/mk808_rk3066/MAINTAINERS
> create mode 100644 board/rikomagic/mk808_rk3066/Makefile
> create mode 100644 board/rikomagic/mk808_rk3066/mk808_rk3066.c
> create mode 100644 configs/mk808-rk3066_defconfig
> create mode 100644 include/configs/mk808_rk3066.h
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,03/13] rockchip: rk3066: add sysreset driver
2017-07-04 17:41 ` Philipp Tomsich
@ 2017-07-07 3:59 ` Simon Glass
0 siblings, 0 replies; 86+ messages in thread
From: Simon Glass @ 2017-07-07 3:59 UTC (permalink / raw)
To: u-boot
On 4 July 2017 at 11:41, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
> Looks like we're ending up with a lot of sysreset_rk3***.o drivers here that
> all have more or less the same logic in them. This one looks like a
> verbatim copy of the RK3188 one...
>
> Can we start deduplicating this and have rk3188/rk3066_sysreset_request as a
> common function that is parameterised using register offsets from a
> driver-data structure?
>
> As a side-note: I think I need to do the same for the other ones (i.e.
> RK32xx and RK33xx sysreset drivers that are basically copy-and-paste...) for
> the next iteration.
Sounds good!
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-06-15 16:40 ` Simon Glass
@ 2017-08-04 16:33 ` Paweł Jarosz
2017-08-04 16:51 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-08-04 16:33 UTC (permalink / raw)
To: u-boot
Hi,
W dniu 15.06.2017 o 18:40, Simon Glass pisze:
> Hi Pawel,
>
> On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>>
>>> (just repeating other thread for completeness)
>>>
>>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>
>>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>>
>>>>> + Some other rockchip people
>>>>>
>>>>> Hi Pawel,
>>>>>
>>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>> wrote:
>>>>>> Hi Simon
>>>>>>
>>>>>>
>>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>>
>>>>>> +Philippe
>>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>>
>>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>>
>>>>>> Hi Simon,
>>>>>>
>>>>>>
>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>> and
>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>> sram
>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>> these two
>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>> 0x60000000
>>>>>> and jumps to it.
>>>>>>
>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>> low for
>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>> support.
>>>>>>
>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>> stage,
>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>> loading
>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>
>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>> 1KB
>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>> 1KB
>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>> tpl
>>>>>> execution.
>>>>>>
>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>> not clear why.
>>>>>>
>>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>>> Bootrom then loads
>>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>>
>>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>>> mmc. To load u-boot from
>>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>>> support) i moved SPL to sdram.
>>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>>> hang the board. Sdram setup
>>>>>> needs to be done by code in SRAM (tpl).
>>>>>>
>>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>>> in
>>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>>> would
>>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>>
>>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>>> driver
>>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>>> actually
>>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>>> possible
>>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>>> full u-boot from without needing back_to_bootrom.
>>>>>>
>>>>>>
>>>>>> Heiko
>>>>>>
>>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>>> for
>>>>>> tpl)size limit.
>>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>>> rk3066.
>>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>>> cpu
>>>>>> in kernel. So it's rk3066 specific.
>>>>>>
>>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>>
>>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>>
>>>>>> To summarise where I think we got to:
>>>>>>
>>>>>> - move DRAM init into SPL
>>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>>> other 31KB
>>>>>>
>>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>>> that others (including rockchip) can chime in? I think either will
>>>>>> work but I think others will have an opinion.
>>>>>>
>>>>>> Regards,
>>>>>> Simon
>>>>>>
>>>>>>
>>>>>> About moving dram init to spl i agree.
>>>>>>
>>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>>> give
>>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>>> tpl
>>>>>> board file. But I would like to hear the opinion of other people on
>>>>>> this.
>>>>> So with this solution there would be no TPL needed? It sounds
>>>>> reasonable to me. I'd like to hear other opinions also.
>>>>
>>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>>> that ok?
>>>
>>> It's OK with me. I don't know how the BROM re-enters SPL after the
>>> first call into the 1KB region. Depending on how that works, it might
>>> be too painful to use SPL only (e.g. if it jumps to a place in the
>>> middle of SPL).
>>
>> BROM re-enters same address 0x10080C04 two times. First when it boots,
>> second after first back to brom. That is why i used counter at address
>> 0x10080900 to count boot entries.
>> So it's not painful at all.
> OK from my POV this seems good.
>
> [..]
>
> Regards,
> Simon
It turns out that i will be needing tpl, spl and main u-boot. Also sdram
initialization will be needed in tpl.
Reason for that is how bootrom on rk3066 executes stuff:
1. At first stage it reads 2KB of data from nand to sram at address
0x10080C00 and decodes 1KB, executes decoded data at 0x10080C04 and
waits for back to bootrom.
2. At second stage it reads 31KB, decodes it and executes again data at
0x10080C04 and waits for second back to bootrom. Also SDRAM init MUST BE
HERE or board hangs at third stage.
3. At third stage bootrom reads ~200KB data to RAM at 0x60000000,
decodes it and do final execution.
All three stages are required or else later kernel will halt at bringup
secondary cpus using bootrom (there is another back to bootrom in kernel
code to bringup secondary cpus)
So there are two ways to boot main u-boot:
1. TPL + SPL loaded to sram (stages one and two) and main u-boot loaded
to sdram(third stage). In this case main u-boot must fit in ~200KB which
is not much and ONLY ONE of the features nand, mmc, usb might be
compiled in.
2. TPL with SDRAM INIT + early back to bootrom patch as stage one and
two, SPL as stage three, and main u-boot loaded from nand by SPL (stage
four).
I know all of this from bootrom disassembly and tests.
So is it ok to go the second way?
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-08-04 16:33 ` Paweł Jarosz
@ 2017-08-04 16:51 ` Dr. Philipp Tomsich
2017-08-04 17:01 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-04 16:51 UTC (permalink / raw)
To: u-boot
> On 04 Aug 2017, at 18:33, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
> Hi,
>
>
> W dniu 15.06.2017 o 18:40, Simon Glass pisze:
>> Hi Pawel,
>>
>> On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>>>
>>>> (just repeating other thread for completeness)
>>>>
>>>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>
>>>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>>>
>>>>>> + Some other rockchip people
>>>>>>
>>>>>> Hi Pawel,
>>>>>>
>>>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>> wrote:
>>>>>>> Hi Simon
>>>>>>>
>>>>>>>
>>>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>>>
>>>>>>> +Philippe
>>>>>>>
>>>>>>> Hi Pawel,
>>>>>>>
>>>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>
>>>>>>> Hi Pawel,
>>>>>>>
>>>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>>>
>>>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>>>
>>>>>>> Hi Simon,
>>>>>>>
>>>>>>>
>>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>>
>>>>>>> Hi Pawel,
>>>>>>>
>>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>>> and
>>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>>> sram
>>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>>> these two
>>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>>> 0x60000000
>>>>>>> and jumps to it.
>>>>>>>
>>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>>> low for
>>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>>> support.
>>>>>>>
>>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>>> stage,
>>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>>> loading
>>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>>
>>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>>> 1KB
>>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>>> 1KB
>>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>>> tpl
>>>>>>> execution.
>>>>>>>
>>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>>> not clear why.
>>>>>>>
>>>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>>>> Bootrom then loads
>>>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>>>
>>>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>>>> mmc. To load u-boot from
>>>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>>>> support) i moved SPL to sdram.
>>>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>>>> hang the board. Sdram setup
>>>>>>> needs to be done by code in SRAM (tpl).
>>>>>>>
>>>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>>>> in
>>>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>>>> would
>>>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>>>
>>>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>>>> driver
>>>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>>>> actually
>>>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>>>> possible
>>>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>>>> full u-boot from without needing back_to_bootrom.
>>>>>>>
>>>>>>>
>>>>>>> Heiko
>>>>>>>
>>>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>>>> for
>>>>>>> tpl)size limit.
>>>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>>>> rk3066.
>>>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>>>> cpu
>>>>>>> in kernel. So it's rk3066 specific.
>>>>>>>
>>>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>>>
>>>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>>>
>>>>>>> To summarise where I think we got to:
>>>>>>>
>>>>>>> - move DRAM init into SPL
>>>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>>>> other 31KB
>>>>>>>
>>>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>>>> that others (including rockchip) can chime in? I think either will
>>>>>>> work but I think others will have an opinion.
>>>>>>>
>>>>>>> Regards,
>>>>>>> Simon
>>>>>>>
>>>>>>>
>>>>>>> About moving dram init to spl i agree.
>>>>>>>
>>>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>>>> give
>>>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>>>> tpl
>>>>>>> board file. But I would like to hear the opinion of other people on
>>>>>>> this.
>>>>>> So with this solution there would be no TPL needed? It sounds
>>>>>> reasonable to me. I'd like to hear other opinions also.
>>>>>
>>>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>>>> that ok?
>>>>
>>>> It's OK with me. I don't know how the BROM re-enters SPL after the
>>>> first call into the 1KB region. Depending on how that works, it might
>>>> be too painful to use SPL only (e.g. if it jumps to a place in the
>>>> middle of SPL).
>>>
>>> BROM re-enters same address 0x10080C04 two times. First when it boots,
>>> second after first back to brom. That is why i used counter at address
>>> 0x10080900 to count boot entries.
>>> So it's not painful at all.
>> OK from my POV this seems good.
>>
>> [..]
>>
>> Regards,
>> Simon
> It turns out that i will be needing tpl, spl and main u-boot. Also sdram initialization will be needed in tpl.
>
> Reason for that is how bootrom on rk3066 executes stuff:
>
> 1. At first stage it reads 2KB of data from nand to sram at address 0x10080C00 and decodes 1KB, executes decoded data at 0x10080C04 and waits for back to bootrom.
> 2. At second stage it reads 31KB, decodes it and executes again data at 0x10080C04 and waits for second back to bootrom. Also SDRAM init MUST BE HERE or board hangs at third stage.
> 3. At third stage bootrom reads ~200KB data to RAM at 0x60000000, decodes it and do final execution.
Are both the first stage and the second stage loaded to SRAM + 0xc00?
I.e. does the second stage (31KB) overwrite the first stage?
> All three stages are required or else later kernel will halt at bringup secondary cpus using bootrom (there is another back to bootrom in kernel code to bringup secondary cpus)
>
> So there are two ways to boot main u-boot:
>
> 1. TPL + SPL loaded to sram (stages one and two) and main u-boot loaded to sdram(third stage). In this case main u-boot must fit in ~200KB which is not much and ONLY ONE of the features nand, mmc, usb might be compiled in.
>
> 2. TPL with SDRAM INIT + early back to bootrom patch as stage one and two, SPL as stage three, and main u-boot loaded from nand by SPL (stage four).
>
> I know all of this from bootrom disassembly and tests.
>
> So is it ok to go the second way?
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-08-04 16:51 ` Dr. Philipp Tomsich
@ 2017-08-04 17:01 ` Paweł Jarosz
2017-08-09 20:01 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 86+ messages in thread
From: Paweł Jarosz @ 2017-08-04 17:01 UTC (permalink / raw)
To: u-boot
Hi Philipp,
W dniu 04.08.2017 o 18:51, Dr. Philipp Tomsich pisze:
>> On 04 Aug 2017, at 18:33, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> Hi,
>>
>>
>> W dniu 15.06.2017 o 18:40, Simon Glass pisze:
>>> Hi Pawel,
>>>
>>> On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>>>>
>>>>> (just repeating other thread for completeness)
>>>>>
>>>>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>>>>
>>>>>>> + Some other rockchip people
>>>>>>>
>>>>>>> Hi Pawel,
>>>>>>>
>>>>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>> wrote:
>>>>>>>> Hi Simon
>>>>>>>>
>>>>>>>>
>>>>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>>>>
>>>>>>>> +Philippe
>>>>>>>>
>>>>>>>> Hi Pawel,
>>>>>>>>
>>>>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>
>>>>>>>> Hi Pawel,
>>>>>>>>
>>>>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>>>>
>>>>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>>>>
>>>>>>>> Hi Simon,
>>>>>>>>
>>>>>>>>
>>>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>>>
>>>>>>>> Hi Pawel,
>>>>>>>>
>>>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>>>> and
>>>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>>>> sram
>>>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>>>> these two
>>>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>>>> 0x60000000
>>>>>>>> and jumps to it.
>>>>>>>>
>>>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>>>> low for
>>>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>>>> support.
>>>>>>>>
>>>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>>>> stage,
>>>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>>>> loading
>>>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>>>
>>>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>>>> 1KB
>>>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>>>> 1KB
>>>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>>>> tpl
>>>>>>>> execution.
>>>>>>>>
>>>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>>>> not clear why.
>>>>>>>>
>>>>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>>>>> Bootrom then loads
>>>>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>>>>
>>>>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>>>>> mmc. To load u-boot from
>>>>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>>>>> support) i moved SPL to sdram.
>>>>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>>>>> hang the board. Sdram setup
>>>>>>>> needs to be done by code in SRAM (tpl).
>>>>>>>>
>>>>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>>>>> in
>>>>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>>>>> would
>>>>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>>>>
>>>>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>>>>> driver
>>>>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>>>>> actually
>>>>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>>>>> possible
>>>>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>>>>> full u-boot from without needing back_to_bootrom.
>>>>>>>>
>>>>>>>>
>>>>>>>> Heiko
>>>>>>>>
>>>>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>>>>> for
>>>>>>>> tpl)size limit.
>>>>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>>>>> rk3066.
>>>>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>>>>> cpu
>>>>>>>> in kernel. So it's rk3066 specific.
>>>>>>>>
>>>>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>>>>
>>>>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>>>>
>>>>>>>> To summarise where I think we got to:
>>>>>>>>
>>>>>>>> - move DRAM init into SPL
>>>>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>>>>> other 31KB
>>>>>>>>
>>>>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>>>>> that others (including rockchip) can chime in? I think either will
>>>>>>>> work but I think others will have an opinion.
>>>>>>>>
>>>>>>>> Regards,
>>>>>>>> Simon
>>>>>>>>
>>>>>>>>
>>>>>>>> About moving dram init to spl i agree.
>>>>>>>>
>>>>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>>>>> give
>>>>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>>>>> tpl
>>>>>>>> board file. But I would like to hear the opinion of other people on
>>>>>>>> this.
>>>>>>> So with this solution there would be no TPL needed? It sounds
>>>>>>> reasonable to me. I'd like to hear other opinions also.
>>>>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>>>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>>>>> that ok?
>>>>> It's OK with me. I don't know how the BROM re-enters SPL after the
>>>>> first call into the 1KB region. Depending on how that works, it might
>>>>> be too painful to use SPL only (e.g. if it jumps to a place in the
>>>>> middle of SPL).
>>>> BROM re-enters same address 0x10080C04 two times. First when it boots,
>>>> second after first back to brom. That is why i used counter at address
>>>> 0x10080900 to count boot entries.
>>>> So it's not painful at all.
>>> OK from my POV this seems good.
>>>
>>> [..]
>>>
>>> Regards,
>>> Simon
>> It turns out that i will be needing tpl, spl and main u-boot. Also sdram initialization will be needed in tpl.
>>
>> Reason for that is how bootrom on rk3066 executes stuff:
>>
>> 1. At first stage it reads 2KB of data from nand to sram at address 0x10080C00 and decodes 1KB, executes decoded data at 0x10080C04 and waits for back to bootrom.
>> 2. At second stage it reads 31KB, decodes it and executes again data at 0x10080C04 and waits for second back to bootrom. Also SDRAM init MUST BE HERE or board hangs at third stage.
>> 3. At third stage bootrom reads ~200KB data to RAM at 0x60000000, decodes it and do final execution.
> Are both the first stage and the second stage loaded to SRAM + 0xc00?
> I.e. does the second stage (31KB) overwrite the first stage?
No. First stage is loaded to 0xC00 in sram(2KB but decoded from rc4 only
1KB), second stage is then loaded to 0xC00 + 2KB(0x400)
>
>> All three stages are required or else later kernel will halt at bringup secondary cpus using bootrom (there is another back to bootrom in kernel code to bringup secondary cpus)
>>
>> So there are two ways to boot main u-boot:
>>
>> 1. TPL + SPL loaded to sram (stages one and two) and main u-boot loaded to sdram(third stage). In this case main u-boot must fit in ~200KB which is not much and ONLY ONE of the features nand, mmc, usb might be compiled in.
>>
>> 2. TPL with SDRAM INIT + early back to bootrom patch as stage one and two, SPL as stage three, and main u-boot loaded from nand by SPL (stage four).
>>
>> I know all of this from bootrom disassembly and tests.
>>
>> So is it ok to go the second way?
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [U-Boot,06/13] rockchip: rk3066: add core support
2017-07-04 17:35 ` Philipp Tomsich
@ 2017-08-09 19:54 ` Paweł Jarosz
0 siblings, 0 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-08-09 19:54 UTC (permalink / raw)
To: u-boot
Hi Phillip,
W dniu 04.07.2017 o 19:35, Philipp Tomsich pisze:
>
>
> On Tue, 6 Jun 2017, Paweł Jarosz wrote:
>
>> Add core skeleton for rk3066
>>
>> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>> arch/arm/mach-rockchip/Kconfig | 16 +++
>> arch/arm/mach-rockchip/Makefile | 4 +
>> arch/arm/mach-rockchip/rk3066-board-spl.c | 173
>> +++++++++++++++++++++++++
>> arch/arm/mach-rockchip/rk3066-board-tpl.c | 46 +++++++
>> arch/arm/mach-rockchip/rk3066-board.c | 180
>> ++++++++++++++++++++++++++
>> arch/arm/mach-rockchip/rk3066/Kconfig | 34 +++++
>> arch/arm/mach-rockchip/rk3066/Makefile | 12 ++
>> arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 +++++
>> arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 54 ++++++++
>> include/configs/rk3066_common.h | 125 ++++++++++++++++++
>> 10 files changed, 677 insertions(+)
>> create mode 100644 arch/arm/mach-rockchip/rk3066-board-spl.c
>> create mode 100644 arch/arm/mach-rockchip/rk3066-board-tpl.c
>> create mode 100644 arch/arm/mach-rockchip/rk3066-board.c
>> create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig
>> create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile
>> create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> create mode 100644 include/configs/rk3066_common.h
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig
>> b/arch/arm/mach-rockchip/Kconfig
>> index 6be2ab5..ad35e0a 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
>> and video codec support. Peripherals include Gigabit Ethernet,
>> USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>>
>> +config ROCKCHIP_RK3066
>> + bool "Support Rockchip RK3066"
>> + select CPU_V7
>> + select SUPPORT_SPL
>> + select SUPPORT_TPL
>> + select SPL
>> + select TPL
>> + select BOARD_LATE_INIT
>> + select ROCKCHIP_BROM_HELPER
>> + help
>> + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A7
>> + including NEON and GPU, Mali-400 graphics, several DDR3 options
>> + and video codec support. Peripherals include Gigabit Ethernet,
>> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
>> +
>> config ROCKCHIP_RK3188
>> bool "Support Rockchip RK3188"
>> select CPU_V7
>> @@ -91,6 +106,7 @@ config SPL_MMC_SUPPORT
>> default y if !ROCKCHIP_SPL_BACK_TO_BROM
>>
>> source "arch/arm/mach-rockchip/rk3036/Kconfig"
>> +source "arch/arm/mach-rockchip/rk3066/Kconfig"
>> source "arch/arm/mach-rockchip/rk3188/Kconfig"
>> source "arch/arm/mach-rockchip/rk3288/Kconfig"
>> source "arch/arm/mach-rockchip/rk3328/Kconfig"
>> diff --git a/arch/arm/mach-rockchip/Makefile
>> b/arch/arm/mach-rockchip/Makefile
>> index 327b267..1ebba0c 100644
>> --- a/arch/arm/mach-rockchip/Makefile
>> +++ b/arch/arm/mach-rockchip/Makefile
>> @@ -7,15 +7,18 @@
>> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
>>
>> ifdef CONFIG_TPL_BUILD
>> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-tpl.o
>> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
>> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
>> else ifdef CONFIG_SPL_BUILD
>> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board-spl.o
>> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
>> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
>> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
>> else
>> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066-board.o
>> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
>> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
>> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
>> @@ -29,6 +32,7 @@ ifndef CONFIG_TPL_BUILD
>> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
>> endif
>>
>> +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
>> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
>> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
>> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
>> diff --git a/arch/arm/mach-rockchip/rk3066-board-spl.c
>> b/arch/arm/mach-rockchip/rk3066-board-spl.c
>> new file mode 100644
>> index 0000000..6f7bfb0
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066-board-spl.c
>> @@ -0,0 +1,173 @@
>> +/*
>> + * (C) Copyright 2015 Google, Inc
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <clk.h>
>> +#include <common.h>
>> +#include <debug_uart.h>
>> +#include <dm.h>
>> +#include <fdtdec.h>
>> +#include <led.h>
>> +#include <malloc.h>
>> +#include <ram.h>
>> +#include <spl.h>
>> +#include <asm/gpio.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/bootrom.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/hardware.h>
>> +#include <asm/arch/periph.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +#include <asm/arch/sdram.h>
>> +#include <asm/arch/timer.h>
>> +#include <dm/pinctrl.h>
>> +#include <dm/root.h>
>> +#include <dm/test.h>
>> +#include <dm/util.h>
>> +#include <power/regulator.h>
>> +#include <syscon.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +u32 spl_boot_device(void)
>> +{
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> + const void *blob = gd->fdt_blob;
>> + struct udevice *dev;
>> + const char *bootdev;
>> + int node;
>> + int ret;
>> +
>> + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
>> + debug("Boot device %s\n", bootdev);
>> + if (!bootdev)
>> + goto fallback;
>> +
>> + node = fdt_path_offset(blob, bootdev);
>> + if (node < 0) {
>> + debug("node=%d\n", node);
>> + goto fallback;
>> + }
>> + ret = device_get_global_by_of_offset(node, &dev);
>> + if (ret) {
>> + debug("device at node %s/%d not found: %d\n", bootdev, node,
>> + ret);
>> + goto fallback;
>> + }
>> + debug("Found device %s\n", dev->name);
>> + switch (device_get_uclass_id(dev)) {
>> + case UCLASS_SPI_FLASH:
>> + return BOOT_DEVICE_SPI;
>> + case UCLASS_MMC:
>> + return BOOT_DEVICE_MMC1;
>> + default:
>> + debug("Booting from device uclass '%s' not supported\n",
>> + dev_get_uclass_name(dev));
>> + }
>> +
>> +fallback:
>> +#endif
>> + return BOOT_DEVICE_MMC1;
>> +}
>> +
>> +u32 spl_boot_mode(const u32 boot_device)
>> +{
>> + return MMCSD_MODE_FS;
>> +}
>> +
>> +static int setup_arm_clock(void)
>> +{
>> + struct udevice *dev;
>> + struct clk clk;
>> + int ret;
>> +
>> + ret = rockchip_get_clk(&dev);
>> + if (ret)
>> + return ret;
>> +
>> + clk.id = CLK_ARM;
>> + ret = clk_request(dev, &clk);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = clk_set_rate(&clk, 600000000);
>> +
>> + clk_free(&clk);
>> + return ret;
>> +}
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> + struct udevice *pinctrl, *dev;
>> + int ret;
>> +
>> + debug_uart_init();
>> +
>> + ret = spl_early_init();
>> + if (ret) {
>> + debug("spl_early_init() failed: %d\n", ret);
>> + hang();
>> + }
>> +
>> + /* Enable Timer0 */
>> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + 0x8, 0x1, 0x1);
>> +
>> + ret = rockchip_get_clk(&dev);
>> + if (ret) {
>> + debug("CLK init failed: %d\n", ret);
>> + return;
>> + }
>> +
>> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> + if (ret) {
>> + debug("Pinctrl init failed: %d\n", ret);
>> + return;
>> + }
>> +
>> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (ret) {
>> + debug("DRAM init failed: %d\n", ret);
>> + return;
>> + }
>> +
>> + setup_arm_clock();
>> +}
>> +
>> +void spl_board_init(void)
>> +{
>> + struct udevice *pinctrl;
>> + int ret;
>> +
>> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> + if (ret) {
>> + debug("%s: Cannot find pinctrl device\n", __func__);
>> + goto err;
>> + }
>> +
>> +#ifdef CONFIG_SPL_MMC_SUPPORT
>> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
>> + if (ret) {
>> + debug("%s: Failed to set up SD card\n", __func__);
>> + goto err;
>> + }
>> +#endif
>> +
>> + /* Enable debug UART */
>> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
>> + if (ret) {
>> + debug("%s: Failed to set up console UART\n", __func__);
>> + goto err;
>> + }
>> +
>> + preloader_console_init();
>> +
>> + return;
>> +
>> +err:
>> + printf("spl_board_init: Error %d\n", ret);
>> +
>> + /* No way to report error here */
>> + hang();
>> +}
>> diff --git a/arch/arm/mach-rockchip/rk3066-board-tpl.c
>> b/arch/arm/mach-rockchip/rk3066-board-tpl.c
>> new file mode 100644
>> index 0000000..d517a33
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066-board-tpl.c
>> @@ -0,0 +1,46 @@
>> +/*
>> + * (C) Copyright 2015 Google, Inc
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <debug_uart.h>
>> +#include <spl.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/bootrom.h>
>> +#include <asm/arch/ddr_rk3188.h>
>> +#include <asm/arch/grf_rk3066.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define RK3066_TIMER_CONTROL 0x8
>> +#define GRF_BASE 0x20008000
>> +
>> +void board_init_f(ulong dummy)
>> +{
>> + /* Enable early UART on the RK3066 */
>> +
>> + struct rk3066_grf * const grf = (void *)GRF_BASE;
>> +
>> + rk_clrsetreg(&grf->gpio1b_iomux,
>> + GPIO1B1_MASK << GPIO1B1_SHIFT |
>> + GPIO1B0_MASK << GPIO1B0_SHIFT,
>> + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
>> + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
>> +
>> + debug_uart_init();
>> +
>> + printch('T');
>> + printch('P');
>> + printch('L');
>> + printch('\n');
>
> Can you make this printascii("TPL\n")?
>
>> +
>> + /* Enable Timer0 */
>> + rk_clrsetreg(CONFIG_SYS_TIMER_BASE + RK3066_TIMER_CONTROL, 0x1,
>> 0x1);
>> +
>> + sdram_initialise();
>> +
>> + back_to_bootrom();
>> +}
>> diff --git a/arch/arm/mach-rockchip/rk3066-board.c
>> b/arch/arm/mach-rockchip/rk3066-board.c
>> new file mode 100644
>> index 0000000..3d92253
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066-board.c
>> @@ -0,0 +1,180 @@
>> +/*
>> + * (C) Copyright 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <ram.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/grf_rk3066.h>
>> +#include <asm/arch/periph.h>
>> +#include <asm/arch/pmu_rk3188.h>
>> +#include <asm/arch/boot_mode.h>
>> +#include <asm/gpio.h>
>> +#include <dm/pinctrl.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_late_init(void)
>> +{
>> + struct rk3066_grf *grf;
>> +
>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> + if (IS_ERR(grf)) {
>> + error("grf syscon returned %ld\n", PTR_ERR(grf));
>> + } else {
>> + /* enable noc remap to mimic legacy loaders */
>> + rk_clrsetreg(&grf->soc_con0,
>> + NOC_REMAP_MASK << NOC_REMAP_SHIFT,
>> + NOC_REMAP_MASK << NOC_REMAP_SHIFT);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
>> + struct udevice *pinctrl;
>> + int ret;
>> +
>> + /*
>> + * We need to implement sdcard iomux here for the further
>> + * initialization, otherwise, it'll hit sdcard command sending
>> + * timeout exception.
>> + */
>> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> + if (ret) {
>> + debug("%s: Cannot find pinctrl device\n", __func__);
>> + goto err;
>> + }
>> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
>> + if (ret) {
>> + debug("%s: Failed to set up SD card\n", __func__);
>> + goto err;
>> + }
>> +
>> + return 0;
>> +err:
>> + printf("board_init: Error %d\n", ret);
>> +
>> + /* No way to report error here */
>> + hang();
>> +
>> + return -1;
>> +#else
>> + return 0;
>> +#endif
>> +}
>> +
>> +int dram_init(void)
>> +{
>> + struct ram_info ram;
>> + struct udevice *dev;
>> + int ret;
>> +
>> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> + if (ret) {
>> + debug("DRAM init failed: %d\n", ret);
>> + return ret;
>> + }
>> + ret = ram_get_info(dev, &ram);
>> + if (ret) {
>> + debug("Cannot get DRAM size: %d\n", ret);
>> + return ret;
>> + }
>> + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
>> + gd->ram_size = ram.size;
>> +
>> + return 0;
>> +}
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +void enable_caches(void)
>> +{
>> + /* Enable D-cache. I-cache is already enabled in start.S */
>> + dcache_enable();
>> +}
>> +#endif
>> +
>> +int print_cpuinfo (void)
>> +{
>> + printf("CPU: Rockchip RK3066\n");
>> + return 0;
>> +}
>
> This should be implemented in a way that we can share this across all
> the Rockchip boards.
>
i've deleted that part because i don't know how to implement this :)
>> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>> +#include <usb.h>
>> +#include <usb/dwc2_udc.h>
>> +
>> +static struct dwc2_plat_otg_data rk3066_otg_data = {
>> + .rx_fifo_sz = 275,
>> + .np_tx_fifo_sz = 16,
>> + .tx_fifo_sz = 256,
>> +};
>> +
>> +int board_usb_init(int index, enum usb_init_type init)
>> +{
>> + int node, phy_node;
>> + const char *mode;
>> + bool matched = false;
>> + const void *blob = gd->fdt_blob;
>> + u32 grf_phy_offset;
>> +
>> + /* find the usb_otg node */
>> + node = fdt_node_offset_by_compatible(blob, -1,
>> + "rockchip,rk3066-usb");
>> +
>> + while (node > 0) {
>> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
>> + if (mode && strcmp(mode, "otg") == 0) {
>> + matched = true;
>> + break;
>> + }
>> +
>> + node = fdt_node_offset_by_compatible(blob, node,
>> + "rockchip,rk3066-usb");
>> + }
>> + if (!matched) {
>> + debug("Not found usb_otg device\n");
>> + return -ENODEV;
>> + }
>> + rk3066_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
>> +
>> + node = fdtdec_lookup_phandle(blob, node, "phys");
>> + if (node <= 0) {
>> + debug("Not found usb phy device\n");
>> + return -ENODEV;
>> + }
>> +
>> + phy_node = fdt_parent_offset(blob, node);
>> + if (phy_node <= 0) {
>> + debug("Not found usb phy device\n");
>> + return -ENODEV;
>> + }
>> +
>> + rk3066_otg_data.phy_of_node = phy_node;
>> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
>> +
>> + node = fdt_node_offset_by_compatible(blob, -1,
>> + "rockchip,rk3066-grf");
>> + if (node <= 0) {
>> + debug("Not found grf device\n");
>> + return -ENODEV;
>> + }
>> + rk3066_otg_data.regs_phy = grf_phy_offset +
>> + fdtdec_get_addr(blob, node, "reg");
>> +
>> + return dwc2_udc_probe(&rk3066_otg_data);
>> +}
>
> This looks a lot like what we have in
> board/rockchip/evb_rk3328/evb-rk3328.c
> (and possibly other places?). Can we deduplicate this for the various
> boards/devices using the DWC2?
>
i have already moved to ofnode api as Simon sugested
>> +int board_usb_cleanup(int index, enum usb_init_type init)
>> +{
>> + return 0;
>> +}
>> +#endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig
>> b/arch/arm/mach-rockchip/rk3066/Kconfig
>> new file mode 100644
>> index 0000000..27d32fd
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/Kconfig
>> @@ -0,0 +1,34 @@
>> +if ROCKCHIP_RK3066
>> +
>> +config TARGET_MK808_RK3066
>> + bool "MK808_RK3066"
>> + help
>> + MK808 is a tv stick with usb host and otg, microsd card slot,
>> hdmi and wifi.
>> +
>> +config SYS_SOC
>> + default "rockchip"
>> +
>> +config SYS_MALLOC_F_LEN
>> + default 0x0800
>> +
>> +config SPL_LIBCOMMON_SUPPORT
>> + default y
>> +
>> +config SPL_LIBGENERIC_SUPPORT
>> + default y
>> +
>> +config SPL_SERIAL_SUPPORT
>> + default y
>> +
>> +config TPL_LIBCOMMON_SUPPORT
>> + default y
>> +
>> +config TPL_LIBGENERIC_SUPPORT
>> + default y
>> +
>> +config TPL_SERIAL_SUPPORT
>> + default y
>> +
>> +source "board/rikomagic/mk808_rk3066/Kconfig"
>> +
>> +endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile
>> b/arch/arm/mach-rockchip/rk3066/Makefile
>> new file mode 100644
>> index 0000000..4cf5df2
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/Makefile
>> @@ -0,0 +1,12 @@
>> +#
>> +# Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +ifndef CONFIG_TPL_BUILD
>> +obj-y += clk_rk3066.o
>> +obj-y += syscon_rk3066.o
>> +else
>> +obj-y += sdram_init.o
>> +endif
>> diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> new file mode 100644
>> index 0000000..ae52902
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c
>> @@ -0,0 +1,33 @@
>> +/*
>> + * Copyright (C) 2016 Google, Inc
>> + * Written by Simon Glass <sjg@chromium.org>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <syscon.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3066.h>
>> +
>> +int rockchip_get_clk(struct udevice **devp)
>> +{
>> + return uclass_get_device_by_driver(UCLASS_CLK,
>> + DM_GET_DRIVER(rockchip_rk3066a_cru), devp);
>> +}
>> +
>> +void *rockchip_get_cru(void)
>> +{
>> + struct rk3066_clk_priv *priv;
>> + struct udevice *dev;
>> + int ret;
>> +
>> + ret = rockchip_get_clk(&dev);
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> + priv = dev_get_priv(dev);
>> +
>> + return priv->cru;
>> +}
>> diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> new file mode 100644
>> index 0000000..57b2376
>> --- /dev/null
>> +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
>> @@ -0,0 +1,54 @@
>> +/*
>> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <syscon.h>
>> +#include <asm/arch/clock.h>
>> +
>> +static const struct udevice_id rk3066_syscon_ids[] = {
>> + { .compatible = "rockchip,rk3188-noc", .data =
>> ROCKCHIP_SYSCON_NOC },
>> + { .compatible = "rockchip,rk3066-grf", .data =
>> ROCKCHIP_SYSCON_GRF },
>> + { .compatible = "rockchip,rk3066-pmu", .data =
>> ROCKCHIP_SYSCON_PMU },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(syscon_rk3066) = {
>> + .name = "rk3066_syscon",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids,
>> +};
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +static int rk3066_syscon_bind_of_platdata(struct udevice *dev)
>> +{
>> + dev->driver_data = dev->driver->of_match->data;
>> + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
>> +
>> + return 0;
>> +}
>> +
>> +U_BOOT_DRIVER(rockchip_rk3188_noc) = {
>> + .name = "rockchip_rk3188_noc",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3066_grf) = {
>> + .name = "rockchip_rk3066_grf",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids + 1,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +
>> +U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
>> + .name = "rockchip_rk3066_pmu",
>> + .id = UCLASS_SYSCON,
>> + .of_match = rk3066_syscon_ids + 2,
>> + .bind = rk3066_syscon_bind_of_platdata,
>> +};
>> +#endif
>> diff --git a/include/configs/rk3066_common.h
>> b/include/configs/rk3066_common.h
>> new file mode 100644
>> index 0000000..7009616
>> --- /dev/null
>> +++ b/include/configs/rk3066_common.h
>> @@ -0,0 +1,125 @@
>> +/*
>> + * Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_RK3066_COMMON_H
>> +#define __CONFIG_RK3066_COMMON_H
>> +
>> +#include <asm/arch/hardware.h>
>> +#include "rockchip-common.h"
>> +
>> +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>> +#define CONFIG_ENV_IS_NOWHERE
>> +#define CONFIG_ENV_SIZE 0x2000
>> +#define CONFIG_SYS_MAXARGS 16
>> +#define CONFIG_BAUDRATE 115200
>> +#define CONFIG_SYS_MALLOC_LEN (64 << 20)
>> +#define CONFIG_SYS_CBSIZE 256
>> +
>> +#define CONFIG_SYS_TIMER_RATE 24000000
>> +#define CONFIG_SYS_TIMER_BASE 0x20038000
>> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 4)
>> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
>> +
>> +#define CONFIG_SPL_BOARD_INIT
>> +
>> +#define CONFIG_SYS_TEXT_BASE 0x60408000
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000
>> +#define CONFIG_SYS_LOAD_ADDR 0x70800800
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> +#define CONFIG_SPL_TEXT_BASE 0x10080C04
>> +#define CONFIG_SPL_STACK 0x1008FFFF
>> +/* tpl size max 32kb - 4byte RK30 header */
>> +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x4)
>> +#elif defined(CONFIG_SPL_BUILD)
>> +/* spl size max 200k */
>> +#define CONFIG_SPL_MAX_SIZE 0x32000
>> +#define CONFIG_SPL_TEXT_BASE 0x60000000
>> +#define CONFIG_SPL_STACK 0x1008FFFF
>> +#define CONFIG_SPL_STACK_R_ADDR 0x70000000
>> +#define CONFIG_SPL_STACK_R 1
>> +#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x200000
>> +#define CONFIG_SPL_OF_CONTROL 1
>> +#define CONFIG_SPL_OF_PLATDATA 1
>> +#define CONFIG_SPL_FRAMEWORK 1
>> +#define CONFIG_SPL_CLK 1
>> +#define CONFIG_SPL_PINCTRL 1
>> +#define CONFIG_SPL_REGMAP 1
>> +#define CONFIG_SPL_SYSCON 1
>> +#define CONFIG_SPL_RAM 1
>> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
>> +#define CONFIG_SPL_MMC_SUPPORT 1
>> +#define CONFIG_ROCKCHIP_SERIAL 1
>> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.bin"
>> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
>> +#define CONFIG_SPL_LIBDISK_SUPPORT 1
>> +#define CONFIG_SPL_EXT_SUPPORT 1
>> +#define CONFIG_SPL_FAT_SUPPORT 1
>> +#define CONFIG_SPL_DM 1
>> +#define CONFIG_SPL_GPIO_SUPPORT 1
>> +#define CONFIG_SPL_POWER_SUPPORT 1
>
> Most of these should be in defconfig.
> Please don't add any configurations via #define that can also go through
> defconfig.
>
>> +#endif
>> +
>> +#define CONFIG_SYS_NS16550_MEM32
>> +
>> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x10000 - 0xC00)
>> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
>
> Why do we have this ROCKCHIP_CHIP_TAG? I can't find any use of it across
> our entire code-base.
I've deleted that ... sorry for the confusion
>
>> +/* MMC/SD IP block */
>> +#define CONFIG_BOUNCE_BUFFER
>> +
>> +#define CONFIG_CMD_CACHE
>> +
>> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +#define SDRAM_BANK_SIZE (1024UL << 20UL)
>> +
>> +#ifndef CONFIG_SPL_BUILD
>> +/* usb */
>> +#define CONFIG_USB
>> +#define CONFIG_DM_USB
>> +#define CONFIG_USB_STORAGE
>> +#define CONFIG_CMD_USB
>> +#define CONFIG_USB_DWC2
>
> Most of these should be in defconfig.
>
>> +#define CONFIG_USB_GADGET
>> +#define CONFIG_USB_GADGET_DUALSPEED
>> +#define CONFIG_USB_GADGET_DWC2_OTG
>> +#define CONFIG_ROCKCHIP_USB2_PHY
>> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
>> +
>> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
>> +#define CONFIG_CMD_USB_MASS_STORAGE
>> +
>> +#define CONFIG_USB_GADGET_DOWNLOAD
>> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
>> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
>> +#define CONFIG_G_DNL_PRODUCT_NUM 0x300a
>
> Again: these should be in *_defconfig and not in the header-file.
> Please check your entire header to make sure we don't add any
> definitions here that could go through defconfig.
>
>> +#define ENV_MEM_LAYOUT_SETTINGS \
>> + "scriptaddr=0x60000000\0" \
>> + "pxefile_addr_r=0x60100000\0" \
>> + "fdt_addr_r=0x61f00000\0" \
>> + "kernel_addr_r=0x62000000\0" \
>> + "ramdisk_addr_r=0x64000000\0"
>> +
>> +#include <config_distro_bootcmd.h>
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + "fdt_high=0x6fffffff\0" \
>> + "initrd_high=0x6fffffff\0" \
>> + "partitions=" PARTS_DEFAULT \
>> + ENV_MEM_LAYOUT_SETTINGS \
>> + ROCKCHIP_DEVICE_SETTINGS \
>> + BOOTENV
>> +
>> +#include <config_distro_defaults.h>
>> +#endif
>> +
>> +#define CONFIG_PREBOOT
>> +
>> +#endif
>>
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-08-04 17:01 ` Paweł Jarosz
@ 2017-08-09 20:01 ` Dr. Philipp Tomsich
2017-08-09 20:08 ` Paweł Jarosz
0 siblings, 1 reply; 86+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-09 20:01 UTC (permalink / raw)
To: u-boot
> On 04 Aug 2017, at 19:01, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>
> Hi Philipp,
>
>
> W dniu 04.08.2017 o 18:51, Dr. Philipp Tomsich pisze:
>>> On 04 Aug 2017, at 18:33, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>
>>> Hi,
>>>
>>>
>>> W dniu 15.06.2017 o 18:40, Simon Glass pisze:
>>>> Hi Pawel,
>>>>
>>>> On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>>>>>
>>>>>> (just repeating other thread for completeness)
>>>>>>
>>>>>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>>>>>
>>>>>>>> + Some other rockchip people
>>>>>>>>
>>>>>>>> Hi Pawel,
>>>>>>>>
>>>>>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>> wrote:
>>>>>>>>> Hi Simon
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>>>>>
>>>>>>>>> +Philippe
>>>>>>>>>
>>>>>>>>> Hi Pawel,
>>>>>>>>>
>>>>>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>
>>>>>>>>> Hi Pawel,
>>>>>>>>>
>>>>>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>>>>>
>>>>>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>>>>>
>>>>>>>>> Hi Simon,
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>>>>
>>>>>>>>> Hi Pawel,
>>>>>>>>>
>>>>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>>>>> and
>>>>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>>>>> sram
>>>>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>>>>> these two
>>>>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>>>>> 0x60000000
>>>>>>>>> and jumps to it.
>>>>>>>>>
>>>>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>>>>> low for
>>>>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>>>>> support.
>>>>>>>>>
>>>>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>>>>> stage,
>>>>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>>>>> loading
>>>>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>>>>
>>>>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>>>>> 1KB
>>>>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>>>>> 1KB
>>>>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>>>>> tpl
>>>>>>>>> execution.
>>>>>>>>>
>>>>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>>>>> not clear why.
>>>>>>>>>
>>>>>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>>>>>> Bootrom then loads
>>>>>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>>>>>
>>>>>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>>>>>> mmc. To load u-boot from
>>>>>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>>>>>> support) i moved SPL to sdram.
>>>>>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>>>>>> hang the board. Sdram setup
>>>>>>>>> needs to be done by code in SRAM (tpl).
>>>>>>>>>
>>>>>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>>>>>> in
>>>>>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>>>>>> would
>>>>>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>>>>>
>>>>>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>>>>>> driver
>>>>>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>>>>>> actually
>>>>>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>>>>>> possible
>>>>>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>>>>>> full u-boot from without needing back_to_bootrom.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Heiko
>>>>>>>>>
>>>>>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>>>>>> for
>>>>>>>>> tpl)size limit.
>>>>>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>>>>>> rk3066.
>>>>>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>>>>>> cpu
>>>>>>>>> in kernel. So it's rk3066 specific.
>>>>>>>>>
>>>>>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>>>>>
>>>>>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>>>>>
>>>>>>>>> To summarise where I think we got to:
>>>>>>>>>
>>>>>>>>> - move DRAM init into SPL
>>>>>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>>>>>> other 31KB
>>>>>>>>>
>>>>>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>>>>>> that others (including rockchip) can chime in? I think either will
>>>>>>>>> work but I think others will have an opinion.
>>>>>>>>>
>>>>>>>>> Regards,
>>>>>>>>> Simon
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> About moving dram init to spl i agree.
>>>>>>>>>
>>>>>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>>>>>> give
>>>>>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>>>>>> tpl
>>>>>>>>> board file. But I would like to hear the opinion of other people on
>>>>>>>>> this.
>>>>>>>> So with this solution there would be no TPL needed? It sounds
>>>>>>>> reasonable to me. I'd like to hear other opinions also.
>>>>>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>>>>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>>>>>> that ok?
>>>>>> It's OK with me. I don't know how the BROM re-enters SPL after the
>>>>>> first call into the 1KB region. Depending on how that works, it might
>>>>>> be too painful to use SPL only (e.g. if it jumps to a place in the
>>>>>> middle of SPL).
>>>>> BROM re-enters same address 0x10080C04 two times. First when it boots,
>>>>> second after first back to brom. That is why i used counter at address
>>>>> 0x10080900 to count boot entries.
>>>>> So it's not painful at all.
>>>> OK from my POV this seems good.
>>>>
>>>> [..]
>>>>
>>>> Regards,
>>>> Simon
>>> It turns out that i will be needing tpl, spl and main u-boot. Also sdram initialization will be needed in tpl.
>>>
>>> Reason for that is how bootrom on rk3066 executes stuff:
>>>
>>> 1. At first stage it reads 2KB of data from nand to sram at address 0x10080C00 and decodes 1KB, executes decoded data at 0x10080C04 and waits for back to bootrom.
>>> 2. At second stage it reads 31KB, decodes it and executes again data at 0x10080C04 and waits for second back to bootrom. Also SDRAM init MUST BE HERE or board hangs at third stage.
>>> 3. At third stage bootrom reads ~200KB data to RAM at 0x60000000, decodes it and do final execution.
>> Are both the first stage and the second stage loaded to SRAM + 0xc00?
>> I.e. does the second stage (31KB) overwrite the first stage?
>
> No. First stage is loaded to 0xC00 in sram(2KB but decoded from rc4 only 1KB), second stage is then loaded to 0xC00 + 2KB(0x400)
If you have no logic (except for counting ‘reentries’) in the first stage, you might be able to implement this as a boot0 hook.
>>> All three stages are required or else later kernel will halt at bringup secondary cpus using bootrom (there is another back to bootrom in kernel code to bringup secondary cpus)
>>>
>>> So there are two ways to boot main u-boot:
>>>
>>> 1. TPL + SPL loaded to sram (stages one and two) and main u-boot loaded to sdram(third stage). In this case main u-boot must fit in ~200KB which is not much and ONLY ONE of the features nand, mmc, usb might be compiled in.
>>>
>>> 2. TPL with SDRAM INIT + early back to bootrom patch as stage one and two, SPL as stage three, and main u-boot loaded from nand by SPL (stage four).
>>>
>>> I know all of this from bootrom disassembly and tests.
>>>
>>> So is it ok to go the second way?
I would view option two as just having the usual three stages, but the TPL stage being loaded in pieces and being entered twice.
So option 2 will then look a lot like other Rockchip boot sequences.
Cheers,
Philipp.
^ permalink raw reply [flat|nested] 86+ messages in thread
* [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S
2017-08-09 20:01 ` Dr. Philipp Tomsich
@ 2017-08-09 20:08 ` Paweł Jarosz
0 siblings, 0 replies; 86+ messages in thread
From: Paweł Jarosz @ 2017-08-09 20:08 UTC (permalink / raw)
To: u-boot
Hi Phillip,
W dniu 09.08.2017 o 22:01, Dr. Philipp Tomsich pisze:
>> On 04 Aug 2017, at 19:01, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>
>> Hi Philipp,
>>
>>
>> W dniu 04.08.2017 o 18:51, Dr. Philipp Tomsich pisze:
>>>> On 04 Aug 2017, at 18:33, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>
>>>> Hi,
>>>>
>>>>
>>>> W dniu 15.06.2017 o 18:40, Simon Glass pisze:
>>>>> Hi Pawel,
>>>>>
>>>>> On 15 June 2017 at 10:32, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>> W dniu 15.06.2017 o 18:00, Simon Glass pisze:
>>>>>>
>>>>>>> (just repeating other thread for completeness)
>>>>>>>
>>>>>>> On 15 June 2017 at 09:42, Paweł Jarosz <paweljarosz3691@gmail.com> wrote:
>>>>>>>> W dniu 15.06.2017 o 16:50, Simon Glass pisze:
>>>>>>>>
>>>>>>>>> + Some other rockchip people
>>>>>>>>>
>>>>>>>>> Hi Pawel,
>>>>>>>>>
>>>>>>>>> On 15 June 2017 at 01:15, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>>> wrote:
>>>>>>>>>> Hi Simon
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> W dniu 14.06.2017 o 13:06, Simon Glass pisze:
>>>>>>>>>>
>>>>>>>>>> +Philippe
>>>>>>>>>>
>>>>>>>>>> Hi Pawel,
>>>>>>>>>>
>>>>>>>>>> On 12 June 2017 at 17:50, Simon Glass <sjg@chromium.org> wrote:
>>>>>>>>>>
>>>>>>>>>> Hi Pawel,
>>>>>>>>>>
>>>>>>>>>> On 9 June 2017 at 06:31, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>> W dniu 09.06.2017 o 13:46, Heiko Stuebner pisze:
>>>>>>>>>>
>>>>>>>>>> Am Mittwoch, 7. Juni 2017, 17:37:13 CEST schrieb Paweł Jarosz:
>>>>>>>>>>
>>>>>>>>>> Hi Simon,
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> W dniu 06.06.2017 o 23:10, Simon Glass pisze:
>>>>>>>>>>
>>>>>>>>>> Hi Pawel,
>>>>>>>>>>
>>>>>>>>>> On 6 June 2017 at 12:53, Paweł Jarosz <paweljarosz3691@gmail.com>
>>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00
>>>>>>>>>> and
>>>>>>>>>> executes it. Then waits for back to bootrom and loads another 32KB to
>>>>>>>>>> sram
>>>>>>>>>> which also executes. Sdram initialisation code needs to be in one of
>>>>>>>>>> these two
>>>>>>>>>> steps. Then bootloader loads another ~200KB of data at offset
>>>>>>>>>> 0x60000000
>>>>>>>>>> and jumps to it.
>>>>>>>>>>
>>>>>>>>>> 32KB of data is a little low for tpl + spl part and ~200KB data is to
>>>>>>>>>> low for
>>>>>>>>>> u-boot part(for example to boot from mmc you need to disable usb
>>>>>>>>>> support.
>>>>>>>>>>
>>>>>>>>>> My solution to size problem is to move sdram initialisation code to tpl
>>>>>>>>>> stage,
>>>>>>>>>> move spl part to third stage(reading 200KB data) and add support for
>>>>>>>>>> loading
>>>>>>>>>> u-boot by spl from ext2/4, fat partitions.
>>>>>>>>>>
>>>>>>>>>> But moving sdram initialisation code to tpl increases size of tpl above
>>>>>>>>>> 1KB
>>>>>>>>>> (first boot stage). Solution to this is to add code which will be below
>>>>>>>>>> 1KB
>>>>>>>>>> offset in tpl binary and do back to bootrom at very beginning of the
>>>>>>>>>> tpl
>>>>>>>>>> execution.
>>>>>>>>>>
>>>>>>>>>> So do you mean that TPL starts and then loads more of itself? Why not
>>>>>>>>>> put SDRAM init in SPL? You say above that 32KB is 'too low', but It's
>>>>>>>>>> not clear why.
>>>>>>>>>>
>>>>>>>>>> Ad.1 No. Tpl starts and at the first execution returns to bootrom.
>>>>>>>>>> Bootrom then loads
>>>>>>>>>> rest of the tpl (31KB) and executes it for a second time.
>>>>>>>>>>
>>>>>>>>>> Ad.2,3 Due to size issues (200KB limit) i needed to move main u-boot to
>>>>>>>>>> mmc. To load u-boot from
>>>>>>>>>> mmc by SPL (there is 32KB bootrom limit, not enough space for mmc
>>>>>>>>>> support) i moved SPL to sdram.
>>>>>>>>>> Code executed in sdram can't mess with sdram settings because it will
>>>>>>>>>> hang the board. Sdram setup
>>>>>>>>>> needs to be done by code in SRAM (tpl).
>>>>>>>>>>
>>>>>>>>>> At least the rk3288-Firefly was able to also have mmc stack in the SPL
>>>>>>>>>> in
>>>>>>>>>> the past, without requiring the back_to_bootrom at all. So question
>>>>>>>>>> would
>>>>>>>>>> be why this doesn't fit anymore, or on the rk3066 specifically.
>>>>>>>>>>
>>>>>>>>>> Also, it seems like I got my hands on a preliminary (linux/mtd) nand
>>>>>>>>>> driver
>>>>>>>>>> (rk3228 but cursory glance at the registers suggests that it may
>>>>>>>>>> actually
>>>>>>>>>> work on previous socs down to the rk3066 as well) and it may be
>>>>>>>>>> possible
>>>>>>>>>> to adapt that for uboot, therefore making the spl able to also load the
>>>>>>>>>> full u-boot from without needing back_to_bootrom.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Heiko
>>>>>>>>>>
>>>>>>>>>> I was not able to get mmc support on rk3066 in spl in ~31kb (32kb - 1kb
>>>>>>>>>> for
>>>>>>>>>> tpl)size limit.
>>>>>>>>>> One (or two i didn't check how much) back to bootrom is required on
>>>>>>>>>> rk3066.
>>>>>>>>>> If not done bootrom stays in weird state and halts on bringup secondary
>>>>>>>>>> cpu
>>>>>>>>>> in kernel. So it's rk3066 specific.
>>>>>>>>>>
>>>>>>>>>> What size do you get? With firefly-rk3288 I get about 25KB with SDRAM
>>>>>>>>>> init and MMC stack. Are you building with Thumb 2?
>>>>>>>>>>
>>>>>>>>>> If you are on irc we could try to clear this up more quicky (I am sjg1)
>>>>>>>>>>
>>>>>>>>>> To summarise where I think we got to:
>>>>>>>>>>
>>>>>>>>>> - move DRAM init into SPL
>>>>>>>>>> - either have a very small TPL which just returns to boot ROM, or
>>>>>>>>>> adjust start.S to return to the boot room early in SPL to load the
>>>>>>>>>> other 31KB
>>>>>>>>>>
>>>>>>>>>> Can you please post to the mailing list with your thoughts on this so
>>>>>>>>>> that others (including rockchip) can chime in? I think either will
>>>>>>>>>> work but I think others will have an opinion.
>>>>>>>>>>
>>>>>>>>>> Regards,
>>>>>>>>>> Simon
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> About moving dram init to spl i agree.
>>>>>>>>>>
>>>>>>>>>> I think early back to bootrom in start.S is a good solution as it would
>>>>>>>>>> give
>>>>>>>>>> me 1KB more space for spl and i could drop hacks like jumping to spl in
>>>>>>>>>> tpl
>>>>>>>>>> board file. But I would like to hear the opinion of other people on
>>>>>>>>>> this.
>>>>>>>>> So with this solution there would be no TPL needed? It sounds
>>>>>>>>> reasonable to me. I'd like to hear other opinions also.
>>>>>>>> We don't need tpl if i use early back to bootrom in start.S patch with
>>>>>>>> spl... but i didn't test it yet. If it will work i will drop the tpl. Is
>>>>>>>> that ok?
>>>>>>> It's OK with me. I don't know how the BROM re-enters SPL after the
>>>>>>> first call into the 1KB region. Depending on how that works, it might
>>>>>>> be too painful to use SPL only (e.g. if it jumps to a place in the
>>>>>>> middle of SPL).
>>>>>> BROM re-enters same address 0x10080C04 two times. First when it boots,
>>>>>> second after first back to brom. That is why i used counter at address
>>>>>> 0x10080900 to count boot entries.
>>>>>> So it's not painful at all.
>>>>> OK from my POV this seems good.
>>>>>
>>>>> [..]
>>>>>
>>>>> Regards,
>>>>> Simon
>>>> It turns out that i will be needing tpl, spl and main u-boot. Also sdram initialization will be needed in tpl.
>>>>
>>>> Reason for that is how bootrom on rk3066 executes stuff:
>>>>
>>>> 1. At first stage it reads 2KB of data from nand to sram at address 0x10080C00 and decodes 1KB, executes decoded data at 0x10080C04 and waits for back to bootrom.
>>>> 2. At second stage it reads 31KB, decodes it and executes again data at 0x10080C04 and waits for second back to bootrom. Also SDRAM init MUST BE HERE or board hangs at third stage.
>>>> 3. At third stage bootrom reads ~200KB data to RAM at 0x60000000, decodes it and do final execution.
>>> Are both the first stage and the second stage loaded to SRAM + 0xc00?
>>> I.e. does the second stage (31KB) overwrite the first stage?
>> No. First stage is loaded to 0xC00 in sram(2KB but decoded from rc4 only 1KB), second stage is then loaded to 0xC00 + 2KB(0x400)
> If you have no logic (except for counting ‘reentries’) in the first stage, you might be able to implement this as a boot0 hook.
I will implement this as boot0 hook.
>
>>>> All three stages are required or else later kernel will halt at bringup secondary cpus using bootrom (there is another back to bootrom in kernel code to bringup secondary cpus)
>>>>
>>>> So there are two ways to boot main u-boot:
>>>>
>>>> 1. TPL + SPL loaded to sram (stages one and two) and main u-boot loaded to sdram(third stage). In this case main u-boot must fit in ~200KB which is not much and ONLY ONE of the features nand, mmc, usb might be compiled in.
>>>>
>>>> 2. TPL with SDRAM INIT + early back to bootrom patch as stage one and two, SPL as stage three, and main u-boot loaded from nand by SPL (stage four).
>>>>
>>>> I know all of this from bootrom disassembly and tests.
>>>>
>>>> So is it ok to go the second way?
> I would view option two as just having the usual three stages, but the TPL stage being loaded in pieces and being entered twice.
> So option 2 will then look a lot like other Rockchip boot sequences.
>
> Cheers,
> Philipp.
>
So i'll go option two.
Cheers,
Paweł
^ permalink raw reply [flat|nested] 86+ messages in thread
end of thread, other threads:[~2017-08-09 20:08 UTC | newest]
Thread overview: 86+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-06 18:48 [U-Boot] [PATCH 00/13] add support for rk3066 platform Paweł Jarosz
2017-06-06 18:48 ` [U-Boot] [PATCH 01/13] rockchip: rk3066: add grf header file Paweł Jarosz
2017-06-06 21:09 ` Simon Glass
2017-06-07 15:07 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot,01/13] " Philipp Tomsich
2017-06-06 18:49 ` [U-Boot] [PATCH 02/13] rockchip: rk3066: add rk3066 pinctrl driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:49 ` [U-Boot] [PATCH 03/13] rockchip: rk3066: add sysreset driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,03/13] " Philipp Tomsich
2017-07-04 17:41 ` Philipp Tomsich
2017-07-07 3:59 ` Simon Glass
2017-06-06 18:50 ` [U-Boot] [PATCH 04/13] rockchip: rk3066: add clock driver for rk3066 soc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:50 ` [U-Boot] [PATCH 05/13] rockchip: rk3066: add rk3066 platform devicetree file Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 15:12 ` Paweł Jarosz
2017-06-08 12:41 ` Heiko Stübner
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2017-06-06 18:50 ` [U-Boot] [PATCH 06/13] rockchip: rk3066: add core support Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 15:22 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
2017-06-09 13:03 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
2017-06-14 12:15 ` Kever Yang
2017-06-15 14:57 ` Simon Glass
2017-06-15 15:41 ` Paweł Jarosz
2017-06-15 15:59 ` Simon Glass
2017-06-07 6:37 ` Andy Yan
2017-06-25 23:23 ` [U-Boot] [U-Boot,06/13] " Philipp Tomsich
2017-07-04 17:35 ` Philipp Tomsich
2017-08-09 19:54 ` Paweł Jarosz
2017-06-06 18:51 ` [U-Boot] [PATCH 07/13] rockchip: rk3066: add mk808 board files Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 17:43 ` Philipp Tomsich
2017-06-06 18:51 ` [U-Boot] [PATCH 08/13] rockchip: mmc: support rk3066 mmc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 3:23 ` Kever Yang
2017-06-08 3:30 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot,08/13] " Philipp Tomsich
2017-06-06 18:52 ` [U-Boot] [PATCH 09/13] rockchip: dts: set fifo mode as default for mmc Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 16:41 ` Philipp Tomsich
2017-06-06 18:52 ` [U-Boot] [PATCH 10/13] rockchip: rk3066: add sdram driver Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 3:14 ` Kever Yang
2017-06-25 23:23 ` [U-Boot] [U-Boot,10/13] " Philipp Tomsich
2017-07-04 16:18 ` Philipp Tomsich
2017-06-06 18:53 ` [U-Boot] [PATCH 11/13] rockchip: serial: support rockchip rk3066 Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-06 18:53 ` [U-Boot] [PATCH 12/13] armv7: support rk3066 early back to bootrom in start.S Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 15:37 ` Paweł Jarosz
2017-06-09 11:46 ` Heiko Stuebner
2017-06-09 12:31 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
2017-06-14 11:06 ` Simon Glass
2017-06-15 7:15 ` Paweł Jarosz
2017-06-15 14:50 ` Simon Glass
2017-06-15 15:42 ` Paweł Jarosz
2017-06-15 16:00 ` Simon Glass
2017-06-15 16:32 ` Paweł Jarosz
2017-06-15 16:40 ` Simon Glass
2017-08-04 16:33 ` Paweł Jarosz
2017-08-04 16:51 ` Dr. Philipp Tomsich
2017-08-04 17:01 ` Paweł Jarosz
2017-08-09 20:01 ` Dr. Philipp Tomsich
2017-08-09 20:08 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
2017-06-09 13:11 ` Paweł Jarosz
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-07-04 16:20 ` Philipp Tomsich
2017-06-06 18:53 ` [U-Boot] [PATCH 13/13] rockchip: rk3066: add sdram init code for tpl Paweł Jarosz
2017-06-06 21:10 ` Simon Glass
2017-06-07 15:44 ` Paweł Jarosz
2017-06-09 12:27 ` Simon Glass
2017-06-09 13:15 ` Paweł Jarosz
2017-06-12 23:50 ` Simon Glass
2017-06-25 23:23 ` [U-Boot] [U-Boot, " Philipp Tomsich
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.