[GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES

[GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES

[Madhav Chauhan]

The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)

Deepak M (7):
  drm/i915/glk: Program dphy param reg for GLK
  drm/i915/glk: Program new MIPI DSI PHY registers for GLK
  drm/i915/glk: Add MIPIIO Enable/disable sequence
  drm/i915: Set the Z inversion overlap field
  drm/i915/glk: Add DSI PLL divider range for glk
  drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
  drm/i915/glk: Program txesc clock divider for GLK

 drivers/gpu/drm/i915/i915_reg.h            |  17 +++
 drivers/gpu/drm/i915/intel_dsi.c           | 207 ++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  33 ++++-
 drivers/gpu/drm/i915/intel_dsi_pll.c       | 106 ++++++++++++---
 4 files changed, 332 insertions(+), 31 deletions(-)

-- 
1.9.1

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[GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock count while for legacy platforms in terms of
HS ddr clk count.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8f683b8..8059cbb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -695,16 +695,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
 	 *
 	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
-	 * DPHY param register are divided by 2
+	 * DPHY param register are divided by 2 except GEMINILAKE where it is
+	 * programmed in terms of HS byte clock so divided by 8
 	 *
 	 * prepare count
 	 */
 	ths_prepare_ns = max(mipi_config->ths_prepare,
 			     mipi_config->tclk_prepare);
-	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
+	if (IS_GEMINILAKE(dev_priv))
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
+	else
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
 
 	/* exit zero count */
-	exit_zero_cnt = DIV_ROUND_UP(
+	if (IS_GEMINILAKE(dev_priv))
+		exit_zero_cnt = DIV_ROUND_UP(
+				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
+				ui_num * 8
+				);
+	else
+		exit_zero_cnt = DIV_ROUND_UP(
 				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
 				ui_num * 2
 				);
@@ -719,13 +729,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 		exit_zero_cnt += 1;
 
 	/* clk zero count */
-	clk_zero_cnt = DIV_ROUND_UP(
-			(tclk_prepare_clkzero -	ths_prepare_ns)
-			* ui_den, 2 * ui_num);
+	if (IS_GEMINILAKE(dev_priv))
+		clk_zero_cnt = DIV_ROUND_UP(
+				(tclk_prepare_clkzero -	ths_prepare_ns)
+				* ui_den, 8 * ui_num);
+	else
+		clk_zero_cnt = DIV_ROUND_UP(
+				(tclk_prepare_clkzero -	ths_prepare_ns)
+				* ui_den, 2 * ui_num);
 
 	/* trail count */
 	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
-	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
+
+	if (IS_GEMINILAKE(dev_priv))
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
+	else
+		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
 
 	if (prepare_cnt > PREPARE_CNT_MAX ||
 		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
-- 
1.9.1

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[GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Program the clk lane and tlpx time count registers
to configure DSI PHY.

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
 drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00970aa..f111c3f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8554,6 +8554,14 @@ enum {
 #define  LP_BYTECLK_SHIFT				0
 #define  LP_BYTECLK_MASK				(0xffff << 0)
 
+#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+
+#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+
 /* bits 31:0 */
 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 16732e7..be81283 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 		 */
 		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 
+		if (IS_GEMINILAKE(dev_priv)) {
+			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
+					intel_dsi->lp_byte_clk);
+			/* Shadow of DPHY reg */
+			I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi->dphy_reg);
+		}
+
 		/* the bw essential for transmitting 16 long packets containing
 		 * 252 bytes meant for dcs write memory command is programmed in
 		 * this register in terms of byte clocks. based on dsi transfer
-- 
1.9.1

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[GLK MIPI DSI V3 3/7] drm/i915/glk: Add MIPIIO Enable/disable sequence

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 183 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 181 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index be81283..3ae70ae 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -357,6 +357,106 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void glk_dsi_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp, val;
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Program LP Wake */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Set the MIPI mode */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
+	}
+
+	/* Wait for Pwr ACK */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+				GLK_MIPIIO_PORT_POWERED, 20))
+			DRM_ERROR("Power ACK not received\n");
+	}
+
+	/* Wait for MIPI PHY status bit to set */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+				GLK_MIPIIO_PORT_POWERED, 20))
+			DRM_ERROR("PHY is not ON\n");
+	}
+
+	/* Get IO out of reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
+
+	/* Get IO out of Low power state*/
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
+			val = I915_READ(MIPI_DEVICE_READY(port));
+			val &= ~ULPS_STATE_MASK;
+			val |= DEVICE_READY;
+			I915_WRITE(MIPI_DEVICE_READY(port), val);
+			usleep_range(10, 15);
+		}
+
+		/* Enter ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Wait for ULPS Not active */
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
+				GLK_ULPS_NOT_ACTIVE, 20))
+
+		/* Exit ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_EXIT | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		/* Enter Normal Mode */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_LP_WAKE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+
+	/* Wait for Stop state */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
+				GLK_DATA_LANE_STOP_STATE, 20))
+			DRM_ERROR("Date lane not in STOP state\n");
+	}
+
+	/* Wait for AFE LATCH */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+				BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
+				AFE_LATCHOUT, 20))
+			DRM_ERROR("D-PHY not entering LP-11 state\n");
+	}
+}
+
 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -442,8 +542,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_device_ready(encoder);
-	else if (IS_GEN9_LP(dev_priv))
+	else if (IS_BROXTON(dev_priv))
 		bxt_dsi_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_device_ready(encoder);
 }
 
 static void intel_dsi_port_enable(struct intel_encoder *encoder)
@@ -658,7 +760,73 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		wait_for_dsi_fifo_empty(intel_dsi, port);
 }
 
-static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 val;
+
+	/* Enter ULPS */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+	}
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Wait for Pwr ACK bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_MIPIIO_PORT_POWERED, 0, 20))
+			DRM_ERROR("MIPI IO Port is not powergated\n");
+	}
+}
+
+static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 tmp;
+
+	/* Put the IO into reset */
+	tmp = I915_READ(MIPI_CTRL(PORT_A));
+	tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+	I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+	/* Wait for MIPI PHY status bit to unset */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (intel_wait_for_register(dev_priv,
+					    MIPI_CTRL(port),
+					    GLK_PHY_STATUS_PORT_READY, 0, 20))
+			DRM_ERROR("PHY is not turning OFF\n");
+	}
+
+	/* Clear MIPI mode */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp = I915_READ(MIPI_CTRL(port));
+		tmp &= ~GLK_MIPIIO_ENABLE;
+		I915_WRITE(MIPI_CTRL(port), tmp);
+	}
+}
+
+static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	glk_dsi_enter_low_power_mode(encoder);
+	glk_dsi_disable_mipi_io(encoder);
+}
+
+static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -701,6 +869,17 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 	}
 }
 
+static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+	    IS_BROXTON(dev_priv))
+		vlv_dsi_clear_device_ready(encoder);
+	else if (IS_GEMINILAKE(dev_priv))
+		glk_dsi_clear_device_ready(encoder);
+}
+
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 				   struct intel_crtc_state *pipe_config,
 				   struct drm_connector_state *conn_state)
-- 
1.9.1

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[GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3ae70ae..95a6cad 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -558,12 +558,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 		u32 temp;
-
-		temp = I915_READ(VLV_CHICKEN_3);
-		temp &= ~PIXEL_OVERLAP_CNT_MASK |
+		if (IS_GEN9_LP(dev_priv)) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				temp = I915_READ(MIPI_CTRL(port));
+				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+					intel_dsi->pixel_overlap <<
+					BXT_PIXEL_OVERLAP_CNT_SHIFT;
+				I915_WRITE(MIPI_CTRL(port), temp);
+			}
+		} else {
+			temp = I915_READ(VLV_CHICKEN_3);
+			temp &= ~PIXEL_OVERLAP_CNT_MASK |
 					intel_dsi->pixel_overlap <<
 					PIXEL_OVERLAP_CNT_SHIFT;
-		I915_WRITE(VLV_CHICKEN_3, temp);
+			I915_WRITE(VLV_CHICKEN_3, temp);
+		}
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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[GLK MIPI DSI V3 5/7] drm/i915/glk: Add DSI PLL divider range for glk

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
 drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f111c3f..b1e679e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8272,10 +8272,12 @@ enum {
 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
 #define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
 #define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define  BXT_DSIC_16X_BY1		(0 << 10)
 #define  BXT_DSIC_16X_BY2		(1 << 10)
 #define  BXT_DSIC_16X_BY3		(2 << 10)
 #define  BXT_DSIC_16X_BY4		(3 << 10)
 #define  BXT_DSIC_16X_MASK		(3 << 10)
+#define  BXT_DSIA_16X_BY1		(0 << 8)
 #define  BXT_DSIA_16X_BY2		(1 << 8)
 #define  BXT_DSIA_16X_BY3		(2 << 8)
 #define  BXT_DSIA_16X_BY4		(3 << 8)
@@ -8285,6 +8287,8 @@ enum {
 
 #define BXT_DSI_PLL_RATIO_MAX		0x7D
 #define BXT_DSI_PLL_RATIO_MIN		0x22
+#define GLK_DSI_PLL_RATIO_MAX		0x6F
+#define GLK_DSI_PLL_RATIO_MIN		0x22
 #define BXT_DSI_PLL_RATIO_MASK		0xFF
 #define BXT_REF_CLOCK_KHZ		19200
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 61440e5..2771c9c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -430,9 +430,10 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
 }
 
-static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
 			       struct intel_crtc_state *config)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u8 dsi_ratio;
 	u32 dsi_clk;
@@ -446,11 +447,18 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
 	 * round 'up' the result
 	 */
 	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
-	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
-	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+
+	if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+			dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
 		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
 		return -ECHRNG;
-	}
+	} else if (IS_GEMINILAKE(dev_priv) &&
+			(dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
+			dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
+		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
+		return -ECHRNG;
+	} else
+		DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
 
 	/*
 	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
@@ -462,7 +470,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
 	/* As per recommendation from hardware team,
 	 * Prog PVD ratio =1 if dsi ratio <= 50
 	 */
-	if (dsi_ratio <= 50)
+	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
 		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
 
 	return 0;
@@ -522,7 +530,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_compute_dsi_pll(encoder, config);
 	else if (IS_GEN9_LP(dev_priv))
-		return bxt_compute_dsi_pll(encoder, config);
+		return gen9lp_compute_dsi_pll(encoder, config);
 
 	return -ENODEV;
 }
-- 
1.9.1

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[GLK MIPI DSI V3 6/7] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 2771c9c..462d42d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -491,8 +491,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 	POSTING_READ(BXT_DSI_PLL_CTL);
 
 	/* Program TX, RX, Dphy clocks */
-	for_each_dsi_port(port, intel_dsi->ports)
-		bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	if (IS_BROXTON(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports)
+			bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	}
 
 	/* Enable DSI PLL */
 	val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -556,19 +558,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 		bxt_disable_dsi_pll(encoder);
 }
 
-static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
+				    enum port port)
 {
 	u32 tmp;
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/* Clear old configurations */
-	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
-	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
-	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
-	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
-	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
-	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	if (IS_BROXTON(dev_priv)) {
+		tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+		tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+		tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
+		I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	}
 	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 }
 
@@ -577,7 +582,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
 	if (IS_GEN9_LP(dev_priv))
-		bxt_dsi_reset_clocks(encoder, port);
+		gen9lp_dsi_reset_clocks(encoder, port);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_dsi_reset_clocks(encoder, port);
 }
-- 
1.9.1

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[GLK MIPI DSI V3 7/7] drm/i915/glk: Program txesc clock divider for GLK

[Madhav Chauhan]

From: Deepak M <m.deepak@intel.com>

v2: Addressed Jani's Review comments(renamed bit field macros)

Txesc clock divider is calculated and programmed
for geminilake platform.

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  5 +++
 drivers/gpu/drm/i915/intel_dsi_pll.c | 61 ++++++++++++++++++++++++++++++++++--
 2 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b1e679e..c8921db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8186,6 +8186,11 @@ enum {
 #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
 #define _MMIO_MIPI(port, a, c)	_MMIO(_MIPI_PORT(port, a, c))
 
+#define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
+#define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
+#define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
+#define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
+
 /* BXT MIPI clock controls */
 #define BXT_MAX_VAR_OUTPUT_KHZ			39500
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 462d42d..b1cc006 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -372,6 +372,53 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 			ESCAPE_CLOCK_DIVIDER_SHIFT);
 }
 
+static void glk_dsi_program_esc_clock(struct drm_device *dev,
+				   const struct intel_crtc_state *config)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 dsi_rate = 0;
+	u32 pll_ratio = 0;
+	u32 ddr_clk = 0;
+	u32 div1_value = 0;
+	u32 div2_value = 0;
+	u32 txesc1_div = 0;
+	u32 txesc2_div = 0;
+
+	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
+
+	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+	ddr_clk = dsi_rate / 2;
+
+	/* Variable divider value */
+	div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
+
+	/* Calculate TXESC1 divider */
+	if (div1_value <= 10)
+		txesc1_div = div1_value;
+	else if ((div1_value > 10) && (div1_value <= 20))
+		txesc1_div = DIV_ROUND_UP(div1_value, 2);
+	else if ((div1_value > 20) && (div1_value <= 30))
+		txesc1_div = DIV_ROUND_UP(div1_value, 4);
+	else if ((div1_value > 30) && (div1_value <= 40))
+		txesc1_div = DIV_ROUND_UP(div1_value, 6);
+	else if ((div1_value > 40) && (div1_value <= 50))
+		txesc1_div = DIV_ROUND_UP(div1_value, 8);
+	else
+		txesc1_div = 10;
+
+	/* Calculate TXESC2 divider */
+	div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
+
+	if (div2_value < 10)
+		txesc2_div = div2_value;
+	else
+		txesc2_div = 10;
+
+	I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
+	I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
+}
+
 /* Program BXT Mipi clocks and dividers */
 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 				   const struct intel_crtc_state *config)
@@ -476,7 +523,7 @@ static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
 	return 0;
 }
 
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -494,6 +541,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
 	if (IS_BROXTON(dev_priv)) {
 		for_each_dsi_port(port, intel_dsi->ports)
 			bxt_dsi_program_clocks(encoder->base.dev, port, config);
+	} else {
+		glk_dsi_program_esc_clock(encoder->base.dev, config);
 	}
 
 	/* Enable DSI PLL */
@@ -545,7 +594,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		vlv_enable_dsi_pll(encoder, config);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_enable_dsi_pll(encoder, config);
+		gen9lp_enable_dsi_pll(encoder, config);
 }
 
 void intel_disable_dsi_pll(struct intel_encoder *encoder)
@@ -573,6 +622,14 @@ static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
 		tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
 		tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
 		I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	} else {
+		tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
+		tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
+		I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
+
+		tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
+		tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
+		I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
 	}
 	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 }
-- 
1.9.1

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✗ Fi.CI.BAT: warning for GLK MIPI DSI VIDEO MODE PATCHES (rev3)

[Patchwork]

== Series Details ==

Series: GLK MIPI DSI VIDEO MODE PATCHES (rev3)
URL   : https://patchwork.freedesktop.org/series/16542/
State : warning

== Summary ==

Series 16542v3 GLK MIPI DSI VIDEO MODE PATCHES
https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/3/mbox/

Test gem_sync:
        Subgroup basic-store-all:
                fail       -> PASS       (fi-ivb-3520m)
Test kms_pipe_crc_basic:
        Subgroup nonblocking-crc-pipe-b-frame-sequence:
                pass       -> DMESG-WARN (fi-snb-2520m)

fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:246  pass:214  dwarn:1   dfail:0   fail:0   skip:31 
fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a07420cecb721150bc4a75369d9d91bd4efe03f6 drm-tip: 2017y-01m-02d-09h-37m-49s UTC integration manifest
61be665 drm/i915/glk: Program txesc clock divider for GLK
f67caa6 drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
eff4064 drm/i915/glk: Add DSI PLL divider range for glk
751227c drm/i915: Set the Z inversion overlap field
e9b44bb drm/i915/glk: Add MIPIIO Enable/disable sequence
66e55e2 drm/i915/glk: Program new MIPI DSI PHY registers for GLK
bfde2c4 drm/i915/glk: Program dphy param reg for GLK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3418/
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Re: ✗ Fi.CI.BAT: warning for GLK MIPI DSI VIDEO MODE PATCHES (rev3)

[Saarinen, Jani]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: Monday, January 2, 2017 3:24 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.BAT: warning for GLK MIPI DSI VIDEO MODE PATCHES
> (rev3)
> 
> == Series Details ==
> 
> Series: GLK MIPI DSI VIDEO MODE PATCHES (rev3)
> URL   : https://patchwork.freedesktop.org/series/16542/
> State : warning
> 
> == Summary ==
> 
> Series 16542v3 GLK MIPI DSI VIDEO MODE PATCHES
> https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/3/mbox/
> 
> Test gem_sync:
>         Subgroup basic-store-all:
>                 fail       -> PASS       (fi-ivb-3520m)
> Test kms_pipe_crc_basic:
>         Subgroup nonblocking-crc-pipe-b-frame-sequence:
>                 pass       -> DMESG-WARN (fi-snb-2520m)
Still there: https://bugs.freedesktop.org/show_bug.cgi?id=98625
> 
> fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14
> fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39
> fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22
> fi-bxt-t5700     total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12
> fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27
> fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31
> fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19
> fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19
> fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21
> fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21
> fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13
> fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20
> fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21
> fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13
> fi-snb-2520m     total:246  pass:214  dwarn:1   dfail:0   fail:0   skip:31
> fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32
> 
> a07420cecb721150bc4a75369d9d91bd4efe03f6 drm-tip: 2017y-01m-02d-09h-
> 37m-49s UTC integration manifest
> 61be665 drm/i915/glk: Program txesc clock divider for GLK
> f67caa6 drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
> eff4064 drm/i915/glk: Add DSI PLL divider range for glk 751227c drm/i915: Set
> the Z inversion overlap field e9b44bb drm/i915/glk: Add MIPIIO Enable/disable
> sequence
> 66e55e2 drm/i915/glk: Program new MIPI DSI PHY registers for GLK
> bfde2c4 drm/i915/glk: Program dphy param reg for GLK
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3418/


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo


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Re: [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK

[Jani Nikula]

On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> For GEMINILAKE, dphy param reg values are programmed in terms
> of HS byte clock count while for legacy platforms in terms of
> HS ddr clk count.

No need to call everything before this one "legacy".

> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++++++++++++++++++++++-------
>  1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 8f683b8..8059cbb 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -695,16 +695,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
>  	 *
>  	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
> -	 * DPHY param register are divided by 2
> +	 * DPHY param register are divided by 2 except GEMINILAKE where it is
> +	 * programmed in terms of HS byte clock so divided by 8

Would you say these two hold?

1) HSDDR = 2 * HS

2) HS byte clock = HS / 8

So it would seem to me either the existing code or your patch is
wrong. (Or I'm seriously confused.)

If the register is in terms of clock *cycles*, not frequency, should the
HSDDR based clock (pre-GLK) actually have *twice* the clock cycles, not
*half*? Making the existing code wrong?

The existing code could use some serious cleanup to make it readable. :(

BR,
Jani.



>  	 *
>  	 * prepare count
>  	 */
>  	ths_prepare_ns = max(mipi_config->ths_prepare,
>  			     mipi_config->tclk_prepare);
> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
> +	if (IS_GEMINILAKE(dev_priv))
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
> +	else
> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
>  
>  	/* exit zero count */
> -	exit_zero_cnt = DIV_ROUND_UP(
> +	if (IS_GEMINILAKE(dev_priv))
> +		exit_zero_cnt = DIV_ROUND_UP(
> +				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
> +				ui_num * 8
> +				);
> +	else
> +		exit_zero_cnt = DIV_ROUND_UP(
>  				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>  				ui_num * 2
>  				);
> @@ -719,13 +729,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>  		exit_zero_cnt += 1;
>  
>  	/* clk zero count */
> -	clk_zero_cnt = DIV_ROUND_UP(
> -			(tclk_prepare_clkzero -	ths_prepare_ns)
> -			* ui_den, 2 * ui_num);
> +	if (IS_GEMINILAKE(dev_priv))
> +		clk_zero_cnt = DIV_ROUND_UP(
> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> +				* ui_den, 8 * ui_num);
> +	else
> +		clk_zero_cnt = DIV_ROUND_UP(
> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> +				* ui_den, 2 * ui_num);
>  
>  	/* trail count */
>  	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> +
> +	if (IS_GEMINILAKE(dev_priv))
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
> +	else
> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
>  
>  	if (prepare_cnt > PREPARE_CNT_MAX ||
>  		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK

[Jani Nikula]

On Wed, 18 Jan 2017, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> From: Deepak M <m.deepak@intel.com>
>>
>> For GEMINILAKE, dphy param reg values are programmed in terms
>> of HS byte clock count while for legacy platforms in terms of
>> HS ddr clk count.
>
> No need to call everything before this one "legacy".
>
>> Signed-off-by: Deepak M <m.deepak@intel.com>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++++++++++++++++++++++-------
>>  1 file changed, 26 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index 8f683b8..8059cbb 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -695,16 +695,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>  	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
>>  	 *
>>  	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
>> -	 * DPHY param register are divided by 2
>> +	 * DPHY param register are divided by 2 except GEMINILAKE where it is
>> +	 * programmed in terms of HS byte clock so divided by 8
>
> Would you say these two hold?
>
> 1) HSDDR = 2 * HS
>
> 2) HS byte clock = HS / 8
>
> So it would seem to me either the existing code or your patch is
> wrong. (Or I'm seriously confused.)
>
> If the register is in terms of clock *cycles*, not frequency, should the
> HSDDR based clock (pre-GLK) actually have *twice* the clock cycles, not
> *half*? Making the existing code wrong?
>
> The existing code could use some serious cleanup to make it readable. :(

Additionally, I think you could use a variable to handle this, to not
add so much duplicated code.

BR,
Jani.



>
> BR,
> Jani.
>
>
>
>>  	 *
>>  	 * prepare count
>>  	 */
>>  	ths_prepare_ns = max(mipi_config->ths_prepare,
>>  			     mipi_config->tclk_prepare);
>> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
>> +	if (IS_GEMINILAKE(dev_priv))
>> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
>> +	else
>> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
>>  
>>  	/* exit zero count */
>> -	exit_zero_cnt = DIV_ROUND_UP(
>> +	if (IS_GEMINILAKE(dev_priv))
>> +		exit_zero_cnt = DIV_ROUND_UP(
>> +				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>> +				ui_num * 8
>> +				);
>> +	else
>> +		exit_zero_cnt = DIV_ROUND_UP(
>>  				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
>>  				ui_num * 2
>>  				);
>> @@ -719,13 +729,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>>  		exit_zero_cnt += 1;
>>  
>>  	/* clk zero count */
>> -	clk_zero_cnt = DIV_ROUND_UP(
>> -			(tclk_prepare_clkzero -	ths_prepare_ns)
>> -			* ui_den, 2 * ui_num);
>> +	if (IS_GEMINILAKE(dev_priv))
>> +		clk_zero_cnt = DIV_ROUND_UP(
>> +				(tclk_prepare_clkzero -	ths_prepare_ns)
>> +				* ui_den, 8 * ui_num);
>> +	else
>> +		clk_zero_cnt = DIV_ROUND_UP(
>> +				(tclk_prepare_clkzero -	ths_prepare_ns)
>> +				* ui_den, 2 * ui_num);
>>  
>>  	/* trail count */
>>  	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
>> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
>> +
>> +	if (IS_GEMINILAKE(dev_priv))
>> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
>> +	else
>> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
>>  
>>  	if (prepare_cnt > PREPARE_CNT_MAX ||
>>  		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Jani Nikula]

On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Program the clk lane and tlpx time count registers
> to configure DSI PHY.
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Program clk lane timing reg same as dphy param reg.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
>  2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa..f111c3f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8554,6 +8554,14 @@ enum {
>  #define  LP_BYTECLK_SHIFT				0
>  #define  LP_BYTECLK_MASK				(0xffff << 0)
>  
> +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
> +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
> +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> +
> +#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
> +#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
> +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> +
>  /* bits 31:0 */
>  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
>  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 16732e7..be81283 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>  		 */
>  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);

IIUC you also need to write 1 to MIPI_LP_BYTECLK(port) on GLK. Or how do
you read the spec on the register?

>  
> +		if (IS_GEMINILAKE(dev_priv)) {
> +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> +					intel_dsi->lp_byte_clk);
> +			/* Shadow of DPHY reg */
> +			I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi->dphy_reg);

The spec lists only specific valid values for the register. Is the spec
right?

BR,
Jani.

> +		}
> +
>  		/* the bw essential for transmitting 16 long packets containing
>  		 * 252 bytes meant for dcs write memory command is programmed in
>  		 * this register in terms of byte clocks. based on dsi transfer

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field

[Jani Nikula]

On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the older platforms,
> hence setting the same in this patch.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3ae70ae..95a6cad 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -558,12 +558,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>  		u32 temp;
> -
> -		temp = I915_READ(VLV_CHICKEN_3);
> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> +		if (IS_GEN9_LP(dev_priv)) {
> +			for_each_dsi_port(port, intel_dsi->ports) {
> +				temp = I915_READ(MIPI_CTRL(port));
> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> +					intel_dsi->pixel_overlap <<
> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> +				I915_WRITE(MIPI_CTRL(port), temp);

I think I'd do this where MIPI_CTRL is updated. If we set
->pixel_overlap to 0 for intel_dsi->dual_link !=
DSI_DUAL_LINK_FRONT_BACK in vbt_panel_init(), we can just write it
instead of checking dual_link.

BR,
Jani.

> +			}
> +		} else {
> +			temp = I915_READ(VLV_CHICKEN_3);
> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
>  					intel_dsi->pixel_overlap <<
>  					PIXEL_OVERLAP_CNT_SHIFT;
> -		I915_WRITE(VLV_CHICKEN_3, temp);
> +			I915_WRITE(VLV_CHICKEN_3, temp);
> +		}
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, January 18, 2017 9:00 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Deepak
> M <m.deepak@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY
> registers for GLK
> 
> On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > Program the clk lane and tlpx time count registers to configure DSI
> > PHY.
> >
> > v2: Addressed Jani's Review comments(renamed bit field macros)
> > v3: Program clk lane timing reg same as dphy param reg.
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
> > drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
> >  2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 00970aa..f111c3f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8554,6 +8554,14 @@ enum {
> >  #define  LP_BYTECLK_SHIFT				0
> >  #define  LP_BYTECLK_MASK				(0xffff << 0)
> >
> > +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base
> + 0xb0a4)
> > +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base
> + 0xb8a4)
> > +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port,
> _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> > +
> > +#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base
> + 0xb098)
> > +#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base
> + 0xb898)
> > +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port,
> _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> > +
> >  /* bits 31:0 */
> >  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base
> + 0xb064)
> >  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base
> + 0xb864)
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 16732e7..be81283 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct
> intel_encoder *intel_encoder,
> >  		 */
> >  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
> 
> IIUC you also need to write 1 to MIPI_LP_BYTECLK(port) on GLK. Or how do
> you read the spec on the register?

Sorry if I missed, is it mentioned in spec that MIPI_LP_BYTECLK(port) will be programmed to '1'?? 
Checked spec, couldn't find this. Please specify.

> 
> >
> > +		if (IS_GEMINILAKE(dev_priv)) {
> > +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> > +					intel_dsi->lp_byte_clk);
> > +			/* Shadow of DPHY reg */
> > +			I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi-
> >dphy_reg);
> 
> The spec lists only specific valid values for the register. Is the spec right?

Spec mentions DPHY parameters i.e. exit, trail, count, prep should be programmed in
terms of byte clock which is same as for DPHY param reg. To confirm this, printed clk lane timing
register value programmed by BIOS and its same as DPHY param reg value.

> 
> BR,
> Jani.
> 
> > +		}
> > +
> >  		/* the bw essential for transmitting 16 long packets
> containing
> >  		 * 252 bytes meant for dcs write memory command is
> programmed in
> >  		 * this register in terms of byte clocks. based on dsi transfer
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Jani Nikula]

On Thu, 19 Jan 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Wednesday, January 18, 2017 9:00 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
>> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
>> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
>> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
>> <chandra.konduru@intel.com>; Kumar, Shobhit
>> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Deepak
>> M <m.deepak@intel.com>; Chauhan, Madhav
>> <madhav.chauhan@intel.com>
>> Subject: Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY
>> registers for GLK
>> 
>> On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com>
>> wrote:
>> > From: Deepak M <m.deepak@intel.com>
>> >
>> > Program the clk lane and tlpx time count registers to configure DSI
>> > PHY.
>> >
>> > v2: Addressed Jani's Review comments(renamed bit field macros)
>> > v3: Program clk lane timing reg same as dphy param reg.
>> >
>> > Signed-off-by: Deepak M <m.deepak@intel.com>
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
>> > drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
>> >  2 files changed, 15 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 00970aa..f111c3f 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -8554,6 +8554,14 @@ enum {
>> >  #define  LP_BYTECLK_SHIFT				0
>> >  #define  LP_BYTECLK_MASK				(0xffff << 0)
>> >
>> > +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base
>> + 0xb0a4)
>> > +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base
>> + 0xb8a4)
>> > +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port,
>> _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
>> > +
>> > +#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base
>> + 0xb098)
>> > +#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base
>> + 0xb898)
>> > +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port,
>> _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
>> > +
>> >  /* bits 31:0 */
>> >  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base
>> + 0xb064)
>> >  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base
>> + 0xb864)
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
>> > b/drivers/gpu/drm/i915/intel_dsi.c
>> > index 16732e7..be81283 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> > @@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct
>> intel_encoder *intel_encoder,
>> >  		 */
>> >  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
>> 
>> IIUC you also need to write 1 to MIPI_LP_BYTECLK(port) on GLK. Or how do
>> you read the spec on the register?
>
> Sorry if I missed, is it mentioned in spec that MIPI_LP_BYTECLK(port) will be programmed to '1'?? 
> Checked spec, couldn't find this. Please specify.

The spec lists "valid values" for MIPI_LP_BYTECLK and there's only value
1 for GLK+. I don't know if they try to list that as just the default,
but it looks odd.

>
>> 
>> >
>> > +		if (IS_GEMINILAKE(dev_priv)) {
>> > +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
>> > +					intel_dsi->lp_byte_clk);
>> > +			/* Shadow of DPHY reg */
>> > +			I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi-
>> >dphy_reg);
>> 
>> The spec lists only specific valid values for the register. Is the spec right?
>
> Spec mentions DPHY parameters i.e. exit, trail, count, prep should be programmed in
> terms of byte clock which is same as for DPHY param reg. To confirm this, printed clk lane timing
> register value programmed by BIOS and its same as DPHY param reg value.

Same here. Perhaps they're trying to just list the defaults, but it
shows up as "valid values"...

In any case, the DPHY register has changed starting in BXT, and the
fields are now 8 bits each rather than fewer as for BYT/CHV.

BR,
Jani.



>
>> 
>> BR,
>> Jani.
>> 
>> > +		}
>> > +
>> >  		/* the bw essential for transmitting 16 long packets
>> containing
>> >  		 * 252 bytes meant for dcs write memory command is
>> programmed in
>> >  		 * this register in terms of byte clocks. based on dsi transfer
>> 
>> --
>> Jani Nikula, Intel Open Source Technology Center

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, January 19, 2017 2:54 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>
> Subject: RE: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY
> registers for GLK
> 
> On Thu, 19 Jan 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com>
> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani
> >> Sent: Wednesday, January 18, 2017 9:00 PM
> >> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> >> <indranil.mukherjee@intel.com>; Kamath, Sunil
> >> <sunil.kamath@intel.com>; Saarinen, Jani <jani.saarinen@intel.com>;
> >> Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> >> Konduru, Chandra <chandra.konduru@intel.com>; Kumar, Shobhit
> >> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> >> Deepak M <m.deepak@intel.com>; Chauhan, Madhav
> >> <madhav.chauhan@intel.com>
> >> Subject: Re: [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI
> >> PHY registers for GLK
> >>
> >> On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> >> wrote:
> >> > From: Deepak M <m.deepak@intel.com>
> >> >
> >> > Program the clk lane and tlpx time count registers to configure DSI
> >> > PHY.
> >> >
> >> > v2: Addressed Jani's Review comments(renamed bit field macros)
> >> > v3: Program clk lane timing reg same as dphy param reg.
> >> >
> >> > Signed-off-by: Deepak M <m.deepak@intel.com>
> >> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
> >> > drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
> >> >  2 files changed, 15 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> > b/drivers/gpu/drm/i915/i915_reg.h index 00970aa..f111c3f 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -8554,6 +8554,14 @@ enum {
> >> >  #define  LP_BYTECLK_SHIFT				0
> >> >  #define  LP_BYTECLK_MASK				(0xffff << 0)
> >> >
> >> > +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv-
> >mipi_mmio_base
> >> + 0xb0a4)
> >> > +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv-
> >mipi_mmio_base
> >> + 0xb8a4)
> >> > +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port,
> >> _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> >> > +
> >> > +#define _MIPIA_CLK_LANE_TIMING		(dev_priv-
> >mipi_mmio_base
> >> + 0xb098)
> >> > +#define _MIPIC_CLK_LANE_TIMING		(dev_priv-
> >mipi_mmio_base
> >> + 0xb898)
> >> > +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port,
> >> _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> >> > +
> >> >  /* bits 31:0 */
> >> >  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base
> >> + 0xb064)
> >> >  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base
> >> + 0xb864)
> >> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> >> > b/drivers/gpu/drm/i915/intel_dsi.c
> >> > index 16732e7..be81283 100644
> >> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> >> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> >> > @@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct
> >> intel_encoder *intel_encoder,
> >> >  		 */
> >> >  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
> >>
> >> IIUC you also need to write 1 to MIPI_LP_BYTECLK(port) on GLK. Or how
> >> do you read the spec on the register?
> >
> > Sorry if I missed, is it mentioned in spec that MIPI_LP_BYTECLK(port) will be
> programmed to '1'??
> > Checked spec, couldn't find this. Please specify.
> 
> The spec lists "valid values" for MIPI_LP_BYTECLK and there's only value
> 1 for GLK+. I don't know if they try to list that as just the default, but it looks
> odd.

Ahh..Got it. That should be the default value not the only correct value.
Might be some mistake to show it as valid value.

> 
> >
> >>
> >> >
> >> > +		if (IS_GEMINILAKE(dev_priv)) {
> >> > +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> >> > +					intel_dsi->lp_byte_clk);
> >> > +			/* Shadow of DPHY reg */
> >> > +			I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi-
> >> >dphy_reg);
> >>
> >> The spec lists only specific valid values for the register. Is the spec right?
> >
> > Spec mentions DPHY parameters i.e. exit, trail, count, prep should be
> > programmed in terms of byte clock which is same as for DPHY param reg.
> > To confirm this, printed clk lane timing register value programmed by BIOS
> and its same as DPHY param reg value.
> 
> Same here. Perhaps they're trying to just list the defaults, but it shows up as
> "valid values"...
> 
> In any case, the DPHY register has changed starting in BXT, and the fields are
> now 8 bits each rather than fewer as for BYT/CHV.

Agree. 

> 
> BR,
> Jani.
> 
> 
> 
> >
> >>
> >> BR,
> >> Jani.
> >>
> >> > +		}
> >> > +
> >> >  		/* the bw essential for transmitting 16 long packets
> >> containing
> >> >  		 * 252 bytes meant for dcs write memory command is
> >> programmed in
> >> >  		 * this register in terms of byte clocks. based on dsi transfer
> >>
> >> --
> >> Jani Nikula, Intel Open Source Technology Center
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, January 18, 2017 7:41 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Deepak
> M <m.deepak@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for
> GLK
> 
> On Wed, 18 Jan 2017, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> >> From: Deepak M <m.deepak@intel.com>
> >>
> >> For GEMINILAKE, dphy param reg values are programmed in terms of HS
> >> byte clock count while for legacy platforms in terms of HS ddr clk
> >> count.
> >
> > No need to call everything before this one "legacy".
> >
> >> Signed-off-by: Deepak M <m.deepak@intel.com>
> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33
> >> +++++++++++++++++++++++-------
> >>  1 file changed, 26 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> index 8f683b8..8059cbb 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> >> @@ -695,16 +695,26 @@ struct drm_panel *vbt_panel_init(struct
> intel_dsi *intel_dsi, u16 panel_id)
> >>  	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> >>  	 *
> >>  	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
> >> -	 * DPHY param register are divided by 2
> >> +	 * DPHY param register are divided by 2 except GEMINILAKE where it
> is
> >> +	 * programmed in terms of HS byte clock so divided by 8
> >
> > Would you say these two hold?
> >
> > 1) HSDDR = 2 * HS
> >
> > 2) HS byte clock = HS / 8
> >
> > So it would seem to me either the existing code or your patch is
> > wrong. (Or I'm seriously confused.)
> >
> > If the register is in terms of clock *cycles*, not frequency, should
> > the HSDDR based clock (pre-GLK) actually have *twice* the clock
> > cycles, not *half*? Making the existing code wrong?
> >
> > The existing code could use some serious cleanup to make it readable.
> > :(
> 
> Additionally, I think you could use a variable to handle this, to not add so
> much duplicated code.

Old Comments are not very clear to justify this calculation.
Went through dphy/IP spec and here is my explanation
1. As per DPHY spec
	DDR Clock period = 1UI + 1UI = 2UI
2. 1UI in terms of time:
	1UI (sec) = 1/(Bitrate *10^3)	// bitrate is in KHZ
	1UI (nsec) = (1*10^9)/(Bitrate*10^3) = 10^6/Bitrate
3. DDR clock period is twice of UI period as per 1 = (2*10^6)/Bitrate
4. ths_prepare_ns (via mipi_config) is to be programmed in terms *DDR clock count*  to dphy register

	DDR clock count = ths_prepare_ns /((2*10^6)/Bitrate)) = (ths_prepare_ns*Bitrate)/(2*10^6)
> 
> BR,
> Jani.
> 
> 
> 
> >
> > BR,
> > Jani.
> >
> >
> >
> >>  	 *
> >>  	 * prepare count
> >>  	 */
> >>  	ths_prepare_ns = max(mipi_config->ths_prepare,
> >>  			     mipi_config->tclk_prepare);
> >> -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num *
> 2);
> >> +	if (IS_GEMINILAKE(dev_priv))
> >> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 8);
> >> +	else
> >> +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 2);
> >>
> >>  	/* exit zero count */
> >> -	exit_zero_cnt = DIV_ROUND_UP(
> >> +	if (IS_GEMINILAKE(dev_priv))
> >> +		exit_zero_cnt = DIV_ROUND_UP(
> >> +				(ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> >> +				ui_num * 8
> >> +				);
> >> +	else
> >> +		exit_zero_cnt = DIV_ROUND_UP(
> >>  				(ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> >>  				ui_num * 2
> >>  				);
> >> @@ -719,13 +729,22 @@ struct drm_panel *vbt_panel_init(struct
> intel_dsi *intel_dsi, u16 panel_id)
> >>  		exit_zero_cnt += 1;
> >>
> >>  	/* clk zero count */
> >> -	clk_zero_cnt = DIV_ROUND_UP(
> >> -			(tclk_prepare_clkzero -	ths_prepare_ns)
> >> -			* ui_den, 2 * ui_num);
> >> +	if (IS_GEMINILAKE(dev_priv))
> >> +		clk_zero_cnt = DIV_ROUND_UP(
> >> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> >> +				* ui_den, 8 * ui_num);
> >> +	else
> >> +		clk_zero_cnt = DIV_ROUND_UP(
> >> +				(tclk_prepare_clkzero -	ths_prepare_ns)
> >> +				* ui_den, 2 * ui_num);
> >>
> >>  	/* trail count */
> >>  	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> >> -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> >> +
> >> +	if (IS_GEMINILAKE(dev_priv))
> >> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 *
> ui_num);
> >> +	else
> >> +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 *
> ui_num);
> >>
> >>  	if (prepare_cnt > PREPARE_CNT_MAX ||
> >>  		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, January 18, 2017 9:21 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Deepak
> M <m.deepak@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field
> 
> On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > Dual link Z-inversion overlap field is present in MIPI_CTRL register
> > unlike the older platforms, hence setting the same in this patch.
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
> >  1 file changed, 13 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 3ae70ae..95a6cad 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -558,12 +558,21 @@ static void intel_dsi_port_enable(struct
> > intel_encoder *encoder)
> >
> >  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> >  		u32 temp;
> > -
> > -		temp = I915_READ(VLV_CHICKEN_3);
> > -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> > +		if (IS_GEN9_LP(dev_priv)) {
> > +			for_each_dsi_port(port, intel_dsi->ports) {
> > +				temp = I915_READ(MIPI_CTRL(port));
> > +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> > +					intel_dsi->pixel_overlap <<
> > +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> > +				I915_WRITE(MIPI_CTRL(port), temp);
> 
> I think I'd do this where MIPI_CTRL is updated. If we set

What to do when MIPI_CTRL is updated and where?? Please specify.

> ->pixel_overlap to 0 for intel_dsi->dual_link !=
> DSI_DUAL_LINK_FRONT_BACK in vbt_panel_init(), we can just write it instead
> of checking dual_link.

Yes we can do this but any way we need to put if condition inside vbt_panel_init. Additional advantage??
It would be more useful if we replace all if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)  checks inside the driver code 
When ->pixel_overlap is used. Am I missing something?? Please clarify.

> 
> BR,
> Jani.
> 
> > +			}
> > +		} else {
> > +			temp = I915_READ(VLV_CHICKEN_3);
> > +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> >  					intel_dsi->pixel_overlap <<
> >  					PIXEL_OVERLAP_CNT_SHIFT;
> > -		I915_WRITE(VLV_CHICKEN_3, temp);
> > +			I915_WRITE(VLV_CHICKEN_3, temp);
> > +		}
> >  	}
> >
> >  	for_each_dsi_port(port, intel_dsi->ports) {
> 
> --
> Jani Nikula, Intel Open Source Technology Center
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Re: [GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES

[Chauhan, Madhav]

> -----Original Message-----
> From: Chauhan, Madhav
> Sent: Monday, January 2, 2017 6:24 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: [GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES
> 
> The patches in this list enable MIPI DSI video mode support for GLK platform.
> Tesed locally.
> v2: Renamed bitfields macros as per review comments(Jani)
> v3: Code alignment/abstraction as per arch (Jani review comments)
> 

Found one issue in the MIPI DSI disable sequence during the testing.
Working on fix. Will be able to publish the next series having fix and Jani review comments for couple of patches.

> Deepak M (7):
>   drm/i915/glk: Program dphy param reg for GLK
>   drm/i915/glk: Program new MIPI DSI PHY registers for GLK
>   drm/i915/glk: Add MIPIIO Enable/disable sequence
>   drm/i915: Set the Z inversion overlap field
>   drm/i915/glk: Add DSI PLL divider range for glk
>   drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
>   drm/i915/glk: Program txesc clock divider for GLK
> 
>  drivers/gpu/drm/i915/i915_reg.h            |  17 +++
>  drivers/gpu/drm/i915/intel_dsi.c           | 207
> ++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  33 ++++-
>  drivers/gpu/drm/i915/intel_dsi_pll.c       | 106 ++++++++++++---
>  4 files changed, 332 insertions(+), 31 deletions(-)
> 
> --
> 1.9.1

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