* Understanding AMD NPT in xen
@ 2012-04-12 17:06 Steven
2012-04-12 21:35 ` Huang2, Wei
0 siblings, 1 reply; 3+ messages in thread
From: Steven @ 2012-04-12 17:06 UTC (permalink / raw)
To: Wei Wang, xen-devel
Hi, Wei,
I have read you slides in xen summit 2007 about NPT in AMD, "AMD
Barcelona and Nested Paging Support in Xen".
However, I have some question regarding the nested page walk in your slide 8.
In your slide 8, the first step is to get gPA from get_PML4(gCR3,gVA).
I assume that it use the [47:39] bit of gVA.
However, in another AMD white paper, "AMD-VTM Nested Paging".
http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf
In its figure 4, I saw that the first step is to translate gCR3 using
nested page walk and then combine with the gVA[47:39] to read the
table entry.
These two documents look having different order of reading the guest
page table. In the slides, it first get_PML4. But in the white paper,
it first does nested page walk.
I am wondering which one is true. Thanks.
- ha
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Understanding AMD NPT in xen
2012-04-12 17:06 Understanding AMD NPT in xen Steven
@ 2012-04-12 21:35 ` Huang2, Wei
[not found] ` <4400B41FB768044EA720935D0808176C090BCDDC@sausexdag02.amd.com>
0 siblings, 1 reply; 3+ messages in thread
From: Huang2, Wei @ 2012-04-12 21:35 UTC (permalink / raw)
To: Steven, Wang2, Wei, xen-devel
White page info is more accurate. The slides was a bit vague. Here are the steps, assuming that CPU doesn't have TLB:
1. To find out gPML4E
* Traverse nested page table using gCR3 to locate guest level-4 page (PML4 table)
* Use PML4 offset (bit 47:39) to get the value of gPML4E
2. To find out gPDPE
* Traverse nested page table using gPML4E to locate guest level-3 page (PDP table)
* Use PDP offset (bit 38:30) to get the value of gPDPE
3. To find out gPDE
* Traverse nested page table using gPDPE to locate guest level-2 page (PD table)
* Use PD offset (bit 29:21) to get the value of gPDE
4. To find out gPTE
* Traverse nested page table using gPDE to locate guest level-1 page (PT table)
* Use PT offset (bit 20:12) to get the value of gPTE
5. To find out gData
* Traverse nested page table using gPTE to locate guest data page
* Use physical page offset (bit 11:0) to get the data value
TLB will accelerate this walking significantly.
-Wei
-----Original Message-----
From: xen-devel-bounces@lists.xen.org [mailto:xen-devel-bounces@lists.xen.org] On Behalf Of Steven
Sent: Thursday, April 12, 2012 12:06 PM
To: Wang2, Wei; xen-devel@lists.xensource.com
Subject: [Xen-devel] Understanding AMD NPT in xen
Hi, Wei,
I have read you slides in xen summit 2007 about NPT in AMD, "AMD
Barcelona and Nested Paging Support in Xen".
However, I have some question regarding the nested page walk in your slide 8.
In your slide 8, the first step is to get gPA from get_PML4(gCR3,gVA).
I assume that it use the [47:39] bit of gVA.
However, in another AMD white paper, "AMD-VTM Nested Paging".
http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf
In its figure 4, I saw that the first step is to translate gCR3 using
nested page walk and then combine with the gVA[47:39] to read the
table entry.
These two documents look having different order of reading the guest
page table. In the slides, it first get_PML4. But in the white paper,
it first does nested page walk.
I am wondering which one is true. Thanks.
- ha
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Understanding AMD NPT in xen
[not found] ` <4400B41FB768044EA720935D0808176C090BCDDC@sausexdag02.amd.com>
@ 2012-04-13 2:29 ` Steven
0 siblings, 0 replies; 3+ messages in thread
From: Steven @ 2012-04-13 2:29 UTC (permalink / raw)
To: Huang2, Wei, xen-devel
This clarifies everything. Thanks.
- Hui
On Thu, Apr 12, 2012 at 5:50 PM, Huang2, Wei <Wei.Huang2@amd.com> wrote:
> Reformat:
>
> 1. To find out gPML4E
> * Traverse nested page table using gCR3 to locate guest level-4 page (PML4 table)
> * Use PML4 offset (bit 47:39) to get the value of gPML4E
>
> 2. To find out gPDPE
> * Traverse nested page table using gPML4E to locate guest level-3 page (PDP table)
> * Use PDP offset (bit 38:30) to get the value of gPDPE
>
> 3. To find out gPDE
> * Traverse nested page table using gPDPE to locate guest level-2 page (PD table)
> * Use PD offset (bit 29:21) to get the value of gPDE
>
> 4. To find out gPTE
> * Traverse nested page table using gPDE to locate guest level-1 page (PT table)
> * Use PT offset (bit 20:12) to get the value of gPTE
>
> 5. To find out gData
> * Traverse nested page table using gPTE to locate guest data page
> * Use physical page offset (bit 11:0) to get the data value
>
>
> -----Original Message-----
> From: xen-devel-bounces@lists.xen.org [mailto:xen-devel-bounces@lists.xen.org] On Behalf Of Huang2, Wei
> Sent: Thursday, April 12, 2012 4:35 PM
> To: Steven; Wang2, Wei; xen-devel@lists.xensource.com
> Subject: Re: [Xen-devel] Understanding AMD NPT in xen
>
> White page info is more accurate. The slides was a bit vague. Here are the steps, assuming that CPU doesn't have TLB:
>
> 1. To find out gPML4E
> * Traverse nested page table using gCR3 to locate guest level-4 page (PML4 table)
> * Use PML4 offset (bit 47:39) to get the value of gPML4E
> 2. To find out gPDPE
> * Traverse nested page table using gPML4E to locate guest level-3 page (PDP table)
> * Use PDP offset (bit 38:30) to get the value of gPDPE
> 3. To find out gPDE
> * Traverse nested page table using gPDPE to locate guest level-2 page (PD table)
> * Use PD offset (bit 29:21) to get the value of gPDE
> 4. To find out gPTE
> * Traverse nested page table using gPDE to locate guest level-1 page (PT table)
> * Use PT offset (bit 20:12) to get the value of gPTE
> 5. To find out gData
> * Traverse nested page table using gPTE to locate guest data page
> * Use physical page offset (bit 11:0) to get the data value
>
> TLB will accelerate this walking significantly.
>
> -Wei
>
> -----Original Message-----
> From: xen-devel-bounces@lists.xen.org [mailto:xen-devel-bounces@lists.xen.org] On Behalf Of Steven
> Sent: Thursday, April 12, 2012 12:06 PM
> To: Wang2, Wei; xen-devel@lists.xensource.com
> Subject: [Xen-devel] Understanding AMD NPT in xen
>
> Hi, Wei,
> I have read you slides in xen summit 2007 about NPT in AMD, "AMD
> Barcelona and Nested Paging Support in Xen".
> However, I have some question regarding the nested page walk in your slide 8.
>
> In your slide 8, the first step is to get gPA from get_PML4(gCR3,gVA).
> I assume that it use the [47:39] bit of gVA.
> However, in another AMD white paper, "AMD-VTM Nested Paging".
> http://developer.amd.com/assets/NPT-WP-1%201-final-TM.pdf
> In its figure 4, I saw that the first step is to translate gCR3 using
> nested page walk and then combine with the gVA[47:39] to read the
> table entry.
>
> These two documents look having different order of reading the guest
> page table. In the slides, it first get_PML4. But in the white paper,
> it first does nested page walk.
> I am wondering which one is true. Thanks.
>
> - ha
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-04-13 2:29 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-04-12 17:06 Understanding AMD NPT in xen Steven
2012-04-12 21:35 ` Huang2, Wei
[not found] ` <4400B41FB768044EA720935D0808176C090BCDDC@sausexdag02.amd.com>
2012-04-13 2:29 ` Steven
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.