[PATCH v1 0/2] New DRM fourcc codes needed by Video DMA Driver

[PATCH v1 0/2] New DRM fourcc codes needed by Video DMA Driver

[Jeffrey Mouroux]

This patch set is introduced to support a driver we are developing
for our new Video Framebuffer DMA IP, a DMA device that is "video format aware".
Clients need only specify memory layout information for a single plane
(i.e. luma) and then provide a video format code (e.g. YUV420) which will permit
for intelligent reads or writes (depending on the IP configuration) to host
memory with only a minimal set of video memory configuration data.

The IP supports a variety of 8-bit and 10-bit video formats, some of which
are not represented in the current DRM user api or framework.  This patch
set introduces these needed video format codes and updates the DRM
framework with the metadata required.

We've endeavored to follow the existing DRM conventions for the new
fourcc codes and, where no comparable examples were present
(e.g. Y8 and Y10), we adopted the V4L2 conventions.

The DMA driver requiring these updates is not being submitted as part of this
patch set as it is still undergoing final development.

We are submitting this patch series for review and comment with regard to
ensuring we haven't missed any required framework updates and/or in regards to
the choices we've made to the fourcc string values.

Jeffrey Mouroux (2):
  uapi: drm: Add fourcc codes needed by Xilinx Video IP
  drm: Update framework with new video formats

 drivers/gpu/drm/drm_fourcc.c  | 7 +++++++
 include/uapi/drm/drm_fourcc.h | 9 +++++++++
 2 files changed, 16 insertions(+)

-- 
1.9.1

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[PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

[Jeffrey Mouroux]

The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
support video memory formats that are not represented in the
current DRM fourcc library.  This patch adds those missing
fourcc codes.

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
---
 include/uapi/drm/drm_fourcc.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index ef20abb..3e80130 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -112,6 +112,14 @@
 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
 
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_AVUY		fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
+#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y little endian */
+#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
+
+/* Grey scale */
+#define DRM_FORMAT_Y8		fourcc_code('G', 'R', 'E', 'Y') /* 8  Greyscale	*/
+#define DRM_FORMAT_Y10		fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale	*/
 
 /*
  * 2 plane YCbCr
@@ -126,6 +134,7 @@
 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
+#define DRM_FORMAT_XV15		fourcc_code('X', 'V', '2', '0') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */
 
 /*
  * 3 plane YCbCr
-- 
1.9.1

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[PATCH v1 2/2] drm: Update framework with new video formats

[Jeffrey Mouroux]

The following new fourcc codes introduced in patch 514b144b2dd7 (uapi: drm:
New fourcc codes needed by Xilinx Video IP) to DRM framework:
* AVUY
* VUY888
* XVUY8888
* XVUY2101010
* Y8
* Y10
* XV15

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
---
 drivers/gpu/drm/drm_fourcc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 90d2cc8..951cebb 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -160,11 +160,18 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_NV61,		.depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1 },
 		{ .format = DRM_FORMAT_NV24,		.depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
 		{ .format = DRM_FORMAT_NV42,		.depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_XV15,		.depth = 0,  .num_planes = 2, .cpp = { 2, 3, 0 }, .hsub = 2, .vsub = 2 },
 		{ .format = DRM_FORMAT_YUYV,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
 		{ .format = DRM_FORMAT_YVYU,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
 		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
 		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
 		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_AVUY,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_VUY888,		.depth = 0,  .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_XVUY8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_XVUY2101010,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_Y8,		.depth = 0,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+		{ .format = DRM_FORMAT_Y10,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
 	};
 
 	unsigned int i;
-- 
1.9.1

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Re: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

[Philipp Zabel]

Hi Jeffrey,

On Fri, 2017-08-04 at 11:49 -0700, Jeffrey Mouroux wrote:
> The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
> support video memory formats that are not represented in the
> current DRM fourcc library.  This patch adds those missing
> fourcc codes.
> 
> Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..3e80130 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -112,6 +112,14 @@
>  #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>  
>  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_AVUY		fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
> +#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y little endian */
> +#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */
> +#define DRM_FORMAT_XVUY2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
> +
> +/* Grey scale */
> +#define DRM_FORMAT_Y8		fourcc_code('G', 'R', 'E', 'Y') /* 8  Greyscale	*/

That would be useful for me as well.

> +#define DRM_FORMAT_Y10		fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale	*/

It is not clear to me from the description, how this should be laid out
in memory. Is it padded to 16 bits? Packed?

>  /*
>   * 2 plane YCbCr
> @@ -126,6 +134,7 @@
>  #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> +#define DRM_FORMAT_XV15		fourcc_code('X', 'V', '2', '0') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */

Same here.

regards
Philipp

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RE: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

[Jeff Mouroux]

Hi Philipp,

Thanks for the reply.   Please see me comments inline:

-----Original Message-----
From: Philipp Zabel [mailto:p.zabel@pengutronix.de] 
Sent: Monday, August 07, 2017 8:14 AM
To: Jeff Mouroux <jmouroux@xilinx.com>
Cc: daniel.vetter@intel.com; jani.nikula@linux.intel.com; seanpaul@chromium.org; airlied@linux.ie; dri-devel@lists.freedesktop.org; Jeff Mouroux <jmouroux@xilinx.com>
Subject: Re: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

Hi Jeffrey,

On Fri, 2017-08-04 at 11:49 -0700, Jeffrey Mouroux wrote:
> The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
> support video memory formats that are not represented in the
> current DRM fourcc library.  This patch adds those missing
> fourcc codes.
> 
> Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index ef20abb..3e80130 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -112,6 +112,14 @@
>  #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>  
>  #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_AVUY		fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
> +#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y little endian */
> +#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */
> +#define DRM_FORMAT_XVUY2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
> +
> +/* Grey scale */
> +#define DRM_FORMAT_Y8		fourcc_code('G', 'R', 'E', 'Y') /* 8  Greyscale	*/

That would be useful for me as well.

> +#define DRM_FORMAT_Y10		fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale	*/

It is not clear to me from the description, how this should be laid out
in memory. Is it padded to 16 bits? Packed?
[Jeff Mouroux]  I expect this is 2:10:10:10 (i.e. x:Y2:Y1:Y0).   I can clarify in the comments for v2.

>  /*
>   * 2 plane YCbCr
> @@ -126,6 +134,7 @@
>  #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> +#define DRM_FORMAT_XV15		fourcc_code('X', 'V', '2', '0') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */

Same here.
[Jeff Mouroux] The chroma plane is described but I suppose the luma is what's missing.  The luma should work just like
Y10 (2:10:10:10 as in x:Y2:Y1:Y0).  I didn't want the comment string to be too long but can reference Y10 layout for luma
if that would help.

regards
Philipp

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Re: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

[David Lechner]

On 08/07/2017 10:13 AM, Philipp Zabel wrote:
> Hi Jeffrey,
> 
> On Fri, 2017-08-04 at 11:49 -0700, Jeffrey Mouroux wrote:
>> The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
>> support video memory formats that are not represented in the
>> current DRM fourcc library.  This patch adds those missing
>> fourcc codes.
>>
>> Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
>> ---
>>   include/uapi/drm/drm_fourcc.h | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index ef20abb..3e80130 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -112,6 +112,14 @@
>>   #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>>   
>>   #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>> +#define DRM_FORMAT_AVUY		fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
>> +#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y little endian */
>> +#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */
>> +#define DRM_FORMAT_XVUY2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
>> +
>> +/* Grey scale */
>> +#define DRM_FORMAT_Y8		fourcc_code('G', 'R', 'E', 'Y') /* 8  Greyscale	*/
> 
> That would be useful for me as well.

I'm also interested in 8-bit grayscale. I applied these patches then 
naively tried to add support for DRM_FORMAT_Y8 to a driver I am working on.

diff --git a/drivers/gpu/drm/tinydrm/st7586.c 
b/drivers/gpu/drm/tinydrm/st7586.c
index 1b39d3f..f6db7be 100644
--- a/drivers/gpu/drm/tinydrm/st7586.c
+++ b/drivers/gpu/drm/tinydrm/st7586.c
@@ -56,6 +56,34 @@

  static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 };

+static void st7586_gray8_to_gray332(u8 *dst, void *vaddr,
+                                   struct drm_framebuffer *fb,
+                                   struct drm_clip_rect *clip)
+{
...
+}
+
  static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr,
                                        struct drm_framebuffer *fb,
                                        struct drm_clip_rect *clip)
@@ -98,7 +126,14 @@ static int st7586_buf_copy(void *dst, struct 
drm_framebuffer *fb,
                         return ret;
         }

-       st7586_xrgb8888_to_gray332(dst, src, fb, clip);
+       switch(fb->format->format) {
+       case DRM_FORMAT_Y8:
+               st7586_gray8_to_gray332(dst, src, fb, clip);
+               break;
+       case DRM_FORMAT_XRGB8888:
+               st7586_xrgb8888_to_gray332(dst, src, fb, clip);
+               break;
+       }

         if (import_attach)
                 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
@@ -260,6 +295,7 @@ static void st7586_pipe_disable(struct 
drm_simple_display_pipe *pipe)
  }

  static const u32 st7586_formats[] = {
+       DRM_FORMAT_Y8,
         DRM_FORMAT_XRGB8888,
  };

@@ -290,7 +326,7 @@ static int st7586_init(struct device *dev, struct 
mipi_dbi *mipi,
         if (ret)
                 return ret;

-       tdev->drm->mode_config.preferred_depth = 32;
+       tdev->drm->mode_config.preferred_depth = 8;
         mipi->rotation = rotation;

         drm_mode_config_reset(tdev->drm);


But it just caused a crash. (Note: had to set fb.lockless_register_fb=1 
in the kernel command line to get stack trace.)


Console: switching to colour frame buffer device 22x16
Unable to handle kernel paging request at virtual address c4bd4158
pgd = c2e0c000
[c4bd4158] *pgd=c2dfd811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT ARM
Modules linked in: st7586(+) mipi_dbi tinydrm drm_kms_helper syscopyarea 
sysfill
rect sysimgblt fb_sys_fops ofpart drm backlight m25p80 spi_nor 
ti_ads7950 indust
rialio_triggered_buffer mtd da8xx kfifo_buf phy_generic pwm_beeper 
ohci_da8xx mu
sb_hdrc ohci_hcd usbcore pwm_tiehrpwm davinci_wdt phy_da8xx_usb 
pinctrl_da850_pu
pd rtc_omap leds_gpio led_class lego_ev3_battery industrialio tun 
libcomposite c
onfigfs udc_core usb_common autofs4
CPU: 0 PID: 126 Comm: systemd-udevd Tainted: G        W 
4.13.0-rc2-dlech-e
v3+ #486
Hardware name: Generic DA850/OMAP-L138/AM18x
task: c3afd4a0 task.stack: c2d36000
PC is at sys_imageblit+0x278/0x4c8 [sysimgblt]
LR is at 0xc4bd3f40
pc : [<bf1ca278>]    lr : [<c4bd3f40>]    psr: 20000013
sp : c2d37810  ip : 00000000  fp : c2d37864
r10: 00000008  r9 : 00000018  r8 : c4bd3f40
r7 : c2d26a42  r6 : 00000000  r5 : 00000007  r4 : 00000008
r3 : 00000010  r2 : c4bd4158  r1 : 000000b0  r0 : 00000000
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
Control: 0005317f  Table: c2e0c000  DAC: 00000051
Process systemd-udevd (pid: 126, stack limit = 0xc2d36190)
Stack: (0xc2d37810 to 0xc2d38000)
7800:                                     000002c8 000000b2 c4bd4158 
00000016
7820: 00000000 c2d26a42 c2d378e8 00000010 00000010 c4bd4158 bf1e6154 
c2d378e8
7840: c1882000 c1882e94 00000016 00000001 000000ff c3808000 c2d37884 
c2d37868
...
7fe0: bec338a8 bec33898 b6ec8610 b6da04d0 60000010 00000017 00000000 
00000000
Backtrace:
[<bf1ca000>] (sys_imageblit [sysimgblt]) from [<bf1e62bc>] 
(drm_fb_helper_sys_imageblit+0x1c/0x34 [drm_kms_helper])
  r10:c3808000 r9:000000ff r8:00000001 r7:00000016 r6:c1882e94 r5:c1882000
  r4:c2d378e8
[<bf1e62a0>] (drm_fb_helper_sys_imageblit [drm_kms_helper]) from 
[<c026697c>] (bit_putcs+0x26c/0x410)
  r5:c2d269be r4:00000000
[<c0266710>] (bit_putcs) from [<c0260464>] (fbcon_putcs+0xf4/0x12c)
  r10:00000007 r9:c0266710 r8:0000000e r7:00000016 r6:c1882e68 r5:c3808000
  r4:c1882000
[<c0260370>] (fbcon_putcs) from [<c0297f50>] (do_update_region+0x174/0x1bc)
  r10:00000016 r9:0000000e r8:c3808000 r7:c1882e68 r6:00000016 r5:c0260370
  r4:c1882e94
[<c0297ddc>] (do_update_region) from [<c0299490>] 
(redraw_screen+0x1dc/0x24c)
  r10:0000003f r9:00000000 r8:c0517e0c r7:00000001 r6:00000001 r5:00000000
  r4:c3808000
[<c02992b4>] (redraw_screen) from [<c029a0cc>] 
(do_bind_con_driver+0x2ac/0x3d4)
  r8:c0517e0c r7:00000001 r6:c06019c8 r5:00000000 r4:00000014
[<c0299e20>] (do_bind_con_driver) from [<c029a5bc>] 
(do_take_over_console+0x144/0x1c4)
  r10:00000001 r9:0000003e r8:00000000 r7:c06019e4 r6:00000000 r5:00000000
  r4:c048f8b4
[<c029a478>] (do_take_over_console) from [<c0263c44>] 
(do_fbcon_takeover+0x70/0xd8)
  r10:c188221c r9:c0601568 r8:c1882000 r7:00000000 r6:c2d37b80 r5:c0601568
  r4:c05d2c00
[<c0263bd4>] (do_fbcon_takeover) from [<c0264a20>] 
(fbcon_event_notify+0x8c4/0x920)
  r5:ffffffff r4:c05d2c00
[<c026415c>] (fbcon_event_notify) from [<c003a23c>] 
(notifier_call_chain+0x4c/0x8c)
  r10:c188221c r9:c05d2c80 r8:00000000 r7:00000005 r6:c2d37b80 r5:ffffffff
  r4:00000000
[<c003a1f0>] (notifier_call_chain) from [<c003a680>] 
(__blocking_notifier_call_chain+0x50/0x68)
  r9:c05d2c80 r8:c188200c r7:ffffffff r6:c2d37b80 r5:c05d2c70 r4:00000005
[<c003a630>] (__blocking_notifier_call_chain) from [<c003a6b8>] 
(blocking_notifier_call_chain+0x20/0x28)
  r7:c059d370 r6:00000000 r5:c1882000 r4:c059d370
[<c003a698>] (blocking_notifier_call_chain) from [<c0266edc>] 
(fb_notifier_call_chain+0x1c/0x24)
[<c0266ec0>] (fb_notifier_call_chain) from [<c0268dd0>] 
(register_framebuffer+0x18c/0x2a8)
[<c0268c44>] (register_framebuffer) from [<bf1e7ae4>] 
(__drm_fb_helper_initial_config_and_unlock+0x20c/0x3ac [drm_kms_helper])
  r10:00000001 r9:c18ffbe8 r8:c1882000 r7:00000000 r6:bf1ed66c r5:00000000
  r4:c2d9db40
[<bf1e78d8>] (__drm_fb_helper_initial_config_and_unlock 
[drm_kms_helper]) from [<bf1e81ec>] 
(drm_fb_helper_initial_config+0x38/0x40 [drm_kms_helper])
  r10:3e70d91c r9:00000019 r8:00000008 r7:bf2169f8 r6:c1879400 r5:00000008
  r4:c2d9db40
[<bf1e81b4>] (drm_fb_helper_initial_config [drm_kms_helper]) from 
[<bf1e8aa8>] (drm_fbdev_cma_init_with_funcs+0x7c/0x100 [drm_kms_helper])
  r5:00000000 r4:c2d9db40
[<bf1e8a2c>] (drm_fbdev_cma_init_with_funcs [drm_kms_helper]) from 
[<bf207180>] (devm_tinydrm_register+0x4c/0xb4 [tinydrm])
  r9:00000019 r8:c3acf400 r7:00000008 r6:c3b96010 r5:00000000 r4:c1879400
[<bf207134>] (devm_tinydrm_register [tinydrm]) from [<bf216904>] 
(st7586_probe+0x164/0x238 [st7586])
  r9:00000019 r8:bf216f98 r7:00000000 r6:c3b96010 r5:c3acf400 r4:00000000
[<bf2167a0>] (st7586_probe [st7586]) from [<c02d5624>] 
(spi_drv_probe+0x74/0xa0)
  r6:00000000 r5:bf216f88 r4:c3acf400
[<c02d55b0>] (spi_drv_probe) from [<c02b2c3c>] 
(driver_probe_device+0x23c/0x300)
  r5:c0602a4c r4:c3acf400
[<c02b2a00>] (driver_probe_device) from [<c02b2dc0>] 
(__driver_attach+0xc0/0xc4)
  r9:bf216fe0 r8:00000001 r7:00000000 r6:c3acf434 r5:bf216f98 r4:c3acf400
[<c02b2d00>] (__driver_attach) from [<c02b0ec0>] 
(bus_for_each_dev+0x74/0xa4)
  r7:00000000 r6:c02b2d00 r5:bf216f98 r4:00000000
[<c02b0e4c>] (bus_for_each_dev) from [<c02b25cc>] (driver_attach+0x20/0x28)
  r6:c05d80d8 r5:c2f47720 r4:bf216f98
[<c02b25ac>] (driver_attach) from [<c02b2190>] (bus_add_driver+0x190/0x218)
[<c02b2000>] (bus_add_driver) from [<c02b3784>] (driver_register+0x80/0x100)
  r7:00000000 r6:bf219000 r5:00000001 r4:bf216f98
[<c02b3704>] (driver_register) from [<c02d5560>] 
(__spi_register_driver+0x50/0x64)
  r5:00000001 r4:ffffe000
[<c02d5510>] (__spi_register_driver) from [<bf219018>] 
(st7586_spi_driver_init+0x18/0x24 [st7586])
[<bf219000>] (st7586_spi_driver_init [st7586]) from [<c00096cc>] 
(do_one_initcall+0x44/0x180)
[<c0009688>] (do_one_initcall) from [<c0082308>] (do_init_module+0x60/0x1b4)
  r9:bf216fe0 r8:00000001 r7:c18f2700 r6:c2d33060 r5:00000001 r4:bf216fe0
[<c00822a8>] (do_init_module) from [<c0081378>] (load_module+0x1d10/0x2168)
  r6:c18f2708 r5:00000001 r4:c2d37f40
[<c007f668>] (load_module) from [<c00819e0>] (SyS_finit_module+0xac/0xc0)
  r10:00000080 r9:c2d36000 r8:c000a5e4 r7:0000017b r6:b6ed13a0 r5:00000017
  r4:00000000
[<c0081934>] (SyS_finit_module) from [<c000a5bc>] 
(__sys_trace_return+0x0/0x10)
  r6:00000000 r5:004665a0 r4:a7d0f000
Code: e3530000 e5921008 151b2030 051b0034 (15920000)
systemd-journald[74]: /dev/kmsg buffer overrun, some messages lost.
---[ end trace dff175813c02c6bb ]---


Looking at the code, drm_fb_helper* looks like it assumes that 8bpp 
means the memory is an indexed color table format. So, there will be 
some work needed to make drm_fb_helper* grayscale aware.



> 
>> +#define DRM_FORMAT_Y10		fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale	*/
> 
> It is not clear to me from the description, how this should be laid out
> in memory. Is it padded to 16 bits? Packed?
> 
>>   /*
>>    * 2 plane YCbCr
>> @@ -126,6 +134,7 @@
>>   #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
>>   #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>>   #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>> +#define DRM_FORMAT_XV15		fourcc_code('X', 'V', '2', '0') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */
> 
> Same here.
> 
> regards
> Philipp
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 

_______________________________________________
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RE: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

[Jeff Mouroux]

Hi David,

Thanks for the feedback.   I'm not as familiar with the FB Dev infrastructure.   Thanks for bringing this to my attention.  

Jeff

-----Original Message-----
From: David Lechner [mailto:david@lechnology.com] 
Sent: Monday, August 07, 2017 2:17 PM
To: Philipp Zabel <p.zabel@pengutronix.de>; Jeff Mouroux <jmouroux@xilinx.com>
Cc: dri-devel@lists.freedesktop.org; daniel.vetter@intel.com; Jeff Mouroux <jmouroux@xilinx.com>; Noralf Trønnes <noralf@tronnes.org>
Subject: Re: [PATCH v1 1/2] uapi: drm: Add fourcc codes needed by Xilinx Video IP

On 08/07/2017 10:13 AM, Philipp Zabel wrote:
> Hi Jeffrey,
> 
> On Fri, 2017-08-04 at 11:49 -0700, Jeffrey Mouroux wrote:
>> The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP support 
>> video memory formats that are not represented in the current DRM 
>> fourcc library.  This patch adds those missing fourcc codes.
>>
>> Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
>> ---
>>   include/uapi/drm/drm_fourcc.h | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h 
>> b/include/uapi/drm/drm_fourcc.h index ef20abb..3e80130 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -112,6 +112,14 @@
>>   #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>>   
>>   #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>> +#define DRM_FORMAT_AVUY		fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
>> +#define DRM_FORMAT_VUY888	fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y little endian */
>> +#define DRM_FORMAT_XVUY8888	fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */
>> +#define DRM_FORMAT_XVUY2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
>> +
>> +/* Grey scale */
>> +#define DRM_FORMAT_Y8		fourcc_code('G', 'R', 'E', 'Y') /* 8  Greyscale	*/
> 
> That would be useful for me as well.

I'm also interested in 8-bit grayscale. I applied these patches then naively tried to add support for DRM_FORMAT_Y8 to a driver I am working on.

diff --git a/drivers/gpu/drm/tinydrm/st7586.c
b/drivers/gpu/drm/tinydrm/st7586.c
index 1b39d3f..f6db7be 100644
--- a/drivers/gpu/drm/tinydrm/st7586.c
+++ b/drivers/gpu/drm/tinydrm/st7586.c
@@ -56,6 +56,34 @@

  static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 };

+static void st7586_gray8_to_gray332(u8 *dst, void *vaddr,
+                                   struct drm_framebuffer *fb,
+                                   struct drm_clip_rect *clip) {
...
+}
+
  static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr,
                                        struct drm_framebuffer *fb,
                                        struct drm_clip_rect *clip) @@ -98,7 +126,14 @@ static int st7586_buf_copy(void *dst, struct drm_framebuffer *fb,
                         return ret;
         }

-       st7586_xrgb8888_to_gray332(dst, src, fb, clip);
+       switch(fb->format->format) {
+       case DRM_FORMAT_Y8:
+               st7586_gray8_to_gray332(dst, src, fb, clip);
+               break;
+       case DRM_FORMAT_XRGB8888:
+               st7586_xrgb8888_to_gray332(dst, src, fb, clip);
+               break;
+       }

         if (import_attach)
                 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
@@ -260,6 +295,7 @@ static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe)
  }

  static const u32 st7586_formats[] = {
+       DRM_FORMAT_Y8,
         DRM_FORMAT_XRGB8888,
  };

@@ -290,7 +326,7 @@ static int st7586_init(struct device *dev, struct mipi_dbi *mipi,
         if (ret)
                 return ret;

-       tdev->drm->mode_config.preferred_depth = 32;
+       tdev->drm->mode_config.preferred_depth = 8;
         mipi->rotation = rotation;

         drm_mode_config_reset(tdev->drm);


But it just caused a crash. (Note: had to set fb.lockless_register_fb=1 in the kernel command line to get stack trace.)


Console: switching to colour frame buffer device 22x16
Unable to handle kernel paging request at virtual address c4bd4158
pgd = c2e0c000
[c4bd4158] *pgd=c2dfd811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT ARM
Modules linked in: st7586(+) mipi_dbi tinydrm drm_kms_helper syscopyarea 
sysfill
rect sysimgblt fb_sys_fops ofpart drm backlight m25p80 spi_nor 
ti_ads7950 indust
rialio_triggered_buffer mtd da8xx kfifo_buf phy_generic pwm_beeper 
ohci_da8xx mu
sb_hdrc ohci_hcd usbcore pwm_tiehrpwm davinci_wdt phy_da8xx_usb 
pinctrl_da850_pu
pd rtc_omap leds_gpio led_class lego_ev3_battery industrialio tun 
libcomposite c
onfigfs udc_core usb_common autofs4
CPU: 0 PID: 126 Comm: systemd-udevd Tainted: G        W 
4.13.0-rc2-dlech-e
v3+ #486
Hardware name: Generic DA850/OMAP-L138/AM18x
task: c3afd4a0 task.stack: c2d36000
PC is at sys_imageblit+0x278/0x4c8 [sysimgblt]
LR is at 0xc4bd3f40
pc : [<bf1ca278>]    lr : [<c4bd3f40>]    psr: 20000013
sp : c2d37810  ip : 00000000  fp : c2d37864
r10: 00000008  r9 : 00000018  r8 : c4bd3f40
r7 : c2d26a42  r6 : 00000000  r5 : 00000007  r4 : 00000008
r3 : 00000010  r2 : c4bd4158  r1 : 000000b0  r0 : 00000000
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
Control: 0005317f  Table: c2e0c000  DAC: 00000051
Process systemd-udevd (pid: 126, stack limit = 0xc2d36190)
Stack: (0xc2d37810 to 0xc2d38000)
7800:                                     000002c8 000000b2 c4bd4158 
00000016
7820: 00000000 c2d26a42 c2d378e8 00000010 00000010 c4bd4158 bf1e6154 
c2d378e8
7840: c1882000 c1882e94 00000016 00000001 000000ff c3808000 c2d37884 
c2d37868
...
7fe0: bec338a8 bec33898 b6ec8610 b6da04d0 60000010 00000017 00000000 
00000000
Backtrace:
[<bf1ca000>] (sys_imageblit [sysimgblt]) from [<bf1e62bc>] 
(drm_fb_helper_sys_imageblit+0x1c/0x34 [drm_kms_helper])
  r10:c3808000 r9:000000ff r8:00000001 r7:00000016 r6:c1882e94 r5:c1882000
  r4:c2d378e8
[<bf1e62a0>] (drm_fb_helper_sys_imageblit [drm_kms_helper]) from 
[<c026697c>] (bit_putcs+0x26c/0x410)
  r5:c2d269be r4:00000000
[<c0266710>] (bit_putcs) from [<c0260464>] (fbcon_putcs+0xf4/0x12c)
  r10:00000007 r9:c0266710 r8:0000000e r7:00000016 r6:c1882e68 r5:c3808000
  r4:c1882000
[<c0260370>] (fbcon_putcs) from [<c0297f50>] (do_update_region+0x174/0x1bc)
  r10:00000016 r9:0000000e r8:c3808000 r7:c1882e68 r6:00000016 r5:c0260370
  r4:c1882e94
[<c0297ddc>] (do_update_region) from [<c0299490>] 
(redraw_screen+0x1dc/0x24c)
  r10:0000003f r9:00000000 r8:c0517e0c r7:00000001 r6:00000001 r5:00000000
  r4:c3808000
[<c02992b4>] (redraw_screen) from [<c029a0cc>] 
(do_bind_con_driver+0x2ac/0x3d4)
  r8:c0517e0c r7:00000001 r6:c06019c8 r5:00000000 r4:00000014
[<c0299e20>] (do_bind_con_driver) from [<c029a5bc>] 
(do_take_over_console+0x144/0x1c4)
  r10:00000001 r9:0000003e r8:00000000 r7:c06019e4 r6:00000000 r5:00000000
  r4:c048f8b4
[<c029a478>] (do_take_over_console) from [<c0263c44>] 
(do_fbcon_takeover+0x70/0xd8)
  r10:c188221c r9:c0601568 r8:c1882000 r7:00000000 r6:c2d37b80 r5:c0601568
  r4:c05d2c00
[<c0263bd4>] (do_fbcon_takeover) from [<c0264a20>] 
(fbcon_event_notify+0x8c4/0x920)
  r5:ffffffff r4:c05d2c00
[<c026415c>] (fbcon_event_notify) from [<c003a23c>] 
(notifier_call_chain+0x4c/0x8c)
  r10:c188221c r9:c05d2c80 r8:00000000 r7:00000005 r6:c2d37b80 r5:ffffffff
  r4:00000000
[<c003a1f0>] (notifier_call_chain) from [<c003a680>] 
(__blocking_notifier_call_chain+0x50/0x68)
  r9:c05d2c80 r8:c188200c r7:ffffffff r6:c2d37b80 r5:c05d2c70 r4:00000005
[<c003a630>] (__blocking_notifier_call_chain) from [<c003a6b8>] 
(blocking_notifier_call_chain+0x20/0x28)
  r7:c059d370 r6:00000000 r5:c1882000 r4:c059d370
[<c003a698>] (blocking_notifier_call_chain) from [<c0266edc>] 
(fb_notifier_call_chain+0x1c/0x24)
[<c0266ec0>] (fb_notifier_call_chain) from [<c0268dd0>] 
(register_framebuffer+0x18c/0x2a8)
[<c0268c44>] (register_framebuffer) from [<bf1e7ae4>] 
(__drm_fb_helper_initial_config_and_unlock+0x20c/0x3ac [drm_kms_helper])
  r10:00000001 r9:c18ffbe8 r8:c1882000 r7:00000000 r6:bf1ed66c r5:00000000
  r4:c2d9db40
[<bf1e78d8>] (__drm_fb_helper_initial_config_and_unlock 
[drm_kms_helper]) from [<bf1e81ec>] 
(drm_fb_helper_initial_config+0x38/0x40 [drm_kms_helper])
  r10:3e70d91c r9:00000019 r8:00000008 r7:bf2169f8 r6:c1879400 r5:00000008
  r4:c2d9db40
[<bf1e81b4>] (drm_fb_helper_initial_config [drm_kms_helper]) from 
[<bf1e8aa8>] (drm_fbdev_cma_init_with_funcs+0x7c/0x100 [drm_kms_helper])
  r5:00000000 r4:c2d9db40
[<bf1e8a2c>] (drm_fbdev_cma_init_with_funcs [drm_kms_helper]) from 
[<bf207180>] (devm_tinydrm_register+0x4c/0xb4 [tinydrm])
  r9:00000019 r8:c3acf400 r7:00000008 r6:c3b96010 r5:00000000 r4:c1879400
[<bf207134>] (devm_tinydrm_register [tinydrm]) from [<bf216904>] 
(st7586_probe+0x164/0x238 [st7586])
  r9:00000019 r8:bf216f98 r7:00000000 r6:c3b96010 r5:c3acf400 r4:00000000
[<bf2167a0>] (st7586_probe [st7586]) from [<c02d5624>] 
(spi_drv_probe+0x74/0xa0)
  r6:00000000 r5:bf216f88 r4:c3acf400
[<c02d55b0>] (spi_drv_probe) from [<c02b2c3c>] 
(driver_probe_device+0x23c/0x300)
  r5:c0602a4c r4:c3acf400
[<c02b2a00>] (driver_probe_device) from [<c02b2dc0>] 
(__driver_attach+0xc0/0xc4)
  r9:bf216fe0 r8:00000001 r7:00000000 r6:c3acf434 r5:bf216f98 r4:c3acf400
[<c02b2d00>] (__driver_attach) from [<c02b0ec0>] 
(bus_for_each_dev+0x74/0xa4)
  r7:00000000 r6:c02b2d00 r5:bf216f98 r4:00000000
[<c02b0e4c>] (bus_for_each_dev) from [<c02b25cc>] (driver_attach+0x20/0x28)
  r6:c05d80d8 r5:c2f47720 r4:bf216f98
[<c02b25ac>] (driver_attach) from [<c02b2190>] (bus_add_driver+0x190/0x218)
[<c02b2000>] (bus_add_driver) from [<c02b3784>] (driver_register+0x80/0x100)
  r7:00000000 r6:bf219000 r5:00000001 r4:bf216f98
[<c02b3704>] (driver_register) from [<c02d5560>] 
(__spi_register_driver+0x50/0x64)
  r5:00000001 r4:ffffe000
[<c02d5510>] (__spi_register_driver) from [<bf219018>] 
(st7586_spi_driver_init+0x18/0x24 [st7586])
[<bf219000>] (st7586_spi_driver_init [st7586]) from [<c00096cc>] 
(do_one_initcall+0x44/0x180)
[<c0009688>] (do_one_initcall) from [<c0082308>] (do_init_module+0x60/0x1b4)
  r9:bf216fe0 r8:00000001 r7:c18f2700 r6:c2d33060 r5:00000001 r4:bf216fe0
[<c00822a8>] (do_init_module) from [<c0081378>] (load_module+0x1d10/0x2168)
  r6:c18f2708 r5:00000001 r4:c2d37f40
[<c007f668>] (load_module) from [<c00819e0>] (SyS_finit_module+0xac/0xc0)
  r10:00000080 r9:c2d36000 r8:c000a5e4 r7:0000017b r6:b6ed13a0 r5:00000017
  r4:00000000
[<c0081934>] (SyS_finit_module) from [<c000a5bc>] 
(__sys_trace_return+0x0/0x10)
  r6:00000000 r5:004665a0 r4:a7d0f000
Code: e3530000 e5921008 151b2030 051b0034 (15920000)
systemd-journald[74]: /dev/kmsg buffer overrun, some messages lost.
---[ end trace dff175813c02c6bb ]---


Looking at the code, drm_fb_helper* looks like it assumes that 8bpp 
means the memory is an indexed color table format. So, there will be 
some work needed to make drm_fb_helper* grayscale aware.



> 
>> +#define DRM_FORMAT_Y10		fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale	*/
> 
> It is not clear to me from the description, how this should be laid out
> in memory. Is it padded to 16 bits? Packed?
> 
>>   /*
>>    * 2 plane YCbCr
>> @@ -126,6 +134,7 @@
>>   #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
>>   #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>>   #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>> +#define DRM_FORMAT_XV15		fourcc_code('X', 'V', '2', '0') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */
> 
> Same here.
> 
> regards
> Philipp
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 

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