* [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
2022-09-08 8:57 [PATCH v1] 1: Adding rngb entry in imx6ull device tree Kshitiz Varshney
@ 2022-09-08 8:57 ` Kshitiz Varshney
2022-09-08 18:19 ` Simon Glass
2022-09-08 8:57 ` [PATCH v1] 3: Added dcp_rng driver device binding code Kshitiz Varshney
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Kshitiz Varshney @ 2022-09-08 8:57 UTC (permalink / raw)
To: u-boot, Horia Geanta, Pankaj Gupta, Varun Sethi, Gaurav Jain,
Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra, Ye Li,
Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Kshitiz
From: Kshitiz <kshitiz.varshney@nxp.com>
This commit introduces Random number generator to uboot. It uses DCP
driver for number generation.
RNG driver can be invoked by using below command on uboot prompt:-
rng <number of bytes>
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
drivers/crypto/fsl/Kconfig | 10 ++
drivers/crypto/fsl/Makefile | 1 +
drivers/crypto/fsl/dcp_rng.c | 184 +++++++++++++++++++++++++++++++++++
3 files changed, 195 insertions(+)
create mode 100644 drivers/crypto/fsl/dcp_rng.c
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 702d204a3d..da5955e31d 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -96,3 +96,13 @@ config RNG_SELF_TEST
must be run before running any RNG based crypto implementation.
endif
+
+config FSL_DCP_RNG
+ bool "Enable Random Number Generator support"
+ depends on DM_RNG
+ default n
+ help
+ Enable support for the hardware based random number generator
+ module of the DCP.It uses the True Random Number Generator (TRNG)
+ and a Pseudo-Random Number Generator (PRNG) to achieve a true
+ randomness and cryptographic strength.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 926300e2ab..c653208d23 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
+obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o
diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
new file mode 100644
index 0000000000..a797710c2e
--- /dev/null
+++ b/drivers/crypto/fsl/dcp_rng.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
+ * Copyright 2022 NXP
+ *
+ * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <rng.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <dm/root.h>
+
+#define DCP_RNG_MAX_FIFO_STORE_SIZE 4
+#define RNGC_VER_ID 0x0000
+#define RNGC_COMMAND 0x0004
+#define RNGC_CONTROL 0x0008
+#define RNGC_STATUS 0x000C
+#define RNGC_ERROR 0x0010
+#define RNGC_FIFO 0x0014
+
+/* the fields in the ver id register */
+#define RNGC_TYPE_SHIFT 28
+
+/* the rng_type field */
+#define RNGC_TYPE_RNGB 0x1
+#define RNGC_TYPE_RNGC 0x2
+
+#define RNGC_CMD_CLR_ERR 0x00000020
+#define RNGC_CMD_SEED 0x00000002
+
+#define RNGC_CTRL_AUTO_SEED 0x00000010
+
+#define RNGC_STATUS_ERROR 0x00010000
+#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
+#define RNGC_STATUS_SEED_DONE 0x00000020
+#define RNGC_STATUS_ST_DONE 0x00000010
+
+#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
+
+#define RNGC_TIMEOUT 3000000U /* 3 sec */
+
+struct imx_rngc {
+ unsigned long base;
+};
+
+static int rngc_read(struct udevice *dev, void *data, size_t len)
+{
+ struct imx_rngc *rngc = dev_get_priv(dev);
+ u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
+ u32 status, level;
+ size_t size;
+
+ while (len) {
+ status = readl(rngc->base + RNGC_STATUS);
+
+ /* is there some error while reading this random number? */
+ if (status & RNGC_STATUS_ERROR)
+ break;
+ /* how many random numbers are in FIFO? [0-16] */
+ level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+ RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+ if (level) {
+ /* retrieve a random number from FIFO */
+ *(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
+ size = min(len, sizeof(u32));
+ memcpy(data, buffer, size);
+ data += size;
+ len -= size;
+ }
+ }
+
+ return len ? -EIO : 0;
+}
+
+static int rngc_init(struct imx_rngc *rngc)
+{
+ u32 cmd, ctrl, status, err_reg = 0;
+ unsigned long long timeval = 0;
+ unsigned long long timeout = RNGC_TIMEOUT;
+
+ /* clear error */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+ /* create seed, repeat while there is some statistical error */
+ do {
+ /* seed creation */
+ cmd = readl(rngc->base + RNGC_COMMAND);
+ writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+ udelay(1);
+ timeval += 1;
+
+ status = readl(rngc->base + RNGC_STATUS);
+ err_reg = readl(rngc->base + RNGC_ERROR);
+
+ if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
+ break;
+
+ if (timeval > timeout) {
+ debug("rngc timed out\n");
+ return -ETIMEDOUT;
+ }
+ } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
+
+ if (err_reg)
+ return -EIO;
+
+ /*
+ * enable automatic seeding, the rngc creates a new seed automatically
+ * after serving 2^20 random 160-bit words
+ */
+ ctrl = readl(rngc->base + RNGC_CONTROL);
+ ctrl |= RNGC_CTRL_AUTO_SEED;
+ writel(ctrl, rngc->base + RNGC_CONTROL);
+ return 0;
+}
+
+static int rngc_probe(struct udevice *dev)
+{
+ struct imx_rngc *rngc = dev_get_priv(dev);
+ fdt_addr_t addr;
+ u32 ver_id;
+ u8 rng_type;
+ int ret;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ rngc->base = addr;
+ ver_id = readl(rngc->base + RNGC_VER_ID);
+ rng_type = ver_id >> RNGC_TYPE_SHIFT;
+ /*
+ * This driver supports only RNGC and RNGB. (There's a different
+ * driver for RNGA.)
+ */
+ if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = rngc_init(rngc);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ printf("%s error = %d\n", __func__, ret);
+ return ret;
+}
+
+static const struct dm_rng_ops rngc_ops = {
+ .read = rngc_read,
+};
+
+static const struct udevice_id rngc_dt_ids[] = {
+ { .compatible = "fsl,imx25-rngb" },
+ { }
+};
+
+U_BOOT_DRIVER(dcp_rng) = {
+ .name = "dcp_rng",
+ .id = UCLASS_RNG,
+ .of_match = rngc_dt_ids,
+ .ops = &rngc_ops,
+ .probe = rngc_probe,
+ .priv_auto = sizeof(struct imx_rngc),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
2022-09-08 8:57 ` [PATCH v1] 2: Uboot RNG Driver using Data Co-processor Kshitiz Varshney
@ 2022-09-08 18:19 ` Simon Glass
2022-09-08 19:29 ` Heinrich Schuchardt
2022-12-21 11:06 ` Kshitiz Varshney
0 siblings, 2 replies; 15+ messages in thread
From: Simon Glass @ 2022-09-08 18:19 UTC (permalink / raw)
To: Kshitiz Varshney
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Heinrich Schuchardt, Stefano Babic, Fabio Estevam,
Peng Fan
Hi Kshitiz,
On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> This commit introduces Random number generator to uboot. It uses DCP
> driver for number generation.
> RNG driver can be invoked by using below command on uboot prompt:-
> rng <number of bytes>
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> drivers/crypto/fsl/Kconfig | 10 ++
> drivers/crypto/fsl/Makefile | 1 +
> drivers/crypto/fsl/dcp_rng.c | 184 +++++++++++++++++++++++++++++++++++
> 3 files changed, 195 insertions(+)
> create mode 100644 drivers/crypto/fsl/dcp_rng.c
Reviewed-by: Simon Glass <sjg@chromium.org>
but please see below
>
> diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
> index 702d204a3d..da5955e31d 100644
> --- a/drivers/crypto/fsl/Kconfig
> +++ b/drivers/crypto/fsl/Kconfig
> @@ -96,3 +96,13 @@ config RNG_SELF_TEST
> must be run before running any RNG based crypto implementation.
>
> endif
> +
> +config FSL_DCP_RNG
> + bool "Enable Random Number Generator support"
> + depends on DM_RNG
> + default n
> + help
> + Enable support for the hardware based random number generator
> + module of the DCP.It uses the True Random Number Generator (TRNG)
Space before It
> + and a Pseudo-Random Number Generator (PRNG) to achieve a true
> + randomness and cryptographic strength.
> diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
> index 926300e2ab..c653208d23 100644
> --- a/drivers/crypto/fsl/Makefile
> +++ b/drivers/crypto/fsl/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
> obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
> obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
> obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
> +obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
> obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
> obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
> obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o
> diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
> new file mode 100644
> index 0000000000..a797710c2e
> --- /dev/null
> +++ b/drivers/crypto/fsl/dcp_rng.c
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * RNG driver for Freescale RNGC
> + *
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
> + * Copyright 2022 NXP
> + *
> + * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
> + */
> +
> +#include <asm/cache.h>
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <rng.h>
> +#include <linux/kernel.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <dm/root.h>
Should be:
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <rng.h>
> +#include <asm/cache.h>
> +#include <asm/io.h>
> +#include <dm/root.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +
> +#define DCP_RNG_MAX_FIFO_STORE_SIZE 4
> +#define RNGC_VER_ID 0x0000
> +#define RNGC_COMMAND 0x0004
> +#define RNGC_CONTROL 0x0008
> +#define RNGC_STATUS 0x000C
> +#define RNGC_ERROR 0x0010
> +#define RNGC_FIFO 0x0014
> +
> +/* the fields in the ver id register */
> +#define RNGC_TYPE_SHIFT 28
> +
> +/* the rng_type field */
> +#define RNGC_TYPE_RNGB 0x1
> +#define RNGC_TYPE_RNGC 0x2
> +
> +#define RNGC_CMD_CLR_ERR 0x00000020
> +#define RNGC_CMD_SEED 0x00000002
> +
> +#define RNGC_CTRL_AUTO_SEED 0x00000010
> +
> +#define RNGC_STATUS_ERROR 0x00010000
> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
> +#define RNGC_STATUS_SEED_DONE 0x00000020
> +#define RNGC_STATUS_ST_DONE 0x00000010
Why all the leading zeroes?
> +
> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
> +
> +#define RNGC_TIMEOUT 3000000U /* 3 sec */
> +
> +struct imx_rngc {
Normally the priv data should have a _priv suffix.
> + unsigned long base;
> +};
> +
> +static int rngc_read(struct udevice *dev, void *data, size_t len)
> +{
> + struct imx_rngc *rngc = dev_get_priv(dev);
Normally the var should be called priv
> + u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
> + u32 status, level;
> + size_t size;
> +
> + while (len) {
> + status = readl(rngc->base + RNGC_STATUS);
> +
> + /* is there some error while reading this random number? */
> + if (status & RNGC_STATUS_ERROR)
> + break;
> + /* how many random numbers are in FIFO? [0-16] */
> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
> +
> + if (level) {
> + /* retrieve a random number from FIFO */
> + *(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
> + size = min(len, sizeof(u32));
> + memcpy(data, buffer, size);
> + data += size;
> + len -= size;
> + }
> + }
> +
> + return len ? -EIO : 0;
> +}
> +
> +static int rngc_init(struct imx_rngc *rngc)
> +{
> + u32 cmd, ctrl, status, err_reg = 0;
> + unsigned long long timeval = 0;
> + unsigned long long timeout = RNGC_TIMEOUT;
> +
> + /* clear error */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
> +
> + /* create seed, repeat while there is some statistical error */
> + do {
> + /* seed creation */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
> +
> + udelay(1);
> + timeval += 1;
> +
> + status = readl(rngc->base + RNGC_STATUS);
> + err_reg = readl(rngc->base + RNGC_ERROR);
> +
> + if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
> + break;
> +
> + if (timeval > timeout) {
> + debug("rngc timed out\n");
> + return -ETIMEDOUT;
> + }
> + } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
> +
> + if (err_reg)
> + return -EIO;
> +
> + /*
> + * enable automatic seeding, the rngc creates a new seed automatically
> + * after serving 2^20 random 160-bit words
> + */
> + ctrl = readl(rngc->base + RNGC_CONTROL);
> + ctrl |= RNGC_CTRL_AUTO_SEED;
> + writel(ctrl, rngc->base + RNGC_CONTROL);
setbits_le32(rngc->base + RNGC_CONTROL, RNGC_CTRL_AUTO_SEED);
> + return 0;
> +}
> +
> +static int rngc_probe(struct udevice *dev)
> +{
> + struct imx_rngc *rngc = dev_get_priv(dev);
> + fdt_addr_t addr;
> + u32 ver_id;
> + u8 rng_type;
> + int ret;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE) {
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + rngc->base = addr;
> + ver_id = readl(rngc->base + RNGC_VER_ID);
> + rng_type = ver_id >> RNGC_TYPE_SHIFT;
> + /*
> + * This driver supports only RNGC and RNGB. (There's a different
> + * driver for RNGA.)
> + */
> + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ret = rngc_init(rngc);
> + if (ret)
> + goto err;
> +
> + return 0;
> +
> +err:
> + printf("%s error = %d\n", __func__, ret);
> + return ret;
> +}
> +
> +static const struct dm_rng_ops rngc_ops = {
> + .read = rngc_read,
> +};
> +
> +static const struct udevice_id rngc_dt_ids[] = {
> + { .compatible = "fsl,imx25-rngb" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dcp_rng) = {
> + .name = "dcp_rng",
> + .id = UCLASS_RNG,
> + .of_match = rngc_dt_ids,
> + .ops = &rngc_ops,
> + .probe = rngc_probe,
> + .priv_auto = sizeof(struct imx_rngc),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> --
> 2.25.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
2022-09-08 18:19 ` Simon Glass
@ 2022-09-08 19:29 ` Heinrich Schuchardt
2022-12-21 11:11 ` [EXT] " Kshitiz Varshney
2022-12-21 11:06 ` Kshitiz Varshney
1 sibling, 1 reply; 15+ messages in thread
From: Heinrich Schuchardt @ 2022-09-08 19:29 UTC (permalink / raw)
To: Kshitiz Varshney
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Stefano Babic, Fabio Estevam, Peng Fan, Sughosh Ganu,
Simon Glass
On 9/8/22 20:19, Simon Glass wrote:
> Hi Kshitiz,
>
> On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>>
>> From: Kshitiz <kshitiz.varshney@nxp.com>
>>
>> This commit introduces Random number generator to uboot. It uses DCP
>> driver for number generation.
>> RNG driver can be invoked by using below command on uboot prompt:-
>> rng <number of bytes>
>>
>> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
CC the maintainer for RNG Sughosh Ganu <sughosh.ganu@linaro.org>.
>> Reviewed-by: Ye Li <ye.li@nxp.com>
>> ---
>> drivers/crypto/fsl/Kconfig | 10 ++
>> drivers/crypto/fsl/Makefile | 1 +
>> drivers/crypto/fsl/dcp_rng.c | 184 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 195 insertions(+)
>> create mode 100644 drivers/crypto/fsl/dcp_rng.c
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> but please see below
>
>>
>> diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
>> index 702d204a3d..da5955e31d 100644
>> --- a/drivers/crypto/fsl/Kconfig
>> +++ b/drivers/crypto/fsl/Kconfig
>> @@ -96,3 +96,13 @@ config RNG_SELF_TEST
>> must be run before running any RNG based crypto implementation.
>>
>> endif
>> +
>> +config FSL_DCP_RNG
>> + bool "Enable Random Number Generator support"
>> + depends on DM_RNG
>> + default n
>> + help
>> + Enable support for the hardware based random number generator
>> + module of the DCP.It uses the True Random Number Generator (TRNG)
Please, use the same indentation as the other Kconfig entries in this
file: Add two space in each line of the help text.
>
> Space before It
>
>> + and a Pseudo-Random Number Generator (PRNG) to achieve a true
>> + randomness and cryptographic strength.
>> diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
>> index 926300e2ab..c653208d23 100644
>> --- a/drivers/crypto/fsl/Makefile
>> +++ b/drivers/crypto/fsl/Makefile
>> @@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
>> obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
>> obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
>> obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
>> +obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
>> obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
>> obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
>> obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o
>> diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
>> new file mode 100644
>> index 0000000000..a797710c2e
>> --- /dev/null
>> +++ b/drivers/crypto/fsl/dcp_rng.c
>> @@ -0,0 +1,184 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * RNG driver for Freescale RNGC
>> + *
>> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
>> + * Copyright 2022 NXP
>> + *
>> + * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
>> + */
>> +
>> +#include <asm/cache.h>
>> +#include <common.h>
>> +#include <cpu_func.h>
>> +#include <dm.h>
>> +#include <rng.h>
>> +#include <linux/kernel.h>
>> +#include <linux/delay.h>
>> +#include <asm/io.h>
>> +#include <dm/root.h>
>
> Should be:
>
>> +#include <common.h>
>> +#include <cpu_func.h>
>> +#include <dm.h>
>> +#include <rng.h>
>> +#include <asm/cache.h>
>> +#include <asm/io.h>
>> +#include <dm/root.h>
>> +#include <linux/delay.h>
>> +#include <linux/kernel.h>
>
>
>> +
>> +#define DCP_RNG_MAX_FIFO_STORE_SIZE 4
>> +#define RNGC_VER_ID 0x0000
>> +#define RNGC_COMMAND 0x0004
>> +#define RNGC_CONTROL 0x0008
>> +#define RNGC_STATUS 0x000C
>> +#define RNGC_ERROR 0x0010
>> +#define RNGC_FIFO 0x0014
>> +
>> +/* the fields in the ver id register */
>> +#define RNGC_TYPE_SHIFT 28
>> +
>> +/* the rng_type field */
>> +#define RNGC_TYPE_RNGB 0x1
>> +#define RNGC_TYPE_RNGC 0x2
>> +
>> +#define RNGC_CMD_CLR_ERR 0x00000020
>> +#define RNGC_CMD_SEED 0x00000002
>> +
>> +#define RNGC_CTRL_AUTO_SEED 0x00000010
>> +
>> +#define RNGC_STATUS_ERROR 0x00010000
>> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
>> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
>> +#define RNGC_STATUS_SEED_DONE 0x00000020
>> +#define RNGC_STATUS_ST_DONE 0x00000010
>
> Why all the leading zeroes?
>
>> +
>> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
>> +
>> +#define RNGC_TIMEOUT 3000000U /* 3 sec */
>> +
>> +struct imx_rngc {
>
> Normally the priv data should have a _priv suffix.
>
>> + unsigned long base;
>> +};
>> +
>> +static int rngc_read(struct udevice *dev, void *data, size_t len)
>> +{
>> + struct imx_rngc *rngc = dev_get_priv(dev);
>
> Normally the var should be called priv
This is described in doc/develop/codingstyle.rst line 192ff.
>
>> + u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
>> + u32 status, level;
>> + size_t size;
>> +
>> + while (len) {
>> + status = readl(rngc->base + RNGC_STATUS);
>> +
>> + /* is there some error while reading this random number? */
>> + if (status & RNGC_STATUS_ERROR)
>> + break;
>> + /* how many random numbers are in FIFO? [0-16] */
>> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
>> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
>> +
>> + if (level) {
>> + /* retrieve a random number from FIFO */
>> + *(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
>> + size = min(len, sizeof(u32));
>> + memcpy(data, buffer, size);
>> + data += size;
>> + len -= size;
>> + }
>> + }
>> +
>> + return len ? -EIO : 0;
>> +}
>> +
>> +static int rngc_init(struct imx_rngc *rngc)
>> +{
>> + u32 cmd, ctrl, status, err_reg = 0;
>> + unsigned long long timeval = 0;
>> + unsigned long long timeout = RNGC_TIMEOUT;
>> +
>> + /* clear error */
>> + cmd = readl(rngc->base + RNGC_COMMAND);
>> + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
>> +
>> + /* create seed, repeat while there is some statistical error */
>> + do {
>> + /* seed creation */
>> + cmd = readl(rngc->base + RNGC_COMMAND);
>> + writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
>> +
>> + udelay(1);
>> + timeval += 1;
As this loop can take rather long, should we call WATCHDOG_RESET()
before and after the loop?
Otherwise looks good to me.
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>> +
>> + status = readl(rngc->base + RNGC_STATUS);
>> + err_reg = readl(rngc->base + RNGC_ERROR);
>> +
>> + if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
>> + break;
>> +
>> + if (timeval > timeout) {
>> + debug("rngc timed out\n");
>> + return -ETIMEDOUT;
>> + }
>> + } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
>> +
>> + if (err_reg)
>> + return -EIO;
>> +
>> + /*
>> + * enable automatic seeding, the rngc creates a new seed automatically
>> + * after serving 2^20 random 160-bit words
>> + */
>> + ctrl = readl(rngc->base + RNGC_CONTROL);
>> + ctrl |= RNGC_CTRL_AUTO_SEED;
>> + writel(ctrl, rngc->base + RNGC_CONTROL);
>
> setbits_le32(rngc->base + RNGC_CONTROL, RNGC_CTRL_AUTO_SEED);
>
>> + return 0;
>> +}
>> +
>> +static int rngc_probe(struct udevice *dev)
>> +{
>> + struct imx_rngc *rngc = dev_get_priv(dev);
>> + fdt_addr_t addr;
>> + u32 ver_id;
>> + u8 rng_type;
>> + int ret;
>> +
>> + addr = dev_read_addr(dev);
>> + if (addr == FDT_ADDR_T_NONE) {
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> +
>> + rngc->base = addr;
>> + ver_id = readl(rngc->base + RNGC_VER_ID);
>> + rng_type = ver_id >> RNGC_TYPE_SHIFT;
>> + /*
>> + * This driver supports only RNGC and RNGB. (There's a different
>> + * driver for RNGA.)
>> + */
>> + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
>> + ret = -ENODEV;
>> + goto err;
>> + }
>> +
>> + ret = rngc_init(rngc);
>> + if (ret)
>> + goto err;
>> +
>> + return 0;
>> +
>> +err:
>> + printf("%s error = %d\n", __func__, ret);
>> + return ret;
>> +}
>> +
>> +static const struct dm_rng_ops rngc_ops = {
>> + .read = rngc_read,
>> +};
>> +
>> +static const struct udevice_id rngc_dt_ids[] = {
>> + { .compatible = "fsl,imx25-rngb" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(dcp_rng) = {
>> + .name = "dcp_rng",
>> + .id = UCLASS_RNG,
>> + .of_match = rngc_dt_ids,
>> + .ops = &rngc_ops,
>> + .probe = rngc_probe,
>> + .priv_auto = sizeof(struct imx_rngc),
>> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>> --
>> 2.25.1
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [EXT] Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
2022-09-08 19:29 ` Heinrich Schuchardt
@ 2022-12-21 11:11 ` Kshitiz Varshney
0 siblings, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-12-21 11:11 UTC (permalink / raw)
To: Heinrich Schuchardt
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Stefano Babic, Fabio Estevam, Peng Fan, Sughosh Ganu,
Simon Glass
Please see the comment inline.
Regards,
Kshitiz
-----Original Message-----
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Sent: Friday, September 9, 2022 1:00 AM
To: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Horia Geanta <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>; Ye Li <ye.li@nxp.com>; Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Sughosh Ganu <sughosh.ganu@linaro.org>; Simon Glass <sjg@chromium.org>
Subject: [EXT] Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
Caution: EXT Email
On 9/8/22 20:19, Simon Glass wrote:
> Hi Kshitiz,
>
> On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>>
>> From: Kshitiz <kshitiz.varshney@nxp.com>
>>
>> This commit introduces Random number generator to uboot. It uses DCP
>> driver for number generation.
>> RNG driver can be invoked by using below command on uboot prompt:-
>> rng <number of bytes>
>>
>> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
CC the maintainer for RNG Sughosh Ganu <sughosh.ganu@linaro.org>.
Will take care of this in next patch.
>> Reviewed-by: Ye Li <ye.li@nxp.com>
>> ---
>> drivers/crypto/fsl/Kconfig | 10 ++
>> drivers/crypto/fsl/Makefile | 1 +
>> drivers/crypto/fsl/dcp_rng.c | 184 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 195 insertions(+)
>> create mode 100644 drivers/crypto/fsl/dcp_rng.c
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> but please see below
>
>>
>> diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
>> index 702d204a3d..da5955e31d 100644
>> --- a/drivers/crypto/fsl/Kconfig
>> +++ b/drivers/crypto/fsl/Kconfig
>> @@ -96,3 +96,13 @@ config RNG_SELF_TEST
>> must be run before running any RNG based crypto implementation.
>>
>> endif
>> +
>> +config FSL_DCP_RNG
>> + bool "Enable Random Number Generator support"
>> + depends on DM_RNG
>> + default n
>> + help
>> + Enable support for the hardware based random number generator
>> + module of the DCP.It uses the True Random Number Generator
>> +(TRNG)
Please, use the same indentation as the other Kconfig entries in this
file: Add two space in each line of the help text.
Done
>
> Space before It
>
>> + and a Pseudo-Random Number Generator (PRNG) to achieve a true
>> + randomness and cryptographic strength.
>> diff --git a/drivers/crypto/fsl/Makefile
>> b/drivers/crypto/fsl/Makefile index 926300e2ab..c653208d23 100644
>> --- a/drivers/crypto/fsl/Makefile
>> +++ b/drivers/crypto/fsl/Makefile
>> @@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
>> obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
>> obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
>> obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
>> +obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
>> obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
>> obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
>> obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o diff
>> --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
>> new file mode 100644 index 0000000000..a797710c2e
>> --- /dev/null
>> +++ b/drivers/crypto/fsl/dcp_rng.c
>> @@ -0,0 +1,184 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * RNG driver for Freescale RNGC
>> + *
>> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
>> + * Copyright 2022 NXP
>> + *
>> + * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in
>> +Linux */
>> +
>> +#include <asm/cache.h>
>> +#include <common.h>
>> +#include <cpu_func.h>
>> +#include <dm.h>
>> +#include <rng.h>
>> +#include <linux/kernel.h>
>> +#include <linux/delay.h>
>> +#include <asm/io.h>
>> +#include <dm/root.h>
>
> Should be:
>
>> +#include <common.h>
>> +#include <cpu_func.h>
>> +#include <dm.h>
>> +#include <rng.h>
>> +#include <asm/cache.h>
>> +#include <asm/io.h>
>> +#include <dm/root.h>
>> +#include <linux/delay.h>
>> +#include <linux/kernel.h>
>
>
>> +
>> +#define DCP_RNG_MAX_FIFO_STORE_SIZE 4
>> +#define RNGC_VER_ID 0x0000
>> +#define RNGC_COMMAND 0x0004
>> +#define RNGC_CONTROL 0x0008
>> +#define RNGC_STATUS 0x000C
>> +#define RNGC_ERROR 0x0010
>> +#define RNGC_FIFO 0x0014
>> +
>> +/* the fields in the ver id register */
>> +#define RNGC_TYPE_SHIFT 28
>> +
>> +/* the rng_type field */
>> +#define RNGC_TYPE_RNGB 0x1
>> +#define RNGC_TYPE_RNGC 0x2
>> +
>> +#define RNGC_CMD_CLR_ERR 0x00000020
>> +#define RNGC_CMD_SEED 0x00000002
>> +
>> +#define RNGC_CTRL_AUTO_SEED 0x00000010
>> +
>> +#define RNGC_STATUS_ERROR 0x00010000
>> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
>> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
>> +#define RNGC_STATUS_SEED_DONE 0x00000020
>> +#define RNGC_STATUS_ST_DONE 0x00000010
>
> Why all the leading zeroes?
>
>> +
>> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
>> +
>> +#define RNGC_TIMEOUT 3000000U /* 3 sec */
>> +
>> +struct imx_rngc {
>
> Normally the priv data should have a _priv suffix.
>
>> + unsigned long base;
>> +};
>> +
>> +static int rngc_read(struct udevice *dev, void *data, size_t len) {
>> + struct imx_rngc *rngc = dev_get_priv(dev);
>
> Normally the var should be called priv
This is described in doc/develop/codingstyle.rst line 192ff.
>
>> + u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
>> + u32 status, level;
>> + size_t size;
>> +
>> + while (len) {
>> + status = readl(rngc->base + RNGC_STATUS);
>> +
>> + /* is there some error while reading this random number? */
>> + if (status & RNGC_STATUS_ERROR)
>> + break;
>> + /* how many random numbers are in FIFO? [0-16] */
>> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
>> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
>> +
>> + if (level) {
>> + /* retrieve a random number from FIFO */
>> + *(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
>> + size = min(len, sizeof(u32));
>> + memcpy(data, buffer, size);
>> + data += size;
>> + len -= size;
>> + }
>> + }
>> +
>> + return len ? -EIO : 0;
>> +}
>> +
>> +static int rngc_init(struct imx_rngc *rngc) {
>> + u32 cmd, ctrl, status, err_reg = 0;
>> + unsigned long long timeval = 0;
>> + unsigned long long timeout = RNGC_TIMEOUT;
>> +
>> + /* clear error */
>> + cmd = readl(rngc->base + RNGC_COMMAND);
>> + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
>> +
>> + /* create seed, repeat while there is some statistical error */
>> + do {
>> + /* seed creation */
>> + cmd = readl(rngc->base + RNGC_COMMAND);
>> + writel(cmd | RNGC_CMD_SEED, rngc->base +
>> + RNGC_COMMAND);
>> +
>> + udelay(1);
>> + timeval += 1;
As this loop can take rather long, should we call WATCHDOG_RESET() before and after the loop?
Otherwise looks good to me.
This is in reference with imx-rngc.c in kernel code.
See this link for more info:- https://elixir.bootlin.com/linux/latest/source/drivers/char/hw_random/imx-rngc.c
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>> +
>> + status = readl(rngc->base + RNGC_STATUS);
>> + err_reg = readl(rngc->base + RNGC_ERROR);
>> +
>> + if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
>> + break;
>> +
>> + if (timeval > timeout) {
>> + debug("rngc timed out\n");
>> + return -ETIMEDOUT;
>> + }
>> + } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
>> +
>> + if (err_reg)
>> + return -EIO;
>> +
>> + /*
>> + * enable automatic seeding, the rngc creates a new seed automatically
>> + * after serving 2^20 random 160-bit words
>> + */
>> + ctrl = readl(rngc->base + RNGC_CONTROL);
>> + ctrl |= RNGC_CTRL_AUTO_SEED;
>> + writel(ctrl, rngc->base + RNGC_CONTROL);
>
> setbits_le32(rngc->base + RNGC_CONTROL, RNGC_CTRL_AUTO_SEED);
>
>> + return 0;
>> +}
>> +
>> +static int rngc_probe(struct udevice *dev) {
>> + struct imx_rngc *rngc = dev_get_priv(dev);
>> + fdt_addr_t addr;
>> + u32 ver_id;
>> + u8 rng_type;
>> + int ret;
>> +
>> + addr = dev_read_addr(dev);
>> + if (addr == FDT_ADDR_T_NONE) {
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> +
>> + rngc->base = addr;
>> + ver_id = readl(rngc->base + RNGC_VER_ID);
>> + rng_type = ver_id >> RNGC_TYPE_SHIFT;
>> + /*
>> + * This driver supports only RNGC and RNGB. (There's a different
>> + * driver for RNGA.)
>> + */
>> + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
>> + ret = -ENODEV;
>> + goto err;
>> + }
>> +
>> + ret = rngc_init(rngc);
>> + if (ret)
>> + goto err;
>> +
>> + return 0;
>> +
>> +err:
>> + printf("%s error = %d\n", __func__, ret);
>> + return ret;
>> +}
>> +
>> +static const struct dm_rng_ops rngc_ops = {
>> + .read = rngc_read,
>> +};
>> +
>> +static const struct udevice_id rngc_dt_ids[] = {
>> + { .compatible = "fsl,imx25-rngb" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(dcp_rng) = {
>> + .name = "dcp_rng",
>> + .id = UCLASS_RNG,
>> + .of_match = rngc_dt_ids,
>> + .ops = &rngc_ops,
>> + .probe = rngc_probe,
>> + .priv_auto = sizeof(struct imx_rngc),
>> + .flags = DM_FLAG_ALLOC_PRIV_DMA, };
>> --
>> 2.25.1
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [EXT] Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
2022-09-08 18:19 ` Simon Glass
2022-09-08 19:29 ` Heinrich Schuchardt
@ 2022-12-21 11:06 ` Kshitiz Varshney
1 sibling, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-12-21 11:06 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Heinrich Schuchardt, Stefano Babic, Fabio Estevam,
Peng Fan
Regards,
Kshitiz
-----Original Message-----
From: Simon Glass <sjg@chromium.org>
Sent: Thursday, September 8, 2022 11:49 PM
To: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Horia Geanta <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>; Ye Li <ye.li@nxp.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>; Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>
Subject: [EXT] Re: [PATCH v1] 2: Uboot RNG Driver using Data Co-processor
Caution: EXT Email
Hi Kshitiz,
On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> This commit introduces Random number generator to uboot. It uses DCP
> driver for number generation.
> RNG driver can be invoked by using below command on uboot prompt:-
> rng <number of bytes>
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> drivers/crypto/fsl/Kconfig | 10 ++
> drivers/crypto/fsl/Makefile | 1 +
> drivers/crypto/fsl/dcp_rng.c | 184
> +++++++++++++++++++++++++++++++++++
> 3 files changed, 195 insertions(+)
> create mode 100644 drivers/crypto/fsl/dcp_rng.c
Reviewed-by: Simon Glass <sjg@chromium.org>
but please see below
>
> diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
> index 702d204a3d..da5955e31d 100644
> --- a/drivers/crypto/fsl/Kconfig
> +++ b/drivers/crypto/fsl/Kconfig
> @@ -96,3 +96,13 @@ config RNG_SELF_TEST
> must be run before running any RNG based crypto implementation.
>
> endif
> +
> +config FSL_DCP_RNG
> + bool "Enable Random Number Generator support"
> + depends on DM_RNG
> + default n
> + help
> + Enable support for the hardware based random number generator
> + module of the DCP.It uses the True Random Number Generator
> +(TRNG)
Space before It
> + and a Pseudo-Random Number Generator (PRNG) to achieve a true
> + randomness and cryptographic strength.
> diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
> index 926300e2ab..c653208d23 100644
> --- a/drivers/crypto/fsl/Makefile
> +++ b/drivers/crypto/fsl/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o
> error.o
> obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
> obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
> obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
> +obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
> obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
> obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
> obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o diff --git
> a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c new file
> mode 100644 index 0000000000..a797710c2e
> --- /dev/null
> +++ b/drivers/crypto/fsl/dcp_rng.c
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * RNG driver for Freescale RNGC
> + *
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
> + * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
> + * Copyright 2022 NXP
> + *
> + * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
> +*/
> +
> +#include <asm/cache.h>
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <rng.h>
> +#include <linux/kernel.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <dm/root.h>
Should be:
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <rng.h>
> +#include <asm/cache.h>
> +#include <asm/io.h>
> +#include <dm/root.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
Taken care of this in next patch.
> +
> +#define DCP_RNG_MAX_FIFO_STORE_SIZE 4
> +#define RNGC_VER_ID 0x0000
> +#define RNGC_COMMAND 0x0004
> +#define RNGC_CONTROL 0x0008
> +#define RNGC_STATUS 0x000C
> +#define RNGC_ERROR 0x0010
> +#define RNGC_FIFO 0x0014
> +
> +/* the fields in the ver id register */
> +#define RNGC_TYPE_SHIFT 28
> +
> +/* the rng_type field */
> +#define RNGC_TYPE_RNGB 0x1
> +#define RNGC_TYPE_RNGC 0x2
> +
> +#define RNGC_CMD_CLR_ERR 0x00000020
> +#define RNGC_CMD_SEED 0x00000002
> +
> +#define RNGC_CTRL_AUTO_SEED 0x00000010
> +
> +#define RNGC_STATUS_ERROR 0x00010000
> +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
> +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
> +#define RNGC_STATUS_SEED_DONE 0x00000020
> +#define RNGC_STATUS_ST_DONE 0x00000010
Why all the leading zeroes?
Removed all the leading zeroes in next patch.
> +
> +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
> +
> +#define RNGC_TIMEOUT 3000000U /* 3 sec */
> +
> +struct imx_rngc {
Normally the priv data should have a _priv suffix.
Done
> + unsigned long base;
> +};
> +
> +static int rngc_read(struct udevice *dev, void *data, size_t len) {
> + struct imx_rngc *rngc = dev_get_priv(dev);
Normally the var should be called priv
Done
> + u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
> + u32 status, level;
> + size_t size;
> +
> + while (len) {
> + status = readl(rngc->base + RNGC_STATUS);
> +
> + /* is there some error while reading this random number? */
> + if (status & RNGC_STATUS_ERROR)
> + break;
> + /* how many random numbers are in FIFO? [0-16] */
> + level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
> + RNGC_STATUS_FIFO_LEVEL_SHIFT;
> +
> + if (level) {
> + /* retrieve a random number from FIFO */
> + *(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
> + size = min(len, sizeof(u32));
> + memcpy(data, buffer, size);
> + data += size;
> + len -= size;
> + }
> + }
> +
> + return len ? -EIO : 0;
> +}
> +
> +static int rngc_init(struct imx_rngc *rngc) {
> + u32 cmd, ctrl, status, err_reg = 0;
> + unsigned long long timeval = 0;
> + unsigned long long timeout = RNGC_TIMEOUT;
> +
> + /* clear error */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
> +
> + /* create seed, repeat while there is some statistical error */
> + do {
> + /* seed creation */
> + cmd = readl(rngc->base + RNGC_COMMAND);
> + writel(cmd | RNGC_CMD_SEED, rngc->base +
> + RNGC_COMMAND);
> +
> + udelay(1);
> + timeval += 1;
> +
> + status = readl(rngc->base + RNGC_STATUS);
> + err_reg = readl(rngc->base + RNGC_ERROR);
> +
> + if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
> + break;
> +
> + if (timeval > timeout) {
> + debug("rngc timed out\n");
> + return -ETIMEDOUT;
> + }
> + } while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
> +
> + if (err_reg)
> + return -EIO;
> +
> + /*
> + * enable automatic seeding, the rngc creates a new seed automatically
> + * after serving 2^20 random 160-bit words
> + */
> + ctrl = readl(rngc->base + RNGC_CONTROL);
> + ctrl |= RNGC_CTRL_AUTO_SEED;
> + writel(ctrl, rngc->base + RNGC_CONTROL);
setbits_le32(rngc->base + RNGC_CONTROL, RNGC_CTRL_AUTO_SEED);
> + return 0;
> +}
> +
> +static int rngc_probe(struct udevice *dev) {
> + struct imx_rngc *rngc = dev_get_priv(dev);
> + fdt_addr_t addr;
> + u32 ver_id;
> + u8 rng_type;
> + int ret;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE) {
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + rngc->base = addr;
> + ver_id = readl(rngc->base + RNGC_VER_ID);
> + rng_type = ver_id >> RNGC_TYPE_SHIFT;
> + /*
> + * This driver supports only RNGC and RNGB. (There's a different
> + * driver for RNGA.)
> + */
> + if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ret = rngc_init(rngc);
> + if (ret)
> + goto err;
> +
> + return 0;
> +
> +err:
> + printf("%s error = %d\n", __func__, ret);
> + return ret;
> +}
> +
> +static const struct dm_rng_ops rngc_ops = {
> + .read = rngc_read,
> +};
> +
> +static const struct udevice_id rngc_dt_ids[] = {
> + { .compatible = "fsl,imx25-rngb" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dcp_rng) = {
> + .name = "dcp_rng",
> + .id = UCLASS_RNG,
> + .of_match = rngc_dt_ids,
> + .ops = &rngc_ops,
> + .probe = rngc_probe,
> + .priv_auto = sizeof(struct imx_rngc),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA, };
> --
> 2.25.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v1] 3: Added dcp_rng driver device binding code
2022-09-08 8:57 [PATCH v1] 1: Adding rngb entry in imx6ull device tree Kshitiz Varshney
2022-09-08 8:57 ` [PATCH v1] 2: Uboot RNG Driver using Data Co-processor Kshitiz Varshney
@ 2022-09-08 8:57 ` Kshitiz Varshney
2022-09-08 18:18 ` Simon Glass
2022-09-08 8:57 ` [PATCH v1] 4: Added configs required for dcp_rng driver Kshitiz Varshney
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Kshitiz Varshney @ 2022-09-08 8:57 UTC (permalink / raw)
To: u-boot, Horia Geanta, Pankaj Gupta, Varun Sethi, Gaurav Jain,
Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra, Ye Li,
Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Kshitiz
From: Kshitiz <kshitiz.varshney@nxp.com>
This commit manually binds dcp_rng device driver and initalizes it inside
arch_misc_init() function.
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/mach-imx/mx6/soc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 3e538754d9..9bf16119c2 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -31,6 +31,8 @@
#include <hang.h>
#include <cpu_func.h>
#include <env.h>
+#include<dm/device-internal.h>
+#include<dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1005,6 +1007,20 @@ int arch_misc_init(void)
if (ret)
printf("Failed to initialize caam_jr: %d\n", ret);
}
+
+ if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
+ if (ret)
+ printf("Couldn't bind dcp rng driver (%d)\n", ret);
+
+ ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
+ if (ret)
+ printf("Failed to initialize dcp rng: %d\n", ret);
+ }
+
setup_serial_number();
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v1] 3: Added dcp_rng driver device binding code
2022-09-08 8:57 ` [PATCH v1] 3: Added dcp_rng driver device binding code Kshitiz Varshney
@ 2022-09-08 18:18 ` Simon Glass
2022-09-08 19:31 ` Heinrich Schuchardt
2022-12-21 11:08 ` [EXT] " Kshitiz Varshney
0 siblings, 2 replies; 15+ messages in thread
From: Simon Glass @ 2022-09-08 18:18 UTC (permalink / raw)
To: Kshitiz Varshney
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Heinrich Schuchardt, Stefano Babic, Fabio Estevam,
Peng Fan
Hi Kshitiz,
+Ilias Apalodimas
On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> This commit manually binds dcp_rng device driver and initalizes it inside
> arch_misc_init() function.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/mach-imx/mx6/soc.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index 3e538754d9..9bf16119c2 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -31,6 +31,8 @@
> #include <hang.h>
> #include <cpu_func.h>
> #include <env.h>
> +#include<dm/device-internal.h>
> +#include<dm/lists.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -1005,6 +1007,20 @@ int arch_misc_init(void)
> if (ret)
> printf("Failed to initialize caam_jr: %d\n", ret);
> }
> +
> + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
> + struct udevice *dev;
> + int ret;
> +
> + ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
This needs to be in the device tree. This it the kind of madness I was
warning about with Ilias, so I have copied him here.
We need to stop manually binding devices when they should be in the DT.
> + if (ret)
> + printf("Couldn't bind dcp rng driver (%d)\n", ret);
> +
> + ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
> + if (ret)
> + printf("Failed to initialize dcp rng: %d\n", ret);
> + }
> +
> setup_serial_number();
> return 0;
> }
> --
> 2.25.1
>
Regards,
SImon
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v1] 3: Added dcp_rng driver device binding code
2022-09-08 18:18 ` Simon Glass
@ 2022-09-08 19:31 ` Heinrich Schuchardt
2022-12-21 11:08 ` [EXT] " Kshitiz Varshney
1 sibling, 0 replies; 15+ messages in thread
From: Heinrich Schuchardt @ 2022-09-08 19:31 UTC (permalink / raw)
To: Simon Glass, Kshitiz Varshney
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Stefano Babic, Fabio Estevam, Peng Fan, Sughosh Ganu
On 9/8/22 20:18, Simon Glass wrote:
> Hi Kshitiz,
>
> +Ilias Apalodimas
>
>
> On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>>
>> From: Kshitiz <kshitiz.varshney@nxp.com>
>>
>> This commit manually binds dcp_rng device driver and initalizes it inside
>> arch_misc_init() function.
>>
>> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
>> Reviewed-by: Ye Li <ye.li@nxp.com>
CC the maintainer of RNG Sughosh Ganu <sughosh.ganu@linaro.org>
>> ---
>> arch/arm/mach-imx/mx6/soc.c | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
>> index 3e538754d9..9bf16119c2 100644
>> --- a/arch/arm/mach-imx/mx6/soc.c
>> +++ b/arch/arm/mach-imx/mx6/soc.c
>> @@ -31,6 +31,8 @@
>> #include <hang.h>
>> #include <cpu_func.h>
>> #include <env.h>
>> +#include<dm/device-internal.h>
>> +#include<dm/lists.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -1005,6 +1007,20 @@ int arch_misc_init(void)
>> if (ret)
>> printf("Failed to initialize caam_jr: %d\n", ret);
>> }
>> +
>> + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
>> + struct udevice *dev;
>> + int ret;
>> +
>> + ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
>
> This needs to be in the device tree. This it the kind of madness I was
> warning about with Ilias, so I have copied him here.
>
> We need to stop manually binding devices when they should be in the DT.
>
>> + if (ret)
>> + printf("Couldn't bind dcp rng driver (%d)\n", ret);
>> +
>> + ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
>> + if (ret)
>> + printf("Failed to initialize dcp rng: %d\n", ret);
>> + }
>> +
>> setup_serial_number();
>> return 0;
>> }
>> --
>> 2.25.1
>>
>
> Regards,
> SImon
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [EXT] Re: [PATCH v1] 3: Added dcp_rng driver device binding code
2022-09-08 18:18 ` Simon Glass
2022-09-08 19:31 ` Heinrich Schuchardt
@ 2022-12-21 11:08 ` Kshitiz Varshney
1 sibling, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-12-21 11:08 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Horia Geanta, Pankaj Gupta, Varun Sethi,
Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra,
Ye Li, Heinrich Schuchardt, Stefano Babic, Fabio Estevam,
Peng Fan
Please find comment inline.
Regards,
Kshitiz
-----Original Message-----
From: Simon Glass <sjg@chromium.org>
Sent: Thursday, September 8, 2022 11:49 PM
To: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Horia Geanta <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>; Ye Li <ye.li@nxp.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>; Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>
Subject: [EXT] Re: [PATCH v1] 3: Added dcp_rng driver device binding code
Caution: EXT Email
Hi Kshitiz,
+Ilias Apalodimas
On Thu, 8 Sept 2022 at 02:59, Kshitiz Varshney <kshitiz.varshney@nxp.com> wrote:
>
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> This commit manually binds dcp_rng device driver and initalizes it
> inside
> arch_misc_init() function.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/mach-imx/mx6/soc.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
> index 3e538754d9..9bf16119c2 100644
> --- a/arch/arm/mach-imx/mx6/soc.c
> +++ b/arch/arm/mach-imx/mx6/soc.c
> @@ -31,6 +31,8 @@
> #include <hang.h>
> #include <cpu_func.h>
> #include <env.h>
> +#include<dm/device-internal.h>
> +#include<dm/lists.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -1005,6 +1007,20 @@ int arch_misc_init(void)
> if (ret)
> printf("Failed to initialize caam_jr: %d\n", ret);
> }
> +
> + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
> + struct udevice *dev;
> + int ret;
> +
> + ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng",
> + NULL);
This needs to be in the device tree. This it the kind of madness I was warning about with Ilias, so I have copied him here.
We need to stop manually binding devices when they should be in the DT.
I have removed manual binding in next patch instead used u-boot device tree rngb entry for binding device automatically.
> + if (ret)
> + printf("Couldn't bind dcp rng driver (%d)\n",
> + ret);
> +
> + ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
> + if (ret)
> + printf("Failed to initialize dcp rng: %d\n", ret);
> + }
> +
> setup_serial_number();
> return 0;
> }
> --
> 2.25.1
>
Regards,
SImon
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v1] 4: Added configs required for dcp_rng driver
2022-09-08 8:57 [PATCH v1] 1: Adding rngb entry in imx6ull device tree Kshitiz Varshney
2022-09-08 8:57 ` [PATCH v1] 2: Uboot RNG Driver using Data Co-processor Kshitiz Varshney
2022-09-08 8:57 ` [PATCH v1] 3: Added dcp_rng driver device binding code Kshitiz Varshney
@ 2022-09-08 8:57 ` Kshitiz Varshney
2022-09-08 19:40 ` [PATCH v1] 1: Adding rngb entry in imx6ull device tree Heinrich Schuchardt
2022-09-12 7:31 ` Peng Fan
4 siblings, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-09-08 8:57 UTC (permalink / raw)
To: u-boot, Horia Geanta, Pankaj Gupta, Varun Sethi, Gaurav Jain,
Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra, Ye Li,
Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Kshitiz
From: Kshitiz <kshitiz.varshney@nxp.com>
This commit adds configs required for using dcp_rng driver in imx6ull
defconfig files.
Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
configs/mx6ull_14x14_evk_defconfig | 4 ++++
configs/mx6ull_14x14_evk_emmc_defconfig | 4 ++++
configs/mx6ull_14x14_evk_nand_defconfig | 4 ++++
configs/mx6ull_14x14_evk_optee_defconfig | 4 ++++
configs/mx6ull_14x14_evk_plugin_defconfig | 4 ++++
configs/mx6ull_14x14_evk_qspi1_defconfig | 4 ++++
configs/mx6ull_9x9_evk_defconfig | 5 +++++
configs/mx6ull_9x9_evk_plugin_defconfig | 4 ++++
configs/mx6ull_9x9_evk_qspi1_defconfig | 4 ++++
9 files changed, 37 insertions(+)
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index cdcd496edd..79964b3ccf 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -99,3 +99,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig
index d94085e13b..f4bcc40544 100644
--- a/configs/mx6ull_14x14_evk_emmc_defconfig
+++ b/configs/mx6ull_14x14_evk_emmc_defconfig
@@ -99,3 +99,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig
index 16900e04f0..1931293bc6 100644
--- a/configs/mx6ull_14x14_evk_nand_defconfig
+++ b/configs/mx6ull_14x14_evk_nand_defconfig
@@ -106,3 +106,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig
index 2bb3d44fa8..ba1c8e02a4 100644
--- a/configs/mx6ull_14x14_evk_optee_defconfig
+++ b/configs/mx6ull_14x14_evk_optee_defconfig
@@ -100,3 +100,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index baab9c2ee8..9c1354981e 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -100,3 +100,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig
index f1fe8b4000..13a1eec75e 100644
--- a/configs/mx6ull_14x14_evk_qspi1_defconfig
+++ b/configs/mx6ull_14x14_evk_qspi1_defconfig
@@ -102,3 +102,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig
index 66eacc55fa..3f73c5e697 100644
--- a/configs/mx6ull_9x9_evk_defconfig
+++ b/configs/mx6ull_9x9_evk_defconfig
@@ -103,3 +103,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig
index 7eace52b5c..41468f2d38 100644
--- a/configs/mx6ull_9x9_evk_plugin_defconfig
+++ b/configs/mx6ull_9x9_evk_plugin_defconfig
@@ -104,3 +104,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig
index f145b65e6c..f1446ef8e0 100644
--- a/configs/mx6ull_9x9_evk_qspi1_defconfig
+++ b/configs/mx6ull_9x9_evk_qspi1_defconfig
@@ -106,3 +106,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
2022-09-08 8:57 [PATCH v1] 1: Adding rngb entry in imx6ull device tree Kshitiz Varshney
` (2 preceding siblings ...)
2022-09-08 8:57 ` [PATCH v1] 4: Added configs required for dcp_rng driver Kshitiz Varshney
@ 2022-09-08 19:40 ` Heinrich Schuchardt
2022-12-21 11:13 ` [EXT] " Kshitiz Varshney
2022-09-12 7:31 ` Peng Fan
4 siblings, 1 reply; 15+ messages in thread
From: Heinrich Schuchardt @ 2022-09-08 19:40 UTC (permalink / raw)
To: Kshitiz Varshney
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Sughosh Ganu, u-boot,
Ye Li, Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma,
Varun Sethi, Sahil Malhotra, Pankaj Gupta, Horia Geanta
On 9/8/22 10:57, Kshitiz Varshney wrote:
> From: Kshitiz <kshitiz.varshney@nxp.com>
If you use format-patch HEAD~3, it will add numbers to the patches as
expected: [PATCH 1/3].
For patch series we typically generate a cover-letter.
>
> Added entry for rngb in imx6ull device tree which is required for
> Random number generation in u-boot.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx6ull.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
> index 46e7ad6bab..c5d5a5ab7b 100644
> --- a/arch/arm/dts/imx6ull.dtsi
> +++ b/arch/arm/dts/imx6ull.dtsi
> @@ -66,6 +66,12 @@
> clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
> clock-names = "dcp";
> };
> + rngb: rng@2284000 {
> + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
> + reg = <0x02284000 0x4000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_DUMMY>;
> + };
This seems to match Linux'
arch/arm/boot/dts/imx6ull.dtsi and
Documentation/devicetree/bindings/rng/imx-rng.yaml.
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>
> iomuxc_snvs: iomuxc-snvs@2290000 {
> compatible = "fsl,imx6ull-iomuxc-snvs";
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [EXT] Re: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
2022-09-08 19:40 ` [PATCH v1] 1: Adding rngb entry in imx6ull device tree Heinrich Schuchardt
@ 2022-12-21 11:13 ` Kshitiz Varshney
0 siblings, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-12-21 11:13 UTC (permalink / raw)
To: Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Sughosh Ganu, u-boot,
Ye Li, Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma,
Varun Sethi, Sahil Malhotra, Pankaj Gupta, Horia Geanta
-----Original Message-----
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Sent: Friday, September 9, 2022 1:10 AM
To: Kshitiz Varshney <kshitiz.varshney@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Sughosh Ganu <sughosh.ganu@linaro.org>; u-boot@lists.denx.de; Ye Li <ye.li@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Horia Geanta <horia.geanta@nxp.com>
Subject: [EXT] Re: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
Caution: EXT Email
On 9/8/22 10:57, Kshitiz Varshney wrote:
> From: Kshitiz <kshitiz.varshney@nxp.com>
If you use format-patch HEAD~3, it will add numbers to the patches as
expected: [PATCH 1/3].
For patch series we typically generate a cover-letter.
Will take care in next patch set.
>
> Added entry for rngb in imx6ull device tree which is required for
> Random number generation in u-boot.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx6ull.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
> index 46e7ad6bab..c5d5a5ab7b 100644
> --- a/arch/arm/dts/imx6ull.dtsi
> +++ b/arch/arm/dts/imx6ull.dtsi
> @@ -66,6 +66,12 @@
> clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
> clock-names = "dcp";
> };
> + rngb: rng@2284000 {
> + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
> + reg = <0x02284000 0x4000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_DUMMY>;
> + };
This seems to match Linux'
arch/arm/boot/dts/imx6ull.dtsi and
Documentation/devicetree/bindings/rng/imx-rng.yaml.
As, this node entry is already present in upstream uboot. Hence, removed this patch from new patchset.
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
>
> iomuxc_snvs: iomuxc-snvs@2290000 {
> compatible = "fsl,imx6ull-iomuxc-snvs";
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
2022-09-08 8:57 [PATCH v1] 1: Adding rngb entry in imx6ull device tree Kshitiz Varshney
` (3 preceding siblings ...)
2022-09-08 19:40 ` [PATCH v1] 1: Adding rngb entry in imx6ull device tree Heinrich Schuchardt
@ 2022-09-12 7:31 ` Peng Fan
2022-12-21 11:19 ` Kshitiz Varshney
4 siblings, 1 reply; 15+ messages in thread
From: Peng Fan @ 2022-09-12 7:31 UTC (permalink / raw)
To: Kshitiz Varshney, u-boot, Horia Geanta, Pankaj Gupta,
Varun Sethi, Gaurav Jain, Rahul Kumar Yadav, Vabhav Sharma,
Sahil Malhotra, Ye Li, Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan
On 9/8/2022 4:57 PM, Kshitiz Varshney wrote:
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> Added entry for rngb in imx6ull device tree which is required for
> Random number generation in u-boot.
Please sync with linux dts, not directly add a node to dtsi
Regards,
Peng.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx6ull.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
> index 46e7ad6bab..c5d5a5ab7b 100644
> --- a/arch/arm/dts/imx6ull.dtsi
> +++ b/arch/arm/dts/imx6ull.dtsi
> @@ -66,6 +66,12 @@
> clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
> clock-names = "dcp";
> };
> + rngb: rng@2284000 {
> + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
> + reg = <0x02284000 0x4000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_DUMMY>;
> + };
>
> iomuxc_snvs: iomuxc-snvs@2290000 {
> compatible = "fsl,imx6ull-iomuxc-snvs";
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
2022-09-12 7:31 ` Peng Fan
@ 2022-12-21 11:19 ` Kshitiz Varshney
0 siblings, 0 replies; 15+ messages in thread
From: Kshitiz Varshney @ 2022-12-21 11:19 UTC (permalink / raw)
To: Peng Fan (OSS),
u-boot, Horia Geanta, Pankaj Gupta, Varun Sethi, Gaurav Jain,
Rahul Kumar Yadav, Vabhav Sharma, Sahil Malhotra, Ye Li,
Heinrich Schuchardt
Cc: Stefano Babic, Fabio Estevam, Peng Fan
-----Original Message-----
From: Peng Fan (OSS) <peng.fan@oss.nxp.com>
Sent: Monday, September 12, 2022 1:01 PM
To: Kshitiz Varshney <kshitiz.varshney@nxp.com>; u-boot@lists.denx.de; Horia Geanta <horia.geanta@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>; Vabhav Sharma <vabhav.sharma@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>; Ye Li <ye.li@nxp.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH v1] 1: Adding rngb entry in imx6ull device tree
On 9/8/2022 4:57 PM, Kshitiz Varshney wrote:
> From: Kshitiz <kshitiz.varshney@nxp.com>
>
> Added entry for rngb in imx6ull device tree which is required for
> Random number generation in u-boot.
Please sync with linux dts, not directly add a node to dtsi
Regards,
Peng.
I have removed this patch from new version of patches as this entry was already present in upstream u-boot.
>
> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> arch/arm/dts/imx6ull.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
> index 46e7ad6bab..c5d5a5ab7b 100644
> --- a/arch/arm/dts/imx6ull.dtsi
> +++ b/arch/arm/dts/imx6ull.dtsi
> @@ -66,6 +66,12 @@
> clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
> clock-names = "dcp";
> };
> + rngb: rng@2284000 {
> + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
> + reg = <0x02284000 0x4000>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6UL_CLK_DUMMY>;
> + };
>
> iomuxc_snvs: iomuxc-snvs@2290000 {
> compatible = "fsl,imx6ull-iomuxc-snvs";
^ permalink raw reply [flat|nested] 15+ messages in thread