From: "Jernej Škrabec" <jernej.skrabec@gmail.com> To: Samuel Holland <samuel@sholland.org>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andre Przywara <andre.przywara@arm.com> Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng <uwu@icenowy.me>, Hans de Goede <hdegoede@redhat.com>, Dmitry Torokhov <dmitry.torokhov@gmail.com>, linux-input@vger.kernel.org Subject: Re: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node Date: Sun, 06 Nov 2022 09:25:55 +0100 [thread overview] Message-ID: <45074583.fMDQidcC6G@jernej-laptop> (raw) In-Reply-To: <20221101141658.3631342-10-andre.przywara@arm.com> Dne torek, 01. november 2022 ob 15:16:58 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) > compatible to the version in other SoCs. > The manual doesn't mention the ratio of the input voltage that is used, > but comparing actual measurements with the values in the register > suggests that it is 3/4 of Vref. > > Add the DT node describing the base address and interrupt. As in the > older SoCs, there is no explicit reset or clock gate, also there is a > dedicated, non-multiplexed pin, so need for more properties. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -262,6 +262,14 @@ ir: ir@1c22c00 { > status = "disabled"; > }; > > + lradc: lradc@1c23400 { > + compatible = "allwinner,suniv-f1c100s- lradc", > + "allwinner,sun8i-a83t-r- lradc"; > + reg = <0x01c23400 0x100>; User manual says 0x400 is reserved for this peripheral. With that fixed: Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej > + interrupts = <22>; > + status = "disabled"; > + }; > + > uart0: serial@1c25000 { > compatible = "snps,dw-apb-uart"; > reg = <0x01c25000 0x400>;
WARNING: multiple messages have this Message-ID (diff)
From: "Jernej Škrabec" <jernej.skrabec@gmail.com> To: Samuel Holland <samuel@sholland.org>, Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andre Przywara <andre.przywara@arm.com> Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng <uwu@icenowy.me>, Hans de Goede <hdegoede@redhat.com>, Dmitry Torokhov <dmitry.torokhov@gmail.com>, linux-input@vger.kernel.org Subject: Re: [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node Date: Sun, 06 Nov 2022 09:25:55 +0100 [thread overview] Message-ID: <45074583.fMDQidcC6G@jernej-laptop> (raw) In-Reply-To: <20221101141658.3631342-10-andre.przywara@arm.com> Dne torek, 01. november 2022 ob 15:16:58 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain a LRADC (aka. KEYADC) > compatible to the version in other SoCs. > The manual doesn't mention the ratio of the input voltage that is used, > but comparing actual measurements with the values in the register > suggests that it is 3/4 of Vref. > > Add the DT node describing the base address and interrupt. As in the > older SoCs, there is no explicit reset or clock gate, also there is a > dedicated, non-multiplexed pin, so need for more properties. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index d29b48f23b89a..03592c8e63fed > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -262,6 +262,14 @@ ir: ir@1c22c00 { > status = "disabled"; > }; > > + lradc: lradc@1c23400 { > + compatible = "allwinner,suniv-f1c100s- lradc", > + "allwinner,sun8i-a83t-r- lradc"; > + reg = <0x01c23400 0x100>; User manual says 0x400 is reserved for this peripheral. With that fixed: Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej > + interrupts = <22>; > + status = "disabled"; > + }; > + > uart0: serial@1c25000 { > compatible = "snps,dw-apb-uart"; > reg = <0x01c25000 0x400>; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-06 8:25 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-01 14:16 [PATCH 0/9] ARM: dts: suniv: F1C100s: add more peripherals Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-01 14:16 ` [PATCH 1/9] dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-02 17:28 ` Rob Herring 2022-11-02 17:28 ` Rob Herring 2022-11-17 12:05 ` Uwe Kleine-König 2022-11-17 12:05 ` Uwe Kleine-König 2022-11-01 14:16 ` [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-06 7:56 ` Jernej Škrabec 2022-11-06 7:56 ` Jernej Škrabec 2022-11-17 12:03 ` Uwe Kleine-König 2022-11-17 12:03 ` Uwe Kleine-König 2022-11-17 13:43 ` Andre Przywara 2022-11-17 13:43 ` Andre Przywara 2022-11-01 14:16 ` [PATCH 3/9] dt-bindings: i2c: mv64xxx: Add F1C100s compatible string Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-02 17:28 ` Rob Herring 2022-11-02 17:28 ` Rob Herring 2022-11-02 20:19 ` Wolfram Sang 2022-11-02 20:19 ` Wolfram Sang 2022-11-01 14:16 ` [PATCH 4/9] ARM: dts: suniv: f1c100s: add I2C DT nodes Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-06 8:09 ` Jernej Škrabec 2022-11-06 8:09 ` Jernej Škrabec 2022-11-06 23:12 ` Andre Przywara 2022-11-06 23:12 ` Andre Przywara 2022-11-01 14:16 ` [PATCH 5/9] clk: sunxi-ng: f1c100s: Add IR mod clock Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-06 8:22 ` Jernej Škrabec 2022-11-06 8:22 ` Jernej Škrabec 2022-11-01 14:16 ` [PATCH 6/9] dt-bindings: media: IR: Add F1C100s IR compatible string Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-02 17:28 ` Rob Herring 2022-11-02 17:28 ` Rob Herring 2022-11-01 14:16 ` [PATCH 7/9] ARM: dts: suniv: f1c100s: add CIR DT node Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-06 8:23 ` Jernej Škrabec 2022-11-06 8:23 ` Jernej Škrabec 2022-11-01 14:16 ` [PATCH 8/9] dt-bindings: input: sun4i-lradc-keys: Add F1C100s compatible Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-02 17:28 ` Rob Herring 2022-11-02 17:28 ` Rob Herring 2022-11-03 20:45 ` Dmitry Torokhov 2022-11-03 20:45 ` Dmitry Torokhov 2022-11-01 14:16 ` [PATCH 9/9] ARM: dts: suniv: f1c100s: add LRADC node Andre Przywara 2022-11-01 14:16 ` Andre Przywara 2022-11-06 8:25 ` Jernej Škrabec [this message] 2022-11-06 8:25 ` Jernej Škrabec
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