* [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-11-30 13:16 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit() Ville Syrjala
` (30 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The ilk fbc watermark computation uses intel_fbc_is_active() which
is racy since we don't know whether FBC will be enabled or not at
some point. So let's just assume it will be if both HAS_FBC()
and the modparam agree.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 01fa3fac1b57..18fbdd204a93 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3369,13 +3369,8 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
}
/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
- /*
- * FIXME this is racy. FBC might get enabled later.
- * What we should check here is whether FBC can be
- * enabled sometime later.
- */
- if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
- intel_fbc_is_active(&dev_priv->fbc)) {
+ if (DISPLAY_VER(dev_priv) == 5 && HAS_FBC(dev_priv) &&
+ dev_priv->params.enable_fbc && !merged->fbc_wm_enabled) {
for (level = 2; level <= max_level; level++) {
struct intel_wm_level *wm = &merged->wm[level];
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
2021-11-24 11:36 ` [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage Ville Syrjala
@ 2021-11-30 13:16 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-11-30 13:16 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy
> intel_fbc_is_active() usage
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The ilk fbc watermark computation uses intel_fbc_is_active() which is racy since
> we don't know whether FBC will be enabled or not at some point. So let's just
> assume it will be if both HAS_FBC() and the modparam agree.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 01fa3fac1b57..18fbdd204a93 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3369,13 +3369,8 @@ static void ilk_wm_merge(struct drm_i915_private
> *dev_priv,
> }
>
> /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled
> */
> - /*
> - * FIXME this is racy. FBC might get enabled later.
> - * What we should check here is whether FBC can be
> - * enabled sometime later.
> - */
> - if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
> - intel_fbc_is_active(&dev_priv->fbc)) {
> + if (DISPLAY_VER(dev_priv) == 5 && HAS_FBC(dev_priv) &&
> + dev_priv->params.enable_fbc && !merged->fbc_wm_enabled) {
> for (level = 2; level <= max_level; level++) {
> struct intel_wm_level *wm = &merged->wm[level];
>
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
2021-11-24 11:36 ` [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-11-30 13:17 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache Ville Syrjala
` (29 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
No reason to burden the caller with the details on how the minimum
compression limit is calculated, so just pass in the whole plane
state instead of just the cpp value.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c..083c0cab4847 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -679,8 +679,10 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
return min(end, intel_fbc_cfb_base_max(i915));
}
-static int intel_fbc_min_limit(int fb_cpp)
+static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
{
+ int fb_cpp = plane_state->hw.fb ? plane_state->hw.fb->format->cpp[0] : 0;
+
return fb_cpp == 2 ? 2 : 1;
}
@@ -1466,8 +1468,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
cache = &fbc->state_cache;
- min_limit = intel_fbc_min_limit(plane_state->hw.fb ?
- plane_state->hw.fb->format->cpp[0] : 0);
+ min_limit = intel_fbc_min_limit(plane_state);
mutex_lock(&fbc->lock);
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
2021-11-24 11:36 ` [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit() Ville Syrjala
@ 2021-11-30 13:17 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-11-30 13:17 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to
> intel_fbc_min_limit()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No reason to burden the caller with the details on how the minimum
> compression limit is calculated, so just pass in the whole plane state instead of
> just the cpp value.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d0c34bc3af6c..083c0cab4847 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -679,8 +679,10 @@ static u64 intel_fbc_stolen_end(struct
> drm_i915_private *i915)
> return min(end, intel_fbc_cfb_base_max(i915)); }
>
> -static int intel_fbc_min_limit(int fb_cpp)
> +static int intel_fbc_min_limit(const struct intel_plane_state
> +*plane_state)
> {
> + int fb_cpp = plane_state->hw.fb ? plane_state->hw.fb->format->cpp[0]
> :
> +0;
> +
> return fb_cpp == 2 ? 2 : 1;
> }
>
> @@ -1466,8 +1468,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
>
> cache = &fbc->state_cache;
>
> - min_limit = intel_fbc_min_limit(plane_state->hw.fb ?
> - plane_state->hw.fb->format->cpp[0] :
> 0);
> + min_limit = intel_fbc_min_limit(plane_state);
>
> mutex_lock(&fbc->lock);
>
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
2021-11-24 11:36 ` [Intel-gfx] [PATCH 01/20] drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage Ville Syrjala
2021-11-24 11:36 ` [Intel-gfx] [PATCH 02/20] drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit() Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-11-30 13:21 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate intel_fbc_override_cfb_stride() Ville Syrjala
` (28 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There's no need to store all this stuff in intel_fbc_state_cache.
Just check it all against the plane/crtc states and store only
what we need. Probably more should get nuked still, but this
is a start.
So what we'll do is:
- each plane will check its own state and update its local
no_fbc_reason
- the per-plane no_fbc_reason (if any) then gets propagated
to the cache->no_fbc_reason while doing the actual update
- fbc->no_fbc_reason gets updated in the end with either
the value from the cache or directly from frontbuffer
tracking
It's still a bit messy, but should hopefuly get cleaned up
more in the future. At least now we can observe each plane's
reasons for rejecting FBC now more consistently, and we don't
have so mcuh redundant state store all over the place.
v2: store no_fbc_reason per-plane instead of per-pipe
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 341 ++++++++----------
drivers/gpu/drm/i915/display/intel_fbc.h | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 20 +-
5 files changed, 166 insertions(+), 207 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b2d51cd79d6c..520a87c814a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8039,7 +8039,6 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- intel_fbc_choose_crtc(dev_priv, state);
ret = intel_compute_global_watermarks(state);
if (ret)
goto fail;
@@ -8071,6 +8070,10 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ ret = intel_fbc_atomic_check(state);
+ if (ret)
+ goto fail;
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (new_crtc_state->uapi.async_flip) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ea1e8a6e10b0..5df477dfb8cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -687,6 +687,8 @@ struct intel_plane_state {
/* Clear Color Value */
u64 ccval;
+
+ const char *no_fbc_reason;
};
struct intel_initial_plane_config {
@@ -1117,8 +1119,6 @@ struct intel_crtc_state {
bool crc_enabled;
- bool enable_fbc;
-
bool double_wide;
int pbn;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 083c0cab4847..8bde3681b96e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -43,6 +43,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
@@ -58,20 +59,6 @@ struct intel_fbc_funcs {
void (*set_false_color)(struct intel_fbc *fbc, bool enable);
};
-/*
- * For SKL+, the plane source size used by the hardware is based on the value we
- * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
- * we wrote to PIPESRC.
- */
-static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
- int *width, int *height)
-{
- if (width)
- *width = cache->plane.src_w;
- if (height)
- *height = cache->plane.src_h;
-}
-
/* plane stride in pixels */
static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
{
@@ -796,9 +783,13 @@ void intel_fbc_cleanup(struct drm_i915_private *i915)
mutex_unlock(&fbc->lock);
}
-static bool stride_is_valid(struct drm_i915_private *i915,
- u64 modifier, unsigned int stride)
+static bool stride_is_valid(const struct intel_plane_state *plane_state)
{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int stride = intel_fbc_plane_stride(plane_state) *
+ fb->format->cpp[0];
+
/* This should have been caught earlier. */
if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
return false;
@@ -815,7 +806,7 @@ static bool stride_is_valid(struct drm_i915_private *i915,
/* Display WA #1105: skl,bxt,kbl,cfl,glk */
if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
- modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
+ fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
return false;
if (stride > 16384)
@@ -824,10 +815,12 @@ static bool stride_is_valid(struct drm_i915_private *i915,
return true;
}
-static bool pixel_format_is_valid(struct drm_i915_private *i915,
- u32 pixel_format)
+static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
{
- switch (pixel_format) {
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ switch (fb->format->format) {
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_XBGR8888:
return true;
@@ -845,10 +838,13 @@ static bool pixel_format_is_valid(struct drm_i915_private *i915,
}
}
-static bool rotation_is_valid(struct drm_i915_private *i915,
- u32 pixel_format, unsigned int rotation)
+static bool rotation_is_valid(const struct intel_plane_state *plane_state)
{
- if (DISPLAY_VER(i915) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int rotation = plane_state->hw.rotation;
+
+ if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
drm_rotation_90_or_270(rotation))
return false;
else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
@@ -864,10 +860,9 @@ static bool rotation_is_valid(struct drm_i915_private *i915,
* the X and Y offset registers. That's why we include the src x/y offsets
* instead of just looking at the plane size.
*/
-static bool intel_fbc_hw_tracking_covers_screen(struct intel_fbc *fbc,
- struct intel_crtc *crtc)
+static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = fbc->i915;
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
unsigned int effective_w, effective_h, max_w, max_h;
if (DISPLAY_VER(i915) >= 10) {
@@ -884,18 +879,20 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_fbc *fbc,
max_h = 1536;
}
- intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
- &effective_h);
- effective_w += fbc->state_cache.plane.adjusted_x;
- effective_h += fbc->state_cache.plane.adjusted_y;
+ effective_w = plane_state->view.color_plane[0].x +
+ (drm_rect_width(&plane_state->uapi.src) >> 16);
+ effective_h = plane_state->view.color_plane[0].y +
+ (drm_rect_height(&plane_state->uapi.src) >> 16);
return effective_w <= max_w && effective_h <= max_h;
}
-static bool tiling_is_valid(struct drm_i915_private *i915,
- u64 modifier)
+static bool tiling_is_valid(const struct intel_plane_state *plane_state)
{
- switch (modifier) {
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
@@ -916,15 +913,10 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
struct intel_fbc_state_cache *cache = &fbc->state_cache;
struct drm_framebuffer *fb = plane_state->hw.fb;
- cache->plane.visible = plane_state->uapi.visible;
- if (!cache->plane.visible)
+ cache->no_fbc_reason = plane_state->no_fbc_reason;
+ if (cache->no_fbc_reason)
return;
- cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
- if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
-
- cache->plane.rotation = plane_state->hw.rotation;
/*
* Src coordinates are already rotated by 270 degrees for
* the 90/270 degree plane rotation cases (to match the
@@ -932,10 +924,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
*/
cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- cache->plane.adjusted_x = plane_state->view.color_plane[0].x;
- cache->plane.adjusted_y = plane_state->view.color_plane[0].y;
-
- cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
cache->fb.format = fb->format;
cache->fb.modifier = fb->modifier;
@@ -954,8 +942,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fence_id = plane_state->ggtt_vma->fence->id;
else
cache->fence_id = -1;
-
- cache->psr2_active = crtc_state->has_psr2;
}
static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
@@ -1007,6 +993,110 @@ static bool intel_fbc_can_enable(struct intel_fbc *fbc)
return true;
}
+static int intel_fbc_check_plane(struct intel_atomic_state *state,
+ struct intel_plane *plane)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
+ const struct intel_crtc_state *crtc_state;
+ struct intel_fbc *fbc = plane->fbc;
+
+ if (!fbc)
+ return 0;
+
+ if (!plane_state->uapi.visible) {
+ plane_state->no_fbc_reason = "plane not visible";
+ return 0;
+ }
+
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ plane_state->no_fbc_reason = "interlaced mode not supported";
+ return 0;
+ }
+
+ /*
+ * Display 12+ is not supporting FBC with PSR2.
+ * Recommendation is to keep this combination disabled
+ * Bspec: 50422 HSD: 14010260002
+ */
+ if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
+ plane_state->no_fbc_reason = "PSR2 enabled";
+ return false;
+ }
+
+ if (!pixel_format_is_valid(plane_state)) {
+ plane_state->no_fbc_reason = "pixel format not supported";
+ return 0;
+ }
+
+ if (!tiling_is_valid(plane_state)) {
+ plane_state->no_fbc_reason = "tiling not supported";
+ return 0;
+ }
+
+ if (!rotation_is_valid(plane_state)) {
+ plane_state->no_fbc_reason = "rotation not supported";
+ return 0;
+ }
+
+ if (!stride_is_valid(plane_state)) {
+ plane_state->no_fbc_reason = "stride not supported";
+ return 0;
+ }
+
+ if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
+ fb->format->has_alpha) {
+ plane_state->no_fbc_reason = "per-pixel alpha not supported";
+ return false;
+ }
+
+ if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
+ plane_state->no_fbc_reason = "plane size too big";
+ return 0;
+ }
+
+ /*
+ * Work around a problem on GEN9+ HW, where enabling FBC on a plane
+ * having a Y offset that isn't divisible by 4 causes FIFO underrun
+ * and screen flicker.
+ */
+ if (DISPLAY_VER(i915) >= 9 &&
+ plane_state->view.color_plane[0].y & 3) {
+ plane_state->no_fbc_reason = "plane start Y offset misaligned";
+ return false;
+ }
+
+ /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
+ if (DISPLAY_VER(i915) >= 11 &&
+ (plane_state->view.color_plane[0].y + drm_rect_height(&plane_state->uapi.src)) & 3) {
+ plane_state->no_fbc_reason = "plane end Y offset misaligned";
+ return false;
+ }
+
+ /* WaFbcExceedCdClockThreshold:hsw,bdw */
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ const struct intel_cdclk_state *cdclk_state;
+
+ cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(cdclk_state))
+ return PTR_ERR(cdclk_state);
+
+ if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
+ plane_state->no_fbc_reason = "pixel rate too high";
+ return 0;
+ }
+ }
+
+ plane_state->no_fbc_reason = NULL;
+
+ return 0;
+}
+
static bool intel_fbc_can_activate(struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -1016,8 +1106,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
if (!intel_fbc_can_enable(fbc))
return false;
- if (!cache->plane.visible) {
- fbc->no_fbc_reason = "primary plane not visible";
+ if (cache->no_fbc_reason) {
+ fbc->no_fbc_reason = cache->no_fbc_reason;
return false;
}
@@ -1029,16 +1119,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
- if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
- fbc->no_fbc_reason = "incompatible mode";
- return false;
- }
-
- if (!intel_fbc_hw_tracking_covers_screen(fbc, crtc)) {
- fbc->no_fbc_reason = "mode too large for compression";
- return false;
- }
-
/* The use of a CPU fence is one of two ways to detect writes by the
* CPU to the scanout and trigger updates to the FBC.
*
@@ -1061,42 +1141,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
- if (!pixel_format_is_valid(i915, cache->fb.format->format)) {
- fbc->no_fbc_reason = "pixel format is invalid";
- return false;
- }
-
- if (!rotation_is_valid(i915, cache->fb.format->format,
- cache->plane.rotation)) {
- fbc->no_fbc_reason = "rotation unsupported";
- return false;
- }
-
- if (!tiling_is_valid(i915, cache->fb.modifier)) {
- fbc->no_fbc_reason = "tiling unsupported";
- return false;
- }
-
- if (!stride_is_valid(i915, cache->fb.modifier,
- cache->fb.stride * cache->fb.format->cpp[0])) {
- fbc->no_fbc_reason = "framebuffer stride not supported";
- return false;
- }
-
- if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
- cache->fb.format->has_alpha) {
- fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
- return false;
- }
-
- /* WaFbcExceedCdClockThreshold:hsw,bdw */
- if ((IS_HASWELL(i915) || IS_BROADWELL(i915)) &&
- cache->crtc.hsw_bdw_pixel_rate >= i915->cdclk.hw.cdclk * 95 / 100) {
- fbc->no_fbc_reason = "pixel rate is too big";
- return false;
- }
-
- /* It is possible for the required CFB size change without a
+ /*
+ * It is possible for the required CFB size change without a
* crtc->disable + crtc->enable since it is possible to change the
* stride without triggering a full modeset. Since we try to
* over-allocate the CFB, there's a chance we may keep FBC enabled even
@@ -1105,40 +1151,13 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
* for a frame, free the stolen node, then try to reenable FBC in case
* we didn't get any invalidate/deactivate calls, but this would require
* a lot of tracking just for a specific case. If we conclude it's an
- * important case, we can implement it later. */
+ * important case, we can implement it later.
+ */
if (intel_fbc_cfb_size_changed(fbc)) {
fbc->no_fbc_reason = "CFB requirements changed";
return false;
}
- /*
- * Work around a problem on GEN9+ HW, where enabling FBC on a plane
- * having a Y offset that isn't divisible by 4 causes FIFO underrun
- * and screen flicker.
- */
- if (DISPLAY_VER(i915) >= 9 &&
- (fbc->state_cache.plane.adjusted_y & 3)) {
- fbc->no_fbc_reason = "plane Y offset is misaligned";
- return false;
- }
-
- /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
- if (DISPLAY_VER(i915) >= 11 &&
- (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
- fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
- return false;
- }
-
- /*
- * Display 12+ is not supporting FBC with PSR2.
- * Recommendation is to keep this combination disabled
- * Bspec: 50422 HSD: 14010260002
- */
- if (fbc->state_cache.psr2_active && DISPLAY_VER(i915) >= 12) {
- fbc->no_fbc_reason = "not supported with PSR2";
- return false;
- }
-
return true;
}
@@ -1157,8 +1176,6 @@ static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
params->fence_y_offset = cache->fence_y_offset;
params->interval = cache->interval;
-
- params->crtc.pipe = crtc->pipe;
params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
params->fb.format = cache->fb.format;
@@ -1168,8 +1185,6 @@ static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
params->cfb_stride = intel_fbc_cfb_stride(fbc, cache);
params->cfb_size = intel_fbc_cfb_size(fbc, cache);
params->override_cfb_stride = intel_fbc_override_cfb_stride(fbc, cache);
-
- params->plane_visible = cache->plane.visible;
}
static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
@@ -1183,9 +1198,6 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
return false;
- if (!params->plane_visible)
- return false;
-
if (!intel_fbc_can_activate(crtc))
return false;
@@ -1381,63 +1393,21 @@ void intel_fbc_flush(struct drm_i915_private *i915,
mutex_unlock(&fbc->lock);
}
-/**
- * intel_fbc_choose_crtc - select a CRTC to enable FBC on
- * @i915: i915 device instance
- * @state: the atomic state structure
- *
- * This function looks at the proposed state for CRTCs and planes, then chooses
- * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
- * true.
- *
- * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
- * enable FBC for the chosen CRTC. If it does, it will set i915->fbc.crtc.
- */
-void intel_fbc_choose_crtc(struct drm_i915_private *i915,
- struct intel_atomic_state *state)
+int intel_fbc_atomic_check(struct intel_atomic_state *state)
{
- struct intel_fbc *fbc = &i915->fbc;
- struct intel_plane *plane;
struct intel_plane_state *plane_state;
- bool crtc_chosen = false;
+ struct intel_plane *plane;
int i;
- mutex_lock(&fbc->lock);
-
- /* Does this atomic commit involve the CRTC currently tied to FBC? */
- if (fbc->crtc &&
- !intel_atomic_get_new_crtc_state(state, fbc->crtc))
- goto out;
-
- if (!intel_fbc_can_enable(fbc))
- goto out;
-
- /* Simply choose the first CRTC that is compatible and has a visible
- * plane. We could go for fancier schemes such as checking the plane
- * size, but this would just affect the few platforms that don't tie FBC
- * to pipe or plane A. */
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
+ int ret;
- if (plane->fbc != fbc)
- continue;
-
- if (!plane_state->uapi.visible)
- continue;
-
- crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-
- crtc_state->enable_fbc = true;
- crtc_chosen = true;
- break;
+ ret = intel_fbc_check_plane(state, plane);
+ if (ret)
+ return ret;
}
- if (!crtc_chosen)
- fbc->no_fbc_reason = "no suitable CRTC for FBC";
-
-out:
- mutex_unlock(&fbc->lock);
+ return 0;
}
/**
@@ -1487,12 +1457,10 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
- /* FIXME crtc_state->enable_fbc lies :( */
- if (!cache->plane.visible)
+ if (cache->no_fbc_reason)
goto out;
if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(fbc, cache), min_limit)) {
- cache->plane.visible = false;
fbc->no_fbc_reason = "not enough stolen memory";
goto out;
}
@@ -1541,10 +1509,17 @@ void intel_fbc_disable(struct intel_crtc *crtc)
void intel_fbc_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ struct intel_fbc *fbc = plane->fbc;
- if (crtc_state->update_pipe && !crtc_state->enable_fbc)
+ if (!fbc || !plane_state)
+ return;
+
+ if (crtc_state->update_pipe && plane_state->no_fbc_reason)
intel_fbc_disable(crtc);
else
intel_fbc_enable(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index ce48a22c5e9e..74492e05a1c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -17,8 +17,7 @@ struct intel_crtc_state;
struct intel_fbc;
struct intel_plane_state;
-void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
- struct intel_atomic_state *state);
+int intel_fbc_atomic_check(struct intel_atomic_state *state);
bool intel_fbc_is_active(struct intel_fbc *fbc);
bool intel_fbc_is_compressing(struct intel_fbc *fbc);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bfadd9127fc..d79aa827d937 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -434,26 +434,11 @@ struct intel_fbc {
* these problems.
*/
struct intel_fbc_state_cache {
- struct {
- unsigned int mode_flags;
- u32 hsw_bdw_pixel_rate;
- } crtc;
+ const char *no_fbc_reason;
struct {
- unsigned int rotation;
int src_w;
int src_h;
- bool visible;
- /*
- * Display surface base address adjustement for
- * pageflips. Note that on gen4+ this only adjusts up
- * to a tile, offsets within a tile are handled in
- * the hw itself (with the TILEOFF register).
- */
- int adjusted_x;
- int adjusted_y;
-
- u16 pixel_blend_mode;
} plane;
struct {
@@ -465,7 +450,6 @@ struct intel_fbc {
unsigned int fence_y_offset;
u16 interval;
s8 fence_id;
- bool psr2_active;
} state_cache;
/*
@@ -477,7 +461,6 @@ struct intel_fbc {
*/
struct intel_fbc_reg_params {
struct {
- enum pipe pipe;
enum i9xx_plane_id i9xx_plane;
} crtc;
@@ -493,7 +476,6 @@ struct intel_fbc {
u16 override_cfb_stride;
u16 interval;
s8 fence_id;
- bool plane_visible;
} params;
const char *no_fbc_reason;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
2021-11-24 11:36 ` [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache Ville Syrjala
@ 2021-11-30 13:21 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-11-30 13:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from
> intel_fbc_state_cache
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's no need to store all this stuff in intel_fbc_state_cache.
> Just check it all against the plane/crtc states and store only what we need.
> Probably more should get nuked still, but this is a start.
>
> So what we'll do is:
> - each plane will check its own state and update its local
> no_fbc_reason
> - the per-plane no_fbc_reason (if any) then gets propagated
> to the cache->no_fbc_reason while doing the actual update
> - fbc->no_fbc_reason gets updated in the end with either
> the value from the cache or directly from frontbuffer
> tracking
>
> It's still a bit messy, but should hopefuly get cleaned up more in the future. At
> least now we can observe each plane's reasons for rejecting FBC now more
> consistently, and we don't have so mcuh redundant state store all over the
> place.
>
> v2: store no_fbc_reason per-plane instead of per-pipe
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 341 ++++++++----------
> drivers/gpu/drm/i915/display/intel_fbc.h | 3 +-
> drivers/gpu/drm/i915/i915_drv.h | 20 +-
> 5 files changed, 166 insertions(+), 207 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b2d51cd79d6c..520a87c814a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8039,7 +8039,6 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> - intel_fbc_choose_crtc(dev_priv, state);
> ret = intel_compute_global_watermarks(state);
> if (ret)
> goto fail;
> @@ -8071,6 +8070,10 @@ static int intel_atomic_check(struct drm_device
> *dev,
> if (ret)
> goto fail;
>
> + ret = intel_fbc_atomic_check(state);
> + if (ret)
> + goto fail;
> +
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (new_crtc_state->uapi.async_flip) { diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ea1e8a6e10b0..5df477dfb8cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -687,6 +687,8 @@ struct intel_plane_state {
>
> /* Clear Color Value */
> u64 ccval;
> +
> + const char *no_fbc_reason;
> };
>
> struct intel_initial_plane_config {
> @@ -1117,8 +1119,6 @@ struct intel_crtc_state {
>
> bool crc_enabled;
>
> - bool enable_fbc;
> -
> bool double_wide;
>
> int pbn;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 083c0cab4847..8bde3681b96e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -43,6 +43,7 @@
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> +#include "intel_cdclk.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> @@ -58,20 +59,6 @@ struct intel_fbc_funcs {
> void (*set_false_color)(struct intel_fbc *fbc, bool enable); };
>
> -/*
> - * For SKL+, the plane source size used by the hardware is based on the value
> we
> - * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
> - * we wrote to PIPESRC.
> - */
> -static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache
> *cache,
> - int *width, int *height)
> -{
> - if (width)
> - *width = cache->plane.src_w;
> - if (height)
> - *height = cache->plane.src_h;
> -}
> -
> /* plane stride in pixels */
> static unsigned int intel_fbc_plane_stride(const struct intel_plane_state
> *plane_state) { @@ -796,9 +783,13 @@ void intel_fbc_cleanup(struct
> drm_i915_private *i915)
> mutex_unlock(&fbc->lock);
> }
>
> -static bool stride_is_valid(struct drm_i915_private *i915,
> - u64 modifier, unsigned int stride)
> +static bool stride_is_valid(const struct intel_plane_state
> +*plane_state)
> {
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + unsigned int stride = intel_fbc_plane_stride(plane_state) *
> + fb->format->cpp[0];
> +
> /* This should have been caught earlier. */
> if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
> return false;
> @@ -815,7 +806,7 @@ static bool stride_is_valid(struct drm_i915_private
> *i915,
>
> /* Display WA #1105: skl,bxt,kbl,cfl,glk */
> if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
> - modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
> + fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
> return false;
>
> if (stride > 16384)
> @@ -824,10 +815,12 @@ static bool stride_is_valid(struct drm_i915_private
> *i915,
> return true;
> }
>
> -static bool pixel_format_is_valid(struct drm_i915_private *i915,
> - u32 pixel_format)
> +static bool pixel_format_is_valid(const struct intel_plane_state
> +*plane_state)
> {
> - switch (pixel_format) {
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> + switch (fb->format->format) {
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_XBGR8888:
> return true;
> @@ -845,10 +838,13 @@ static bool pixel_format_is_valid(struct
> drm_i915_private *i915,
> }
> }
>
> -static bool rotation_is_valid(struct drm_i915_private *i915,
> - u32 pixel_format, unsigned int rotation)
> +static bool rotation_is_valid(const struct intel_plane_state
> +*plane_state)
> {
> - if (DISPLAY_VER(i915) >= 9 && pixel_format == DRM_FORMAT_RGB565
> &&
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + unsigned int rotation = plane_state->hw.rotation;
> +
> + if (DISPLAY_VER(i915) >= 9 && fb->format->format ==
> DRM_FORMAT_RGB565
> +&&
> drm_rotation_90_or_270(rotation))
> return false;
> else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) && @@ -864,10
> +860,9 @@ static bool rotation_is_valid(struct drm_i915_private *i915,
> * the X and Y offset registers. That's why we include the src x/y offsets
> * instead of just looking at the plane size.
> */
> -static bool intel_fbc_hw_tracking_covers_screen(struct intel_fbc *fbc,
> - struct intel_crtc *crtc)
> +static bool intel_fbc_hw_tracking_covers_screen(const struct
> +intel_plane_state *plane_state)
> {
> - struct drm_i915_private *i915 = fbc->i915;
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> unsigned int effective_w, effective_h, max_w, max_h;
>
> if (DISPLAY_VER(i915) >= 10) {
> @@ -884,18 +879,20 @@ static bool
> intel_fbc_hw_tracking_covers_screen(struct intel_fbc *fbc,
> max_h = 1536;
> }
>
> - intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
> - &effective_h);
> - effective_w += fbc->state_cache.plane.adjusted_x;
> - effective_h += fbc->state_cache.plane.adjusted_y;
> + effective_w = plane_state->view.color_plane[0].x +
> + (drm_rect_width(&plane_state->uapi.src) >> 16);
> + effective_h = plane_state->view.color_plane[0].y +
> + (drm_rect_height(&plane_state->uapi.src) >> 16);
>
> return effective_w <= max_w && effective_h <= max_h; }
>
> -static bool tiling_is_valid(struct drm_i915_private *i915,
> - u64 modifier)
> +static bool tiling_is_valid(const struct intel_plane_state
> +*plane_state)
> {
> - switch (modifier) {
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> + switch (fb->modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -916,15 +913,10 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
> struct drm_framebuffer *fb = plane_state->hw.fb;
>
> - cache->plane.visible = plane_state->uapi.visible;
> - if (!cache->plane.visible)
> + cache->no_fbc_reason = plane_state->no_fbc_reason;
> + if (cache->no_fbc_reason)
> return;
>
> - cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
> - if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
> -
> - cache->plane.rotation = plane_state->hw.rotation;
> /*
> * Src coordinates are already rotated by 270 degrees for
> * the 90/270 degree plane rotation cases (to match the @@ -932,10
> +924,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> */
> cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - cache->plane.adjusted_x = plane_state->view.color_plane[0].x;
> - cache->plane.adjusted_y = plane_state->view.color_plane[0].y;
> -
> - cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
>
> cache->fb.format = fb->format;
> cache->fb.modifier = fb->modifier;
> @@ -954,8 +942,6 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> cache->fence_id = plane_state->ggtt_vma->fence->id;
> else
> cache->fence_id = -1;
> -
> - cache->psr2_active = crtc_state->has_psr2;
> }
>
> static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc) @@ -1007,6
> +993,110 @@ static bool intel_fbc_can_enable(struct intel_fbc *fbc)
> return true;
> }
>
> +static int intel_fbc_check_plane(struct intel_atomic_state *state,
> + struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_plane_state *plane_state =
> + intel_atomic_get_new_plane_state(state, plane);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
> + const struct intel_crtc_state *crtc_state;
> + struct intel_fbc *fbc = plane->fbc;
> +
> + if (!fbc)
> + return 0;
> +
> + if (!plane_state->uapi.visible) {
> + plane_state->no_fbc_reason = "plane not visible";
> + return 0;
> + }
> +
> + crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (crtc_state->hw.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE) {
> + plane_state->no_fbc_reason = "interlaced mode not
> supported";
> + return 0;
> + }
> +
> + /*
> + * Display 12+ is not supporting FBC with PSR2.
> + * Recommendation is to keep this combination disabled
> + * Bspec: 50422 HSD: 14010260002
> + */
> + if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
> + plane_state->no_fbc_reason = "PSR2 enabled";
> + return false;
> + }
> +
> + if (!pixel_format_is_valid(plane_state)) {
> + plane_state->no_fbc_reason = "pixel format not supported";
> + return 0;
> + }
> +
> + if (!tiling_is_valid(plane_state)) {
> + plane_state->no_fbc_reason = "tiling not supported";
> + return 0;
> + }
> +
> + if (!rotation_is_valid(plane_state)) {
> + plane_state->no_fbc_reason = "rotation not supported";
> + return 0;
> + }
> +
> + if (!stride_is_valid(plane_state)) {
> + plane_state->no_fbc_reason = "stride not supported";
> + return 0;
> + }
> +
> + if (plane_state->hw.pixel_blend_mode !=
> DRM_MODE_BLEND_PIXEL_NONE &&
> + fb->format->has_alpha) {
> + plane_state->no_fbc_reason = "per-pixel alpha not supported";
> + return false;
> + }
> +
> + if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
> + plane_state->no_fbc_reason = "plane size too big";
> + return 0;
> + }
> +
> + /*
> + * Work around a problem on GEN9+ HW, where enabling FBC on a
> plane
> + * having a Y offset that isn't divisible by 4 causes FIFO underrun
> + * and screen flicker.
> + */
> + if (DISPLAY_VER(i915) >= 9 &&
> + plane_state->view.color_plane[0].y & 3) {
> + plane_state->no_fbc_reason = "plane start Y offset misaligned";
> + return false;
> + }
> +
> + /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
> + if (DISPLAY_VER(i915) >= 11 &&
> + (plane_state->view.color_plane[0].y +
> drm_rect_height(&plane_state->uapi.src)) & 3) {
> + plane_state->no_fbc_reason = "plane end Y offset misaligned";
> + return false;
> + }
> +
> + /* WaFbcExceedCdClockThreshold:hsw,bdw */
> + if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> + const struct intel_cdclk_state *cdclk_state;
> +
> + cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(cdclk_state))
> + return PTR_ERR(cdclk_state);
> +
> + if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 /
> 100) {
> + plane_state->no_fbc_reason = "pixel rate too high";
> + return 0;
> + }
> + }
> +
> + plane_state->no_fbc_reason = NULL;
> +
> + return 0;
> +}
> +
> static bool intel_fbc_can_activate(struct intel_crtc *crtc) {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -1016,8
> +1106,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> if (!intel_fbc_can_enable(fbc))
> return false;
>
> - if (!cache->plane.visible) {
> - fbc->no_fbc_reason = "primary plane not visible";
> + if (cache->no_fbc_reason) {
> + fbc->no_fbc_reason = cache->no_fbc_reason;
> return false;
> }
>
> @@ -1029,16 +1119,6 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> return false;
> }
>
> - if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
> - fbc->no_fbc_reason = "incompatible mode";
> - return false;
> - }
> -
> - if (!intel_fbc_hw_tracking_covers_screen(fbc, crtc)) {
> - fbc->no_fbc_reason = "mode too large for compression";
> - return false;
> - }
> -
> /* The use of a CPU fence is one of two ways to detect writes by the
> * CPU to the scanout and trigger updates to the FBC.
> *
> @@ -1061,42 +1141,8 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> return false;
> }
>
> - if (!pixel_format_is_valid(i915, cache->fb.format->format)) {
> - fbc->no_fbc_reason = "pixel format is invalid";
> - return false;
> - }
> -
> - if (!rotation_is_valid(i915, cache->fb.format->format,
> - cache->plane.rotation)) {
> - fbc->no_fbc_reason = "rotation unsupported";
> - return false;
> - }
> -
> - if (!tiling_is_valid(i915, cache->fb.modifier)) {
> - fbc->no_fbc_reason = "tiling unsupported";
> - return false;
> - }
> -
> - if (!stride_is_valid(i915, cache->fb.modifier,
> - cache->fb.stride * cache->fb.format->cpp[0])) {
> - fbc->no_fbc_reason = "framebuffer stride not supported";
> - return false;
> - }
> -
> - if (cache->plane.pixel_blend_mode !=
> DRM_MODE_BLEND_PIXEL_NONE &&
> - cache->fb.format->has_alpha) {
> - fbc->no_fbc_reason = "per-pixel alpha blending is incompatible
> with FBC";
> - return false;
> - }
> -
> - /* WaFbcExceedCdClockThreshold:hsw,bdw */
> - if ((IS_HASWELL(i915) || IS_BROADWELL(i915)) &&
> - cache->crtc.hsw_bdw_pixel_rate >= i915->cdclk.hw.cdclk * 95 / 100) {
> - fbc->no_fbc_reason = "pixel rate is too big";
> - return false;
> - }
> -
> - /* It is possible for the required CFB size change without a
> + /*
> + * It is possible for the required CFB size change without a
> * crtc->disable + crtc->enable since it is possible to change the
> * stride without triggering a full modeset. Since we try to
> * over-allocate the CFB, there's a chance we may keep FBC enabled
> even @@ -1105,40 +1151,13 @@ static bool intel_fbc_can_activate(struct
> intel_crtc *crtc)
> * for a frame, free the stolen node, then try to reenable FBC in case
> * we didn't get any invalidate/deactivate calls, but this would require
> * a lot of tracking just for a specific case. If we conclude it's an
> - * important case, we can implement it later. */
> + * important case, we can implement it later.
> + */
> if (intel_fbc_cfb_size_changed(fbc)) {
> fbc->no_fbc_reason = "CFB requirements changed";
> return false;
> }
>
> - /*
> - * Work around a problem on GEN9+ HW, where enabling FBC on a
> plane
> - * having a Y offset that isn't divisible by 4 causes FIFO underrun
> - * and screen flicker.
> - */
> - if (DISPLAY_VER(i915) >= 9 &&
> - (fbc->state_cache.plane.adjusted_y & 3)) {
> - fbc->no_fbc_reason = "plane Y offset is misaligned";
> - return false;
> - }
> -
> - /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
> - if (DISPLAY_VER(i915) >= 11 &&
> - (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
> - fbc->no_fbc_reason = "plane height + offset is non-modulo of
> 4";
> - return false;
> - }
> -
> - /*
> - * Display 12+ is not supporting FBC with PSR2.
> - * Recommendation is to keep this combination disabled
> - * Bspec: 50422 HSD: 14010260002
> - */
> - if (fbc->state_cache.psr2_active && DISPLAY_VER(i915) >= 12) {
> - fbc->no_fbc_reason = "not supported with PSR2";
> - return false;
> - }
> -
> return true;
> }
>
> @@ -1157,8 +1176,6 @@ static void intel_fbc_get_reg_params(struct intel_fbc
> *fbc,
> params->fence_y_offset = cache->fence_y_offset;
>
> params->interval = cache->interval;
> -
> - params->crtc.pipe = crtc->pipe;
> params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)-
> >i9xx_plane;
>
> params->fb.format = cache->fb.format;
> @@ -1168,8 +1185,6 @@ static void intel_fbc_get_reg_params(struct intel_fbc
> *fbc,
> params->cfb_stride = intel_fbc_cfb_stride(fbc, cache);
> params->cfb_size = intel_fbc_cfb_size(fbc, cache);
> params->override_cfb_stride = intel_fbc_override_cfb_stride(fbc,
> cache);
> -
> - params->plane_visible = cache->plane.visible;
> }
>
> static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
> @@ -1183,9 +1198,6 @@ static bool intel_fbc_can_flip_nuke(const struct
> intel_crtc_state *crtc_state)
> if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> return false;
>
> - if (!params->plane_visible)
> - return false;
> -
> if (!intel_fbc_can_activate(crtc))
> return false;
>
> @@ -1381,63 +1393,21 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> mutex_unlock(&fbc->lock);
> }
>
> -/**
> - * intel_fbc_choose_crtc - select a CRTC to enable FBC on
> - * @i915: i915 device instance
> - * @state: the atomic state structure
> - *
> - * This function looks at the proposed state for CRTCs and planes, then chooses
> - * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
> - * true.
> - *
> - * Later, intel_fbc_enable is going to look for state->enable_fbc and then
> maybe
> - * enable FBC for the chosen CRTC. If it does, it will set i915->fbc.crtc.
> - */
> -void intel_fbc_choose_crtc(struct drm_i915_private *i915,
> - struct intel_atomic_state *state)
> +int intel_fbc_atomic_check(struct intel_atomic_state *state)
> {
> - struct intel_fbc *fbc = &i915->fbc;
> - struct intel_plane *plane;
> struct intel_plane_state *plane_state;
> - bool crtc_chosen = false;
> + struct intel_plane *plane;
> int i;
>
> - mutex_lock(&fbc->lock);
> -
> - /* Does this atomic commit involve the CRTC currently tied to FBC? */
> - if (fbc->crtc &&
> - !intel_atomic_get_new_crtc_state(state, fbc->crtc))
> - goto out;
> -
> - if (!intel_fbc_can_enable(fbc))
> - goto out;
> -
> - /* Simply choose the first CRTC that is compatible and has a visible
> - * plane. We could go for fancier schemes such as checking the plane
> - * size, but this would just affect the few platforms that don't tie FBC
> - * to pipe or plane A. */
> for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> - struct intel_crtc_state *crtc_state;
> - struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
> + int ret;
>
> - if (plane->fbc != fbc)
> - continue;
> -
> - if (!plane_state->uapi.visible)
> - continue;
> -
> - crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> -
> - crtc_state->enable_fbc = true;
> - crtc_chosen = true;
> - break;
> + ret = intel_fbc_check_plane(state, plane);
> + if (ret)
> + return ret;
> }
>
> - if (!crtc_chosen)
> - fbc->no_fbc_reason = "no suitable CRTC for FBC";
> -
> -out:
> - mutex_unlock(&fbc->lock);
> + return 0;
> }
>
> /**
> @@ -1487,12 +1457,10 @@ static void intel_fbc_enable(struct
> intel_atomic_state *state,
>
> intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
>
> - /* FIXME crtc_state->enable_fbc lies :( */
> - if (!cache->plane.visible)
> + if (cache->no_fbc_reason)
> goto out;
>
> if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(fbc, cache), min_limit)) {
> - cache->plane.visible = false;
> fbc->no_fbc_reason = "not enough stolen memory";
> goto out;
> }
> @@ -1541,10 +1509,17 @@ void intel_fbc_disable(struct intel_crtc *crtc) void
> intel_fbc_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> const struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_plane_state *plane_state =
> + intel_atomic_get_new_plane_state(state, plane);
> + struct intel_fbc *fbc = plane->fbc;
>
> - if (crtc_state->update_pipe && !crtc_state->enable_fbc)
> + if (!fbc || !plane_state)
> + return;
> +
> + if (crtc_state->update_pipe && plane_state->no_fbc_reason)
> intel_fbc_disable(crtc);
> else
> intel_fbc_enable(state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index ce48a22c5e9e..74492e05a1c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -17,8 +17,7 @@ struct intel_crtc_state; struct intel_fbc; struct
> intel_plane_state;
>
> -void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
> - struct intel_atomic_state *state);
> +int intel_fbc_atomic_check(struct intel_atomic_state *state);
> bool intel_fbc_is_active(struct intel_fbc *fbc); bool
> intel_fbc_is_compressing(struct intel_fbc *fbc); bool
> intel_fbc_pre_update(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index
> 1bfadd9127fc..d79aa827d937 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -434,26 +434,11 @@ struct intel_fbc {
> * these problems.
> */
> struct intel_fbc_state_cache {
> - struct {
> - unsigned int mode_flags;
> - u32 hsw_bdw_pixel_rate;
> - } crtc;
> + const char *no_fbc_reason;
>
> struct {
> - unsigned int rotation;
> int src_w;
> int src_h;
> - bool visible;
> - /*
> - * Display surface base address adjustement for
> - * pageflips. Note that on gen4+ this only adjusts up
> - * to a tile, offsets within a tile are handled in
> - * the hw itself (with the TILEOFF register).
> - */
> - int adjusted_x;
> - int adjusted_y;
> -
> - u16 pixel_blend_mode;
> } plane;
>
> struct {
> @@ -465,7 +450,6 @@ struct intel_fbc {
> unsigned int fence_y_offset;
> u16 interval;
> s8 fence_id;
> - bool psr2_active;
> } state_cache;
>
> /*
> @@ -477,7 +461,6 @@ struct intel_fbc {
> */
> struct intel_fbc_reg_params {
> struct {
> - enum pipe pipe;
> enum i9xx_plane_id i9xx_plane;
> } crtc;
>
> @@ -493,7 +476,6 @@ struct intel_fbc {
> u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> - bool plane_visible;
> } params;
>
> const char *no_fbc_reason;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (2 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 03/20] drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-11-30 13:22 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state Ville Syrjala
` (27 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move intel_fbc_override_cfb_stride() next to its cousins.
Helps with later patches.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 42 ++++++++++++------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8bde3681b96e..6368dddf977c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -142,6 +142,27 @@ static unsigned int intel_fbc_cfb_size(struct intel_fbc *fbc,
return lines * intel_fbc_cfb_stride(fbc, cache);
}
+static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
+ const struct intel_fbc_state_cache *cache)
+{
+ unsigned int stride = _intel_fbc_cfb_stride(cache);
+ unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
+
+ /*
+ * Override stride in 64 byte units per 4 line segment.
+ *
+ * Gen9 hw miscalculates cfb stride for linear as
+ * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
+ * we always need to use the override there.
+ */
+ if (stride != stride_aligned ||
+ (DISPLAY_VER(fbc->i915) == 9 &&
+ cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
+ return stride_aligned * 4 / 64;
+
+ return 0;
+}
+
static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
{
const struct intel_fbc_reg_params *params = &fbc->params;
@@ -950,27 +971,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
fbc->compressed_fb.size * fbc->limit;
}
-static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
- const struct intel_fbc_state_cache *cache)
-{
- unsigned int stride = _intel_fbc_cfb_stride(cache);
- unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
-
- /*
- * Override stride in 64 byte units per 4 line segment.
- *
- * Gen9 hw miscalculates cfb stride for linear as
- * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
- * we always need to use the override there.
- */
- if (stride != stride_aligned ||
- (DISPLAY_VER(fbc->i915) == 9 &&
- cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
- return stride_aligned * 4 / 64;
-
- return 0;
-}
-
static bool intel_fbc_can_enable(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
2021-11-24 11:36 ` [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate intel_fbc_override_cfb_stride() Ville Syrjala
@ 2021-11-30 13:22 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-11-30 13:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate
> intel_fbc_override_cfb_stride()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move intel_fbc_override_cfb_stride() next to its cousins.
> Helps with later patches.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 42 ++++++++++++------------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 8bde3681b96e..6368dddf977c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -142,6 +142,27 @@ static unsigned int intel_fbc_cfb_size(struct intel_fbc
> *fbc,
> return lines * intel_fbc_cfb_stride(fbc, cache); }
>
> +static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
> + const struct intel_fbc_state_cache
> *cache) {
> + unsigned int stride = _intel_fbc_cfb_stride(cache);
> + unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
> +
> + /*
> + * Override stride in 64 byte units per 4 line segment.
> + *
> + * Gen9 hw miscalculates cfb stride for linear as
> + * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
> + * we always need to use the override there.
> + */
> + if (stride != stride_aligned ||
> + (DISPLAY_VER(fbc->i915) == 9 &&
> + cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> + return stride_aligned * 4 / 64;
> +
> + return 0;
> +}
> +
> static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) {
> const struct intel_fbc_reg_params *params = &fbc->params; @@ -
> 950,27 +971,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
> fbc->compressed_fb.size * fbc->limit; }
>
> -static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
> - const struct intel_fbc_state_cache
> *cache)
> -{
> - unsigned int stride = _intel_fbc_cfb_stride(cache);
> - unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
> -
> - /*
> - * Override stride in 64 byte units per 4 line segment.
> - *
> - * Gen9 hw miscalculates cfb stride for linear as
> - * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
> - * we always need to use the override there.
> - */
> - if (stride != stride_aligned ||
> - (DISPLAY_VER(fbc->i915) == 9 &&
> - cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> - return stride_aligned * 4 / 64;
> -
> - return 0;
> -}
> -
> static bool intel_fbc_can_enable(struct intel_fbc *fbc) {
> struct drm_i915_private *i915 = fbc->i915;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (3 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 04/20] drm/i915/fbc: Relocate intel_fbc_override_cfb_stride() Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 9:44 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params Ville Syrjala
` (26 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There isn't a good reason why we'd have to cache all this
plane state stuff in the FBC state. Instead we can just
pre-calculate what FBC will really need.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 132 +++++++++++------------
drivers/gpu/drm/i915/i915_drv.h | 20 +---
2 files changed, 67 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 6368dddf977c..1e8b75cdfad8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -73,25 +73,25 @@ static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane
}
/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
-static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache *cache)
+static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
{
unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
- return cache->fb.stride * cpp;
+ return intel_fbc_plane_stride(plane_state) * cpp;
}
/* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
-static unsigned int skl_fbc_min_cfb_stride(struct intel_fbc *fbc,
- const struct intel_fbc_state_cache *cache)
+static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = fbc->i915;
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
unsigned int limit = 4; /* 1:4 compression limit is the worst case */
unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
+ unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
unsigned int height = 4; /* FBC segment is 4 lines */
unsigned int stride;
/* minimum segment stride we can use */
- stride = cache->plane.src_w * cpp * height / limit;
+ stride = width * cpp * height / limit;
/*
* Wa_16011863758: icl+
@@ -111,11 +111,10 @@ static unsigned int skl_fbc_min_cfb_stride(struct intel_fbc *fbc,
}
/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
-static unsigned int intel_fbc_cfb_stride(struct intel_fbc *fbc,
- const struct intel_fbc_state_cache *cache)
+static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = fbc->i915;
- unsigned int stride = _intel_fbc_cfb_stride(cache);
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ unsigned int stride = _intel_fbc_cfb_stride(plane_state);
/*
* At least some of the platforms require each 4 line segment to
@@ -123,30 +122,30 @@ static unsigned int intel_fbc_cfb_stride(struct intel_fbc *fbc,
* that regardless of the compression limit we choose later.
*/
if (DISPLAY_VER(i915) >= 9)
- return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(fbc, cache));
+ return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
else
return stride;
}
-static unsigned int intel_fbc_cfb_size(struct intel_fbc *fbc,
- const struct intel_fbc_state_cache *cache)
+static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = fbc->i915;
- int lines = cache->plane.src_h;
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
if (DISPLAY_VER(i915) == 7)
lines = min(lines, 2048);
else if (DISPLAY_VER(i915) >= 8)
lines = min(lines, 2560);
- return lines * intel_fbc_cfb_stride(fbc, cache);
+ return lines * intel_fbc_cfb_stride(plane_state);
}
-static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
- const struct intel_fbc_state_cache *cache)
+static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
{
- unsigned int stride = _intel_fbc_cfb_stride(cache);
- unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
+ unsigned int stride = _intel_fbc_cfb_stride(plane_state);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
/*
* Override stride in 64 byte units per 4 line segment.
@@ -156,8 +155,7 @@ static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
* we always need to use the override there.
*/
if (stride != stride_aligned ||
- (DISPLAY_VER(fbc->i915) == 9 &&
- cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
+ (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
return stride_aligned * 4 / 64;
return 0;
@@ -925,31 +923,22 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
}
}
-static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_plane *plane)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &i915->fbc;
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ struct intel_fbc *fbc = plane->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
- struct drm_framebuffer *fb = plane_state->hw.fb;
cache->no_fbc_reason = plane_state->no_fbc_reason;
if (cache->no_fbc_reason)
return;
- /*
- * Src coordinates are already rotated by 270 degrees for
- * the 90/270 degree plane rotation cases (to match the
- * GTT mapping), hence no need to account for rotation here.
- */
- cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
- cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
-
- cache->fb.format = fb->format;
- cache->fb.modifier = fb->modifier;
- cache->fb.stride = intel_fbc_plane_stride(plane_state);
-
/* FBC1 compression interval: arbitrary choice of 1 second */
cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
@@ -963,12 +952,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fence_id = plane_state->ggtt_vma->fence->id;
else
cache->fence_id = -1;
+
+ cache->cfb_stride = intel_fbc_cfb_stride(plane_state);
+ cache->cfb_size = intel_fbc_cfb_size(plane_state);
+ cache->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
}
static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
{
- return intel_fbc_cfb_size(fbc, &fbc->state_cache) >
- fbc->compressed_fb.size * fbc->limit;
+ return fbc->state_cache.cfb_size > fbc->compressed_fb.size * fbc->limit;
}
static bool intel_fbc_can_enable(struct intel_fbc *fbc)
@@ -1178,45 +1170,53 @@ static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
params->interval = cache->interval;
params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
- params->fb.format = cache->fb.format;
- params->fb.modifier = cache->fb.modifier;
- params->fb.stride = cache->fb.stride;
-
- params->cfb_stride = intel_fbc_cfb_stride(fbc, cache);
- params->cfb_size = intel_fbc_cfb_size(fbc, cache);
- params->override_cfb_stride = intel_fbc_override_cfb_stride(fbc, cache);
+ params->cfb_stride = cache->cfb_stride;
+ params->cfb_size = cache->cfb_size;
+ params->override_cfb_stride = cache->override_cfb_stride;
}
-static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
+static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_plane *plane)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = plane->fbc;
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ const struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
+ const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
const struct intel_fbc_state_cache *cache = &fbc->state_cache;
const struct intel_fbc_reg_params *params = &fbc->params;
- if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
return false;
if (!intel_fbc_can_activate(crtc))
return false;
- if (params->fb.format != cache->fb.format)
+ if (!old_fb || !new_fb)
return false;
- if (params->fb.modifier != cache->fb.modifier)
+ if (old_fb->format->format != new_fb->format->format)
return false;
- if (params->fb.stride != cache->fb.stride)
+ if (old_fb->modifier != new_fb->modifier)
return false;
- if (params->cfb_stride != intel_fbc_cfb_stride(fbc, cache))
+ if (intel_fbc_plane_stride(old_plane_state) !=
+ intel_fbc_plane_stride(new_plane_state))
return false;
- if (params->cfb_size != intel_fbc_cfb_size(fbc, cache))
+ if (params->cfb_stride != cache->cfb_stride)
return false;
- if (params->override_cfb_stride != intel_fbc_override_cfb_stride(fbc, cache))
+ if (params->cfb_size != cache->cfb_size)
+ return false;
+
+ if (params->override_cfb_stride != cache->override_cfb_stride)
return false;
return true;
@@ -1226,8 +1226,6 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -1243,10 +1241,10 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
if (fbc->crtc != crtc)
goto unlock;
- intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
+ intel_fbc_update_state_cache(state, crtc, plane);
fbc->flip_pending = true;
- if (!intel_fbc_can_flip_nuke(crtc_state)) {
+ if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
intel_fbc_deactivate(fbc, reason);
/*
@@ -1425,8 +1423,6 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- const struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
@@ -1455,12 +1451,12 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
drm_WARN_ON(&i915->drm, fbc->active);
- intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
+ intel_fbc_update_state_cache(state, crtc, plane);
if (cache->no_fbc_reason)
goto out;
- if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(fbc, cache), min_limit)) {
+ if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
fbc->no_fbc_reason = "not enough stolen memory";
goto out;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d79aa827d937..66fa46d41fa5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -436,18 +436,10 @@ struct intel_fbc {
struct intel_fbc_state_cache {
const char *no_fbc_reason;
- struct {
- int src_w;
- int src_h;
- } plane;
-
- struct {
- const struct drm_format_info *format;
- unsigned int stride;
- u64 modifier;
- } fb;
-
+ unsigned int cfb_stride;
+ unsigned int cfb_size;
unsigned int fence_y_offset;
+ u16 override_cfb_stride;
u16 interval;
s8 fence_id;
} state_cache;
@@ -464,12 +456,6 @@ struct intel_fbc {
enum i9xx_plane_id i9xx_plane;
} crtc;
- struct {
- const struct drm_format_info *format;
- unsigned int stride;
- u64 modifier;
- } fb;
-
unsigned int cfb_stride;
unsigned int cfb_size;
unsigned int fence_y_offset;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state
2021-11-24 11:36 ` [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state Ville Syrjala
@ 2021-12-01 9:44 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 9:44 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There isn't a good reason why we'd have to cache all this plane state stuff in the
> FBC state. Instead we can just pre-calculate what FBC will really need.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 132 +++++++++++------------
> drivers/gpu/drm/i915/i915_drv.h | 20 +---
> 2 files changed, 67 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 6368dddf977c..1e8b75cdfad8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -73,25 +73,25 @@ static unsigned int intel_fbc_plane_stride(const struct
> intel_plane_state *plane }
>
> /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ -
> static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache
> *cache)
> +static unsigned int _intel_fbc_cfb_stride(const struct
> +intel_plane_state *plane_state)
> {
> unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
>
> - return cache->fb.stride * cpp;
> + return intel_fbc_plane_stride(plane_state) * cpp;
> }
>
> /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ -
> static unsigned int skl_fbc_min_cfb_stride(struct intel_fbc *fbc,
> - const struct intel_fbc_state_cache
> *cache)
> +static unsigned int skl_fbc_min_cfb_stride(const struct
> +intel_plane_state *plane_state)
> {
> - struct drm_i915_private *i915 = fbc->i915;
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> unsigned int limit = 4; /* 1:4 compression limit is the worst case */
> unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
> + unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
> unsigned int height = 4; /* FBC segment is 4 lines */
> unsigned int stride;
>
> /* minimum segment stride we can use */
> - stride = cache->plane.src_w * cpp * height / limit;
> + stride = width * cpp * height / limit;
>
> /*
> * Wa_16011863758: icl+
> @@ -111,11 +111,10 @@ static unsigned int skl_fbc_min_cfb_stride(struct
> intel_fbc *fbc, }
>
> /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ -static
> unsigned int intel_fbc_cfb_stride(struct intel_fbc *fbc,
> - const struct intel_fbc_state_cache
> *cache)
> +static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state
> +*plane_state)
> {
> - struct drm_i915_private *i915 = fbc->i915;
> - unsigned int stride = _intel_fbc_cfb_stride(cache);
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + unsigned int stride = _intel_fbc_cfb_stride(plane_state);
>
> /*
> * At least some of the platforms require each 4 line segment to @@ -
> 123,30 +122,30 @@ static unsigned int intel_fbc_cfb_stride(struct intel_fbc
> *fbc,
> * that regardless of the compression limit we choose later.
> */
> if (DISPLAY_VER(i915) >= 9)
> - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(fbc,
> cache));
> + return max(ALIGN(stride, 512),
> skl_fbc_min_cfb_stride(plane_state));
> else
> return stride;
> }
>
> -static unsigned int intel_fbc_cfb_size(struct intel_fbc *fbc,
> - const struct intel_fbc_state_cache *cache)
> +static unsigned int intel_fbc_cfb_size(const struct intel_plane_state
> +*plane_state)
> {
> - struct drm_i915_private *i915 = fbc->i915;
> - int lines = cache->plane.src_h;
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
>
> if (DISPLAY_VER(i915) == 7)
> lines = min(lines, 2048);
> else if (DISPLAY_VER(i915) >= 8)
> lines = min(lines, 2560);
>
> - return lines * intel_fbc_cfb_stride(fbc, cache);
> + return lines * intel_fbc_cfb_stride(plane_state);
> }
>
> -static u16 intel_fbc_override_cfb_stride(struct intel_fbc *fbc,
> - const struct intel_fbc_state_cache
> *cache)
> +static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state
> +*plane_state)
> {
> - unsigned int stride = _intel_fbc_cfb_stride(cache);
> - unsigned int stride_aligned = intel_fbc_cfb_stride(fbc, cache);
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
> + unsigned int stride = _intel_fbc_cfb_stride(plane_state);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
>
> /*
> * Override stride in 64 byte units per 4 line segment.
> @@ -156,8 +155,7 @@ static u16 intel_fbc_override_cfb_stride(struct intel_fbc
> *fbc,
> * we always need to use the override there.
> */
> if (stride != stride_aligned ||
> - (DISPLAY_VER(fbc->i915) == 9 &&
> - cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> + (DISPLAY_VER(i915) == 9 && fb->modifier ==
> DRM_FORMAT_MOD_LINEAR))
> return stride_aligned * 4 / 64;
>
> return 0;
> @@ -925,31 +923,22 @@ static bool tiling_is_valid(const struct
> intel_plane_state *plane_state)
> }
> }
>
> -static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> - const struct intel_crtc_state
> *crtc_state,
> - const struct intel_plane_state
> *plane_state)
> +static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_plane *plane)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_fbc *fbc = &i915->fbc;
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_plane_state *plane_state =
> + intel_atomic_get_new_plane_state(state, plane);
> + struct intel_fbc *fbc = plane->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
> - struct drm_framebuffer *fb = plane_state->hw.fb;
>
> cache->no_fbc_reason = plane_state->no_fbc_reason;
> if (cache->no_fbc_reason)
> return;
>
> - /*
> - * Src coordinates are already rotated by 270 degrees for
> - * the 90/270 degree plane rotation cases (to match the
> - * GTT mapping), hence no need to account for rotation here.
> - */
> - cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> - cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> -
> - cache->fb.format = fb->format;
> - cache->fb.modifier = fb->modifier;
> - cache->fb.stride = intel_fbc_plane_stride(plane_state);
> -
> /* FBC1 compression interval: arbitrary choice of 1 second */
> cache->interval = drm_mode_vrefresh(&crtc_state-
> >hw.adjusted_mode);
>
> @@ -963,12 +952,15 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> cache->fence_id = plane_state->ggtt_vma->fence->id;
> else
> cache->fence_id = -1;
> +
> + cache->cfb_stride = intel_fbc_cfb_stride(plane_state);
> + cache->cfb_size = intel_fbc_cfb_size(plane_state);
> + cache->override_cfb_stride =
> +intel_fbc_override_cfb_stride(plane_state);
> }
>
> static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc) {
> - return intel_fbc_cfb_size(fbc, &fbc->state_cache) >
> - fbc->compressed_fb.size * fbc->limit;
> + return fbc->state_cache.cfb_size > fbc->compressed_fb.size *
> +fbc->limit;
> }
>
> static bool intel_fbc_can_enable(struct intel_fbc *fbc) @@ -1178,45 +1170,53
> @@ static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
> params->interval = cache->interval;
> params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)-
> >i9xx_plane;
>
> - params->fb.format = cache->fb.format;
> - params->fb.modifier = cache->fb.modifier;
> - params->fb.stride = cache->fb.stride;
> -
> - params->cfb_stride = intel_fbc_cfb_stride(fbc, cache);
> - params->cfb_size = intel_fbc_cfb_size(fbc, cache);
> - params->override_cfb_stride = intel_fbc_override_cfb_stride(fbc,
> cache);
> + params->cfb_stride = cache->cfb_stride;
> + params->cfb_size = cache->cfb_size;
> + params->override_cfb_stride = cache->override_cfb_stride;
> }
>
> -static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
> +static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_plane *plane)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = plane->fbc;
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_plane_state *old_plane_state =
> + intel_atomic_get_old_plane_state(state, plane);
> + const struct intel_plane_state *new_plane_state =
> + intel_atomic_get_new_plane_state(state, plane);
> + const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
> + const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
> const struct intel_fbc_state_cache *cache = &fbc->state_cache;
> const struct intel_fbc_reg_params *params = &fbc->params;
>
> - if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> + if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return false;
>
> if (!intel_fbc_can_activate(crtc))
> return false;
>
> - if (params->fb.format != cache->fb.format)
> + if (!old_fb || !new_fb)
> return false;
>
> - if (params->fb.modifier != cache->fb.modifier)
> + if (old_fb->format->format != new_fb->format->format)
> return false;
>
> - if (params->fb.stride != cache->fb.stride)
> + if (old_fb->modifier != new_fb->modifier)
> return false;
>
> - if (params->cfb_stride != intel_fbc_cfb_stride(fbc, cache))
> + if (intel_fbc_plane_stride(old_plane_state) !=
> + intel_fbc_plane_stride(new_plane_state))
> return false;
>
> - if (params->cfb_size != intel_fbc_cfb_size(fbc, cache))
> + if (params->cfb_stride != cache->cfb_stride)
> return false;
>
> - if (params->override_cfb_stride != intel_fbc_override_cfb_stride(fbc,
> cache))
> + if (params->cfb_size != cache->cfb_size)
> + return false;
> +
> + if (params->override_cfb_stride != cache->override_cfb_stride)
> return false;
>
> return true;
> @@ -1226,8 +1226,6 @@ bool intel_fbc_pre_update(struct intel_atomic_state
> *state,
> struct intel_crtc *crtc)
> {
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> - const struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -1243,10
> +1241,10 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
> if (fbc->crtc != crtc)
> goto unlock;
>
> - intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
> + intel_fbc_update_state_cache(state, crtc, plane);
> fbc->flip_pending = true;
>
> - if (!intel_fbc_can_flip_nuke(crtc_state)) {
> + if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
> intel_fbc_deactivate(fbc, reason);
>
> /*
> @@ -1425,8 +1423,6 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state, {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> - const struct intel_crtc_state *crtc_state =
> - intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> @@ -1455,12 +1451,12 @@ static void intel_fbc_enable(struct
> intel_atomic_state *state,
>
> drm_WARN_ON(&i915->drm, fbc->active);
>
> - intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
> + intel_fbc_update_state_cache(state, crtc, plane);
>
> if (cache->no_fbc_reason)
> goto out;
>
> - if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(fbc, cache), min_limit)) {
> + if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
> +min_limit)) {
> fbc->no_fbc_reason = "not enough stolen memory";
> goto out;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d79aa827d937..66fa46d41fa5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -436,18 +436,10 @@ struct intel_fbc {
> struct intel_fbc_state_cache {
> const char *no_fbc_reason;
>
> - struct {
> - int src_w;
> - int src_h;
> - } plane;
> -
> - struct {
> - const struct drm_format_info *format;
> - unsigned int stride;
> - u64 modifier;
> - } fb;
> -
> + unsigned int cfb_stride;
> + unsigned int cfb_size;
> unsigned int fence_y_offset;
> + u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> } state_cache;
> @@ -464,12 +456,6 @@ struct intel_fbc {
> enum i9xx_plane_id i9xx_plane;
> } crtc;
>
> - struct {
> - const struct drm_format_info *format;
> - unsigned int stride;
> - u64 modifier;
> - } fb;
> -
> unsigned int cfb_stride;
> unsigned int cfb_size;
> unsigned int fence_y_offset;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (4 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 05/20] drm/i915/fbc: Nuke more FBC state Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:00 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc Ville Syrjala
` (25 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The FBC state cache and params are now nearly identical. Just
use the same structure for both.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 62 +++++++++++-------------
drivers/gpu/drm/i915/i915_drv.h | 36 +++++---------
2 files changed, 40 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1e8b75cdfad8..8625825cbee8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -163,7 +163,7 @@ static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_s
static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
unsigned int cfb_stride;
u32 fbc_ctl;
@@ -191,11 +191,11 @@ static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
u32 fbc_ctl2;
fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
- FBC_CTL_PLANE(params->crtc.i9xx_plane);
+ FBC_CTL_PLANE(params->i9xx_plane);
if (params->fence_id >= 0)
fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
@@ -226,7 +226,7 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
static void i8xx_fbc_activate(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
int i;
@@ -258,8 +258,8 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
static void i8xx_fbc_nuke(struct intel_fbc *fbc)
{
- struct intel_fbc_reg_params *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+ struct intel_fbc_state *params = &fbc->params;
+ enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -294,8 +294,8 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
static void i965_fbc_nuke(struct intel_fbc *fbc)
{
- struct intel_fbc_reg_params *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+ struct intel_fbc_state *params = &fbc->params;
+ enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -330,12 +330,12 @@ static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
u32 dpfc_ctl;
dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
- DPFC_CTL_PLANE_G4X(params->crtc.i9xx_plane);
+ DPFC_CTL_PLANE_G4X(params->i9xx_plane);
if (IS_G4X(i915))
dpfc_ctl |= DPFC_CTL_SR_EN;
@@ -352,7 +352,7 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
static void g4x_fbc_activate(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
intel_de_write(i915, DPFC_FENCE_YOFF,
@@ -403,7 +403,7 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = {
static void ilk_fbc_activate(struct intel_fbc *fbc)
{
- struct intel_fbc_reg_params *params = &fbc->params;
+ struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
@@ -454,7 +454,7 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = {
static void snb_fbc_program_fence(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
u32 ctl = 0;
@@ -491,7 +491,7 @@ static const struct intel_fbc_funcs snb_fbc_funcs = {
static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
u32 val = 0;
@@ -504,7 +504,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
u32 val = 0;
@@ -520,14 +520,14 @@ static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *params = &fbc->params;
struct drm_i915_private *i915 = fbc->i915;
u32 dpfc_ctl;
dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
if (IS_IVYBRIDGE(i915))
- dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->crtc.i9xx_plane);
+ dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->i9xx_plane);
if (params->fence_id >= 0)
dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
@@ -933,12 +933,14 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ struct intel_fbc_state *cache = &fbc->state_cache;
cache->no_fbc_reason = plane_state->no_fbc_reason;
if (cache->no_fbc_reason)
return;
+ cache->i9xx_plane = plane->i9xx_plane;
+
/* FBC1 compression interval: arbitrary choice of 1 second */
cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
@@ -1093,7 +1095,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_fbc *fbc = &i915->fbc;
- struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ struct intel_fbc_state *cache = &fbc->state_cache;
if (!intel_fbc_can_enable(fbc))
return false;
@@ -1156,23 +1158,13 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
struct intel_crtc *crtc)
{
- const struct intel_fbc_state_cache *cache = &fbc->state_cache;
- struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *cache = &fbc->state_cache;
+ struct intel_fbc_state *params = &fbc->params;
/* Since all our fields are integer types, use memset here so the
* comparison function can rely on memcmp because the padding will be
* zero. */
- memset(params, 0, sizeof(*params));
-
- params->fence_id = cache->fence_id;
- params->fence_y_offset = cache->fence_y_offset;
-
- params->interval = cache->interval;
- params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
-
- params->cfb_stride = cache->cfb_stride;
- params->cfb_size = cache->cfb_size;
- params->override_cfb_stride = cache->override_cfb_stride;
+ *params = *cache;
}
static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
@@ -1188,8 +1180,8 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
intel_atomic_get_new_plane_state(state, plane);
const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
- const struct intel_fbc_state_cache *cache = &fbc->state_cache;
- const struct intel_fbc_reg_params *params = &fbc->params;
+ const struct intel_fbc_state *cache = &fbc->state_cache;
+ const struct intel_fbc_state *params = &fbc->params;
if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
return false;
@@ -1426,7 +1418,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state_cache *cache;
+ struct intel_fbc_state *cache;
int min_limit;
if (!fbc || !plane_state)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66fa46d41fa5..a737fa483cf3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -403,6 +403,17 @@ struct intel_fbc_funcs;
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
+struct intel_fbc_state {
+ const char *no_fbc_reason;
+ enum i9xx_plane_id i9xx_plane;
+ unsigned int cfb_stride;
+ unsigned int cfb_size;
+ unsigned int fence_y_offset;
+ u16 override_cfb_stride;
+ u16 interval;
+ s8 fence_id;
+};
+
struct intel_fbc {
struct drm_i915_private *i915;
const struct intel_fbc_funcs *funcs;
@@ -433,16 +444,7 @@ struct intel_fbc {
* appropriate locking, so we cache information here in order to avoid
* these problems.
*/
- struct intel_fbc_state_cache {
- const char *no_fbc_reason;
-
- unsigned int cfb_stride;
- unsigned int cfb_size;
- unsigned int fence_y_offset;
- u16 override_cfb_stride;
- u16 interval;
- s8 fence_id;
- } state_cache;
+ struct intel_fbc_state state_cache;
/*
* This structure contains everything that's relevant to program the
@@ -451,19 +453,7 @@ struct intel_fbc {
* something different in the struct. The genx_fbc_activate functions
* are supposed to read from it in order to program the registers.
*/
- struct intel_fbc_reg_params {
- struct {
- enum i9xx_plane_id i9xx_plane;
- } crtc;
-
- unsigned int cfb_stride;
- unsigned int cfb_size;
- unsigned int fence_y_offset;
- u16 override_cfb_stride;
- u16 interval;
- s8 fence_id;
- } params;
-
+ struct intel_fbc_state params;
const char *no_fbc_reason;
};
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params
2021-11-24 11:36 ` [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params Ville Syrjala
@ 2021-12-01 10:00 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:00 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the
> cache and params
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The FBC state cache and params are now nearly identical. Just use the same
> structure for both.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 62 +++++++++++-------------
> drivers/gpu/drm/i915/i915_drv.h | 36 +++++---------
> 2 files changed, 40 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1e8b75cdfad8..8625825cbee8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -163,7 +163,7 @@ static u16 intel_fbc_override_cfb_stride(const struct
> intel_plane_state *plane_s
>
> static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> unsigned int cfb_stride;
> u32 fbc_ctl;
> @@ -191,11 +191,11 @@ static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
>
> static u32 i965_fbc_ctl2(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> u32 fbc_ctl2;
>
> fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
> - FBC_CTL_PLANE(params->crtc.i9xx_plane);
> + FBC_CTL_PLANE(params->i9xx_plane);
>
> if (params->fence_id >= 0)
> fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
> @@ -226,7 +226,7 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
>
> static void i8xx_fbc_activate(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> int i;
>
> @@ -258,8 +258,8 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc
> *fbc)
>
> static void i8xx_fbc_nuke(struct intel_fbc *fbc) {
> - struct intel_fbc_reg_params *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> + struct intel_fbc_state *params = &fbc->params;
> + enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -294,8 +294,8 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
>
> static void i965_fbc_nuke(struct intel_fbc *fbc) {
> - struct intel_fbc_reg_params *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
> + struct intel_fbc_state *params = &fbc->params;
> + enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -330,12 +330,12 @@ static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
>
> static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> u32 dpfc_ctl;
>
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
> - DPFC_CTL_PLANE_G4X(params->crtc.i9xx_plane);
> + DPFC_CTL_PLANE_G4X(params->i9xx_plane);
>
> if (IS_G4X(i915))
> dpfc_ctl |= DPFC_CTL_SR_EN;
> @@ -352,7 +352,7 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
>
> static void g4x_fbc_activate(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
>
> intel_de_write(i915, DPFC_FENCE_YOFF,
> @@ -403,7 +403,7 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = {
>
> static void ilk_fbc_activate(struct intel_fbc *fbc) {
> - struct intel_fbc_reg_params *params = &fbc->params;
> + struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
>
> intel_de_write(i915, ILK_DPFC_FENCE_YOFF, @@ -454,7 +454,7 @@
> static const struct intel_fbc_funcs ilk_fbc_funcs = {
>
> static void snb_fbc_program_fence(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> u32 ctl = 0;
>
> @@ -491,7 +491,7 @@ static const struct intel_fbc_funcs snb_fbc_funcs = {
>
> static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> u32 val = 0;
>
> @@ -504,7 +504,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc
> *fbc)
>
> static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> u32 val = 0;
>
> @@ -520,14 +520,14 @@ static void skl_fbc_program_cfb_stride(struct
> intel_fbc *fbc)
>
> static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *params = &fbc->params;
> struct drm_i915_private *i915 = fbc->i915;
> u32 dpfc_ctl;
>
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
>
> if (IS_IVYBRIDGE(i915))
> - dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->crtc.i9xx_plane);
> + dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->i9xx_plane);
>
> if (params->fence_id >= 0)
> dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
> @@ -933,12 +933,14 @@ static void intel_fbc_update_state_cache(struct
> intel_atomic_state *state,
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state_cache *cache = &fbc->state_cache;
> + struct intel_fbc_state *cache = &fbc->state_cache;
>
> cache->no_fbc_reason = plane_state->no_fbc_reason;
> if (cache->no_fbc_reason)
> return;
>
> + cache->i9xx_plane = plane->i9xx_plane;
> +
> /* FBC1 compression interval: arbitrary choice of 1 second */
> cache->interval = drm_mode_vrefresh(&crtc_state-
> >hw.adjusted_mode);
>
> @@ -1093,7 +1095,7 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc) {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_fbc *fbc = &i915->fbc;
> - struct intel_fbc_state_cache *cache = &fbc->state_cache;
> + struct intel_fbc_state *cache = &fbc->state_cache;
>
> if (!intel_fbc_can_enable(fbc))
> return false;
> @@ -1156,23 +1158,13 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc) static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
> struct intel_crtc *crtc)
> {
> - const struct intel_fbc_state_cache *cache = &fbc->state_cache;
> - struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *cache = &fbc->state_cache;
> + struct intel_fbc_state *params = &fbc->params;
>
> /* Since all our fields are integer types, use memset here so the
> * comparison function can rely on memcmp because the padding will
> be
> * zero. */
> - memset(params, 0, sizeof(*params));
> -
> - params->fence_id = cache->fence_id;
> - params->fence_y_offset = cache->fence_y_offset;
> -
> - params->interval = cache->interval;
> - params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)-
> >i9xx_plane;
> -
> - params->cfb_stride = cache->cfb_stride;
> - params->cfb_size = cache->cfb_size;
> - params->override_cfb_stride = cache->override_cfb_stride;
> + *params = *cache;
> }
>
> static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, @@ -
> 1188,8 +1180,8 @@ static bool intel_fbc_can_flip_nuke(struct
> intel_atomic_state *state,
> intel_atomic_get_new_plane_state(state, plane);
> const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
> const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
> - const struct intel_fbc_state_cache *cache = &fbc->state_cache;
> - const struct intel_fbc_reg_params *params = &fbc->params;
> + const struct intel_fbc_state *cache = &fbc->state_cache;
> + const struct intel_fbc_state *params = &fbc->params;
>
> if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return false;
> @@ -1426,7 +1418,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state_cache *cache;
> + struct intel_fbc_state *cache;
> int min_limit;
>
> if (!fbc || !plane_state)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 66fa46d41fa5..a737fa483cf3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -403,6 +403,17 @@ struct intel_fbc_funcs;
>
> #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address
> space */
>
> +struct intel_fbc_state {
> + const char *no_fbc_reason;
> + enum i9xx_plane_id i9xx_plane;
> + unsigned int cfb_stride;
> + unsigned int cfb_size;
> + unsigned int fence_y_offset;
> + u16 override_cfb_stride;
> + u16 interval;
> + s8 fence_id;
> +};
> +
> struct intel_fbc {
> struct drm_i915_private *i915;
> const struct intel_fbc_funcs *funcs;
> @@ -433,16 +444,7 @@ struct intel_fbc {
> * appropriate locking, so we cache information here in order to avoid
> * these problems.
> */
> - struct intel_fbc_state_cache {
> - const char *no_fbc_reason;
> -
> - unsigned int cfb_stride;
> - unsigned int cfb_size;
> - unsigned int fence_y_offset;
> - u16 override_cfb_stride;
> - u16 interval;
> - s8 fence_id;
> - } state_cache;
> + struct intel_fbc_state state_cache;
>
> /*
> * This structure contains everything that's relevant to program the @@
> -451,19 +453,7 @@ struct intel_fbc {
> * something different in the struct. The genx_fbc_activate functions
> * are supposed to read from it in order to program the registers.
> */
> - struct intel_fbc_reg_params {
> - struct {
> - enum i9xx_plane_id i9xx_plane;
> - } crtc;
> -
> - unsigned int cfb_stride;
> - unsigned int cfb_size;
> - unsigned int fence_y_offset;
> - u16 override_cfb_stride;
> - u16 interval;
> - s8 fence_id;
> - } params;
> -
> + struct intel_fbc_state params;
> const char *no_fbc_reason;
> };
>
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (5 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 06/20] drm/i915/fbc: Reuse the same struct for the cache and params Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:03 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane Ville Syrjala
` (24 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass the FBC instance instead of the crtc to a bunch of places.
We also adjust intel_fbc_post_update() to do the
intel_fbc_get_reg_params() things instead of doing it from the lower
level function (which also gets called for front buffer tracking).
Nothing in there will change during front buffer updates.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++--------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8625825cbee8..db390c29c665 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1091,10 +1091,9 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
return 0;
}
-static bool intel_fbc_can_activate(struct intel_crtc *crtc)
+static bool intel_fbc_can_activate(struct intel_fbc *fbc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &i915->fbc;
+ struct drm_i915_private *i915 = fbc->i915;
struct intel_fbc_state *cache = &fbc->state_cache;
if (!intel_fbc_can_enable(fbc))
@@ -1186,7 +1185,7 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
return false;
- if (!intel_fbc_can_activate(crtc))
+ if (!intel_fbc_can_activate(fbc))
return false;
if (!old_fb || !new_fb)
@@ -1280,18 +1279,12 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
fbc->crtc = NULL;
}
-static void __intel_fbc_post_update(struct intel_crtc *crtc)
+static void __intel_fbc_post_update(struct intel_fbc *fbc)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &i915->fbc;
+ struct drm_i915_private *i915 = fbc->i915;
drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
- if (fbc->crtc != crtc)
- return;
-
- fbc->flip_pending = false;
-
if (!i915->params.enable_fbc) {
intel_fbc_deactivate(fbc, "disabled at runtime per module param");
__intel_fbc_disable(fbc);
@@ -1299,9 +1292,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc)
return;
}
- intel_fbc_get_reg_params(fbc, crtc);
-
- if (!intel_fbc_can_activate(crtc))
+ if (!intel_fbc_can_activate(fbc))
return;
if (!fbc->busy_bits)
@@ -1322,7 +1313,11 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
return;
mutex_lock(&fbc->lock);
- __intel_fbc_post_update(crtc);
+ if (fbc->crtc == crtc) {
+ fbc->flip_pending = false;
+ intel_fbc_get_reg_params(fbc, crtc);
+ __intel_fbc_post_update(fbc);
+ }
mutex_unlock(&fbc->lock);
}
@@ -1376,7 +1371,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
if (fbc->active)
intel_fbc_nuke(fbc);
else if (!fbc->flip_pending)
- __intel_fbc_post_update(fbc->crtc);
+ __intel_fbc_post_update(fbc);
}
out:
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc
2021-11-24 11:36 ` [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc Ville Syrjala
@ 2021-12-01 10:03 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:03 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance
> instead of crtc
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pass the FBC instance instead of the crtc to a bunch of places.
>
> We also adjust intel_fbc_post_update() to do the
> intel_fbc_get_reg_params() things instead of doing it from the lower level
> function (which also gets called for front buffer tracking).
> Nothing in there will change during front buffer updates.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 29 ++++++++++--------------
> 1 file changed, 12 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 8625825cbee8..db390c29c665 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1091,10 +1091,9 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> -static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> +static bool intel_fbc_can_activate(struct intel_fbc *fbc)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_fbc *fbc = &i915->fbc;
> + struct drm_i915_private *i915 = fbc->i915;
> struct intel_fbc_state *cache = &fbc->state_cache;
>
> if (!intel_fbc_can_enable(fbc))
> @@ -1186,7 +1185,7 @@ static bool intel_fbc_can_flip_nuke(struct
> intel_atomic_state *state,
> if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return false;
>
> - if (!intel_fbc_can_activate(crtc))
> + if (!intel_fbc_can_activate(fbc))
> return false;
>
> if (!old_fb || !new_fb)
> @@ -1280,18 +1279,12 @@ static void __intel_fbc_disable(struct intel_fbc
> *fbc)
> fbc->crtc = NULL;
> }
>
> -static void __intel_fbc_post_update(struct intel_crtc *crtc)
> +static void __intel_fbc_post_update(struct intel_fbc *fbc)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_fbc *fbc = &i915->fbc;
> + struct drm_i915_private *i915 = fbc->i915;
>
> drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
>
> - if (fbc->crtc != crtc)
> - return;
> -
> - fbc->flip_pending = false;
> -
> if (!i915->params.enable_fbc) {
> intel_fbc_deactivate(fbc, "disabled at runtime per module
> param");
> __intel_fbc_disable(fbc);
> @@ -1299,9 +1292,7 @@ static void __intel_fbc_post_update(struct intel_crtc
> *crtc)
> return;
> }
>
> - intel_fbc_get_reg_params(fbc, crtc);
> -
> - if (!intel_fbc_can_activate(crtc))
> + if (!intel_fbc_can_activate(fbc))
> return;
>
> if (!fbc->busy_bits)
> @@ -1322,7 +1313,11 @@ void intel_fbc_post_update(struct
> intel_atomic_state *state,
> return;
>
> mutex_lock(&fbc->lock);
> - __intel_fbc_post_update(crtc);
> + if (fbc->crtc == crtc) {
> + fbc->flip_pending = false;
> + intel_fbc_get_reg_params(fbc, crtc);
> + __intel_fbc_post_update(fbc);
> + }
> mutex_unlock(&fbc->lock);
> }
>
> @@ -1376,7 +1371,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> if (fbc->active)
> intel_fbc_nuke(fbc);
> else if (!fbc->flip_pending)
> - __intel_fbc_post_update(fbc->crtc);
> + __intel_fbc_post_update(fbc);
> }
>
> out:
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (6 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 07/20] drm/i915/fbc: Pass around FBC instance instead of crtc Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:04 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update() Ville Syrjala
` (23 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In the future we may have multiple planes on the same pipe
capable of using FBC. Prepare for that by tracking FBC usage
per-plane rather than per-crtc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 224 +++++++++++------------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_trace.h | 18 +-
3 files changed, 123 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index db390c29c665..cf7fc0de6081 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -583,7 +583,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
static void intel_fbc_hw_activate(struct intel_fbc *fbc)
{
- trace_intel_fbc_activate(fbc->crtc);
+ trace_intel_fbc_activate(fbc->plane);
fbc->active = true;
fbc->activated = true;
@@ -593,7 +593,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
{
- trace_intel_fbc_deactivate(fbc->crtc);
+ trace_intel_fbc_deactivate(fbc->plane);
fbc->active = false;
@@ -607,7 +607,7 @@ bool intel_fbc_is_compressing(struct intel_fbc *fbc)
static void intel_fbc_nuke(struct intel_fbc *fbc)
{
- trace_intel_fbc_nuke(fbc->crtc);
+ trace_intel_fbc_nuke(fbc->plane);
fbc->funcs->nuke(fbc);
}
@@ -1154,8 +1154,7 @@ static bool intel_fbc_can_activate(struct intel_fbc *fbc)
return true;
}
-static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
- struct intel_crtc *crtc)
+static void intel_fbc_get_reg_params(struct intel_fbc *fbc)
{
const struct intel_fbc_state *cache = &fbc->state_cache;
struct intel_fbc_state *params = &fbc->params;
@@ -1213,30 +1212,19 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
return true;
}
-bool intel_fbc_pre_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_plane *plane)
{
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- const struct intel_plane_state *plane_state =
- intel_atomic_get_new_plane_state(state, plane);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_fbc *fbc = plane->fbc;
- const char *reason = "update pending";
bool need_vblank_wait = false;
- if (!fbc || !plane_state)
- return need_vblank_wait;
-
- mutex_lock(&fbc->lock);
-
- if (fbc->crtc != crtc)
- goto unlock;
-
intel_fbc_update_state_cache(state, crtc, plane);
fbc->flip_pending = true;
if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
- intel_fbc_deactivate(fbc, reason);
+ intel_fbc_deactivate(fbc, "update pending");
/*
* Display WA #1198: glk+
@@ -1256,8 +1244,31 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
need_vblank_wait = true;
fbc->activated = false;
}
-unlock:
- mutex_unlock(&fbc->lock);
+
+ return need_vblank_wait;
+}
+
+bool intel_fbc_pre_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_plane_state *plane_state;
+ bool need_vblank_wait = false;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ struct intel_fbc *fbc = plane->fbc;
+
+ if (!fbc || plane->pipe != crtc->pipe)
+ continue;
+
+ mutex_lock(&fbc->lock);
+
+ if (fbc->plane == plane)
+ need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
+
+ mutex_unlock(&fbc->lock);
+ }
return need_vblank_wait;
}
@@ -1265,18 +1276,18 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
static void __intel_fbc_disable(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- struct intel_crtc *crtc = fbc->crtc;
+ struct intel_plane *plane = fbc->plane;
drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
- drm_WARN_ON(&i915->drm, !fbc->crtc);
+ drm_WARN_ON(&i915->drm, !fbc->plane);
drm_WARN_ON(&i915->drm, fbc->active);
- drm_dbg_kms(&i915->drm, "Disabling FBC on pipe %c\n",
- pipe_name(crtc->pipe));
+ drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
+ plane->base.base.id, plane->base.name);
__intel_fbc_cleanup_cfb(fbc);
- fbc->crtc = NULL;
+ fbc->plane = NULL;
}
static void __intel_fbc_post_update(struct intel_fbc *fbc)
@@ -1304,27 +1315,32 @@ static void __intel_fbc_post_update(struct intel_fbc *fbc)
void intel_fbc_post_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- const struct intel_plane_state *plane_state =
- intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = plane->fbc;
-
- if (!fbc || !plane_state)
- return;
-
- mutex_lock(&fbc->lock);
- if (fbc->crtc == crtc) {
- fbc->flip_pending = false;
- intel_fbc_get_reg_params(fbc, crtc);
- __intel_fbc_post_update(fbc);
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ struct intel_fbc *fbc = plane->fbc;
+
+ if (!fbc || plane->pipe != crtc->pipe)
+ continue;
+
+ mutex_lock(&fbc->lock);
+
+ if (fbc->plane == plane) {
+ fbc->flip_pending = false;
+ intel_fbc_get_reg_params(fbc);
+ __intel_fbc_post_update(fbc);
+ }
+
+ mutex_unlock(&fbc->lock);
}
- mutex_unlock(&fbc->lock);
}
static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
{
- if (fbc->crtc)
- return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
+ if (fbc->plane)
+ return fbc->plane->frontbuffer_bit;
else
return fbc->possible_framebuffer_bits;
}
@@ -1345,7 +1361,7 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
- if (fbc->crtc && fbc->busy_bits)
+ if (fbc->plane && fbc->busy_bits)
intel_fbc_deactivate(fbc, "frontbuffer write");
mutex_unlock(&fbc->lock);
@@ -1366,7 +1382,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
goto out;
- if (!fbc->busy_bits && fbc->crtc &&
+ if (!fbc->busy_bits && fbc->plane &&
(frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
if (fbc->active)
intel_fbc_nuke(fbc);
@@ -1395,43 +1411,24 @@ int intel_fbc_atomic_check(struct intel_atomic_state *state)
return 0;
}
-/**
- * intel_fbc_enable: tries to enable FBC on the CRTC
- * @crtc: the CRTC
- * @state: corresponding &drm_crtc_state for @crtc
- *
- * This function checks if the given CRTC was chosen for FBC, then enables it if
- * possible. Notice that it doesn't activate FBC. It is valid to call
- * intel_fbc_enable multiple times for the same pipe without an
- * intel_fbc_disable in the middle, as long as it is deactivated.
- */
-static void intel_fbc_enable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void __intel_fbc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_plane *plane)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state *cache;
- int min_limit;
+ struct intel_fbc_state *cache = &fbc->state_cache;
+ int min_limit = intel_fbc_min_limit(plane_state);
- if (!fbc || !plane_state)
- return;
-
- cache = &fbc->state_cache;
-
- min_limit = intel_fbc_min_limit(plane_state);
-
- mutex_lock(&fbc->lock);
-
- if (fbc->crtc) {
- if (fbc->crtc != crtc)
- goto out;
+ if (fbc->plane) {
+ if (fbc->plane != plane)
+ return;
if (fbc->limit >= min_limit &&
!intel_fbc_cfb_size_changed(fbc))
- goto out;
+ return;
__intel_fbc_disable(fbc);
}
@@ -1441,22 +1438,20 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
intel_fbc_update_state_cache(state, crtc, plane);
if (cache->no_fbc_reason)
- goto out;
+ return;
if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
fbc->no_fbc_reason = "not enough stolen memory";
- goto out;
+ return;
}
- drm_dbg_kms(&i915->drm, "Enabling FBC on pipe %c\n",
- pipe_name(crtc->pipe));
+ drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
+ plane->base.base.id, plane->base.name);
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
- fbc->crtc = crtc;
+ fbc->plane = plane;
intel_fbc_program_cfb(fbc);
-out:
- mutex_unlock(&fbc->lock);
}
/**
@@ -1467,45 +1462,48 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
*/
void intel_fbc_disable(struct intel_crtc *crtc)
{
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- struct intel_fbc *fbc = plane->fbc;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_plane *plane;
- if (!fbc)
- return;
+ for_each_intel_plane(&i915->drm, plane) {
+ struct intel_fbc *fbc = plane->fbc;
- mutex_lock(&fbc->lock);
- if (fbc->crtc == crtc)
- __intel_fbc_disable(fbc);
- mutex_unlock(&fbc->lock);
+ if (!fbc || plane->pipe != crtc->pipe)
+ continue;
+
+ mutex_lock(&fbc->lock);
+ if (fbc->plane == plane)
+ __intel_fbc_disable(fbc);
+ mutex_unlock(&fbc->lock);
+ }
}
-/**
- * intel_fbc_update: enable/disable FBC on the CRTC
- * @state: atomic state
- * @crtc: the CRTC
- *
- * This function checks if the given CRTC was chosen for FBC, then enables it if
- * possible. Notice that it doesn't activate FBC. It is valid to call
- * intel_fbc_update multiple times for the same pipe without an
- * intel_fbc_disable in the middle.
- */
void intel_fbc_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct intel_plane_state *plane_state =
- intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = plane->fbc;
+ const struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i;
- if (!fbc || !plane_state)
- return;
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ struct intel_fbc *fbc = plane->fbc;
- if (crtc_state->update_pipe && plane_state->no_fbc_reason)
- intel_fbc_disable(crtc);
- else
- intel_fbc_enable(state, crtc);
+ if (!fbc || plane->pipe != crtc->pipe)
+ continue;
+
+ mutex_lock(&fbc->lock);
+
+ if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
+ if (fbc->plane == plane)
+ __intel_fbc_disable(fbc);
+ } else {
+ __intel_fbc_enable(state, crtc, plane);
+ }
+
+ mutex_unlock(&fbc->lock);
+ }
}
/**
@@ -1522,10 +1520,8 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
return;
mutex_lock(&fbc->lock);
- if (fbc->crtc) {
- drm_WARN_ON(&i915->drm, fbc->crtc->active);
+ if (fbc->plane)
__intel_fbc_disable(fbc);
- }
mutex_unlock(&fbc->lock);
}
@@ -1538,7 +1534,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
mutex_lock(&fbc->lock);
/* Maybe we were scheduled twice. */
- if (fbc->underrun_detected || !fbc->crtc)
+ if (fbc->underrun_detected || !fbc->plane)
goto out;
drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a737fa483cf3..f632b026ce34 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -423,7 +423,7 @@ struct intel_fbc {
struct mutex lock;
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
- struct intel_crtc *crtc;
+ struct intel_plane *plane;
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 6b8fb6ffe8da..7d6e638dcccb 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -372,8 +372,8 @@ TRACE_EVENT(intel_plane_disable_arm,
/* fbc */
TRACE_EVENT(intel_fbc_activate,
- TP_PROTO(struct intel_crtc *crtc),
- TP_ARGS(crtc),
+ TP_PROTO(struct intel_plane *plane),
+ TP_ARGS(plane),
TP_STRUCT__entry(
__field(enum pipe, pipe)
@@ -382,6 +382,8 @@ TRACE_EVENT(intel_fbc_activate,
),
TP_fast_assign(
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
+ plane->pipe);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@@ -392,8 +394,8 @@ TRACE_EVENT(intel_fbc_activate,
);
TRACE_EVENT(intel_fbc_deactivate,
- TP_PROTO(struct intel_crtc *crtc),
- TP_ARGS(crtc),
+ TP_PROTO(struct intel_plane *plane),
+ TP_ARGS(plane),
TP_STRUCT__entry(
__field(enum pipe, pipe)
@@ -402,6 +404,8 @@ TRACE_EVENT(intel_fbc_deactivate,
),
TP_fast_assign(
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
+ plane->pipe);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
@@ -412,8 +416,8 @@ TRACE_EVENT(intel_fbc_deactivate,
);
TRACE_EVENT(intel_fbc_nuke,
- TP_PROTO(struct intel_crtc *crtc),
- TP_ARGS(crtc),
+ TP_PROTO(struct intel_plane *plane),
+ TP_ARGS(plane),
TP_STRUCT__entry(
__field(enum pipe, pipe)
@@ -422,6 +426,8 @@ TRACE_EVENT(intel_fbc_nuke,
),
TP_fast_assign(
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
+ plane->pipe);
__entry->pipe = crtc->pipe;
__entry->frame = intel_crtc_get_vblank_counter(crtc);
__entry->scanline = intel_get_crtc_scanline(crtc);
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane
2021-11-24 11:36 ` [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane Ville Syrjala
@ 2021-12-01 10:04 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:04 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In the future we may have multiple planes on the same pipe capable of using
> FBC. Prepare for that by tracking FBC usage per-plane rather than per-crtc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 224 +++++++++++------------
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_trace.h | 18 +-
> 3 files changed, 123 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index db390c29c665..cf7fc0de6081 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -583,7 +583,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_activate(struct intel_fbc *fbc) {
> - trace_intel_fbc_activate(fbc->crtc);
> + trace_intel_fbc_activate(fbc->plane);
>
> fbc->active = true;
> fbc->activated = true;
> @@ -593,7 +593,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) {
> - trace_intel_fbc_deactivate(fbc->crtc);
> + trace_intel_fbc_deactivate(fbc->plane);
>
> fbc->active = false;
>
> @@ -607,7 +607,7 @@ bool intel_fbc_is_compressing(struct intel_fbc *fbc)
>
> static void intel_fbc_nuke(struct intel_fbc *fbc) {
> - trace_intel_fbc_nuke(fbc->crtc);
> + trace_intel_fbc_nuke(fbc->plane);
>
> fbc->funcs->nuke(fbc);
> }
> @@ -1154,8 +1154,7 @@ static bool intel_fbc_can_activate(struct intel_fbc
> *fbc)
> return true;
> }
>
> -static void intel_fbc_get_reg_params(struct intel_fbc *fbc,
> - struct intel_crtc *crtc)
> +static void intel_fbc_get_reg_params(struct intel_fbc *fbc)
> {
> const struct intel_fbc_state *cache = &fbc->state_cache;
> struct intel_fbc_state *params = &fbc->params; @@ -1213,30 +1212,19
> @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> return true;
> }
>
> -bool intel_fbc_pre_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_plane *plane)
> {
> - struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> - const struct intel_plane_state *plane_state =
> - intel_atomic_get_new_plane_state(state, plane);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_fbc *fbc = plane->fbc;
> - const char *reason = "update pending";
> bool need_vblank_wait = false;
>
> - if (!fbc || !plane_state)
> - return need_vblank_wait;
> -
> - mutex_lock(&fbc->lock);
> -
> - if (fbc->crtc != crtc)
> - goto unlock;
> -
> intel_fbc_update_state_cache(state, crtc, plane);
> fbc->flip_pending = true;
>
> if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
> - intel_fbc_deactivate(fbc, reason);
> + intel_fbc_deactivate(fbc, "update pending");
>
> /*
> * Display WA #1198: glk+
> @@ -1256,8 +1244,31 @@ bool intel_fbc_pre_update(struct intel_atomic_state
> *state,
> need_vblank_wait = true;
> fbc->activated = false;
> }
> -unlock:
> - mutex_unlock(&fbc->lock);
> +
> + return need_vblank_wait;
> +}
> +
> +bool intel_fbc_pre_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + const struct intel_plane_state *plane_state;
> + bool need_vblank_wait = false;
> + struct intel_plane *plane;
> + int i;
> +
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + struct intel_fbc *fbc = plane->fbc;
> +
> + if (!fbc || plane->pipe != crtc->pipe)
> + continue;
> +
> + mutex_lock(&fbc->lock);
> +
> + if (fbc->plane == plane)
> + need_vblank_wait |= __intel_fbc_pre_update(state,
> crtc, plane);
> +
> + mutex_unlock(&fbc->lock);
> + }
>
> return need_vblank_wait;
> }
> @@ -1265,18 +1276,18 @@ bool intel_fbc_pre_update(struct
> intel_atomic_state *state, static void __intel_fbc_disable(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
> - struct intel_crtc *crtc = fbc->crtc;
> + struct intel_plane *plane = fbc->plane;
>
> drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
> - drm_WARN_ON(&i915->drm, !fbc->crtc);
> + drm_WARN_ON(&i915->drm, !fbc->plane);
> drm_WARN_ON(&i915->drm, fbc->active);
>
> - drm_dbg_kms(&i915->drm, "Disabling FBC on pipe %c\n",
> - pipe_name(crtc->pipe));
> + drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
> + plane->base.base.id, plane->base.name);
>
> __intel_fbc_cleanup_cfb(fbc);
>
> - fbc->crtc = NULL;
> + fbc->plane = NULL;
> }
>
> static void __intel_fbc_post_update(struct intel_fbc *fbc) @@ -1304,27
> +1315,32 @@ static void __intel_fbc_post_update(struct intel_fbc *fbc) void
> intel_fbc_post_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> - const struct intel_plane_state *plane_state =
> - intel_atomic_get_new_plane_state(state, plane);
> - struct intel_fbc *fbc = plane->fbc;
> -
> - if (!fbc || !plane_state)
> - return;
> -
> - mutex_lock(&fbc->lock);
> - if (fbc->crtc == crtc) {
> - fbc->flip_pending = false;
> - intel_fbc_get_reg_params(fbc, crtc);
> - __intel_fbc_post_update(fbc);
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> + int i;
> +
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + struct intel_fbc *fbc = plane->fbc;
> +
> + if (!fbc || plane->pipe != crtc->pipe)
> + continue;
> +
> + mutex_lock(&fbc->lock);
> +
> + if (fbc->plane == plane) {
> + fbc->flip_pending = false;
> + intel_fbc_get_reg_params(fbc);
> + __intel_fbc_post_update(fbc);
> + }
> +
> + mutex_unlock(&fbc->lock);
> }
> - mutex_unlock(&fbc->lock);
> }
>
> static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) {
> - if (fbc->crtc)
> - return to_intel_plane(fbc->crtc->base.primary)-
> >frontbuffer_bit;
> + if (fbc->plane)
> + return fbc->plane->frontbuffer_bit;
> else
> return fbc->possible_framebuffer_bits; } @@ -1345,7 +1361,7
> @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
>
> fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
>
> - if (fbc->crtc && fbc->busy_bits)
> + if (fbc->plane && fbc->busy_bits)
> intel_fbc_deactivate(fbc, "frontbuffer write");
>
> mutex_unlock(&fbc->lock);
> @@ -1366,7 +1382,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
> goto out;
>
> - if (!fbc->busy_bits && fbc->crtc &&
> + if (!fbc->busy_bits && fbc->plane &&
> (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
> if (fbc->active)
> intel_fbc_nuke(fbc);
> @@ -1395,43 +1411,24 @@ int intel_fbc_atomic_check(struct
> intel_atomic_state *state)
> return 0;
> }
>
> -/**
> - * intel_fbc_enable: tries to enable FBC on the CRTC
> - * @crtc: the CRTC
> - * @state: corresponding &drm_crtc_state for @crtc
> - *
> - * This function checks if the given CRTC was chosen for FBC, then enables it if
> - * possible. Notice that it doesn't activate FBC. It is valid to call
> - * intel_fbc_enable multiple times for the same pipe without an
> - * intel_fbc_disable in the middle, as long as it is deactivated.
> - */
> -static void intel_fbc_enable(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static void __intel_fbc_enable(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_plane *plane)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state *cache;
> - int min_limit;
> + struct intel_fbc_state *cache = &fbc->state_cache;
> + int min_limit = intel_fbc_min_limit(plane_state);
>
> - if (!fbc || !plane_state)
> - return;
> -
> - cache = &fbc->state_cache;
> -
> - min_limit = intel_fbc_min_limit(plane_state);
> -
> - mutex_lock(&fbc->lock);
> -
> - if (fbc->crtc) {
> - if (fbc->crtc != crtc)
> - goto out;
> + if (fbc->plane) {
> + if (fbc->plane != plane)
> + return;
>
> if (fbc->limit >= min_limit &&
> !intel_fbc_cfb_size_changed(fbc))
> - goto out;
> + return;
>
> __intel_fbc_disable(fbc);
> }
> @@ -1441,22 +1438,20 @@ static void intel_fbc_enable(struct
> intel_atomic_state *state,
> intel_fbc_update_state_cache(state, crtc, plane);
>
> if (cache->no_fbc_reason)
> - goto out;
> + return;
>
> if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
> fbc->no_fbc_reason = "not enough stolen memory";
> - goto out;
> + return;
> }
>
> - drm_dbg_kms(&i915->drm, "Enabling FBC on pipe %c\n",
> - pipe_name(crtc->pipe));
> + drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
> + plane->base.base.id, plane->base.name);
> fbc->no_fbc_reason = "FBC enabled but not active yet\n";
>
> - fbc->crtc = crtc;
> + fbc->plane = plane;
>
> intel_fbc_program_cfb(fbc);
> -out:
> - mutex_unlock(&fbc->lock);
> }
>
> /**
> @@ -1467,45 +1462,48 @@ static void intel_fbc_enable(struct
> intel_atomic_state *state,
> */
> void intel_fbc_disable(struct intel_crtc *crtc) {
> - struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> - struct intel_fbc *fbc = plane->fbc;
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_plane *plane;
>
> - if (!fbc)
> - return;
> + for_each_intel_plane(&i915->drm, plane) {
> + struct intel_fbc *fbc = plane->fbc;
>
> - mutex_lock(&fbc->lock);
> - if (fbc->crtc == crtc)
> - __intel_fbc_disable(fbc);
> - mutex_unlock(&fbc->lock);
> + if (!fbc || plane->pipe != crtc->pipe)
> + continue;
> +
> + mutex_lock(&fbc->lock);
> + if (fbc->plane == plane)
> + __intel_fbc_disable(fbc);
> + mutex_unlock(&fbc->lock);
> + }
> }
>
> -/**
> - * intel_fbc_update: enable/disable FBC on the CRTC
> - * @state: atomic state
> - * @crtc: the CRTC
> - *
> - * This function checks if the given CRTC was chosen for FBC, then enables it if
> - * possible. Notice that it doesn't activate FBC. It is valid to call
> - * intel_fbc_update multiple times for the same pipe without an
> - * intel_fbc_disable in the middle.
> - */
> void intel_fbc_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> const struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct intel_plane_state *plane_state =
> - intel_atomic_get_new_plane_state(state, plane);
> - struct intel_fbc *fbc = plane->fbc;
> + const struct intel_plane_state *plane_state;
> + struct intel_plane *plane;
> + int i;
>
> - if (!fbc || !plane_state)
> - return;
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + struct intel_fbc *fbc = plane->fbc;
>
> - if (crtc_state->update_pipe && plane_state->no_fbc_reason)
> - intel_fbc_disable(crtc);
> - else
> - intel_fbc_enable(state, crtc);
> + if (!fbc || plane->pipe != crtc->pipe)
> + continue;
> +
> + mutex_lock(&fbc->lock);
> +
> + if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
> + if (fbc->plane == plane)
> + __intel_fbc_disable(fbc);
> + } else {
> + __intel_fbc_enable(state, crtc, plane);
> + }
> +
> + mutex_unlock(&fbc->lock);
> + }
> }
>
> /**
> @@ -1522,10 +1520,8 @@ void intel_fbc_global_disable(struct
> drm_i915_private *i915)
> return;
>
> mutex_lock(&fbc->lock);
> - if (fbc->crtc) {
> - drm_WARN_ON(&i915->drm, fbc->crtc->active);
> + if (fbc->plane)
> __intel_fbc_disable(fbc);
> - }
> mutex_unlock(&fbc->lock);
> }
>
> @@ -1538,7 +1534,7 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
> mutex_lock(&fbc->lock);
>
> /* Maybe we were scheduled twice. */
> - if (fbc->underrun_detected || !fbc->crtc)
> + if (fbc->underrun_detected || !fbc->plane)
> goto out;
>
> drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a737fa483cf3..f632b026ce34 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -423,7 +423,7 @@ struct intel_fbc {
> struct mutex lock;
> unsigned int possible_framebuffer_bits;
> unsigned int busy_bits;
> - struct intel_crtc *crtc;
> + struct intel_plane *plane;
>
> struct drm_mm_node compressed_fb;
> struct drm_mm_node compressed_llb;
> diff --git a/drivers/gpu/drm/i915/i915_trace.h
> b/drivers/gpu/drm/i915/i915_trace.h
> index 6b8fb6ffe8da..7d6e638dcccb 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -372,8 +372,8 @@ TRACE_EVENT(intel_plane_disable_arm,
> /* fbc */
>
> TRACE_EVENT(intel_fbc_activate,
> - TP_PROTO(struct intel_crtc *crtc),
> - TP_ARGS(crtc),
> + TP_PROTO(struct intel_plane *plane),
> + TP_ARGS(plane),
>
> TP_STRUCT__entry(
> __field(enum pipe, pipe)
> @@ -382,6 +382,8 @@ TRACE_EVENT(intel_fbc_activate,
> ),
>
> TP_fast_assign(
> + struct intel_crtc *crtc =
> intel_get_crtc_for_pipe(to_i915(plane->base.dev),
> +
> plane->pipe);
> __entry->pipe = crtc->pipe;
> __entry->frame =
> intel_crtc_get_vblank_counter(crtc);
> __entry->scanline = intel_get_crtc_scanline(crtc); @@
> -392,8 +394,8 @@ TRACE_EVENT(intel_fbc_activate, );
>
> TRACE_EVENT(intel_fbc_deactivate,
> - TP_PROTO(struct intel_crtc *crtc),
> - TP_ARGS(crtc),
> + TP_PROTO(struct intel_plane *plane),
> + TP_ARGS(plane),
>
> TP_STRUCT__entry(
> __field(enum pipe, pipe)
> @@ -402,6 +404,8 @@ TRACE_EVENT(intel_fbc_deactivate,
> ),
>
> TP_fast_assign(
> + struct intel_crtc *crtc =
> intel_get_crtc_for_pipe(to_i915(plane->base.dev),
> +
> plane->pipe);
> __entry->pipe = crtc->pipe;
> __entry->frame =
> intel_crtc_get_vblank_counter(crtc);
> __entry->scanline = intel_get_crtc_scanline(crtc); @@
> -412,8 +416,8 @@ TRACE_EVENT(intel_fbc_deactivate, );
>
> TRACE_EVENT(intel_fbc_nuke,
> - TP_PROTO(struct intel_crtc *crtc),
> - TP_ARGS(crtc),
> + TP_PROTO(struct intel_plane *plane),
> + TP_ARGS(plane),
>
> TP_STRUCT__entry(
> __field(enum pipe, pipe)
> @@ -422,6 +426,8 @@ TRACE_EVENT(intel_fbc_nuke,
> ),
>
> TP_fast_assign(
> + struct intel_crtc *crtc =
> intel_get_crtc_for_pipe(to_i915(plane->base.dev),
> +
> plane->pipe);
> __entry->pipe = crtc->pipe;
> __entry->frame =
> intel_crtc_get_vblank_counter(crtc);
> __entry->scanline = intel_get_crtc_scanline(crtc);
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update()
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (7 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 08/20] drm/i915/fbc: Track FBC usage per-plane Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:04 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff Ville Syrjala
` (22 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use an early return to flatten most of __intel_fbc_pre_update().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 40 ++++++++++++------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index cf7fc0de6081..0bef3b948670 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1223,27 +1223,27 @@ static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
intel_fbc_update_state_cache(state, crtc, plane);
fbc->flip_pending = true;
- if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
- intel_fbc_deactivate(fbc, "update pending");
+ if (intel_fbc_can_flip_nuke(state, crtc, plane))
+ return need_vblank_wait;
- /*
- * Display WA #1198: glk+
- * Need an extra vblank wait between FBC disable and most plane
- * updates. Bspec says this is only needed for plane disable, but
- * that is not true. Touching most plane registers will cause the
- * corruption to appear. Also SKL/derivatives do not seem to be
- * affected.
- *
- * TODO: could optimize this a bit by sampling the frame
- * counter when we disable FBC (if it was already done earlier)
- * and skipping the extra vblank wait before the plane update
- * if at least one frame has already passed.
- */
- if (fbc->activated &&
- DISPLAY_VER(i915) >= 10)
- need_vblank_wait = true;
- fbc->activated = false;
- }
+ intel_fbc_deactivate(fbc, "update pending");
+
+ /*
+ * Display WA #1198: glk+
+ * Need an extra vblank wait between FBC disable and most plane
+ * updates. Bspec says this is only needed for plane disable, but
+ * that is not true. Touching most plane registers will cause the
+ * corruption to appear. Also SKL/derivatives do not seem to be
+ * affected.
+ *
+ * TODO: could optimize this a bit by sampling the frame
+ * counter when we disable FBC (if it was already done earlier)
+ * and skipping the extra vblank wait before the plane update
+ * if at least one frame has already passed.
+ */
+ if (fbc->activated && DISPLAY_VER(i915) >= 10)
+ need_vblank_wait = true;
+ fbc->activated = false;
return need_vblank_wait;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update()
2021-11-24 11:36 ` [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update() Ville Syrjala
@ 2021-12-01 10:04 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:04 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten
> __intel_fbc_pre_update()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use an early return to flatten most of __intel_fbc_pre_update().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 40 ++++++++++++------------
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index cf7fc0de6081..0bef3b948670 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1223,27 +1223,27 @@ static bool __intel_fbc_pre_update(struct
> intel_atomic_state *state,
> intel_fbc_update_state_cache(state, crtc, plane);
> fbc->flip_pending = true;
>
> - if (!intel_fbc_can_flip_nuke(state, crtc, plane)) {
> - intel_fbc_deactivate(fbc, "update pending");
> + if (intel_fbc_can_flip_nuke(state, crtc, plane))
> + return need_vblank_wait;
>
> - /*
> - * Display WA #1198: glk+
> - * Need an extra vblank wait between FBC disable and most
> plane
> - * updates. Bspec says this is only needed for plane disable, but
> - * that is not true. Touching most plane registers will cause the
> - * corruption to appear. Also SKL/derivatives do not seem to be
> - * affected.
> - *
> - * TODO: could optimize this a bit by sampling the frame
> - * counter when we disable FBC (if it was already done earlier)
> - * and skipping the extra vblank wait before the plane update
> - * if at least one frame has already passed.
> - */
> - if (fbc->activated &&
> - DISPLAY_VER(i915) >= 10)
> - need_vblank_wait = true;
> - fbc->activated = false;
> - }
> + intel_fbc_deactivate(fbc, "update pending");
> +
> + /*
> + * Display WA #1198: glk+
> + * Need an extra vblank wait between FBC disable and most plane
> + * updates. Bspec says this is only needed for plane disable, but
> + * that is not true. Touching most plane registers will cause the
> + * corruption to appear. Also SKL/derivatives do not seem to be
> + * affected.
> + *
> + * TODO: could optimize this a bit by sampling the frame
> + * counter when we disable FBC (if it was already done earlier)
> + * and skipping the extra vblank wait before the plane update
> + * if at least one frame has already passed.
> + */
> + if (fbc->activated && DISPLAY_VER(i915) >= 10)
> + need_vblank_wait = true;
> + fbc->activated = false;
>
> return need_vblank_wait;
> }
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (8 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 09/20] drm/i915/fbc: Flatten __intel_fbc_pre_update() Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:08 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c Ville Syrjala
` (21 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The underrun code doesn't need to know any details about FBC, so
just pass in the whole device rather than a specific FBC instance.
We could make this a bit more fine grained by also passing in the
pipe to intel_fbc_handle_fifo_underrun_irq() and letting the FBC
code figure which FBC instance (if any) is active on said pipe.
But that seems a bit overkill for this so don't bother.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 4 +---
drivers/gpu/drm/i915/display/intel_fbc.c | 24 +++++++++----------
drivers/gpu/drm/i915/display/intel_fbc.h | 4 ++--
.../drm/i915/display/intel_fifo_underrun.c | 2 +-
4 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index acf70ae66a29..3e456e595010 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2044,9 +2044,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
return ret;
}
- ret = intel_fbc_reset_underrun(&dev_priv->fbc);
- if (ret)
- return ret;
+ intel_fbc_reset_underrun(dev_priv);
return cnt;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 0bef3b948670..00c93040529e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1547,21 +1547,21 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
/*
* intel_fbc_reset_underrun - reset FBC fifo underrun status.
- * @fbc: The FBC instance
+ * @i915: the i915 device
*
* See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
* want to re-enable FBC after an underrun to increase test coverage.
*/
-int intel_fbc_reset_underrun(struct intel_fbc *fbc)
+void intel_fbc_reset_underrun(struct drm_i915_private *i915)
{
- struct drm_i915_private *i915 = fbc->i915;
- int ret;
+ struct intel_fbc *fbc = &i915->fbc;
+
+ if (!HAS_FBC(i915))
+ return;
cancel_work_sync(&fbc->underrun_work);
- ret = mutex_lock_interruptible(&fbc->lock);
- if (ret)
- return ret;
+ mutex_lock(&fbc->lock);
if (fbc->underrun_detected) {
drm_dbg_kms(&i915->drm,
@@ -1571,13 +1571,11 @@ int intel_fbc_reset_underrun(struct intel_fbc *fbc)
fbc->underrun_detected = false;
mutex_unlock(&fbc->lock);
-
- return 0;
}
/**
* intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
- * @fbc: The FBC instance
+ * @i915: i915 device
*
* Without FBC, most underruns are harmless and don't really cause too many
* problems, except for an annoying message on dmesg. With FBC, underruns can
@@ -1589,9 +1587,11 @@ int intel_fbc_reset_underrun(struct intel_fbc *fbc)
*
* This function is called from the IRQ handler.
*/
-void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
+void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
{
- if (!HAS_FBC(fbc->i915))
+ struct intel_fbc *fbc = &i915->fbc;
+
+ if (!HAS_FBC(i915))
return;
/* There's no guarantee that underrun_detected won't be set to true
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 74492e05a1c9..36e9e5f93bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -35,8 +35,8 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin);
-void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc);
-int intel_fbc_reset_underrun(struct intel_fbc *fbc);
+void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
+void intel_fbc_reset_underrun(struct drm_i915_private *i915);
int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable);
#endif /* __INTEL_FBC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 28d9eeb7b4f3..eb841960840d 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -434,7 +434,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
}
- intel_fbc_handle_fifo_underrun_irq(&dev_priv->fbc);
+ intel_fbc_handle_fifo_underrun_irq(dev_priv);
}
/**
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
2021-11-24 11:36 ` [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff Ville Syrjala
@ 2021-12-01 10:08 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC
> instance to FBC underrun stuff
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The underrun code doesn't need to know any details about FBC, so just pass in
> the whole device rather than a specific FBC instance.
> We could make this a bit more fine grained by also passing in the pipe to
> intel_fbc_handle_fifo_underrun_irq() and letting the FBC code figure which FBC
> instance (if any) is active on said pipe.
> But that seems a bit overkill for this so don't bother.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 4 +---
> drivers/gpu/drm/i915/display/intel_fbc.c | 24 +++++++++----------
> drivers/gpu/drm/i915/display/intel_fbc.h | 4 ++--
> .../drm/i915/display/intel_fifo_underrun.c | 2 +-
> 4 files changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index acf70ae66a29..3e456e595010 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2044,9 +2044,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
> return ret;
> }
>
> - ret = intel_fbc_reset_underrun(&dev_priv->fbc);
> - if (ret)
> - return ret;
> + intel_fbc_reset_underrun(dev_priv);
>
> return cnt;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 0bef3b948670..00c93040529e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1547,21 +1547,21 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
>
> /*
> * intel_fbc_reset_underrun - reset FBC fifo underrun status.
> - * @fbc: The FBC instance
> + * @i915: the i915 device
> *
> * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
> * want to re-enable FBC after an underrun to increase test coverage.
> */
> -int intel_fbc_reset_underrun(struct intel_fbc *fbc)
> +void intel_fbc_reset_underrun(struct drm_i915_private *i915)
> {
> - struct drm_i915_private *i915 = fbc->i915;
> - int ret;
> + struct intel_fbc *fbc = &i915->fbc;
> +
> + if (!HAS_FBC(i915))
> + return;
>
> cancel_work_sync(&fbc->underrun_work);
>
> - ret = mutex_lock_interruptible(&fbc->lock);
> - if (ret)
> - return ret;
> + mutex_lock(&fbc->lock);
>
> if (fbc->underrun_detected) {
> drm_dbg_kms(&i915->drm,
> @@ -1571,13 +1571,11 @@ int intel_fbc_reset_underrun(struct intel_fbc *fbc)
>
> fbc->underrun_detected = false;
> mutex_unlock(&fbc->lock);
> -
> - return 0;
> }
>
> /**
> * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO
> underrun
> - * @fbc: The FBC instance
> + * @i915: i915 device
> *
> * Without FBC, most underruns are harmless and don't really cause too many
> * problems, except for an annoying message on dmesg. With FBC, underruns
> can @@ -1589,9 +1587,11 @@ int intel_fbc_reset_underrun(struct intel_fbc
> *fbc)
> *
> * This function is called from the IRQ handler.
> */
> -void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
> +void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
> {
> - if (!HAS_FBC(fbc->i915))
> + struct intel_fbc *fbc = &i915->fbc;
> +
> + if (!HAS_FBC(i915))
> return;
>
> /* There's no guarantee that underrun_detected won't be set to true
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 74492e05a1c9..36e9e5f93bcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -35,8 +35,8 @@ void intel_fbc_invalidate(struct drm_i915_private
> *dev_priv,
> enum fb_op_origin origin);
> void intel_fbc_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits, enum fb_op_origin origin); -
> void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc); -int
> intel_fbc_reset_underrun(struct intel_fbc *fbc);
> +void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
> +void intel_fbc_reset_underrun(struct drm_i915_private *i915);
> int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable);
>
> #endif /* __INTEL_FBC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 28d9eeb7b4f3..eb841960840d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -434,7 +434,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct
> drm_i915_private *dev_priv,
> drm_err(&dev_priv->drm, "CPU pipe %c FIFO
> underrun\n", pipe_name(pipe));
> }
>
> - intel_fbc_handle_fifo_underrun_irq(&dev_priv->fbc);
> + intel_fbc_handle_fifo_underrun_irq(dev_priv);
> }
>
> /**
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (9 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 10/20] drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-11-24 15:43 ` Jani Nikula
2021-11-24 11:36 ` [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane() Ville Syrjala
` (20 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to encapsulate FBC harder let's just move the debugfs
stuff into intel_fbc.c.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 50 +-------
drivers/gpu/drm/i915/display/intel_fbc.c | 110 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_fbc.h | 4 +-
3 files changed, 82 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3e456e595010..572445299b04 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -40,52 +40,6 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
return 0;
}
-static int i915_fbc_status(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_fbc *fbc = &dev_priv->fbc;
- intel_wakeref_t wakeref;
-
- if (!HAS_FBC(dev_priv))
- return -ENODEV;
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- mutex_lock(&fbc->lock);
-
- if (intel_fbc_is_active(fbc)) {
- seq_puts(m, "FBC enabled\n");
- seq_printf(m, "Compressing: %s\n",
- yesno(intel_fbc_is_compressing(fbc)));
- } else {
- seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
- }
-
- mutex_unlock(&fbc->lock);
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-
- return 0;
-}
-
-static int i915_fbc_false_color_get(void *data, u64 *val)
-{
- struct drm_i915_private *dev_priv = data;
-
- *val = dev_priv->fbc.false_color;
-
- return 0;
-}
-
-static int i915_fbc_false_color_set(void *data, u64 val)
-{
- struct drm_i915_private *dev_priv = data;
-
- return intel_fbc_set_false_color(&dev_priv->fbc, val);
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
- i915_fbc_false_color_get, i915_fbc_false_color_set,
- "%llu\n");
-
static int i915_ips_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2058,7 +2012,6 @@ static const struct file_operations i915_fifo_underrun_reset_ops = {
static const struct drm_info_list intel_display_debugfs_list[] = {
{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
- {"i915_fbc_status", i915_fbc_status, 0},
{"i915_ips_status", i915_ips_status, 0},
{"i915_sr_status", i915_sr_status, 0},
{"i915_opregion", i915_opregion, 0},
@@ -2083,7 +2036,6 @@ static const struct {
{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
- {"i915_fbc_false_color", &i915_fbc_false_color_fops},
{"i915_dp_test_data", &i915_displayport_test_data_fops},
{"i915_dp_test_type", &i915_displayport_test_type_fops},
{"i915_dp_test_active", &i915_displayport_test_active_fops},
@@ -2110,6 +2062,8 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
drm_debugfs_create_files(intel_display_debugfs_list,
ARRAY_SIZE(intel_display_debugfs_list),
minor->debugfs_root, minor);
+
+ intel_fbc_debugfs_register(i915);
}
static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 00c93040529e..ee4e3186cc9c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -600,7 +600,7 @@ static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
fbc->funcs->deactivate(fbc);
}
-bool intel_fbc_is_compressing(struct intel_fbc *fbc)
+static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
{
return fbc->funcs->is_compressing(fbc);
}
@@ -612,36 +612,6 @@ static void intel_fbc_nuke(struct intel_fbc *fbc)
fbc->funcs->nuke(fbc);
}
-int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable)
-{
- if (!fbc->funcs || !fbc->funcs->set_false_color)
- return -ENODEV;
-
- mutex_lock(&fbc->lock);
-
- fbc->false_color = enable;
-
- fbc->funcs->set_false_color(fbc, enable);
-
- mutex_unlock(&fbc->lock);
-
- return 0;
-}
-
-/**
- * intel_fbc_is_active - Is FBC active?
- * @fbc: The FBC instance
- *
- * This function is used to verify the current state of FBC.
- *
- * FIXME: This should be tracked in the plane config eventually
- * instead of queried at runtime for most callers.
- */
-bool intel_fbc_is_active(struct intel_fbc *fbc)
-{
- return fbc->active;
-}
-
static void intel_fbc_activate(struct intel_fbc *fbc)
{
intel_fbc_hw_activate(fbc);
@@ -1691,3 +1661,81 @@ void intel_fbc_init(struct drm_i915_private *i915)
if (intel_fbc_hw_is_active(fbc))
intel_fbc_hw_deactivate(fbc);
}
+
+static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
+{
+ struct intel_fbc *fbc = m->private;
+ struct drm_i915_private *i915 = fbc->i915;
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ mutex_lock(&fbc->lock);
+
+ if (fbc->active) {
+ seq_puts(m, "FBC enabled\n");
+ seq_printf(m, "Compressing: %s\n",
+ yesno(intel_fbc_is_compressing(fbc)));
+ } else {
+ seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
+ }
+
+ mutex_unlock(&fbc->lock);
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
+
+static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
+{
+ struct intel_fbc *fbc = data;
+
+ *val = fbc->false_color;
+
+ return 0;
+}
+
+static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
+{
+ struct intel_fbc *fbc = data;
+
+ mutex_lock(&fbc->lock);
+
+ fbc->false_color = val;
+
+ if (fbc->active)
+ fbc->funcs->set_false_color(fbc, fbc->false_color);
+
+ mutex_unlock(&fbc->lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
+ intel_fbc_debugfs_false_color_get,
+ intel_fbc_debugfs_false_color_set,
+ "%llu\n");
+
+static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
+{
+ struct drm_i915_private *i915 = fbc->i915;
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_file("i915_fbc_status", 0444,
+ minor->debugfs_root, fbc,
+ &intel_fbc_debugfs_status_fops);
+
+ if (fbc->funcs->set_false_color)
+ debugfs_create_file("i915_fbc_false_color", 0644,
+ minor->debugfs_root, fbc,
+ &intel_fbc_debugfs_false_color_fops);
+}
+
+void intel_fbc_debugfs_register(struct drm_i915_private *i915)
+{
+ struct intel_fbc *fbc = &i915->fbc;
+
+ if (HAS_FBC(i915))
+ intel_fbc_debugfs_add(fbc);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 36e9e5f93bcb..0f5884f1e095 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -18,8 +18,6 @@ struct intel_fbc;
struct intel_plane_state;
int intel_fbc_atomic_check(struct intel_atomic_state *state);
-bool intel_fbc_is_active(struct intel_fbc *fbc);
-bool intel_fbc_is_compressing(struct intel_fbc *fbc);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_post_update(struct intel_atomic_state *state,
@@ -37,6 +35,6 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin);
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
void intel_fbc_reset_underrun(struct drm_i915_private *i915);
-int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable);
+void intel_fbc_debugfs_register(struct drm_i915_private *i915);
#endif /* __INTEL_FBC_H__ */
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-24 11:36 ` [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c Ville Syrjala
@ 2021-11-24 15:43 ` Jani Nikula
2021-11-25 9:43 ` Ville Syrjälä
0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2021-11-24 15:43 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to encapsulate FBC harder let's just move the debugfs
> stuff into intel_fbc.c.
Mmmh, I've kind of moved towards a split where i915_debugfs.c and
intel_display_debugfs.c have all the debugfs boilerplate, while the
implementation files have the guts with struct drm_i915_private *i915
(or something more specific) and struct seq_file *m passed in.
In some ways the split is arbitrary, but I kind of find the debugfs
boilerplate a distraction in the implementation files, and we also skip
building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
think I'd want to add #ifdefs on that spread around either.
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 50 +-------
> drivers/gpu/drm/i915/display/intel_fbc.c | 110 +++++++++++++-----
> drivers/gpu/drm/i915/display/intel_fbc.h | 4 +-
> 3 files changed, 82 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3e456e595010..572445299b04 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -40,52 +40,6 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
> return 0;
> }
>
> -static int i915_fbc_status(struct seq_file *m, void *unused)
> -{
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct intel_fbc *fbc = &dev_priv->fbc;
> - intel_wakeref_t wakeref;
> -
> - if (!HAS_FBC(dev_priv))
> - return -ENODEV;
> -
> - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> - mutex_lock(&fbc->lock);
> -
> - if (intel_fbc_is_active(fbc)) {
> - seq_puts(m, "FBC enabled\n");
> - seq_printf(m, "Compressing: %s\n",
> - yesno(intel_fbc_is_compressing(fbc)));
> - } else {
> - seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
> - }
> -
> - mutex_unlock(&fbc->lock);
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> -
> - return 0;
> -}
> -
> -static int i915_fbc_false_color_get(void *data, u64 *val)
> -{
> - struct drm_i915_private *dev_priv = data;
> -
> - *val = dev_priv->fbc.false_color;
> -
> - return 0;
> -}
> -
> -static int i915_fbc_false_color_set(void *data, u64 val)
> -{
> - struct drm_i915_private *dev_priv = data;
> -
> - return intel_fbc_set_false_color(&dev_priv->fbc, val);
> -}
> -
> -DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
> - i915_fbc_false_color_get, i915_fbc_false_color_set,
> - "%llu\n");
> -
> static int i915_ips_status(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -2058,7 +2012,6 @@ static const struct file_operations i915_fifo_underrun_reset_ops = {
>
> static const struct drm_info_list intel_display_debugfs_list[] = {
> {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
> - {"i915_fbc_status", i915_fbc_status, 0},
> {"i915_ips_status", i915_ips_status, 0},
> {"i915_sr_status", i915_sr_status, 0},
> {"i915_opregion", i915_opregion, 0},
> @@ -2083,7 +2036,6 @@ static const struct {
> {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
> {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
> {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
> - {"i915_fbc_false_color", &i915_fbc_false_color_fops},
> {"i915_dp_test_data", &i915_displayport_test_data_fops},
> {"i915_dp_test_type", &i915_displayport_test_type_fops},
> {"i915_dp_test_active", &i915_displayport_test_active_fops},
> @@ -2110,6 +2062,8 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
> drm_debugfs_create_files(intel_display_debugfs_list,
> ARRAY_SIZE(intel_display_debugfs_list),
> minor->debugfs_root, minor);
> +
> + intel_fbc_debugfs_register(i915);
> }
>
> static int i915_panel_show(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 00c93040529e..ee4e3186cc9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -600,7 +600,7 @@ static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
> fbc->funcs->deactivate(fbc);
> }
>
> -bool intel_fbc_is_compressing(struct intel_fbc *fbc)
> +static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
> {
> return fbc->funcs->is_compressing(fbc);
> }
> @@ -612,36 +612,6 @@ static void intel_fbc_nuke(struct intel_fbc *fbc)
> fbc->funcs->nuke(fbc);
> }
>
> -int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable)
> -{
> - if (!fbc->funcs || !fbc->funcs->set_false_color)
> - return -ENODEV;
> -
> - mutex_lock(&fbc->lock);
> -
> - fbc->false_color = enable;
> -
> - fbc->funcs->set_false_color(fbc, enable);
> -
> - mutex_unlock(&fbc->lock);
> -
> - return 0;
> -}
> -
> -/**
> - * intel_fbc_is_active - Is FBC active?
> - * @fbc: The FBC instance
> - *
> - * This function is used to verify the current state of FBC.
> - *
> - * FIXME: This should be tracked in the plane config eventually
> - * instead of queried at runtime for most callers.
> - */
> -bool intel_fbc_is_active(struct intel_fbc *fbc)
> -{
> - return fbc->active;
> -}
> -
> static void intel_fbc_activate(struct intel_fbc *fbc)
> {
> intel_fbc_hw_activate(fbc);
> @@ -1691,3 +1661,81 @@ void intel_fbc_init(struct drm_i915_private *i915)
> if (intel_fbc_hw_is_active(fbc))
> intel_fbc_hw_deactivate(fbc);
> }
> +
> +static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> +{
> + struct intel_fbc *fbc = m->private;
> + struct drm_i915_private *i915 = fbc->i915;
> + intel_wakeref_t wakeref;
> +
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> + mutex_lock(&fbc->lock);
> +
> + if (fbc->active) {
> + seq_puts(m, "FBC enabled\n");
> + seq_printf(m, "Compressing: %s\n",
> + yesno(intel_fbc_is_compressing(fbc)));
> + } else {
> + seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
> + }
> +
> + mutex_unlock(&fbc->lock);
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> +
> + return 0;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
> +
> +static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
> +{
> + struct intel_fbc *fbc = data;
> +
> + *val = fbc->false_color;
> +
> + return 0;
> +}
> +
> +static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
> +{
> + struct intel_fbc *fbc = data;
> +
> + mutex_lock(&fbc->lock);
> +
> + fbc->false_color = val;
> +
> + if (fbc->active)
> + fbc->funcs->set_false_color(fbc, fbc->false_color);
> +
> + mutex_unlock(&fbc->lock);
> +
> + return 0;
> +}
> +
> +DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
> + intel_fbc_debugfs_false_color_get,
> + intel_fbc_debugfs_false_color_set,
> + "%llu\n");
> +
> +static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
> +{
> + struct drm_i915_private *i915 = fbc->i915;
> + struct drm_minor *minor = i915->drm.primary;
> +
> + debugfs_create_file("i915_fbc_status", 0444,
> + minor->debugfs_root, fbc,
> + &intel_fbc_debugfs_status_fops);
> +
> + if (fbc->funcs->set_false_color)
> + debugfs_create_file("i915_fbc_false_color", 0644,
> + minor->debugfs_root, fbc,
> + &intel_fbc_debugfs_false_color_fops);
> +}
> +
> +void intel_fbc_debugfs_register(struct drm_i915_private *i915)
> +{
> + struct intel_fbc *fbc = &i915->fbc;
> +
> + if (HAS_FBC(i915))
> + intel_fbc_debugfs_add(fbc);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 36e9e5f93bcb..0f5884f1e095 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -18,8 +18,6 @@ struct intel_fbc;
> struct intel_plane_state;
>
> int intel_fbc_atomic_check(struct intel_atomic_state *state);
> -bool intel_fbc_is_active(struct intel_fbc *fbc);
> -bool intel_fbc_is_compressing(struct intel_fbc *fbc);
> bool intel_fbc_pre_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_fbc_post_update(struct intel_atomic_state *state,
> @@ -37,6 +35,6 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits, enum fb_op_origin origin);
> void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
> void intel_fbc_reset_underrun(struct drm_i915_private *i915);
> -int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable);
> +void intel_fbc_debugfs_register(struct drm_i915_private *i915);
>
> #endif /* __INTEL_FBC_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-24 15:43 ` Jani Nikula
@ 2021-11-25 9:43 ` Ville Syrjälä
2021-11-25 10:57 ` Jani Nikula
0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2021-11-25 9:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In order to encapsulate FBC harder let's just move the debugfs
> > stuff into intel_fbc.c.
>
> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
> intel_display_debugfs.c have all the debugfs boilerplate, while the
> implementation files have the guts with struct drm_i915_private *i915
> (or something more specific) and struct seq_file *m passed in.
>
> In some ways the split is arbitrary, but I kind of find the debugfs
> boilerplate a distraction in the implementation files, and we also skip
> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
> think I'd want to add #ifdefs on that spread around either.
If we want to keep the debugfs in a separate file then we'll have to
expose the guts of the FBC implementation in intel_fbc.h (or some other
header) just for that, or we add a whole bunch of otherwise useless
functions that pretend to provide some higher level of abstraction.
Not really a fan of either of those options.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-25 9:43 ` Ville Syrjälä
@ 2021-11-25 10:57 ` Jani Nikula
2021-11-25 12:13 ` Ville Syrjälä
0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2021-11-25 10:57 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, intel-gfx
On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > In order to encapsulate FBC harder let's just move the debugfs
>> > stuff into intel_fbc.c.
>>
>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
>> intel_display_debugfs.c have all the debugfs boilerplate, while the
>> implementation files have the guts with struct drm_i915_private *i915
>> (or something more specific) and struct seq_file *m passed in.
>>
>> In some ways the split is arbitrary, but I kind of find the debugfs
>> boilerplate a distraction in the implementation files, and we also skip
>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
>> think I'd want to add #ifdefs on that spread around either.
>
> If we want to keep the debugfs in a separate file then we'll have to
> expose the guts of the FBC implementation in intel_fbc.h (or some other
> header) just for that, or we add a whole bunch of otherwise useless
> functions that pretend to provide some higher level of abstraction.
>
> Not really a fan of either of those options.
Obviously I'm in favour of hiding the guts, no question about it. I'm
also very much in favour of moving the details out of our *debugfs.c
files. It's just a question of where to draw the line, and which side of
the line the debugfs boilerplate lands.
Which leaves us either your approach in the patch at hand, or adding the
fbc helper functions for debugfs, which would be something like:
intel_fbc_get_status
intel_fbc_get_false_color
intel_fbc_set_false_color
From a technical standpoint, I can appreciate the pros and cons of both
approaches. And I could be persuaded either way.
With the maintainer hat on, I'm considering the precedent this sets, and
where things start flowing after that. Do we accept all options for
other files, case by case, making this a continuous bikeshedding topic,
or do we want to choose an approach and start driving it everywhere?
Frankly I'm not all that fond of giving people a lot of options on stuff
like this, I prefer saying this is how we roll, let's stick to
it. (Until we decide otherwise, and stick to something else! ;)
Sooo... what would it be like if every file had their own
intel_foo_debugfs_register()? Including connector specific stuff such as
"i915_psr_status".
Cc'd other maintainers for good measure. Let's have one debugfs
bikeshedding now, and stick to it, instead of every time this pops up?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-25 10:57 ` Jani Nikula
@ 2021-11-25 12:13 ` Ville Syrjälä
2021-11-25 14:06 ` Tvrtko Ursulin
0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2021-11-25 12:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
> >> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > In order to encapsulate FBC harder let's just move the debugfs
> >> > stuff into intel_fbc.c.
> >>
> >> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
> >> intel_display_debugfs.c have all the debugfs boilerplate, while the
> >> implementation files have the guts with struct drm_i915_private *i915
> >> (or something more specific) and struct seq_file *m passed in.
> >>
> >> In some ways the split is arbitrary, but I kind of find the debugfs
> >> boilerplate a distraction in the implementation files, and we also skip
> >> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
> >> think I'd want to add #ifdefs on that spread around either.
> >
> > If we want to keep the debugfs in a separate file then we'll have to
> > expose the guts of the FBC implementation in intel_fbc.h (or some other
> > header) just for that, or we add a whole bunch of otherwise useless
> > functions that pretend to provide some higher level of abstraction.
> >
> > Not really a fan of either of those options.
>
> Obviously I'm in favour of hiding the guts, no question about it. I'm
> also very much in favour of moving the details out of our *debugfs.c
> files. It's just a question of where to draw the line, and which side of
> the line the debugfs boilerplate lands.
>
> Which leaves us either your approach in the patch at hand, or adding the
> fbc helper functions for debugfs, which would be something like:
>
> intel_fbc_get_status
> intel_fbc_get_false_color
> intel_fbc_set_false_color
So I guess you're suggesting that just the DEFINE_ATTRIBUTE
and debugfs_create_file() stuff should remain in
intel_display_debugfs.c?
Not sure that approach has any benefits whatsoever. The get/set
functions will need to be non-static and they'll get included in
the binary whether or not debugfs is enabled or not (unless you
lto it perhaps). If everything is in intel_fbc.c all that stuff
just gets optimized out entirely when not needed.
Also then I couldn't do this sort of stuff:
if (fbc->funcs->set_false_color)
debugfs_create_file(...)
because that requires knowledge only available to intel_fbc.c.
I'd need to add some kind of intel_fbc_has_false_color() thing
just for that.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-25 12:13 ` Ville Syrjälä
@ 2021-11-25 14:06 ` Tvrtko Ursulin
2021-11-25 14:27 ` Jani Nikula
0 siblings, 1 reply; 63+ messages in thread
From: Tvrtko Ursulin @ 2021-11-25 14:06 UTC (permalink / raw)
To: Ville Syrjälä, Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On 25/11/2021 12:13, Ville Syrjälä wrote:
> On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
>> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
>>>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>
>>>>> In order to encapsulate FBC harder let's just move the debugfs
>>>>> stuff into intel_fbc.c.
>>>>
>>>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
>>>> intel_display_debugfs.c have all the debugfs boilerplate, while the
>>>> implementation files have the guts with struct drm_i915_private *i915
>>>> (or something more specific) and struct seq_file *m passed in.
>>>>
>>>> In some ways the split is arbitrary, but I kind of find the debugfs
>>>> boilerplate a distraction in the implementation files, and we also skip
>>>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
>>>> think I'd want to add #ifdefs on that spread around either.
>>>
>>> If we want to keep the debugfs in a separate file then we'll have to
>>> expose the guts of the FBC implementation in intel_fbc.h (or some other
>>> header) just for that, or we add a whole bunch of otherwise useless
>>> functions that pretend to provide some higher level of abstraction.
>>>
>>> Not really a fan of either of those options.
>>
>> Obviously I'm in favour of hiding the guts, no question about it. I'm
>> also very much in favour of moving the details out of our *debugfs.c
>> files. It's just a question of where to draw the line, and which side of
>> the line the debugfs boilerplate lands.
>>
>> Which leaves us either your approach in the patch at hand, or adding the
>> fbc helper functions for debugfs, which would be something like:
>>
>> intel_fbc_get_status
>> intel_fbc_get_false_color
>> intel_fbc_set_false_color
>
> So I guess you're suggesting that just the DEFINE_ATTRIBUTE
> and debugfs_create_file() stuff should remain in
> intel_display_debugfs.c?
>
> Not sure that approach has any benefits whatsoever. The get/set
> functions will need to be non-static and they'll get included in
> the binary whether or not debugfs is enabled or not (unless you
> lto it perhaps). If everything is in intel_fbc.c all that stuff
> just gets optimized out entirely when not needed.
>
> Also then I couldn't do this sort of stuff:
> if (fbc->funcs->set_false_color)
> debugfs_create_file(...)
> because that requires knowledge only available to intel_fbc.c.
> I'd need to add some kind of intel_fbc_has_false_color() thing
> just for that.
Not guaranteeing I captured all the nuances here but how about an
approach similar to selftests? That is, have a separate file for debugfs
registration and bits (each "module" explicitly registers as in Ville's
patch), and have the owning "module" include the debugfs part at the end
of it. That way no exports, or defining too much API, would be needed.
And not needing common debugfs code to know the guts of any module.
Benefit of not compiling any of it when !CONFIG_DEBUG_FS is kept (or
gained, not even sure any more..).
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-25 14:06 ` Tvrtko Ursulin
@ 2021-11-25 14:27 ` Jani Nikula
2021-12-03 9:13 ` Ville Syrjälä
0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2021-11-25 14:27 UTC (permalink / raw)
To: Tvrtko Ursulin, Ville Syrjälä; +Cc: Daniel Vetter, intel-gfx
On Thu, 25 Nov 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 25/11/2021 12:13, Ville Syrjälä wrote:
>> On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
>>> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>>>> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
>>>>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>>
>>>>>> In order to encapsulate FBC harder let's just move the debugfs
>>>>>> stuff into intel_fbc.c.
>>>>>
>>>>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
>>>>> intel_display_debugfs.c have all the debugfs boilerplate, while the
>>>>> implementation files have the guts with struct drm_i915_private *i915
>>>>> (or something more specific) and struct seq_file *m passed in.
>>>>>
>>>>> In some ways the split is arbitrary, but I kind of find the debugfs
>>>>> boilerplate a distraction in the implementation files, and we also skip
>>>>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
>>>>> think I'd want to add #ifdefs on that spread around either.
>>>>
>>>> If we want to keep the debugfs in a separate file then we'll have to
>>>> expose the guts of the FBC implementation in intel_fbc.h (or some other
>>>> header) just for that, or we add a whole bunch of otherwise useless
>>>> functions that pretend to provide some higher level of abstraction.
>>>>
>>>> Not really a fan of either of those options.
>>>
>>> Obviously I'm in favour of hiding the guts, no question about it. I'm
>>> also very much in favour of moving the details out of our *debugfs.c
>>> files. It's just a question of where to draw the line, and which side of
>>> the line the debugfs boilerplate lands.
>>>
>>> Which leaves us either your approach in the patch at hand, or adding the
>>> fbc helper functions for debugfs, which would be something like:
>>>
>>> intel_fbc_get_status
>>> intel_fbc_get_false_color
>>> intel_fbc_set_false_color
>>
>> So I guess you're suggesting that just the DEFINE_ATTRIBUTE
>> and debugfs_create_file() stuff should remain in
>> intel_display_debugfs.c?
>>
>> Not sure that approach has any benefits whatsoever. The get/set
>> functions will need to be non-static and they'll get included in
>> the binary whether or not debugfs is enabled or not (unless you
>> lto it perhaps). If everything is in intel_fbc.c all that stuff
>> just gets optimized out entirely when not needed.
>>
>> Also then I couldn't do this sort of stuff:
>> if (fbc->funcs->set_false_color)
>> debugfs_create_file(...)
>> because that requires knowledge only available to intel_fbc.c.
>> I'd need to add some kind of intel_fbc_has_false_color() thing
>> just for that.
>
> Not guaranteeing I captured all the nuances here but how about an
> approach similar to selftests? That is, have a separate file for debugfs
> registration and bits (each "module" explicitly registers as in Ville's
> patch), and have the owning "module" include the debugfs part at the end
> of it. That way no exports, or defining too much API, would be needed.
> And not needing common debugfs code to know the guts of any module.
> Benefit of not compiling any of it when !CONFIG_DEBUG_FS is kept (or
> gained, not even sure any more..).
Frankly, I really dislike the "include code" part about selftests...
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-11-25 14:27 ` Jani Nikula
@ 2021-12-03 9:13 ` Ville Syrjälä
2021-12-03 9:55 ` Jani Nikula
0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2021-12-03 9:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Thu, Nov 25, 2021 at 04:27:18PM +0200, Jani Nikula wrote:
> On Thu, 25 Nov 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> > On 25/11/2021 12:13, Ville Syrjälä wrote:
> >> On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
> >>> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >>>> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
> >>>>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>>>>
> >>>>>> In order to encapsulate FBC harder let's just move the debugfs
> >>>>>> stuff into intel_fbc.c.
> >>>>>
> >>>>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
> >>>>> intel_display_debugfs.c have all the debugfs boilerplate, while the
> >>>>> implementation files have the guts with struct drm_i915_private *i915
> >>>>> (or something more specific) and struct seq_file *m passed in.
> >>>>>
> >>>>> In some ways the split is arbitrary, but I kind of find the debugfs
> >>>>> boilerplate a distraction in the implementation files, and we also skip
> >>>>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
> >>>>> think I'd want to add #ifdefs on that spread around either.
> >>>>
> >>>> If we want to keep the debugfs in a separate file then we'll have to
> >>>> expose the guts of the FBC implementation in intel_fbc.h (or some other
> >>>> header) just for that, or we add a whole bunch of otherwise useless
> >>>> functions that pretend to provide some higher level of abstraction.
> >>>>
> >>>> Not really a fan of either of those options.
> >>>
> >>> Obviously I'm in favour of hiding the guts, no question about it. I'm
> >>> also very much in favour of moving the details out of our *debugfs.c
> >>> files. It's just a question of where to draw the line, and which side of
> >>> the line the debugfs boilerplate lands.
> >>>
> >>> Which leaves us either your approach in the patch at hand, or adding the
> >>> fbc helper functions for debugfs, which would be something like:
> >>>
> >>> intel_fbc_get_status
> >>> intel_fbc_get_false_color
> >>> intel_fbc_set_false_color
> >>
> >> So I guess you're suggesting that just the DEFINE_ATTRIBUTE
> >> and debugfs_create_file() stuff should remain in
> >> intel_display_debugfs.c?
> >>
> >> Not sure that approach has any benefits whatsoever. The get/set
> >> functions will need to be non-static and they'll get included in
> >> the binary whether or not debugfs is enabled or not (unless you
> >> lto it perhaps). If everything is in intel_fbc.c all that stuff
> >> just gets optimized out entirely when not needed.
> >>
> >> Also then I couldn't do this sort of stuff:
> >> if (fbc->funcs->set_false_color)
> >> debugfs_create_file(...)
> >> because that requires knowledge only available to intel_fbc.c.
> >> I'd need to add some kind of intel_fbc_has_false_color() thing
> >> just for that.
> >
> > Not guaranteeing I captured all the nuances here but how about an
> > approach similar to selftests? That is, have a separate file for debugfs
> > registration and bits (each "module" explicitly registers as in Ville's
> > patch), and have the owning "module" include the debugfs part at the end
> > of it. That way no exports, or defining too much API, would be needed.
> > And not needing common debugfs code to know the guts of any module.
> > Benefit of not compiling any of it when !CONFIG_DEBUG_FS is kept (or
> > gained, not even sure any more..).
>
> Frankly, I really dislike the "include code" part about selftests...
We seem to have gone a bit off track in the discussion here. There
is no plan to do any kind of "include code" or anything here. All
I want to do is put the debugfs stuff into the same file as the
real implementation so that a) no implementation details need to
leak outside, b) the code gets optimized away when debufs is
disabled resulting in a smaller binary. Though I don't know if
anyone seriously compiles w/o debugfs anyway.
I guess another benefit is that it's harder to forget to
update the debugfs code when making changes to the rest of the
implementation. I've lost count how many times I've forgeotten
to do that with the debugfs code living in a totally separate
file.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-12-03 9:13 ` Ville Syrjälä
@ 2021-12-03 9:55 ` Jani Nikula
2021-12-03 10:06 ` Ville Syrjälä
0 siblings, 1 reply; 63+ messages in thread
From: Jani Nikula @ 2021-12-03 9:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, intel-gfx
On Fri, 03 Dec 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Nov 25, 2021 at 04:27:18PM +0200, Jani Nikula wrote:
>> On Thu, 25 Nov 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> > On 25/11/2021 12:13, Ville Syrjälä wrote:
>> >> On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
>> >>> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> >>>> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
>> >>>>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> >>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >>>>>>
>> >>>>>> In order to encapsulate FBC harder let's just move the debugfs
>> >>>>>> stuff into intel_fbc.c.
>> >>>>>
>> >>>>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
>> >>>>> intel_display_debugfs.c have all the debugfs boilerplate, while the
>> >>>>> implementation files have the guts with struct drm_i915_private *i915
>> >>>>> (or something more specific) and struct seq_file *m passed in.
>> >>>>>
>> >>>>> In some ways the split is arbitrary, but I kind of find the debugfs
>> >>>>> boilerplate a distraction in the implementation files, and we also skip
>> >>>>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
>> >>>>> think I'd want to add #ifdefs on that spread around either.
>> >>>>
>> >>>> If we want to keep the debugfs in a separate file then we'll have to
>> >>>> expose the guts of the FBC implementation in intel_fbc.h (or some other
>> >>>> header) just for that, or we add a whole bunch of otherwise useless
>> >>>> functions that pretend to provide some higher level of abstraction.
>> >>>>
>> >>>> Not really a fan of either of those options.
>> >>>
>> >>> Obviously I'm in favour of hiding the guts, no question about it. I'm
>> >>> also very much in favour of moving the details out of our *debugfs.c
>> >>> files. It's just a question of where to draw the line, and which side of
>> >>> the line the debugfs boilerplate lands.
>> >>>
>> >>> Which leaves us either your approach in the patch at hand, or adding the
>> >>> fbc helper functions for debugfs, which would be something like:
>> >>>
>> >>> intel_fbc_get_status
>> >>> intel_fbc_get_false_color
>> >>> intel_fbc_set_false_color
>> >>
>> >> So I guess you're suggesting that just the DEFINE_ATTRIBUTE
>> >> and debugfs_create_file() stuff should remain in
>> >> intel_display_debugfs.c?
>> >>
>> >> Not sure that approach has any benefits whatsoever. The get/set
>> >> functions will need to be non-static and they'll get included in
>> >> the binary whether or not debugfs is enabled or not (unless you
>> >> lto it perhaps). If everything is in intel_fbc.c all that stuff
>> >> just gets optimized out entirely when not needed.
>> >>
>> >> Also then I couldn't do this sort of stuff:
>> >> if (fbc->funcs->set_false_color)
>> >> debugfs_create_file(...)
>> >> because that requires knowledge only available to intel_fbc.c.
>> >> I'd need to add some kind of intel_fbc_has_false_color() thing
>> >> just for that.
>> >
>> > Not guaranteeing I captured all the nuances here but how about an
>> > approach similar to selftests? That is, have a separate file for debugfs
>> > registration and bits (each "module" explicitly registers as in Ville's
>> > patch), and have the owning "module" include the debugfs part at the end
>> > of it. That way no exports, or defining too much API, would be needed.
>> > And not needing common debugfs code to know the guts of any module.
>> > Benefit of not compiling any of it when !CONFIG_DEBUG_FS is kept (or
>> > gained, not even sure any more..).
>>
>> Frankly, I really dislike the "include code" part about selftests...
>
> We seem to have gone a bit off track in the discussion here. There
> is no plan to do any kind of "include code" or anything here. All
> I want to do is put the debugfs stuff into the same file as the
> real implementation so that a) no implementation details need to
> leak outside, b) the code gets optimized away when debufs is
> disabled resulting in a smaller binary. Though I don't know if
> anyone seriously compiles w/o debugfs anyway.
>
> I guess another benefit is that it's harder to forget to
> update the debugfs code when making changes to the rest of the
> implementation. I've lost count how many times I've forgeotten
> to do that with the debugfs code living in a totally separate
> file.
Yeah, let's un-stall this.
Acked-by: Jani Nikula <jani.nikula@intel.com>
on the change here, better abstractions and smaller interfaces being the
main rationale for it.
I think an insteresting question is, with all the debugfs stuff being
static in intel_fbc.c, is the compiler actually smart enough to optimize
the static code and data away when CONFIG_DEBUG_FS=n, even without
#ifdefs? Or is that something you're already claiming above?
If that's the case, my objection to adding #ifdefs just goes away.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-12-03 9:55 ` Jani Nikula
@ 2021-12-03 10:06 ` Ville Syrjälä
2021-12-03 10:47 ` Jani Nikula
0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2021-12-03 10:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Fri, Dec 03, 2021 at 11:55:43AM +0200, Jani Nikula wrote:
> On Fri, 03 Dec 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Nov 25, 2021 at 04:27:18PM +0200, Jani Nikula wrote:
> >> On Thu, 25 Nov 2021, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> >> > On 25/11/2021 12:13, Ville Syrjälä wrote:
> >> >> On Thu, Nov 25, 2021 at 12:57:27PM +0200, Jani Nikula wrote:
> >> >>> On Thu, 25 Nov 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> >>>> On Wed, Nov 24, 2021 at 05:43:52PM +0200, Jani Nikula wrote:
> >> >>>>> On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> >>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >>>>>>
> >> >>>>>> In order to encapsulate FBC harder let's just move the debugfs
> >> >>>>>> stuff into intel_fbc.c.
> >> >>>>>
> >> >>>>> Mmmh, I've kind of moved towards a split where i915_debugfs.c and
> >> >>>>> intel_display_debugfs.c have all the debugfs boilerplate, while the
> >> >>>>> implementation files have the guts with struct drm_i915_private *i915
> >> >>>>> (or something more specific) and struct seq_file *m passed in.
> >> >>>>>
> >> >>>>> In some ways the split is arbitrary, but I kind of find the debugfs
> >> >>>>> boilerplate a distraction in the implementation files, and we also skip
> >> >>>>> building the debugfs files completely for CONFIG_DEBUG_FS=n. I don't
> >> >>>>> think I'd want to add #ifdefs on that spread around either.
> >> >>>>
> >> >>>> If we want to keep the debugfs in a separate file then we'll have to
> >> >>>> expose the guts of the FBC implementation in intel_fbc.h (or some other
> >> >>>> header) just for that, or we add a whole bunch of otherwise useless
> >> >>>> functions that pretend to provide some higher level of abstraction.
> >> >>>>
> >> >>>> Not really a fan of either of those options.
> >> >>>
> >> >>> Obviously I'm in favour of hiding the guts, no question about it. I'm
> >> >>> also very much in favour of moving the details out of our *debugfs.c
> >> >>> files. It's just a question of where to draw the line, and which side of
> >> >>> the line the debugfs boilerplate lands.
> >> >>>
> >> >>> Which leaves us either your approach in the patch at hand, or adding the
> >> >>> fbc helper functions for debugfs, which would be something like:
> >> >>>
> >> >>> intel_fbc_get_status
> >> >>> intel_fbc_get_false_color
> >> >>> intel_fbc_set_false_color
> >> >>
> >> >> So I guess you're suggesting that just the DEFINE_ATTRIBUTE
> >> >> and debugfs_create_file() stuff should remain in
> >> >> intel_display_debugfs.c?
> >> >>
> >> >> Not sure that approach has any benefits whatsoever. The get/set
> >> >> functions will need to be non-static and they'll get included in
> >> >> the binary whether or not debugfs is enabled or not (unless you
> >> >> lto it perhaps). If everything is in intel_fbc.c all that stuff
> >> >> just gets optimized out entirely when not needed.
> >> >>
> >> >> Also then I couldn't do this sort of stuff:
> >> >> if (fbc->funcs->set_false_color)
> >> >> debugfs_create_file(...)
> >> >> because that requires knowledge only available to intel_fbc.c.
> >> >> I'd need to add some kind of intel_fbc_has_false_color() thing
> >> >> just for that.
> >> >
> >> > Not guaranteeing I captured all the nuances here but how about an
> >> > approach similar to selftests? That is, have a separate file for debugfs
> >> > registration and bits (each "module" explicitly registers as in Ville's
> >> > patch), and have the owning "module" include the debugfs part at the end
> >> > of it. That way no exports, or defining too much API, would be needed.
> >> > And not needing common debugfs code to know the guts of any module.
> >> > Benefit of not compiling any of it when !CONFIG_DEBUG_FS is kept (or
> >> > gained, not even sure any more..).
> >>
> >> Frankly, I really dislike the "include code" part about selftests...
> >
> > We seem to have gone a bit off track in the discussion here. There
> > is no plan to do any kind of "include code" or anything here. All
> > I want to do is put the debugfs stuff into the same file as the
> > real implementation so that a) no implementation details need to
> > leak outside, b) the code gets optimized away when debufs is
> > disabled resulting in a smaller binary. Though I don't know if
> > anyone seriously compiles w/o debugfs anyway.
> >
> > I guess another benefit is that it's harder to forget to
> > update the debugfs code when making changes to the rest of the
> > implementation. I've lost count how many times I've forgeotten
> > to do that with the debugfs code living in a totally separate
> > file.
>
> Yeah, let's un-stall this.
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> on the change here, better abstractions and smaller interfaces being the
> main rationale for it.
>
> I think an insteresting question is, with all the debugfs stuff being
> static in intel_fbc.c, is the compiler actually smart enough to optimize
> the static code and data away when CONFIG_DEBUG_FS=n, even without
> #ifdefs? Or is that something you're already claiming above?
Yes it all disappeared from the binary when I tried it.
Only thing left was an empty intel_fbc_debugfs_register().
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
2021-12-03 10:06 ` Ville Syrjälä
@ 2021-12-03 10:47 ` Jani Nikula
0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2021-12-03 10:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, intel-gfx
On Fri, 03 Dec 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Dec 03, 2021 at 11:55:43AM +0200, Jani Nikula wrote:
>> I think an insteresting question is, with all the debugfs stuff being
>> static in intel_fbc.c, is the compiler actually smart enough to optimize
>> the static code and data away when CONFIG_DEBUG_FS=n, even without
>> #ifdefs? Or is that something you're already claiming above?
>
> Yes it all disappeared from the binary when I tried it.
> Only thing left was an empty intel_fbc_debugfs_register().
\o/
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane()
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (10 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 11/20] drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 10:40 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically Ville Syrjala
` (19 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to better encapsulate the FBC implementation
introduce a small helper to do the plane<->FBC instance
association.
We'll also try to structure the plane init code such
that introducing multiple FBC instances will be easier
down the line.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 15 +++++++++++----
drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
.../gpu/drm/i915/display/skl_universal_plane.c | 15 +++++++++++----
4 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 2194f74101ae..84f50c90728f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -13,6 +13,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fb.h"
+#include "intel_fbc.h"
#include "intel_sprite.h"
#include "i9xx_plane.h"
@@ -120,6 +121,15 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
return i9xx_plane == PLANE_A;
}
+static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
+ enum i9xx_plane_id i9xx_plane)
+{
+ if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
+ return &dev_priv->fbc;
+ else
+ return NULL;
+}
+
static bool i9xx_plane_has_windowing(struct intel_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
@@ -807,10 +817,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->id = PLANE_PRIMARY;
plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
- if (i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane))
- plane->fbc = &dev_priv->fbc;
- if (plane->fbc)
- plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
+ intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
formats = vlv_primary_formats;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ee4e3186cc9c..9be8e7dcaab6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1612,6 +1612,15 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
return false;
}
+void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
+{
+ if (!fbc)
+ return;
+
+ plane->fbc = fbc;
+ fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
+}
+
/**
* intel_fbc_init - Initialize FBC
* @i915: the i915 device
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 0f5884f1e095..b8d9cda85cfc 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -15,6 +15,7 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_fbc;
+struct intel_plane;
struct intel_plane_state;
int intel_fbc_atomic_check(struct intel_atomic_state *state);
@@ -33,6 +34,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin);
+void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915);
void intel_fbc_reset_underrun(struct drm_i915_private *i915);
void intel_fbc_debugfs_register(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..22ec6901ee30 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -13,6 +13,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_fb.h"
+#include "intel_fbc.h"
#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -1815,6 +1816,15 @@ static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
}
+static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
+ return &dev_priv->fbc;
+ else
+ return NULL;
+}
+
static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2101,10 +2111,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->id = plane_id;
plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
- if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
- plane->fbc = &dev_priv->fbc;
- if (plane->fbc)
- plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
+ intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
if (DISPLAY_VER(dev_priv) >= 11) {
plane->min_width = icl_plane_min_width;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane()
2021-11-24 11:36 ` [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane() Ville Syrjala
@ 2021-12-01 10:40 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 10:40 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce
> intel_fbc_add_plane()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to better encapsulate the FBC implementation introduce a small helper
> to do the plane<->FBC instance association.
>
> We'll also try to structure the plane init code such that introducing multiple FBC
> instances will be easier down the line.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 15 +++++++++++----
> drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
> .../gpu/drm/i915/display/skl_universal_plane.c | 15 +++++++++++----
> 4 files changed, 33 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 2194f74101ae..84f50c90728f 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -13,6 +13,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> +#include "intel_fbc.h"
> #include "intel_sprite.h"
> #include "i9xx_plane.h"
>
> @@ -120,6 +121,15 @@ static bool i9xx_plane_has_fbc(struct
> drm_i915_private *dev_priv,
> return i9xx_plane == PLANE_A;
> }
>
> +static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
> + enum i9xx_plane_id i9xx_plane)
> +{
> + if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
> + return &dev_priv->fbc;
> + else
> + return NULL;
> +}
> +
> static bool i9xx_plane_has_windowing(struct intel_plane *plane) {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev); @@ -
> 807,10 +817,7 @@ intel_primary_plane_create(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> plane->id = PLANE_PRIMARY;
> plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
>
> - if (i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane))
> - plane->fbc = &dev_priv->fbc;
> - if (plane->fbc)
> - plane->fbc->possible_framebuffer_bits |= plane-
> >frontbuffer_bit;
> + intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane),
> +plane);
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index ee4e3186cc9c..9be8e7dcaab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1612,6 +1612,15 @@ static bool need_fbc_vtd_wa(struct
> drm_i915_private *i915)
> return false;
> }
>
> +void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane
> +*plane) {
> + if (!fbc)
> + return;
> +
> + plane->fbc = fbc;
> + fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; }
> +
> /**
> * intel_fbc_init - Initialize FBC
> * @i915: the i915 device
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 0f5884f1e095..b8d9cda85cfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -15,6 +15,7 @@ struct intel_atomic_state; struct intel_crtc; struct
> intel_crtc_state; struct intel_fbc;
> +struct intel_plane;
> struct intel_plane_state;
>
> int intel_fbc_atomic_check(struct intel_atomic_state *state); @@ -33,6 +34,7
> @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
> enum fb_op_origin origin);
> void intel_fbc_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits, enum fb_op_origin origin);
> +void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane
> +*plane);
> void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915); void
> intel_fbc_reset_underrun(struct drm_i915_private *i915); void
> intel_fbc_debugfs_register(struct drm_i915_private *i915); diff --git
> a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..22ec6901ee30 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -13,6 +13,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_fb.h"
> +#include "intel_fbc.h"
> #include "intel_pm.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> @@ -1815,6 +1816,15 @@ static bool skl_plane_has_fbc(struct
> drm_i915_private *dev_priv,
> return pipe == PIPE_A && plane_id == PLANE_PRIMARY; }
>
> +static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
> + enum pipe pipe, enum plane_id plane_id) {
> + if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> + return &dev_priv->fbc;
> + else
> + return NULL;
> +}
> +
> static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id) {
> @@ -2101,10 +2111,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> plane->id = plane_id;
> plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
>
> - if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> - plane->fbc = &dev_priv->fbc;
> - if (plane->fbc)
> - plane->fbc->possible_framebuffer_bits |= plane-
> >frontbuffer_bit;
> + intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> plane->min_width = icl_plane_min_width;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (11 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 12/20] drm/i915/fbc: Introduce intel_fbc_add_plane() Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:02 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane() Ville Syrjala
` (18 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In the future we may have more than one FBC instance on some
platforms. So let's just allocate it dynamically. This also
lets us fully hide the implementation from prying eyes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 154 +++++++++++++-----
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 59 +------
4 files changed, 116 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 84f50c90728f..85950ff67609 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return &dev_priv->fbc;
+ return dev_priv->fbc;
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 9be8e7dcaab6..1daf4f7b5d80 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -59,6 +59,63 @@ struct intel_fbc_funcs {
void (*set_false_color)(struct intel_fbc *fbc, bool enable);
};
+struct intel_fbc_state {
+ const char *no_fbc_reason;
+ enum i9xx_plane_id i9xx_plane;
+ unsigned int cfb_stride;
+ unsigned int cfb_size;
+ unsigned int fence_y_offset;
+ u16 override_cfb_stride;
+ u16 interval;
+ s8 fence_id;
+};
+
+struct intel_fbc {
+ struct drm_i915_private *i915;
+ const struct intel_fbc_funcs *funcs;
+
+ /*
+ * This is always the inner lock when overlapping with
+ * struct_mutex and it's the outer lock when overlapping
+ * with stolen_lock.
+ */
+ struct mutex lock;
+ unsigned int possible_framebuffer_bits;
+ unsigned int busy_bits;
+ struct intel_plane *plane;
+
+ struct drm_mm_node compressed_fb;
+ struct drm_mm_node compressed_llb;
+
+ u8 limit;
+
+ bool false_color;
+
+ bool active;
+ bool activated;
+ bool flip_pending;
+
+ bool underrun_detected;
+ struct work_struct underrun_work;
+
+ /*
+ * Due to the atomic rules we can't access some structures without the
+ * appropriate locking, so we cache information here in order to avoid
+ * these problems.
+ */
+ struct intel_fbc_state state_cache;
+
+ /*
+ * This structure contains everything that's relevant to program the
+ * hardware registers. When we want to figure out if we need to disable
+ * and re-enable FBC for a new configuration we just check if there's
+ * something different in the struct. The genx_fbc_activate functions
+ * are supposed to read from it in order to program the registers.
+ */
+ struct intel_fbc_state params;
+ const char *no_fbc_reason;
+};
+
/* plane stride in pixels */
static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
{
@@ -762,14 +819,16 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
void intel_fbc_cleanup(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
mutex_lock(&fbc->lock);
__intel_fbc_cleanup_cfb(fbc);
mutex_unlock(&fbc->lock);
+
+ kfree(fbc);
}
static bool stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1319,9 +1378,9 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
unsigned int frontbuffer_bits,
enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
@@ -1340,9 +1399,9 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
void intel_fbc_flush(struct drm_i915_private *i915,
unsigned int frontbuffer_bits, enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
mutex_lock(&fbc->lock);
@@ -1484,9 +1543,9 @@ void intel_fbc_update(struct intel_atomic_state *state,
*/
void intel_fbc_global_disable(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
mutex_lock(&fbc->lock);
@@ -1497,9 +1556,8 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
static void intel_fbc_underrun_work_fn(struct work_struct *work)
{
- struct drm_i915_private *i915 =
- container_of(work, struct drm_i915_private, fbc.underrun_work);
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
+ struct drm_i915_private *i915 = fbc->i915;
mutex_lock(&fbc->lock);
@@ -1524,9 +1582,9 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
*/
void intel_fbc_reset_underrun(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
cancel_work_sync(&fbc->underrun_work);
@@ -1559,9 +1617,9 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915)
*/
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (!HAS_FBC(i915))
+ if (!fbc)
return;
/* There's no guarantee that underrun_detected won't be set to true
@@ -1621,35 +1679,17 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
-/**
- * intel_fbc_init - Initialize FBC
- * @i915: the i915 device
- *
- * This function might be called during PM init process.
- */
-void intel_fbc_init(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc;
+
+ fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
+ if (!fbc)
+ return NULL;
fbc->i915 = i915;
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
- fbc->active = false;
-
- if (!drm_mm_initialized(&i915->mm.stolen))
- mkwrite_device_info(i915)->display.has_fbc = false;
-
- if (need_fbc_vtd_wa(i915))
- mkwrite_device_info(i915)->display.has_fbc = false;
-
- i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
- drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
- i915->params.enable_fbc);
-
- if (!HAS_FBC(i915)) {
- fbc->no_fbc_reason = "unsupported by this chipset";
- return;
- }
if (DISPLAY_VER(i915) >= 7)
fbc->funcs = &ivb_fbc_funcs;
@@ -1664,11 +1704,43 @@ void intel_fbc_init(struct drm_i915_private *i915)
else
fbc->funcs = &i8xx_fbc_funcs;
+ return fbc;
+}
+
+/**
+ * intel_fbc_init - Initialize FBC
+ * @i915: the i915 device
+ *
+ * This function might be called during PM init process.
+ */
+void intel_fbc_init(struct drm_i915_private *i915)
+{
+ struct intel_fbc *fbc;
+
+ if (!drm_mm_initialized(&i915->mm.stolen))
+ mkwrite_device_info(i915)->display.has_fbc = false;
+
+ if (need_fbc_vtd_wa(i915))
+ mkwrite_device_info(i915)->display.has_fbc = false;
+
+ i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
+ drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
+ i915->params.enable_fbc);
+
+ if (!HAS_FBC(i915))
+ return;
+
+ fbc = intel_fbc_create(i915);
+ if (!fbc)
+ return;
+
/* We still don't have any sort of hardware state readout for FBC, so
* deactivate it in case the BIOS activated it to make sure software
* matches the hardware state. */
if (intel_fbc_hw_is_active(fbc))
intel_fbc_hw_deactivate(fbc);
+
+ i915->fbc = fbc;
}
static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -1743,8 +1815,8 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
void intel_fbc_debugfs_register(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = &i915->fbc;
+ struct intel_fbc *fbc = i915->fbc;
- if (HAS_FBC(i915))
+ if (fbc)
intel_fbc_debugfs_add(fbc);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 22ec6901ee30..980f23680842 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1820,7 +1820,7 @@ static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
- return &dev_priv->fbc;
+ return dev_priv->fbc;
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f632b026ce34..12099f7ff98e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -399,64 +399,8 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
};
-struct intel_fbc_funcs;
-
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
-struct intel_fbc_state {
- const char *no_fbc_reason;
- enum i9xx_plane_id i9xx_plane;
- unsigned int cfb_stride;
- unsigned int cfb_size;
- unsigned int fence_y_offset;
- u16 override_cfb_stride;
- u16 interval;
- s8 fence_id;
-};
-
-struct intel_fbc {
- struct drm_i915_private *i915;
- const struct intel_fbc_funcs *funcs;
-
- /* This is always the inner lock when overlapping with struct_mutex and
- * it's the outer lock when overlapping with stolen_lock. */
- struct mutex lock;
- unsigned int possible_framebuffer_bits;
- unsigned int busy_bits;
- struct intel_plane *plane;
-
- struct drm_mm_node compressed_fb;
- struct drm_mm_node compressed_llb;
-
- u8 limit;
-
- bool false_color;
-
- bool active;
- bool activated;
- bool flip_pending;
-
- bool underrun_detected;
- struct work_struct underrun_work;
-
- /*
- * Due to the atomic rules we can't access some structures without the
- * appropriate locking, so we cache information here in order to avoid
- * these problems.
- */
- struct intel_fbc_state state_cache;
-
- /*
- * This structure contains everything that's relevant to program the
- * hardware registers. When we want to figure out if we need to disable
- * and re-enable FBC for a new configuration we just check if there's
- * something different in the struct. The genx_fbc_activate functions
- * are supposed to read from it in order to program the registers.
- */
- struct intel_fbc_state params;
- const char *no_fbc_reason;
-};
-
/*
* HIGH_RR is the highest eDP panel refresh rate read from EDID
* LOW_RR is the lowest eDP panel refresh rate found from EDID
@@ -493,7 +437,6 @@ struct i915_drrs {
#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
struct intel_fbdev;
-struct intel_fbc_work;
struct intel_gmbus {
struct i2c_adapter adapter;
@@ -892,7 +835,7 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
- struct intel_fbc fbc;
+ struct intel_fbc *fbc;
struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically
2021-11-24 11:36 ` [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically Ville Syrjala
@ 2021-12-01 11:02 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:02 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In the future we may have more than one FBC instance on some platforms. So
> let's just allocate it dynamically. This also lets us fully hide the implementation
> from prying eyes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 154 +++++++++++++-----
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 59 +------
> 4 files changed, 116 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 84f50c90728f..85950ff67609 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct
> drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane)
> {
> if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
> - return &dev_priv->fbc;
> + return dev_priv->fbc;
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 9be8e7dcaab6..1daf4f7b5d80 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -59,6 +59,63 @@ struct intel_fbc_funcs {
> void (*set_false_color)(struct intel_fbc *fbc, bool enable); };
>
> +struct intel_fbc_state {
> + const char *no_fbc_reason;
> + enum i9xx_plane_id i9xx_plane;
> + unsigned int cfb_stride;
> + unsigned int cfb_size;
> + unsigned int fence_y_offset;
> + u16 override_cfb_stride;
> + u16 interval;
> + s8 fence_id;
> +};
> +
> +struct intel_fbc {
> + struct drm_i915_private *i915;
> + const struct intel_fbc_funcs *funcs;
> +
> + /*
> + * This is always the inner lock when overlapping with
> + * struct_mutex and it's the outer lock when overlapping
> + * with stolen_lock.
> + */
> + struct mutex lock;
> + unsigned int possible_framebuffer_bits;
> + unsigned int busy_bits;
> + struct intel_plane *plane;
> +
> + struct drm_mm_node compressed_fb;
> + struct drm_mm_node compressed_llb;
> +
> + u8 limit;
> +
> + bool false_color;
> +
> + bool active;
> + bool activated;
> + bool flip_pending;
> +
> + bool underrun_detected;
> + struct work_struct underrun_work;
> +
> + /*
> + * Due to the atomic rules we can't access some structures without the
> + * appropriate locking, so we cache information here in order to avoid
> + * these problems.
> + */
> + struct intel_fbc_state state_cache;
> +
> + /*
> + * This structure contains everything that's relevant to program the
> + * hardware registers. When we want to figure out if we need to disable
> + * and re-enable FBC for a new configuration we just check if there's
> + * something different in the struct. The genx_fbc_activate functions
> + * are supposed to read from it in order to program the registers.
> + */
> + struct intel_fbc_state params;
> + const char *no_fbc_reason;
> +};
> +
> /* plane stride in pixels */
> static unsigned int intel_fbc_plane_stride(const struct intel_plane_state
> *plane_state) { @@ -762,14 +819,16 @@ static void
> __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>
> void intel_fbc_cleanup(struct drm_i915_private *i915) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> mutex_lock(&fbc->lock);
> __intel_fbc_cleanup_cfb(fbc);
> mutex_unlock(&fbc->lock);
> +
> + kfree(fbc);
> }
>
> static bool stride_is_valid(const struct intel_plane_state *plane_state) @@ -
> 1319,9 +1378,9 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
> unsigned int frontbuffer_bits,
> enum fb_op_origin origin)
> {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) @@ -
> 1340,9 +1399,9 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
> void intel_fbc_flush(struct drm_i915_private *i915,
> unsigned int frontbuffer_bits, enum fb_op_origin origin) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> mutex_lock(&fbc->lock);
> @@ -1484,9 +1543,9 @@ void intel_fbc_update(struct intel_atomic_state
> *state,
> */
> void intel_fbc_global_disable(struct drm_i915_private *i915) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> mutex_lock(&fbc->lock);
> @@ -1497,9 +1556,8 @@ void intel_fbc_global_disable(struct drm_i915_private
> *i915)
>
> static void intel_fbc_underrun_work_fn(struct work_struct *work) {
> - struct drm_i915_private *i915 =
> - container_of(work, struct drm_i915_private,
> fbc.underrun_work);
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = container_of(work, typeof(*fbc),
> underrun_work);
> + struct drm_i915_private *i915 = fbc->i915;
>
> mutex_lock(&fbc->lock);
>
> @@ -1524,9 +1582,9 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
> */
> void intel_fbc_reset_underrun(struct drm_i915_private *i915) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> cancel_work_sync(&fbc->underrun_work);
> @@ -1559,9 +1617,9 @@ void intel_fbc_reset_underrun(struct
> drm_i915_private *i915)
> */
> void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (!HAS_FBC(i915))
> + if (!fbc)
> return;
>
> /* There's no guarantee that underrun_detected won't be set to true
> @@ -1621,35 +1679,17 @@ void intel_fbc_add_plane(struct intel_fbc *fbc,
> struct intel_plane *plane)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; }
>
> -/**
> - * intel_fbc_init - Initialize FBC
> - * @i915: the i915 device
> - *
> - * This function might be called during PM init process.
> - */
> -void intel_fbc_init(struct drm_i915_private *i915)
> +static struct intel_fbc *intel_fbc_create(struct drm_i915_private
> +*i915)
> {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc;
> +
> + fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
> + if (!fbc)
> + return NULL;
>
> fbc->i915 = i915;
> INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
> mutex_init(&fbc->lock);
> - fbc->active = false;
> -
> - if (!drm_mm_initialized(&i915->mm.stolen))
> - mkwrite_device_info(i915)->display.has_fbc = false;
> -
> - if (need_fbc_vtd_wa(i915))
> - mkwrite_device_info(i915)->display.has_fbc = false;
> -
> - i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
> - drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> - i915->params.enable_fbc);
> -
> - if (!HAS_FBC(i915)) {
> - fbc->no_fbc_reason = "unsupported by this chipset";
> - return;
> - }
>
> if (DISPLAY_VER(i915) >= 7)
> fbc->funcs = &ivb_fbc_funcs;
> @@ -1664,11 +1704,43 @@ void intel_fbc_init(struct drm_i915_private *i915)
> else
> fbc->funcs = &i8xx_fbc_funcs;
>
> + return fbc;
> +}
> +
> +/**
> + * intel_fbc_init - Initialize FBC
> + * @i915: the i915 device
> + *
> + * This function might be called during PM init process.
> + */
> +void intel_fbc_init(struct drm_i915_private *i915) {
> + struct intel_fbc *fbc;
> +
> + if (!drm_mm_initialized(&i915->mm.stolen))
> + mkwrite_device_info(i915)->display.has_fbc = false;
> +
> + if (need_fbc_vtd_wa(i915))
> + mkwrite_device_info(i915)->display.has_fbc = false;
> +
> + i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
> + drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> + i915->params.enable_fbc);
> +
> + if (!HAS_FBC(i915))
> + return;
> +
> + fbc = intel_fbc_create(i915);
> + if (!fbc)
> + return;
> +
> /* We still don't have any sort of hardware state readout for FBC, so
> * deactivate it in case the BIOS activated it to make sure software
> * matches the hardware state. */
> if (intel_fbc_hw_is_active(fbc))
> intel_fbc_hw_deactivate(fbc);
> +
> + i915->fbc = fbc;
> }
>
> static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) @@
> -1743,8 +1815,8 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
>
> void intel_fbc_debugfs_register(struct drm_i915_private *i915) {
> - struct intel_fbc *fbc = &i915->fbc;
> + struct intel_fbc *fbc = i915->fbc;
>
> - if (HAS_FBC(i915))
> + if (fbc)
> intel_fbc_debugfs_add(fbc);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 22ec6901ee30..980f23680842 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1820,7 +1820,7 @@ static struct intel_fbc *skl_plane_fbc(struct
> drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id) {
> if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> - return &dev_priv->fbc;
> + return dev_priv->fbc;
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f632b026ce34..12099f7ff98e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -399,64 +399,8 @@ struct drm_i915_display_funcs {
> void (*commit_modeset_enables)(struct intel_atomic_state *state); };
>
> -struct intel_fbc_funcs;
> -
> #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address
> space */
>
> -struct intel_fbc_state {
> - const char *no_fbc_reason;
> - enum i9xx_plane_id i9xx_plane;
> - unsigned int cfb_stride;
> - unsigned int cfb_size;
> - unsigned int fence_y_offset;
> - u16 override_cfb_stride;
> - u16 interval;
> - s8 fence_id;
> -};
> -
> -struct intel_fbc {
> - struct drm_i915_private *i915;
> - const struct intel_fbc_funcs *funcs;
> -
> - /* This is always the inner lock when overlapping with struct_mutex and
> - * it's the outer lock when overlapping with stolen_lock. */
> - struct mutex lock;
> - unsigned int possible_framebuffer_bits;
> - unsigned int busy_bits;
> - struct intel_plane *plane;
> -
> - struct drm_mm_node compressed_fb;
> - struct drm_mm_node compressed_llb;
> -
> - u8 limit;
> -
> - bool false_color;
> -
> - bool active;
> - bool activated;
> - bool flip_pending;
> -
> - bool underrun_detected;
> - struct work_struct underrun_work;
> -
> - /*
> - * Due to the atomic rules we can't access some structures without the
> - * appropriate locking, so we cache information here in order to avoid
> - * these problems.
> - */
> - struct intel_fbc_state state_cache;
> -
> - /*
> - * This structure contains everything that's relevant to program the
> - * hardware registers. When we want to figure out if we need to disable
> - * and re-enable FBC for a new configuration we just check if there's
> - * something different in the struct. The genx_fbc_activate functions
> - * are supposed to read from it in order to program the registers.
> - */
> - struct intel_fbc_state params;
> - const char *no_fbc_reason;
> -};
> -
> /*
> * HIGH_RR is the highest eDP panel refresh rate read from EDID
> * LOW_RR is the lowest eDP panel refresh rate found from EDID @@ -493,7
> +437,6 @@ struct i915_drrs { #define
> QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
>
> struct intel_fbdev;
> -struct intel_fbc_work;
>
> struct intel_gmbus {
> struct i2c_adapter adapter;
> @@ -892,7 +835,7 @@ struct drm_i915_private {
> u32 pipestat_irq_mask[I915_MAX_PIPES];
>
> struct i915_hotplug hotplug;
> - struct intel_fbc fbc;
> + struct intel_fbc *fbc;
> struct i915_drrs drrs;
> struct intel_opregion opregion;
> struct intel_vbt_data vbt;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (12 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 13/20] drm/i915/fbc: Allocate intel_fbc dynamically Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:03 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun Ville Syrjala
` (17 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Don't really see a good reason why we can't just do the vgpu and
modparam checks already in intel_fbc_check_plane().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1daf4f7b5d80..616ab95766b2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -996,18 +996,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
static bool intel_fbc_can_enable(struct intel_fbc *fbc)
{
- struct drm_i915_private *i915 = fbc->i915;
-
- if (intel_vgpu_active(i915)) {
- fbc->no_fbc_reason = "VGPU is active";
- return false;
- }
-
- if (!i915->params.enable_fbc) {
- fbc->no_fbc_reason = "disabled per module param or by default";
- return false;
- }
-
if (fbc->underrun_detected) {
fbc->no_fbc_reason = "underrun detected";
return false;
@@ -1030,6 +1018,16 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
if (!fbc)
return 0;
+ if (intel_vgpu_active(i915)) {
+ plane_state->no_fbc_reason = "VGPU active";
+ return 0;
+ }
+
+ if (!i915->params.enable_fbc) {
+ plane_state->no_fbc_reason = "disabled per module param or by default";
+ return 0;
+ }
+
if (!plane_state->uapi.visible) {
plane_state->no_fbc_reason = "plane not visible";
return 0;
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
2021-11-24 11:36 ` [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane() Ville Syrjala
@ 2021-12-01 11:03 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:03 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from
> intel_fbc_can_enable() into intel_fbc_check_plane()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Don't really see a good reason why we can't just do the vgpu and modparam
> checks already in intel_fbc_check_plane().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++++++++++------------
> 1 file changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1daf4f7b5d80..616ab95766b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -996,18 +996,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc
> *fbc)
>
> static bool intel_fbc_can_enable(struct intel_fbc *fbc) {
> - struct drm_i915_private *i915 = fbc->i915;
> -
> - if (intel_vgpu_active(i915)) {
> - fbc->no_fbc_reason = "VGPU is active";
> - return false;
> - }
> -
> - if (!i915->params.enable_fbc) {
> - fbc->no_fbc_reason = "disabled per module param or by
> default";
> - return false;
> - }
> -
> if (fbc->underrun_detected) {
> fbc->no_fbc_reason = "underrun detected";
> return false;
> @@ -1030,6 +1018,16 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> if (!fbc)
> return 0;
>
> + if (intel_vgpu_active(i915)) {
> + plane_state->no_fbc_reason = "VGPU active";
> + return 0;
> + }
> +
> + if (!i915->params.enable_fbc) {
> + plane_state->no_fbc_reason = "disabled per module param or
> by default";
> + return 0;
> + }
> +
> if (!plane_state->uapi.visible) {
> plane_state->no_fbc_reason = "plane not visible";
> return 0;
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (13 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 14/20] drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane() Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:04 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache Ville Syrjala
` (16 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently a FIFO underrun just causes FBC to be deactivated,
and later checks then prevent it from being reactivated. We
can simpify our lives a bit by logically disabling FBC on
FIFO underruna. This avoids the funny intermediate state where
FBC is logically enabled but can't actually be activated.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 29 +++++++-----------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 616ab95766b2..74ba54d70e57 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -994,16 +994,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
return fbc->state_cache.cfb_size > fbc->compressed_fb.size * fbc->limit;
}
-static bool intel_fbc_can_enable(struct intel_fbc *fbc)
-{
- if (fbc->underrun_detected) {
- fbc->no_fbc_reason = "underrun detected";
- return false;
- }
-
- return true;
-}
-
static int intel_fbc_check_plane(struct intel_atomic_state *state,
struct intel_plane *plane)
{
@@ -1123,22 +1113,11 @@ static bool intel_fbc_can_activate(struct intel_fbc *fbc)
struct drm_i915_private *i915 = fbc->i915;
struct intel_fbc_state *cache = &fbc->state_cache;
- if (!intel_fbc_can_enable(fbc))
- return false;
-
if (cache->no_fbc_reason) {
fbc->no_fbc_reason = cache->no_fbc_reason;
return false;
}
- /* We don't need to use a state cache here since this information is
- * global for all CRTC.
- */
- if (fbc->underrun_detected) {
- fbc->no_fbc_reason = "underrun detected";
- return false;
- }
-
/* The use of a CPU fence is one of two ways to detect writes by the
* CPU to the scanout and trigger updates to the FBC.
*
@@ -1467,6 +1446,11 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
if (cache->no_fbc_reason)
return;
+ if (fbc->underrun_detected) {
+ fbc->no_fbc_reason = "FIFO underrun";
+ return;
+ }
+
if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
fbc->no_fbc_reason = "not enough stolen memory";
return;
@@ -1567,6 +1551,9 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
fbc->underrun_detected = true;
intel_fbc_deactivate(fbc, "FIFO underrun");
+ if (!fbc->flip_pending)
+ intel_wait_for_vblank(i915, fbc->plane->pipe);
+ __intel_fbc_disable(fbc);
out:
mutex_unlock(&fbc->lock);
}
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun
2021-11-24 11:36 ` [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun Ville Syrjala
@ 2021-12-01 11:04 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:04 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO
> underrun
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently a FIFO underrun just causes FBC to be deactivated, and later checks
> then prevent it from being reactivated. We can simpify our lives a bit by logically
> disabling FBC on FIFO underruna. This avoids the funny intermediate state where
> FBC is logically enabled but can't actually be activated.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 29 +++++++-----------------
> 1 file changed, 8 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 616ab95766b2..74ba54d70e57 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -994,16 +994,6 @@ static bool intel_fbc_cfb_size_changed(struct intel_fbc
> *fbc)
> return fbc->state_cache.cfb_size > fbc->compressed_fb.size * fbc-
> >limit; }
>
> -static bool intel_fbc_can_enable(struct intel_fbc *fbc) -{
> - if (fbc->underrun_detected) {
> - fbc->no_fbc_reason = "underrun detected";
> - return false;
> - }
> -
> - return true;
> -}
> -
> static int intel_fbc_check_plane(struct intel_atomic_state *state,
> struct intel_plane *plane)
> {
> @@ -1123,22 +1113,11 @@ static bool intel_fbc_can_activate(struct intel_fbc
> *fbc)
> struct drm_i915_private *i915 = fbc->i915;
> struct intel_fbc_state *cache = &fbc->state_cache;
>
> - if (!intel_fbc_can_enable(fbc))
> - return false;
> -
> if (cache->no_fbc_reason) {
> fbc->no_fbc_reason = cache->no_fbc_reason;
> return false;
> }
>
> - /* We don't need to use a state cache here since this information is
> - * global for all CRTC.
> - */
> - if (fbc->underrun_detected) {
> - fbc->no_fbc_reason = "underrun detected";
> - return false;
> - }
> -
> /* The use of a CPU fence is one of two ways to detect writes by the
> * CPU to the scanout and trigger updates to the FBC.
> *
> @@ -1467,6 +1446,11 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> if (cache->no_fbc_reason)
> return;
>
> + if (fbc->underrun_detected) {
> + fbc->no_fbc_reason = "FIFO underrun";
> + return;
> + }
> +
> if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
> fbc->no_fbc_reason = "not enough stolen memory";
> return;
> @@ -1567,6 +1551,9 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
> fbc->underrun_detected = true;
>
> intel_fbc_deactivate(fbc, "FIFO underrun");
> + if (!fbc->flip_pending)
> + intel_wait_for_vblank(i915, fbc->plane->pipe);
> + __intel_fbc_disable(fbc);
> out:
> mutex_unlock(&fbc->lock);
> }
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (14 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 15/20] drm/i915/fbc: Disable FBC fully on FIFO underrun Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:06 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state Ville Syrjala
` (15 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
fbc->state_cache has now become useless. We can simply update
the reg params directly from the plane/crtc states during
__intel_fbc_enable().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 169 +++++++++--------------
1 file changed, 62 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 74ba54d70e57..7d128a49e8e1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -60,7 +60,6 @@ struct intel_fbc_funcs {
};
struct intel_fbc_state {
- const char *no_fbc_reason;
enum i9xx_plane_id i9xx_plane;
unsigned int cfb_stride;
unsigned int cfb_size;
@@ -98,13 +97,6 @@ struct intel_fbc {
bool underrun_detected;
struct work_struct underrun_work;
- /*
- * Due to the atomic rules we can't access some structures without the
- * appropriate locking, so we cache information here in order to avoid
- * these problems.
- */
- struct intel_fbc_state state_cache;
-
/*
* This structure contains everything that's relevant to program the
* hardware registers. When we want to figure out if we need to disable
@@ -673,6 +665,8 @@ static void intel_fbc_activate(struct intel_fbc *fbc)
{
intel_fbc_hw_activate(fbc);
intel_fbc_nuke(fbc);
+
+ fbc->no_fbc_reason = NULL;
}
static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
@@ -714,9 +708,7 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
{
- int fb_cpp = plane_state->hw.fb ? plane_state->hw.fb->format->cpp[0] : 0;
-
- return fb_cpp == 2 ? 2 : 1;
+ return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
}
static int intel_fbc_max_limit(struct drm_i915_private *i915)
@@ -962,10 +954,9 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state *cache = &fbc->state_cache;
+ struct intel_fbc_state *cache = &fbc->params;
- cache->no_fbc_reason = plane_state->no_fbc_reason;
- if (cache->no_fbc_reason)
+ if (plane_state->no_fbc_reason)
return;
cache->i9xx_plane = plane->i9xx_plane;
@@ -989,9 +980,46 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
cache->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
}
-static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
+static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
{
- return fbc->state_cache.cfb_size > fbc->compressed_fb.size * fbc->limit;
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+ /* The use of a CPU fence is one of two ways to detect writes by the
+ * CPU to the scanout and trigger updates to the FBC.
+ *
+ * The other method is by software tracking (see
+ * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
+ * the current compressed buffer and recompress it.
+ *
+ * Note that is possible for a tiled surface to be unmappable (and
+ * so have no fence associated with it) due to aperture constraints
+ * at the time of pinning.
+ *
+ * FIXME with 90/270 degree rotation we should use the fence on
+ * the normal GTT view (the rotated view doesn't even have a
+ * fence). Would need changes to the FBC fence Y offset as well.
+ * For now this will effectively disable FBC with 90/270 degree
+ * rotation.
+ */
+ return DISPLAY_VER(i915) >= 9 ||
+ (plane_state->flags & PLANE_HAS_FENCE &&
+ plane_state->ggtt_vma->fence);
+}
+
+static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct intel_fbc *fbc = plane->fbc;
+
+ return intel_fbc_min_limit(plane_state) <= fbc->limit &&
+ intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit;
+}
+
+static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
+{
+ return !plane_state->no_fbc_reason &&
+ intel_fbc_is_fence_ok(plane_state) &&
+ intel_fbc_is_cfb_ok(plane_state);
}
static int intel_fbc_check_plane(struct intel_atomic_state *state,
@@ -1108,74 +1136,11 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
return 0;
}
-static bool intel_fbc_can_activate(struct intel_fbc *fbc)
-{
- struct drm_i915_private *i915 = fbc->i915;
- struct intel_fbc_state *cache = &fbc->state_cache;
-
- if (cache->no_fbc_reason) {
- fbc->no_fbc_reason = cache->no_fbc_reason;
- return false;
- }
-
- /* The use of a CPU fence is one of two ways to detect writes by the
- * CPU to the scanout and trigger updates to the FBC.
- *
- * The other method is by software tracking (see
- * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
- * the current compressed buffer and recompress it.
- *
- * Note that is possible for a tiled surface to be unmappable (and
- * so have no fence associated with it) due to aperture constraints
- * at the time of pinning.
- *
- * FIXME with 90/270 degree rotation we should use the fence on
- * the normal GTT view (the rotated view doesn't even have a
- * fence). Would need changes to the FBC fence Y offset as well.
- * For now this will effectively disable FBC with 90/270 degree
- * rotation.
- */
- if (DISPLAY_VER(i915) < 9 && cache->fence_id < 0) {
- fbc->no_fbc_reason = "framebuffer not tiled or fenced";
- return false;
- }
-
- /*
- * It is possible for the required CFB size change without a
- * crtc->disable + crtc->enable since it is possible to change the
- * stride without triggering a full modeset. Since we try to
- * over-allocate the CFB, there's a chance we may keep FBC enabled even
- * if this happens, but if we exceed the current CFB size we'll have to
- * disable FBC. Notice that it would be possible to disable FBC, wait
- * for a frame, free the stolen node, then try to reenable FBC in case
- * we didn't get any invalidate/deactivate calls, but this would require
- * a lot of tracking just for a specific case. If we conclude it's an
- * important case, we can implement it later.
- */
- if (intel_fbc_cfb_size_changed(fbc)) {
- fbc->no_fbc_reason = "CFB requirements changed";
- return false;
- }
-
- return true;
-}
-
-static void intel_fbc_get_reg_params(struct intel_fbc *fbc)
-{
- const struct intel_fbc_state *cache = &fbc->state_cache;
- struct intel_fbc_state *params = &fbc->params;
-
- /* Since all our fields are integer types, use memset here so the
- * comparison function can rely on memcmp because the padding will be
- * zero. */
- *params = *cache;
-}
static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_plane *plane)
{
- struct intel_fbc *fbc = plane->fbc;
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *old_plane_state =
@@ -1184,16 +1149,12 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
intel_atomic_get_new_plane_state(state, plane);
const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
- const struct intel_fbc_state *cache = &fbc->state_cache;
- const struct intel_fbc_state *params = &fbc->params;
if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
return false;
- if (!intel_fbc_can_activate(fbc))
- return false;
-
- if (!old_fb || !new_fb)
+ if (!intel_fbc_is_ok(old_plane_state) ||
+ !intel_fbc_is_ok(new_plane_state))
return false;
if (old_fb->format->format != new_fb->format->format)
@@ -1206,13 +1167,16 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
intel_fbc_plane_stride(new_plane_state))
return false;
- if (params->cfb_stride != cache->cfb_stride)
+ if (intel_fbc_cfb_stride(old_plane_state) !=
+ intel_fbc_cfb_stride(new_plane_state))
return false;
- if (params->cfb_size != cache->cfb_size)
+ if (intel_fbc_cfb_size(old_plane_state) !=
+ intel_fbc_cfb_size(new_plane_state))
return false;
- if (params->override_cfb_stride != cache->override_cfb_stride)
+ if (intel_fbc_override_cfb_stride(old_plane_state) !=
+ intel_fbc_override_cfb_stride(new_plane_state))
return false;
return true;
@@ -1226,7 +1190,6 @@ static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_fbc *fbc = plane->fbc;
bool need_vblank_wait = false;
- intel_fbc_update_state_cache(state, crtc, plane);
fbc->flip_pending = true;
if (intel_fbc_can_flip_nuke(state, crtc, plane))
@@ -1302,16 +1265,6 @@ static void __intel_fbc_post_update(struct intel_fbc *fbc)
drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
- if (!i915->params.enable_fbc) {
- intel_fbc_deactivate(fbc, "disabled at runtime per module param");
- __intel_fbc_disable(fbc);
-
- return;
- }
-
- if (!intel_fbc_can_activate(fbc))
- return;
-
if (!fbc->busy_bits)
intel_fbc_activate(fbc);
else
@@ -1335,7 +1288,6 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
if (fbc->plane == plane) {
fbc->flip_pending = false;
- intel_fbc_get_reg_params(fbc);
__intel_fbc_post_update(fbc);
}
@@ -1425,15 +1377,12 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state *cache = &fbc->state_cache;
- int min_limit = intel_fbc_min_limit(plane_state);
if (fbc->plane) {
if (fbc->plane != plane)
return;
- if (fbc->limit >= min_limit &&
- !intel_fbc_cfb_size_changed(fbc))
+ if (intel_fbc_is_ok(plane_state))
return;
__intel_fbc_disable(fbc);
@@ -1441,17 +1390,22 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
drm_WARN_ON(&i915->drm, fbc->active);
- intel_fbc_update_state_cache(state, crtc, plane);
+ fbc->no_fbc_reason = plane_state->no_fbc_reason;
+ if (fbc->no_fbc_reason)
+ return;
- if (cache->no_fbc_reason)
+ if (!intel_fbc_is_fence_ok(plane_state)) {
+ fbc->no_fbc_reason = "framebuffer not fenced";
return;
+ }
if (fbc->underrun_detected) {
fbc->no_fbc_reason = "FIFO underrun";
return;
}
- if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
+ if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
+ intel_fbc_min_limit(plane_state))) {
fbc->no_fbc_reason = "not enough stolen memory";
return;
}
@@ -1460,6 +1414,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
plane->base.base.id, plane->base.name);
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
+ intel_fbc_update_state_cache(state, crtc, plane);
fbc->plane = plane;
intel_fbc_program_cfb(fbc);
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache
2021-11-24 11:36 ` [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache Ville Syrjala
@ 2021-12-01 11:06 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:06 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> fbc->state_cache has now become useless. We can simply update
> the reg params directly from the plane/crtc states during __intel_fbc_enable().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 169 +++++++++--------------
> 1 file changed, 62 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 74ba54d70e57..7d128a49e8e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -60,7 +60,6 @@ struct intel_fbc_funcs { };
>
> struct intel_fbc_state {
> - const char *no_fbc_reason;
> enum i9xx_plane_id i9xx_plane;
> unsigned int cfb_stride;
> unsigned int cfb_size;
> @@ -98,13 +97,6 @@ struct intel_fbc {
> bool underrun_detected;
> struct work_struct underrun_work;
>
> - /*
> - * Due to the atomic rules we can't access some structures without the
> - * appropriate locking, so we cache information here in order to avoid
> - * these problems.
> - */
> - struct intel_fbc_state state_cache;
> -
> /*
> * This structure contains everything that's relevant to program the
> * hardware registers. When we want to figure out if we need to disable
> @@ -673,6 +665,8 @@ static void intel_fbc_activate(struct intel_fbc *fbc) {
> intel_fbc_hw_activate(fbc);
> intel_fbc_nuke(fbc);
> +
> + fbc->no_fbc_reason = NULL;
> }
>
> static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) @@ -
> 714,9 +708,7 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private
> *i915)
>
> static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) {
> - int fb_cpp = plane_state->hw.fb ? plane_state->hw.fb->format->cpp[0]
> : 0;
> -
> - return fb_cpp == 2 ? 2 : 1;
> + return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
> }
>
> static int intel_fbc_max_limit(struct drm_i915_private *i915) @@ -962,10
> +954,9 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state
> *state,
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state *cache = &fbc->state_cache;
> + struct intel_fbc_state *cache = &fbc->params;
>
> - cache->no_fbc_reason = plane_state->no_fbc_reason;
> - if (cache->no_fbc_reason)
> + if (plane_state->no_fbc_reason)
> return;
>
> cache->i9xx_plane = plane->i9xx_plane; @@ -989,9 +980,46 @@ static
> void intel_fbc_update_state_cache(struct intel_atomic_state *state,
> cache->override_cfb_stride =
> intel_fbc_override_cfb_stride(plane_state);
> }
>
> -static bool intel_fbc_cfb_size_changed(struct intel_fbc *fbc)
> +static bool intel_fbc_is_fence_ok(const struct intel_plane_state
> +*plane_state)
> {
> - return fbc->state_cache.cfb_size > fbc->compressed_fb.size * fbc-
> >limit;
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> +
> + /* The use of a CPU fence is one of two ways to detect writes by the
> + * CPU to the scanout and trigger updates to the FBC.
> + *
> + * The other method is by software tracking (see
> + * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
> + * the current compressed buffer and recompress it.
> + *
> + * Note that is possible for a tiled surface to be unmappable (and
> + * so have no fence associated with it) due to aperture constraints
> + * at the time of pinning.
> + *
> + * FIXME with 90/270 degree rotation we should use the fence on
> + * the normal GTT view (the rotated view doesn't even have a
> + * fence). Would need changes to the FBC fence Y offset as well.
> + * For now this will effectively disable FBC with 90/270 degree
> + * rotation.
> + */
> + return DISPLAY_VER(i915) >= 9 ||
> + (plane_state->flags & PLANE_HAS_FENCE &&
> + plane_state->ggtt_vma->fence);
> +}
> +
> +static bool intel_fbc_is_cfb_ok(const struct intel_plane_state
> +*plane_state) {
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> + struct intel_fbc *fbc = plane->fbc;
> +
> + return intel_fbc_min_limit(plane_state) <= fbc->limit &&
> + intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size *
> +fbc->limit; }
> +
> +static bool intel_fbc_is_ok(const struct intel_plane_state
> +*plane_state) {
> + return !plane_state->no_fbc_reason &&
> + intel_fbc_is_fence_ok(plane_state) &&
> + intel_fbc_is_cfb_ok(plane_state);
> }
>
> static int intel_fbc_check_plane(struct intel_atomic_state *state, @@ -1108,74
> +1136,11 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
> return 0;
> }
>
> -static bool intel_fbc_can_activate(struct intel_fbc *fbc) -{
> - struct drm_i915_private *i915 = fbc->i915;
> - struct intel_fbc_state *cache = &fbc->state_cache;
> -
> - if (cache->no_fbc_reason) {
> - fbc->no_fbc_reason = cache->no_fbc_reason;
> - return false;
> - }
> -
> - /* The use of a CPU fence is one of two ways to detect writes by the
> - * CPU to the scanout and trigger updates to the FBC.
> - *
> - * The other method is by software tracking (see
> - * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
> - * the current compressed buffer and recompress it.
> - *
> - * Note that is possible for a tiled surface to be unmappable (and
> - * so have no fence associated with it) due to aperture constraints
> - * at the time of pinning.
> - *
> - * FIXME with 90/270 degree rotation we should use the fence on
> - * the normal GTT view (the rotated view doesn't even have a
> - * fence). Would need changes to the FBC fence Y offset as well.
> - * For now this will effectively disable FBC with 90/270 degree
> - * rotation.
> - */
> - if (DISPLAY_VER(i915) < 9 && cache->fence_id < 0) {
> - fbc->no_fbc_reason = "framebuffer not tiled or fenced";
> - return false;
> - }
> -
> - /*
> - * It is possible for the required CFB size change without a
> - * crtc->disable + crtc->enable since it is possible to change the
> - * stride without triggering a full modeset. Since we try to
> - * over-allocate the CFB, there's a chance we may keep FBC enabled
> even
> - * if this happens, but if we exceed the current CFB size we'll have to
> - * disable FBC. Notice that it would be possible to disable FBC, wait
> - * for a frame, free the stolen node, then try to reenable FBC in case
> - * we didn't get any invalidate/deactivate calls, but this would require
> - * a lot of tracking just for a specific case. If we conclude it's an
> - * important case, we can implement it later.
> - */
> - if (intel_fbc_cfb_size_changed(fbc)) {
> - fbc->no_fbc_reason = "CFB requirements changed";
> - return false;
> - }
> -
> - return true;
> -}
> -
> -static void intel_fbc_get_reg_params(struct intel_fbc *fbc) -{
> - const struct intel_fbc_state *cache = &fbc->state_cache;
> - struct intel_fbc_state *params = &fbc->params;
> -
> - /* Since all our fields are integer types, use memset here so the
> - * comparison function can rely on memcmp because the padding will
> be
> - * zero. */
> - *params = *cache;
> -}
>
> static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_plane *plane)
> {
> - struct intel_fbc *fbc = plane->fbc;
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> const struct intel_plane_state *old_plane_state = @@ -1184,16
> +1149,12 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state
> *state,
> intel_atomic_get_new_plane_state(state, plane);
> const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
> const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
> - const struct intel_fbc_state *cache = &fbc->state_cache;
> - const struct intel_fbc_state *params = &fbc->params;
>
> if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
> return false;
>
> - if (!intel_fbc_can_activate(fbc))
> - return false;
> -
> - if (!old_fb || !new_fb)
> + if (!intel_fbc_is_ok(old_plane_state) ||
> + !intel_fbc_is_ok(new_plane_state))
> return false;
>
> if (old_fb->format->format != new_fb->format->format) @@ -1206,13
> +1167,16 @@ static bool intel_fbc_can_flip_nuke(struct intel_atomic_state
> *state,
> intel_fbc_plane_stride(new_plane_state))
> return false;
>
> - if (params->cfb_stride != cache->cfb_stride)
> + if (intel_fbc_cfb_stride(old_plane_state) !=
> + intel_fbc_cfb_stride(new_plane_state))
> return false;
>
> - if (params->cfb_size != cache->cfb_size)
> + if (intel_fbc_cfb_size(old_plane_state) !=
> + intel_fbc_cfb_size(new_plane_state))
> return false;
>
> - if (params->override_cfb_stride != cache->override_cfb_stride)
> + if (intel_fbc_override_cfb_stride(old_plane_state) !=
> + intel_fbc_override_cfb_stride(new_plane_state))
> return false;
>
> return true;
> @@ -1226,7 +1190,6 @@ static bool __intel_fbc_pre_update(struct
> intel_atomic_state *state,
> struct intel_fbc *fbc = plane->fbc;
> bool need_vblank_wait = false;
>
> - intel_fbc_update_state_cache(state, crtc, plane);
> fbc->flip_pending = true;
>
> if (intel_fbc_can_flip_nuke(state, crtc, plane)) @@ -1302,16 +1265,6
> @@ static void __intel_fbc_post_update(struct intel_fbc *fbc)
>
> drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
>
> - if (!i915->params.enable_fbc) {
> - intel_fbc_deactivate(fbc, "disabled at runtime per module
> param");
> - __intel_fbc_disable(fbc);
> -
> - return;
> - }
> -
> - if (!intel_fbc_can_activate(fbc))
> - return;
> -
> if (!fbc->busy_bits)
> intel_fbc_activate(fbc);
> else
> @@ -1335,7 +1288,6 @@ void intel_fbc_post_update(struct intel_atomic_state
> *state,
>
> if (fbc->plane == plane) {
> fbc->flip_pending = false;
> - intel_fbc_get_reg_params(fbc);
> __intel_fbc_post_update(fbc);
> }
>
> @@ -1425,15 +1377,12 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state *cache = &fbc->state_cache;
> - int min_limit = intel_fbc_min_limit(plane_state);
>
> if (fbc->plane) {
> if (fbc->plane != plane)
> return;
>
> - if (fbc->limit >= min_limit &&
> - !intel_fbc_cfb_size_changed(fbc))
> + if (intel_fbc_is_ok(plane_state))
> return;
>
> __intel_fbc_disable(fbc);
> @@ -1441,17 +1390,22 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
>
> drm_WARN_ON(&i915->drm, fbc->active);
>
> - intel_fbc_update_state_cache(state, crtc, plane);
> + fbc->no_fbc_reason = plane_state->no_fbc_reason;
> + if (fbc->no_fbc_reason)
> + return;
>
> - if (cache->no_fbc_reason)
> + if (!intel_fbc_is_fence_ok(plane_state)) {
> + fbc->no_fbc_reason = "framebuffer not fenced";
> return;
> + }
>
> if (fbc->underrun_detected) {
> fbc->no_fbc_reason = "FIFO underrun";
> return;
> }
>
> - if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), min_limit)) {
> + if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
> + intel_fbc_min_limit(plane_state))) {
> fbc->no_fbc_reason = "not enough stolen memory";
> return;
> }
> @@ -1460,6 +1414,7 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> plane->base.base.id, plane->base.name);
> fbc->no_fbc_reason = "FBC enabled but not active yet\n";
>
> + intel_fbc_update_state_cache(state, crtc, plane);
> fbc->plane = plane;
>
> intel_fbc_program_cfb(fbc);
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (15 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 16/20] drm/i915/fbc: Nuke state_cache Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:30 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/ Ville Syrjala
` (14 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we track the FBC plane as a pointer under intel_fbc
and also as a i9xx_plane_id under intel_fbc_state. Just store
the pointer once in the fbc state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 54 ++++++++++++------------
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7d128a49e8e1..b6919ca87138 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -60,7 +60,7 @@ struct intel_fbc_funcs {
};
struct intel_fbc_state {
- enum i9xx_plane_id i9xx_plane;
+ struct intel_plane *plane;
unsigned int cfb_stride;
unsigned int cfb_size;
unsigned int fence_y_offset;
@@ -81,7 +81,6 @@ struct intel_fbc {
struct mutex lock;
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
- struct intel_plane *plane;
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
@@ -244,7 +243,7 @@ static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
u32 fbc_ctl2;
fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
- FBC_CTL_PLANE(params->i9xx_plane);
+ FBC_CTL_PLANE(params->plane->i9xx_plane);
if (params->fence_id >= 0)
fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
@@ -308,7 +307,7 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
static void i8xx_fbc_nuke(struct intel_fbc *fbc)
{
struct intel_fbc_state *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
+ enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -344,7 +343,7 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
static void i965_fbc_nuke(struct intel_fbc *fbc)
{
struct intel_fbc_state *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
+ enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -384,7 +383,7 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
u32 dpfc_ctl;
dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
- DPFC_CTL_PLANE_G4X(params->i9xx_plane);
+ DPFC_CTL_PLANE_G4X(params->plane->i9xx_plane);
if (IS_G4X(i915))
dpfc_ctl |= DPFC_CTL_SR_EN;
@@ -576,7 +575,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
if (IS_IVYBRIDGE(i915))
- dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->i9xx_plane);
+ dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->plane->i9xx_plane);
if (params->fence_id >= 0)
dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
@@ -632,7 +631,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
static void intel_fbc_hw_activate(struct intel_fbc *fbc)
{
- trace_intel_fbc_activate(fbc->plane);
+ trace_intel_fbc_activate(fbc->params.plane);
fbc->active = true;
fbc->activated = true;
@@ -642,7 +641,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
{
- trace_intel_fbc_deactivate(fbc->plane);
+ trace_intel_fbc_deactivate(fbc->params.plane);
fbc->active = false;
@@ -656,7 +655,7 @@ static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
static void intel_fbc_nuke(struct intel_fbc *fbc)
{
- trace_intel_fbc_nuke(fbc->plane);
+ trace_intel_fbc_nuke(fbc->params.plane);
fbc->funcs->nuke(fbc);
}
@@ -959,7 +958,7 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
if (plane_state->no_fbc_reason)
return;
- cache->i9xx_plane = plane->i9xx_plane;
+ cache->plane = plane;
/* FBC1 compression interval: arbitrary choice of 1 second */
cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
@@ -1233,7 +1232,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
- if (fbc->plane == plane)
+ if (fbc->params.plane == plane)
need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
mutex_unlock(&fbc->lock);
@@ -1245,10 +1244,10 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
static void __intel_fbc_disable(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- struct intel_plane *plane = fbc->plane;
+ struct intel_plane *plane = fbc->params.plane;
drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
- drm_WARN_ON(&i915->drm, !fbc->plane);
+ drm_WARN_ON(&i915->drm, !fbc->params.plane);
drm_WARN_ON(&i915->drm, fbc->active);
drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
@@ -1256,7 +1255,7 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
__intel_fbc_cleanup_cfb(fbc);
- fbc->plane = NULL;
+ fbc->params.plane = NULL;
}
static void __intel_fbc_post_update(struct intel_fbc *fbc)
@@ -1286,7 +1285,7 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
- if (fbc->plane == plane) {
+ if (fbc->params.plane == plane) {
fbc->flip_pending = false;
__intel_fbc_post_update(fbc);
}
@@ -1297,8 +1296,8 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
{
- if (fbc->plane)
- return fbc->plane->frontbuffer_bit;
+ if (fbc->params.plane)
+ return fbc->params.plane->frontbuffer_bit;
else
return fbc->possible_framebuffer_bits;
}
@@ -1319,7 +1318,7 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
- if (fbc->plane && fbc->busy_bits)
+ if (fbc->params.plane && fbc->busy_bits)
intel_fbc_deactivate(fbc, "frontbuffer write");
mutex_unlock(&fbc->lock);
@@ -1340,7 +1339,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
goto out;
- if (!fbc->busy_bits && fbc->plane &&
+ if (!fbc->busy_bits && fbc->params.plane &&
(frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
if (fbc->active)
intel_fbc_nuke(fbc);
@@ -1378,8 +1377,8 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- if (fbc->plane) {
- if (fbc->plane != plane)
+ if (fbc->params.plane) {
+ if (fbc->params.plane != plane)
return;
if (intel_fbc_is_ok(plane_state))
@@ -1415,7 +1414,6 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
intel_fbc_update_state_cache(state, crtc, plane);
- fbc->plane = plane;
intel_fbc_program_cfb(fbc);
}
@@ -1438,7 +1436,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
continue;
mutex_lock(&fbc->lock);
- if (fbc->plane == plane)
+ if (fbc->params.plane == plane)
__intel_fbc_disable(fbc);
mutex_unlock(&fbc->lock);
}
@@ -1462,7 +1460,7 @@ void intel_fbc_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
- if (fbc->plane == plane)
+ if (fbc->params.plane == plane)
__intel_fbc_disable(fbc);
} else {
__intel_fbc_enable(state, crtc, plane);
@@ -1486,7 +1484,7 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
return;
mutex_lock(&fbc->lock);
- if (fbc->plane)
+ if (fbc->params.plane)
__intel_fbc_disable(fbc);
mutex_unlock(&fbc->lock);
}
@@ -1499,7 +1497,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
mutex_lock(&fbc->lock);
/* Maybe we were scheduled twice. */
- if (fbc->underrun_detected || !fbc->plane)
+ if (fbc->underrun_detected || !fbc->params.plane)
goto out;
drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
@@ -1507,7 +1505,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
intel_fbc_deactivate(fbc, "FIFO underrun");
if (!fbc->flip_pending)
- intel_wait_for_vblank(i915, fbc->plane->pipe);
+ intel_wait_for_vblank(i915, fbc->params.plane->pipe);
__intel_fbc_disable(fbc);
out:
mutex_unlock(&fbc->lock);
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state
2021-11-24 11:36 ` [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state Ville Syrjala
@ 2021-12-01 11:30 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:30 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into
> intel_fbc_state
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we track the FBC plane as a pointer under intel_fbc and also as a
> i9xx_plane_id under intel_fbc_state. Just store the pointer once in the fbc state.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 54 ++++++++++++------------
> 1 file changed, 26 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7d128a49e8e1..b6919ca87138 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -60,7 +60,7 @@ struct intel_fbc_funcs { };
>
> struct intel_fbc_state {
> - enum i9xx_plane_id i9xx_plane;
> + struct intel_plane *plane;
> unsigned int cfb_stride;
> unsigned int cfb_size;
> unsigned int fence_y_offset;
> @@ -81,7 +81,6 @@ struct intel_fbc {
> struct mutex lock;
> unsigned int possible_framebuffer_bits;
> unsigned int busy_bits;
> - struct intel_plane *plane;
>
> struct drm_mm_node compressed_fb;
> struct drm_mm_node compressed_llb;
> @@ -244,7 +243,7 @@ static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
> u32 fbc_ctl2;
>
> fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
> - FBC_CTL_PLANE(params->i9xx_plane);
> + FBC_CTL_PLANE(params->plane->i9xx_plane);
>
> if (params->fence_id >= 0)
> fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
> @@ -308,7 +307,7 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc
> *fbc) static void i8xx_fbc_nuke(struct intel_fbc *fbc) {
> struct intel_fbc_state *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
> + enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -344,7 +343,7 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
> static void i965_fbc_nuke(struct intel_fbc *fbc) {
> struct intel_fbc_state *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->i9xx_plane;
> + enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -384,7 +383,7 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
> u32 dpfc_ctl;
>
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
> - DPFC_CTL_PLANE_G4X(params->i9xx_plane);
> + DPFC_CTL_PLANE_G4X(params->plane->i9xx_plane);
>
> if (IS_G4X(i915))
> dpfc_ctl |= DPFC_CTL_SR_EN;
> @@ -576,7 +575,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
>
> if (IS_IVYBRIDGE(i915))
> - dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->i9xx_plane);
> + dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->plane->i9xx_plane);
>
> if (params->fence_id >= 0)
> dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
> @@ -632,7 +631,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_activate(struct intel_fbc *fbc) {
> - trace_intel_fbc_activate(fbc->plane);
> + trace_intel_fbc_activate(fbc->params.plane);
>
> fbc->active = true;
> fbc->activated = true;
> @@ -642,7 +641,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) {
> - trace_intel_fbc_deactivate(fbc->plane);
> + trace_intel_fbc_deactivate(fbc->params.plane);
>
> fbc->active = false;
>
> @@ -656,7 +655,7 @@ static bool intel_fbc_is_compressing(struct intel_fbc
> *fbc)
>
> static void intel_fbc_nuke(struct intel_fbc *fbc) {
> - trace_intel_fbc_nuke(fbc->plane);
> + trace_intel_fbc_nuke(fbc->params.plane);
>
> fbc->funcs->nuke(fbc);
> }
> @@ -959,7 +958,7 @@ static void intel_fbc_update_state_cache(struct
> intel_atomic_state *state,
> if (plane_state->no_fbc_reason)
> return;
>
> - cache->i9xx_plane = plane->i9xx_plane;
> + cache->plane = plane;
>
> /* FBC1 compression interval: arbitrary choice of 1 second */
> cache->interval = drm_mode_vrefresh(&crtc_state-
> >hw.adjusted_mode);
> @@ -1233,7 +1232,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state
> *state,
>
> mutex_lock(&fbc->lock);
>
> - if (fbc->plane == plane)
> + if (fbc->params.plane == plane)
> need_vblank_wait |= __intel_fbc_pre_update(state,
> crtc, plane);
>
> mutex_unlock(&fbc->lock);
> @@ -1245,10 +1244,10 @@ bool intel_fbc_pre_update(struct
> intel_atomic_state *state, static void __intel_fbc_disable(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
> - struct intel_plane *plane = fbc->plane;
> + struct intel_plane *plane = fbc->params.plane;
>
> drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
> - drm_WARN_ON(&i915->drm, !fbc->plane);
> + drm_WARN_ON(&i915->drm, !fbc->params.plane);
> drm_WARN_ON(&i915->drm, fbc->active);
>
> drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n", @@ -
> 1256,7 +1255,7 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
>
> __intel_fbc_cleanup_cfb(fbc);
>
> - fbc->plane = NULL;
> + fbc->params.plane = NULL;
> }
>
> static void __intel_fbc_post_update(struct intel_fbc *fbc) @@ -1286,7 +1285,7
> @@ void intel_fbc_post_update(struct intel_atomic_state *state,
>
> mutex_lock(&fbc->lock);
>
> - if (fbc->plane == plane) {
> + if (fbc->params.plane == plane) {
> fbc->flip_pending = false;
> __intel_fbc_post_update(fbc);
> }
> @@ -1297,8 +1296,8 @@ void intel_fbc_post_update(struct intel_atomic_state
> *state,
>
> static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) {
> - if (fbc->plane)
> - return fbc->plane->frontbuffer_bit;
> + if (fbc->params.plane)
> + return fbc->params.plane->frontbuffer_bit;
> else
> return fbc->possible_framebuffer_bits; } @@ -1319,7 +1318,7
> @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
>
> fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
>
> - if (fbc->plane && fbc->busy_bits)
> + if (fbc->params.plane && fbc->busy_bits)
> intel_fbc_deactivate(fbc, "frontbuffer write");
>
> mutex_unlock(&fbc->lock);
> @@ -1340,7 +1339,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
> goto out;
>
> - if (!fbc->busy_bits && fbc->plane &&
> + if (!fbc->busy_bits && fbc->params.plane &&
> (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
> if (fbc->active)
> intel_fbc_nuke(fbc);
> @@ -1378,8 +1377,8 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
>
> - if (fbc->plane) {
> - if (fbc->plane != plane)
> + if (fbc->params.plane) {
> + if (fbc->params.plane != plane)
> return;
>
> if (intel_fbc_is_ok(plane_state))
> @@ -1415,7 +1414,6 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> fbc->no_fbc_reason = "FBC enabled but not active yet\n";
>
> intel_fbc_update_state_cache(state, crtc, plane);
> - fbc->plane = plane;
>
> intel_fbc_program_cfb(fbc);
> }
> @@ -1438,7 +1436,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
> continue;
>
> mutex_lock(&fbc->lock);
> - if (fbc->plane == plane)
> + if (fbc->params.plane == plane)
> __intel_fbc_disable(fbc);
> mutex_unlock(&fbc->lock);
> }
> @@ -1462,7 +1460,7 @@ void intel_fbc_update(struct intel_atomic_state
> *state,
> mutex_lock(&fbc->lock);
>
> if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
> - if (fbc->plane == plane)
> + if (fbc->params.plane == plane)
> __intel_fbc_disable(fbc);
> } else {
> __intel_fbc_enable(state, crtc, plane); @@ -1486,7
> +1484,7 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
> return;
>
> mutex_lock(&fbc->lock);
> - if (fbc->plane)
> + if (fbc->params.plane)
> __intel_fbc_disable(fbc);
> mutex_unlock(&fbc->lock);
> }
> @@ -1499,7 +1497,7 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
> mutex_lock(&fbc->lock);
>
> /* Maybe we were scheduled twice. */
> - if (fbc->underrun_detected || !fbc->plane)
> + if (fbc->underrun_detected || !fbc->params.plane)
> goto out;
>
> drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
> @@ -1507,7 +1505,7 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
>
> intel_fbc_deactivate(fbc, "FIFO underrun");
> if (!fbc->flip_pending)
> - intel_wait_for_vblank(i915, fbc->plane->pipe);
> + intel_wait_for_vblank(i915, fbc->params.plane->pipe);
> __intel_fbc_disable(fbc);
> out:
> mutex_unlock(&fbc->lock);
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (16 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 17/20] drm/i915/fbc: Move plane pointer into intel_fbc_state Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:31 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe Ville Syrjala
` (13 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the 'params' to just fbc state.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 138 +++++++++++------------
1 file changed, 68 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b6919ca87138..4d2c54acdc89 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -103,7 +103,7 @@ struct intel_fbc {
* something different in the struct. The genx_fbc_activate functions
* are supposed to read from it in order to program the registers.
*/
- struct intel_fbc_state params;
+ struct intel_fbc_state state;
const char *no_fbc_reason;
};
@@ -211,12 +211,12 @@ static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_s
static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
unsigned int cfb_stride;
u32 fbc_ctl;
- cfb_stride = params->cfb_stride / fbc->limit;
+ cfb_stride = fbc_state->cfb_stride / fbc->limit;
/* FBC_CTL wants 32B or 64B units */
if (DISPLAY_VER(i915) == 2)
@@ -225,27 +225,27 @@ static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
cfb_stride = (cfb_stride / 64) - 1;
fbc_ctl = FBC_CTL_PERIODIC |
- FBC_CTL_INTERVAL(params->interval) |
+ FBC_CTL_INTERVAL(fbc_state->interval) |
FBC_CTL_STRIDE(cfb_stride);
if (IS_I945GM(i915))
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
- if (params->fence_id >= 0)
- fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
+ if (fbc_state->fence_id >= 0)
+ fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
return fbc_ctl;
}
static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
u32 fbc_ctl2;
fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
- FBC_CTL_PLANE(params->plane->i9xx_plane);
+ FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
- if (params->fence_id >= 0)
+ if (fbc_state->fence_id >= 0)
fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
return fbc_ctl2;
@@ -274,7 +274,7 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
static void i8xx_fbc_activate(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
int i;
@@ -286,7 +286,7 @@ static void i8xx_fbc_activate(struct intel_fbc *fbc)
intel_de_write(i915, FBC_CONTROL2,
i965_fbc_ctl2(fbc));
intel_de_write(i915, FBC_FENCE_OFF,
- params->fence_y_offset);
+ fbc_state->fence_y_offset);
}
intel_de_write(i915, FBC_CONTROL,
@@ -306,8 +306,8 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
static void i8xx_fbc_nuke(struct intel_fbc *fbc)
{
- struct intel_fbc_state *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
+ struct intel_fbc_state *fbc_state = &fbc->state;
+ enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -342,8 +342,8 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
static void i965_fbc_nuke(struct intel_fbc *fbc)
{
- struct intel_fbc_state *params = &fbc->params;
- enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
+ struct intel_fbc_state *fbc_state = &fbc->state;
+ enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -378,21 +378,21 @@ static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
u32 dpfc_ctl;
dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
- DPFC_CTL_PLANE_G4X(params->plane->i9xx_plane);
+ DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
if (IS_G4X(i915))
dpfc_ctl |= DPFC_CTL_SR_EN;
- if (params->fence_id >= 0) {
+ if (fbc_state->fence_id >= 0) {
dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
if (DISPLAY_VER(i915) < 6)
- dpfc_ctl |= DPFC_CTL_FENCENO(params->fence_id);
+ dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
}
return dpfc_ctl;
@@ -400,11 +400,11 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
static void g4x_fbc_activate(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
intel_de_write(i915, DPFC_FENCE_YOFF,
- params->fence_y_offset);
+ fbc_state->fence_y_offset);
intel_de_write(i915, DPFC_CONTROL,
DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
@@ -451,11 +451,11 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = {
static void ilk_fbc_activate(struct intel_fbc *fbc)
{
- struct intel_fbc_state *params = &fbc->params;
+ struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
- params->fence_y_offset);
+ fbc_state->fence_y_offset);
intel_de_write(i915, ILK_DPFC_CONTROL,
DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
@@ -502,15 +502,15 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = {
static void snb_fbc_program_fence(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
u32 ctl = 0;
- if (params->fence_id >= 0)
- ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(params->fence_id);
+ if (fbc_state->fence_id >= 0)
+ ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
- intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params->fence_y_offset);
+ intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
}
static void snb_fbc_activate(struct intel_fbc *fbc)
@@ -539,27 +539,27 @@ static const struct intel_fbc_funcs snb_fbc_funcs = {
static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
u32 val = 0;
- if (params->override_cfb_stride)
+ if (fbc_state->override_cfb_stride)
val |= FBC_STRIDE_OVERRIDE |
- FBC_STRIDE(params->override_cfb_stride / fbc->limit);
+ FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
intel_de_write(i915, GLK_FBC_STRIDE, val);
}
static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
u32 val = 0;
/* Display WA #0529: skl, kbl, bxt. */
- if (params->override_cfb_stride)
+ if (fbc_state->override_cfb_stride)
val |= CHICKEN_FBC_STRIDE_OVERRIDE |
- CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit);
+ CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
intel_de_rmw(i915, CHICKEN_MISC_4,
CHICKEN_FBC_STRIDE_OVERRIDE |
@@ -568,16 +568,16 @@ static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
{
- const struct intel_fbc_state *params = &fbc->params;
+ const struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
u32 dpfc_ctl;
dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
if (IS_IVYBRIDGE(i915))
- dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->plane->i9xx_plane);
+ dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
- if (params->fence_id >= 0)
+ if (fbc_state->fence_id >= 0)
dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
if (fbc->false_color)
@@ -631,7 +631,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
static void intel_fbc_hw_activate(struct intel_fbc *fbc)
{
- trace_intel_fbc_activate(fbc->params.plane);
+ trace_intel_fbc_activate(fbc->state.plane);
fbc->active = true;
fbc->activated = true;
@@ -641,7 +641,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
{
- trace_intel_fbc_deactivate(fbc->params.plane);
+ trace_intel_fbc_deactivate(fbc->state.plane);
fbc->active = false;
@@ -655,7 +655,7 @@ static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
static void intel_fbc_nuke(struct intel_fbc *fbc)
{
- trace_intel_fbc_nuke(fbc->params.plane);
+ trace_intel_fbc_nuke(fbc->state.plane);
fbc->funcs->nuke(fbc);
}
@@ -943,9 +943,9 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
}
}
-static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_plane *plane)
+static void intel_fbc_update_state(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *crtc_state =
@@ -953,30 +953,29 @@ static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- struct intel_fbc_state *cache = &fbc->params;
+ struct intel_fbc_state *fbc_state = &fbc->state;
- if (plane_state->no_fbc_reason)
- return;
+ WARN_ON(plane_state->no_fbc_reason);
- cache->plane = plane;
+ fbc_state->plane = plane;
/* FBC1 compression interval: arbitrary choice of 1 second */
- cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
+ fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
- cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
+ fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
!plane_state->ggtt_vma->fence);
if (plane_state->flags & PLANE_HAS_FENCE &&
plane_state->ggtt_vma->fence)
- cache->fence_id = plane_state->ggtt_vma->fence->id;
+ fbc_state->fence_id = plane_state->ggtt_vma->fence->id;
else
- cache->fence_id = -1;
+ fbc_state->fence_id = -1;
- cache->cfb_stride = intel_fbc_cfb_stride(plane_state);
- cache->cfb_size = intel_fbc_cfb_size(plane_state);
- cache->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
+ fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
+ fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
+ fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
}
static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
@@ -1232,7 +1231,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
- if (fbc->params.plane == plane)
+ if (fbc->state.plane == plane)
need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
mutex_unlock(&fbc->lock);
@@ -1244,10 +1243,9 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
static void __intel_fbc_disable(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- struct intel_plane *plane = fbc->params.plane;
+ struct intel_plane *plane = fbc->state.plane;
drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
- drm_WARN_ON(&i915->drm, !fbc->params.plane);
drm_WARN_ON(&i915->drm, fbc->active);
drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
@@ -1255,7 +1253,7 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
__intel_fbc_cleanup_cfb(fbc);
- fbc->params.plane = NULL;
+ fbc->state.plane = NULL;
}
static void __intel_fbc_post_update(struct intel_fbc *fbc)
@@ -1285,7 +1283,7 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
- if (fbc->params.plane == plane) {
+ if (fbc->state.plane == plane) {
fbc->flip_pending = false;
__intel_fbc_post_update(fbc);
}
@@ -1296,8 +1294,8 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
{
- if (fbc->params.plane)
- return fbc->params.plane->frontbuffer_bit;
+ if (fbc->state.plane)
+ return fbc->state.plane->frontbuffer_bit;
else
return fbc->possible_framebuffer_bits;
}
@@ -1318,7 +1316,7 @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
- if (fbc->params.plane && fbc->busy_bits)
+ if (fbc->state.plane && fbc->busy_bits)
intel_fbc_deactivate(fbc, "frontbuffer write");
mutex_unlock(&fbc->lock);
@@ -1339,7 +1337,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
goto out;
- if (!fbc->busy_bits && fbc->params.plane &&
+ if (!fbc->busy_bits && fbc->state.plane &&
(frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
if (fbc->active)
intel_fbc_nuke(fbc);
@@ -1377,8 +1375,8 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
intel_atomic_get_new_plane_state(state, plane);
struct intel_fbc *fbc = plane->fbc;
- if (fbc->params.plane) {
- if (fbc->params.plane != plane)
+ if (fbc->state.plane) {
+ if (fbc->state.plane != plane)
return;
if (intel_fbc_is_ok(plane_state))
@@ -1413,7 +1411,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
plane->base.base.id, plane->base.name);
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
- intel_fbc_update_state_cache(state, crtc, plane);
+ intel_fbc_update_state(state, crtc, plane);
intel_fbc_program_cfb(fbc);
}
@@ -1436,7 +1434,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
continue;
mutex_lock(&fbc->lock);
- if (fbc->params.plane == plane)
+ if (fbc->state.plane == plane)
__intel_fbc_disable(fbc);
mutex_unlock(&fbc->lock);
}
@@ -1460,7 +1458,7 @@ void intel_fbc_update(struct intel_atomic_state *state,
mutex_lock(&fbc->lock);
if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
- if (fbc->params.plane == plane)
+ if (fbc->state.plane == plane)
__intel_fbc_disable(fbc);
} else {
__intel_fbc_enable(state, crtc, plane);
@@ -1484,7 +1482,7 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
return;
mutex_lock(&fbc->lock);
- if (fbc->params.plane)
+ if (fbc->state.plane)
__intel_fbc_disable(fbc);
mutex_unlock(&fbc->lock);
}
@@ -1497,7 +1495,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
mutex_lock(&fbc->lock);
/* Maybe we were scheduled twice. */
- if (fbc->underrun_detected || !fbc->params.plane)
+ if (fbc->underrun_detected || !fbc->state.plane)
goto out;
drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
@@ -1505,7 +1503,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
intel_fbc_deactivate(fbc, "FIFO underrun");
if (!fbc->flip_pending)
- intel_wait_for_vblank(i915, fbc->params.plane->pipe);
+ intel_wait_for_vblank(i915, fbc->state.plane->pipe);
__intel_fbc_disable(fbc);
out:
mutex_unlock(&fbc->lock);
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/
2021-11-24 11:36 ` [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/ Ville Syrjala
@ 2021-12-01 11:31 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:31 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the 'params' to just fbc state.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 138 +++++++++++------------
> 1 file changed, 68 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b6919ca87138..4d2c54acdc89 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -103,7 +103,7 @@ struct intel_fbc {
> * something different in the struct. The genx_fbc_activate functions
> * are supposed to read from it in order to program the registers.
> */
> - struct intel_fbc_state params;
> + struct intel_fbc_state state;
> const char *no_fbc_reason;
> };
>
> @@ -211,12 +211,12 @@ static u16 intel_fbc_override_cfb_stride(const struct
> intel_plane_state *plane_s
>
> static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> unsigned int cfb_stride;
> u32 fbc_ctl;
>
> - cfb_stride = params->cfb_stride / fbc->limit;
> + cfb_stride = fbc_state->cfb_stride / fbc->limit;
>
> /* FBC_CTL wants 32B or 64B units */
> if (DISPLAY_VER(i915) == 2)
> @@ -225,27 +225,27 @@ static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
> cfb_stride = (cfb_stride / 64) - 1;
>
> fbc_ctl = FBC_CTL_PERIODIC |
> - FBC_CTL_INTERVAL(params->interval) |
> + FBC_CTL_INTERVAL(fbc_state->interval) |
> FBC_CTL_STRIDE(cfb_stride);
>
> if (IS_I945GM(i915))
> fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling
> */
>
> - if (params->fence_id >= 0)
> - fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
> + if (fbc_state->fence_id >= 0)
> + fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
>
> return fbc_ctl;
> }
>
> static u32 i965_fbc_ctl2(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> u32 fbc_ctl2;
>
> fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
> - FBC_CTL_PLANE(params->plane->i9xx_plane);
> + FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
>
> - if (params->fence_id >= 0)
> + if (fbc_state->fence_id >= 0)
> fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
>
> return fbc_ctl2;
> @@ -274,7 +274,7 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
>
> static void i8xx_fbc_activate(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> int i;
>
> @@ -286,7 +286,7 @@ static void i8xx_fbc_activate(struct intel_fbc *fbc)
> intel_de_write(i915, FBC_CONTROL2,
> i965_fbc_ctl2(fbc));
> intel_de_write(i915, FBC_FENCE_OFF,
> - params->fence_y_offset);
> + fbc_state->fence_y_offset);
> }
>
> intel_de_write(i915, FBC_CONTROL,
> @@ -306,8 +306,8 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc
> *fbc)
>
> static void i8xx_fbc_nuke(struct intel_fbc *fbc) {
> - struct intel_fbc_state *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
> + struct intel_fbc_state *fbc_state = &fbc->state;
> + enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -342,8 +342,8 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = {
>
> static void i965_fbc_nuke(struct intel_fbc *fbc) {
> - struct intel_fbc_state *params = &fbc->params;
> - enum i9xx_plane_id i9xx_plane = params->plane->i9xx_plane;
> + struct intel_fbc_state *fbc_state = &fbc->state;
> + enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
> struct drm_i915_private *dev_priv = fbc->i915;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> @@ -378,21 +378,21 @@ static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
>
> static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> u32 dpfc_ctl;
>
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
> - DPFC_CTL_PLANE_G4X(params->plane->i9xx_plane);
> + DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
>
> if (IS_G4X(i915))
> dpfc_ctl |= DPFC_CTL_SR_EN;
>
> - if (params->fence_id >= 0) {
> + if (fbc_state->fence_id >= 0) {
> dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
>
> if (DISPLAY_VER(i915) < 6)
> - dpfc_ctl |= DPFC_CTL_FENCENO(params->fence_id);
> + dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
> }
>
> return dpfc_ctl;
> @@ -400,11 +400,11 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
>
> static void g4x_fbc_activate(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
>
> intel_de_write(i915, DPFC_FENCE_YOFF,
> - params->fence_y_offset);
> + fbc_state->fence_y_offset);
>
> intel_de_write(i915, DPFC_CONTROL,
> DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); @@ -451,11 +451,11
> @@ static const struct intel_fbc_funcs g4x_fbc_funcs = {
>
> static void ilk_fbc_activate(struct intel_fbc *fbc) {
> - struct intel_fbc_state *params = &fbc->params;
> + struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
>
> intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
> - params->fence_y_offset);
> + fbc_state->fence_y_offset);
>
> intel_de_write(i915, ILK_DPFC_CONTROL,
> DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); @@ -502,15 +502,15
> @@ static const struct intel_fbc_funcs ilk_fbc_funcs = {
>
> static void snb_fbc_program_fence(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> u32 ctl = 0;
>
> - if (params->fence_id >= 0)
> - ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(params-
> >fence_id);
> + if (fbc_state->fence_id >= 0)
> + ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state-
> >fence_id);
>
> intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
> - intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, params-
> >fence_y_offset);
> + intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET,
> +fbc_state->fence_y_offset);
> }
>
> static void snb_fbc_activate(struct intel_fbc *fbc) @@ -539,27 +539,27 @@
> static const struct intel_fbc_funcs snb_fbc_funcs = {
>
> static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> u32 val = 0;
>
> - if (params->override_cfb_stride)
> + if (fbc_state->override_cfb_stride)
> val |= FBC_STRIDE_OVERRIDE |
> - FBC_STRIDE(params->override_cfb_stride / fbc->limit);
> + FBC_STRIDE(fbc_state->override_cfb_stride / fbc-
> >limit);
>
> intel_de_write(i915, GLK_FBC_STRIDE, val); }
>
> static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> u32 val = 0;
>
> /* Display WA #0529: skl, kbl, bxt. */
> - if (params->override_cfb_stride)
> + if (fbc_state->override_cfb_stride)
> val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> - CHICKEN_FBC_STRIDE(params->override_cfb_stride /
> fbc->limit);
> + CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride /
> fbc->limit);
>
> intel_de_rmw(i915, CHICKEN_MISC_4,
> CHICKEN_FBC_STRIDE_OVERRIDE |
> @@ -568,16 +568,16 @@ static void skl_fbc_program_cfb_stride(struct
> intel_fbc *fbc)
>
> static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) {
> - const struct intel_fbc_state *params = &fbc->params;
> + const struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
> u32 dpfc_ctl;
>
> dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
>
> if (IS_IVYBRIDGE(i915))
> - dpfc_ctl |= DPFC_CTL_PLANE_IVB(params->plane->i9xx_plane);
> + dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane-
> >i9xx_plane);
>
> - if (params->fence_id >= 0)
> + if (fbc_state->fence_id >= 0)
> dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
>
> if (fbc->false_color)
> @@ -631,7 +631,7 @@ static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_activate(struct intel_fbc *fbc) {
> - trace_intel_fbc_activate(fbc->params.plane);
> + trace_intel_fbc_activate(fbc->state.plane);
>
> fbc->active = true;
> fbc->activated = true;
> @@ -641,7 +641,7 @@ static void intel_fbc_hw_activate(struct intel_fbc *fbc)
>
> static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) {
> - trace_intel_fbc_deactivate(fbc->params.plane);
> + trace_intel_fbc_deactivate(fbc->state.plane);
>
> fbc->active = false;
>
> @@ -655,7 +655,7 @@ static bool intel_fbc_is_compressing(struct intel_fbc
> *fbc)
>
> static void intel_fbc_nuke(struct intel_fbc *fbc) {
> - trace_intel_fbc_nuke(fbc->params.plane);
> + trace_intel_fbc_nuke(fbc->state.plane);
>
> fbc->funcs->nuke(fbc);
> }
> @@ -943,9 +943,9 @@ static bool tiling_is_valid(const struct intel_plane_state
> *plane_state)
> }
> }
>
> -static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_plane *plane)
> +static void intel_fbc_update_state(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_crtc_state *crtc_state = @@ -953,30 +953,29 @@
> static void intel_fbc_update_state_cache(struct intel_atomic_state *state,
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
> - struct intel_fbc_state *cache = &fbc->params;
> + struct intel_fbc_state *fbc_state = &fbc->state;
>
> - if (plane_state->no_fbc_reason)
> - return;
> + WARN_ON(plane_state->no_fbc_reason);
>
> - cache->plane = plane;
> + fbc_state->plane = plane;
>
> /* FBC1 compression interval: arbitrary choice of 1 second */
> - cache->interval = drm_mode_vrefresh(&crtc_state-
> >hw.adjusted_mode);
> + fbc_state->interval =
> +drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
>
> - cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
> + fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
>
> drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE
> &&
> !plane_state->ggtt_vma->fence);
>
> if (plane_state->flags & PLANE_HAS_FENCE &&
> plane_state->ggtt_vma->fence)
> - cache->fence_id = plane_state->ggtt_vma->fence->id;
> + fbc_state->fence_id = plane_state->ggtt_vma->fence->id;
> else
> - cache->fence_id = -1;
> + fbc_state->fence_id = -1;
>
> - cache->cfb_stride = intel_fbc_cfb_stride(plane_state);
> - cache->cfb_size = intel_fbc_cfb_size(plane_state);
> - cache->override_cfb_stride =
> intel_fbc_override_cfb_stride(plane_state);
> + fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
> + fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
> + fbc_state->override_cfb_stride =
> +intel_fbc_override_cfb_stride(plane_state);
> }
>
> static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
> @@ -1232,7 +1231,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state
> *state,
>
> mutex_lock(&fbc->lock);
>
> - if (fbc->params.plane == plane)
> + if (fbc->state.plane == plane)
> need_vblank_wait |= __intel_fbc_pre_update(state,
> crtc, plane);
>
> mutex_unlock(&fbc->lock);
> @@ -1244,10 +1243,9 @@ bool intel_fbc_pre_update(struct intel_atomic_state
> *state, static void __intel_fbc_disable(struct intel_fbc *fbc) {
> struct drm_i915_private *i915 = fbc->i915;
> - struct intel_plane *plane = fbc->params.plane;
> + struct intel_plane *plane = fbc->state.plane;
>
> drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
> - drm_WARN_ON(&i915->drm, !fbc->params.plane);
> drm_WARN_ON(&i915->drm, fbc->active);
>
> drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n", @@ -
> 1255,7 +1253,7 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
>
> __intel_fbc_cleanup_cfb(fbc);
>
> - fbc->params.plane = NULL;
> + fbc->state.plane = NULL;
> }
>
> static void __intel_fbc_post_update(struct intel_fbc *fbc) @@ -1285,7 +1283,7
> @@ void intel_fbc_post_update(struct intel_atomic_state *state,
>
> mutex_lock(&fbc->lock);
>
> - if (fbc->params.plane == plane) {
> + if (fbc->state.plane == plane) {
> fbc->flip_pending = false;
> __intel_fbc_post_update(fbc);
> }
> @@ -1296,8 +1294,8 @@ void intel_fbc_post_update(struct intel_atomic_state
> *state,
>
> static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) {
> - if (fbc->params.plane)
> - return fbc->params.plane->frontbuffer_bit;
> + if (fbc->state.plane)
> + return fbc->state.plane->frontbuffer_bit;
> else
> return fbc->possible_framebuffer_bits; } @@ -1318,7 +1316,7
> @@ void intel_fbc_invalidate(struct drm_i915_private *i915,
>
> fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
>
> - if (fbc->params.plane && fbc->busy_bits)
> + if (fbc->state.plane && fbc->busy_bits)
> intel_fbc_deactivate(fbc, "frontbuffer write");
>
> mutex_unlock(&fbc->lock);
> @@ -1339,7 +1337,7 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
> goto out;
>
> - if (!fbc->busy_bits && fbc->params.plane &&
> + if (!fbc->busy_bits && fbc->state.plane &&
> (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
> if (fbc->active)
> intel_fbc_nuke(fbc);
> @@ -1377,8 +1375,8 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> intel_atomic_get_new_plane_state(state, plane);
> struct intel_fbc *fbc = plane->fbc;
>
> - if (fbc->params.plane) {
> - if (fbc->params.plane != plane)
> + if (fbc->state.plane) {
> + if (fbc->state.plane != plane)
> return;
>
> if (intel_fbc_is_ok(plane_state))
> @@ -1413,7 +1411,7 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
> plane->base.base.id, plane->base.name);
> fbc->no_fbc_reason = "FBC enabled but not active yet\n";
>
> - intel_fbc_update_state_cache(state, crtc, plane);
> + intel_fbc_update_state(state, crtc, plane);
>
> intel_fbc_program_cfb(fbc);
> }
> @@ -1436,7 +1434,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
> continue;
>
> mutex_lock(&fbc->lock);
> - if (fbc->params.plane == plane)
> + if (fbc->state.plane == plane)
> __intel_fbc_disable(fbc);
> mutex_unlock(&fbc->lock);
> }
> @@ -1460,7 +1458,7 @@ void intel_fbc_update(struct intel_atomic_state
> *state,
> mutex_lock(&fbc->lock);
>
> if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
> - if (fbc->params.plane == plane)
> + if (fbc->state.plane == plane)
> __intel_fbc_disable(fbc);
> } else {
> __intel_fbc_enable(state, crtc, plane); @@ -1484,7
> +1482,7 @@ void intel_fbc_global_disable(struct drm_i915_private *i915)
> return;
>
> mutex_lock(&fbc->lock);
> - if (fbc->params.plane)
> + if (fbc->state.plane)
> __intel_fbc_disable(fbc);
> mutex_unlock(&fbc->lock);
> }
> @@ -1497,7 +1495,7 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
> mutex_lock(&fbc->lock);
>
> /* Maybe we were scheduled twice. */
> - if (fbc->underrun_detected || !fbc->params.plane)
> + if (fbc->underrun_detected || !fbc->state.plane)
> goto out;
>
> drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
> @@ -1505,7 +1503,7 @@ static void intel_fbc_underrun_work_fn(struct
> work_struct *work)
>
> intel_fbc_deactivate(fbc, "FIFO underrun");
> if (!fbc->flip_pending)
> - intel_wait_for_vblank(i915, fbc->params.plane->pipe);
> + intel_wait_for_vblank(i915, fbc->state.plane->pipe);
> __intel_fbc_disable(fbc);
> out:
> mutex_unlock(&fbc->lock);
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (17 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 18/20] drm/i915/fbc: s/parms/fbc_state/ Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-01 11:32 ` Kahola, Mika
2021-11-24 11:36 ` [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output Ville Syrjala
` (12 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
FBC and double wide pipe are mutually exclusive. Disable FBC when
we have to resort to double wide.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4d2c54acdc89..072509b04de5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1056,6 +1056,11 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
return 0;
}
+ if (crtc_state->double_wide) {
+ plane_state->no_fbc_reason = "double wide pipe not supported";
+ return 0;
+ }
+
/*
* Display 12+ is not supporting FBC with PSR2.
* Recommendation is to keep this combination disabled
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe
2021-11-24 11:36 ` [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe Ville Syrjala
@ 2021-12-01 11:32 ` Kahola, Mika
0 siblings, 0 replies; 63+ messages in thread
From: Kahola, Mika @ 2021-12-01 11:32 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, November 24, 2021 1:37 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> FBC and double wide pipe are mutually exclusive. Disable FBC when we have to
> resort to double wide.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 4d2c54acdc89..072509b04de5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1056,6 +1056,11 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> + if (crtc_state->double_wide) {
> + plane_state->no_fbc_reason = "double wide pipe not
> supported";
> + return 0;
> + }
> +
> /*
> * Display 12+ is not supporting FBC with PSR2.
> * Recommendation is to keep this combination disabled
> --
> 2.32.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (18 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 19/20] drm/i915/fbc: No FBC+double wide pipe Ville Syrjala
@ 2021-11-24 11:36 ` Ville Syrjala
2021-12-03 11:48 ` Ville Syrjälä
2021-11-24 13:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring Patchwork
` (11 subsequent siblings)
31 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjala @ 2021-11-24 11:36 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that each plane tracks its own no_fbc_reason we can print that
out in debugfs, and we can also show which plane is currently
selected for FBC duty.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 072509b04de5..8f8512f685eb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1688,8 +1688,11 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
{
struct intel_fbc *fbc = m->private;
struct drm_i915_private *i915 = fbc->i915;
+ struct intel_plane *plane;
intel_wakeref_t wakeref;
+ drm_modeset_lock_all(&i915->drm);
+
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
mutex_lock(&fbc->lock);
@@ -1701,9 +1704,24 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
}
+ for_each_intel_plane(&i915->drm, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ if (plane->fbc != fbc)
+ continue;
+
+ seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
+ fbc->state.plane == plane ? '*' : ' ',
+ plane->base.base.id, plane->base.name,
+ plane_state->no_fbc_reason ?: "FBC possible");
+ }
+
mutex_unlock(&fbc->lock);
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ drm_modeset_unlock_all(&i915->drm);
+
return 0;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output
2021-11-24 11:36 ` [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output Ville Syrjala
@ 2021-12-03 11:48 ` Ville Syrjälä
2021-12-03 16:11 ` Jani Nikula
0 siblings, 1 reply; 63+ messages in thread
From: Ville Syrjälä @ 2021-12-03 11:48 UTC (permalink / raw)
To: intel-gfx
On Wed, Nov 24, 2021 at 01:36:52PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that each plane tracks its own no_fbc_reason we can print that
> out in debugfs, and we can also show which plane is currently
> selected for FBC duty.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
This one is still missing review.
I've pushed everything else, thans for the reviews so far.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output
2021-12-03 11:48 ` Ville Syrjälä
@ 2021-12-03 16:11 ` Jani Nikula
0 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2021-12-03 16:11 UTC (permalink / raw)
To: Ville Syrjälä, intel-gfx
On Fri, 03 Dec 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Nov 24, 2021 at 01:36:52PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Now that each plane tracks its own no_fbc_reason we can print that
>> out in debugfs, and we can also show which plane is currently
>> selected for FBC duty.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This one is still missing review.
>
> I've pushed everything else, thans for the reviews so far.
Seems fine.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (19 preceding siblings ...)
2021-11-24 11:36 ` [Intel-gfx] [PATCH 20/20] drm/i915/fbc: Pimp the FBC debugfs output Ville Syrjala
@ 2021-11-24 13:31 ` Patchwork
2021-11-24 13:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (10 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-24 13:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
daf75ef5fa24 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
af7d3467e59a drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
766554ded9a6 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
d39a6774d015 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
6d32c9dc060d drm/i915/fbc: Nuke more FBC state
eddfad2b1288 drm/i915/fbc: Reuse the same struct for the cache and params
31e06105aefc drm/i915/fbc: Pass around FBC instance instead of crtc
8611830ea672 drm/i915/fbc: Track FBC usage per-plane
-:427: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:427: WARNING:TABSTOP: Statements should start on a tabstop
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:TABSTOP: Statements should start on a tabstop
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:TABSTOP: Statements should start on a tabstop
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
total: 0 errors, 6 warnings, 0 checks, 423 lines checked
850242482fdc drm/i915/fbc: Flatten __intel_fbc_pre_update()
277d0981c162 drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
5f0b99188755 drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
c62767b59742 drm/i915/fbc: Introduce intel_fbc_add_plane()
da0902427db7 drm/i915/fbc: Allocate intel_fbc dynamically
c6c6f9f8c3f8 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
e0bd9ec2a43d drm/i915/fbc: Disable FBC fully on FIFO underrun
af74b495dd54 drm/i915/fbc: Nuke state_cache
33c7b45b4f46 drm/i915/fbc: Move plane pointer into intel_fbc_state
dac670cc9e0d drm/i915/fbc: s/parms/fbc_state/
a70975006ff0 drm/i915/fbc: No FBC+double wide pipe
3d901c6ba4e2 drm/i915/fbc: Pimp the FBC debugfs output
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: More FBC refactoring
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (20 preceding siblings ...)
2021-11-24 13:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring Patchwork
@ 2021-11-24 13:32 ` Patchwork
2021-11-24 14:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (9 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-24 13:32 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/fbc: More FBC refactoring
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (21 preceding siblings ...)
2021-11-24 13:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-11-24 14:02 ` Patchwork
2021-11-24 15:48 ` [Intel-gfx] [PATCH 00/20] " Jani Nikula
` (8 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-24 14:02 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10836 bytes --]
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring
URL : https://patchwork.freedesktop.org/series/97239/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10923 -> Patchwork_21674
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21674 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21674, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/index.html
Participating hosts (39 -> 34)
------------------------------
Additional (2): fi-skl-guc fi-tgl-u2
Missing (7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-jsl-2 bat-jsl-1 fi-skl-6600u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21674:
### IGT changes ###
#### Possible regressions ####
* igt@kms_frontbuffer_tracking@basic:
- fi-bsw-n3050: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-bsw-n3050/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-bsw-n3050/igt@kms_frontbuffer_tracking@basic.html
- fi-bsw-kefka: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-bsw-kefka/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-bsw-kefka/igt@kms_frontbuffer_tracking@basic.html
- fi-ilk-650: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-ilk-650/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-ilk-650/igt@kms_frontbuffer_tracking@basic.html
- fi-ivb-3770: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-ivb-3770/igt@kms_frontbuffer_tracking@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-ivb-3770/igt@kms_frontbuffer_tracking@basic.html
- fi-skl-guc: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-skl-guc/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@kms_frontbuffer_tracking@basic:
- fi-elk-e7500: [SKIP][10] ([fdo#109271]) -> [FAIL][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-elk-e7500/igt@kms_frontbuffer_tracking@basic.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-elk-e7500/igt@kms_frontbuffer_tracking@basic.html
Known issues
------------
Here are the changes found in Patchwork_21674 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([fdo#109315]) +17 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][13] ([i915#4006])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-skl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#4613]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][17] -> [INCOMPLETE][18] ([i915#3921])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick: [PASS][19] -> [DMESG-FAIL][20] ([i915#2927] / [i915#3428])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_chamelium@dp-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +8 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][22] ([fdo#109284] / [fdo#111827]) +8 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-skl-guc: NOTRUN -> [SKIP][23] ([fdo#109271]) +28 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-tgl-u2: NOTRUN -> [SKIP][24] ([i915#4103]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][25] ([fdo#109285])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#533])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][27] ([i915#3301])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-nick: NOTRUN -> [FAIL][28] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-bsw-nick/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][29] ([i915#1602] / [i915#2722] / [i915#4312])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][30] ([i915#4432]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][32] ([i915#295]) -> [PASS][33] +12 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10923/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_10923 -> Patchwork_21674
CI-20190529: 20190529
CI_DRM_10923: 9884a105da0c9d4513b67b3d89ceb9a7086bb972 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6288: a5ac2c3e67bc9a9c8d3f440a0324ee2c5d49eb49 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21674: 3d901c6ba4e251d07ee94f629fdb2f8d219d01df @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3d901c6ba4e2 drm/i915/fbc: Pimp the FBC debugfs output
a70975006ff0 drm/i915/fbc: No FBC+double wide pipe
dac670cc9e0d drm/i915/fbc: s/parms/fbc_state/
33c7b45b4f46 drm/i915/fbc: Move plane pointer into intel_fbc_state
af74b495dd54 drm/i915/fbc: Nuke state_cache
e0bd9ec2a43d drm/i915/fbc: Disable FBC fully on FIFO underrun
c6c6f9f8c3f8 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
da0902427db7 drm/i915/fbc: Allocate intel_fbc dynamically
c62767b59742 drm/i915/fbc: Introduce intel_fbc_add_plane()
5f0b99188755 drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
277d0981c162 drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
850242482fdc drm/i915/fbc: Flatten __intel_fbc_pre_update()
8611830ea672 drm/i915/fbc: Track FBC usage per-plane
31e06105aefc drm/i915/fbc: Pass around FBC instance instead of crtc
eddfad2b1288 drm/i915/fbc: Reuse the same struct for the cache and params
6d32c9dc060d drm/i915/fbc: Nuke more FBC state
d39a6774d015 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
766554ded9a6 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
af7d3467e59a drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
daf75ef5fa24 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21674/index.html
[-- Attachment #2: Type: text/html, Size: 12708 bytes --]
^ permalink raw reply [flat|nested] 63+ messages in thread* Re: [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (22 preceding siblings ...)
2021-11-24 14:02 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-11-24 15:48 ` Jani Nikula
2021-11-26 6:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev2) Patchwork
` (7 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Jani Nikula @ 2021-11-24 15:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 24 Nov 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Continue refactoring the FBC code towards multiple FBC
> instances and more flexible plane<->FBC assignment.
There's a lot to like here. I haven't done detailed review, but apart
from the comment on the debugfs split, the series is
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> Ville Syrjälä (20):
> drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
> drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
> drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
> drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
> drm/i915/fbc: Nuke more FBC state
> drm/i915/fbc: Reuse the same struct for the cache and params
> drm/i915/fbc: Pass around FBC instance instead of crtc
> drm/i915/fbc: Track FBC usage per-plane
> drm/i915/fbc: Flatten __intel_fbc_pre_update()
> drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
> drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
> drm/i915/fbc: Introduce intel_fbc_add_plane()
> drm/i915/fbc: Allocate intel_fbc dynamically
> drm/i915/fbc: Move stuff from intel_fbc_can_enable() into
> intel_fbc_check_plane()
> drm/i915/fbc: Disable FBC fully on FIFO underrun
> drm/i915/fbc: Nuke state_cache
> drm/i915/fbc: Move plane pointer into intel_fbc_state
> drm/i915/fbc: s/parms/fbc_state/
> drm/i915/fbc: No FBC+double wide pipe
> drm/i915/fbc: Pimp the FBC debugfs output
>
> drivers/gpu/drm/i915/display/i9xx_plane.c | 15 +-
> drivers/gpu/drm/i915/display/intel_display.c | 5 +-
> .../drm/i915/display/intel_display_debugfs.c | 54 +-
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 1231 +++++++++--------
> drivers/gpu/drm/i915/display/intel_fbc.h | 13 +-
> .../drm/i915/display/intel_fifo_underrun.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c | 15 +-
> drivers/gpu/drm/i915/i915_drv.h | 101 +-
> drivers/gpu/drm/i915/i915_trace.h | 18 +-
> drivers/gpu/drm/i915/intel_pm.c | 9 +-
> 11 files changed, 690 insertions(+), 777 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev2)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (23 preceding siblings ...)
2021-11-24 15:48 ` [Intel-gfx] [PATCH 00/20] " Jani Nikula
@ 2021-11-26 6:48 ` Patchwork
2021-11-26 6:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-26 6:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b0fe40e87a84 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
bed0959cfa5b drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
efd77e8334c0 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
545993666997 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
c8cc75f5871a drm/i915/fbc: Nuke more FBC state
f83f4327755d drm/i915/fbc: Reuse the same struct for the cache and params
8f85614ed262 drm/i915/fbc: Pass around FBC instance instead of crtc
2e39a4018470 drm/i915/fbc: Track FBC usage per-plane
-:427: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:427: WARNING:TABSTOP: Statements should start on a tabstop
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:TABSTOP: Statements should start on a tabstop
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:TABSTOP: Statements should start on a tabstop
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
total: 0 errors, 6 warnings, 0 checks, 423 lines checked
ff34e90358e2 drm/i915/fbc: Flatten __intel_fbc_pre_update()
3a841917eade drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
30449365cb8d drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
fe90fc1caab3 drm/i915/fbc: Introduce intel_fbc_add_plane()
17e23c924c3e drm/i915/fbc: Allocate intel_fbc dynamically
66c429270725 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
80232297151f drm/i915/fbc: Disable FBC fully on FIFO underrun
333fc023eb02 drm/i915/fbc: Nuke state_cache
0d101081f6ba drm/i915/fbc: Move plane pointer into intel_fbc_state
1613ba4b582f drm/i915/fbc: s/parms/fbc_state/
265f35c68dfa drm/i915/fbc: No FBC+double wide pipe
707fe3ea76e0 drm/i915/fbc: Pimp the FBC debugfs output
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: More FBC refactoring (rev2)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (24 preceding siblings ...)
2021-11-26 6:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev2) Patchwork
@ 2021-11-26 6:49 ` Patchwork
2021-11-26 7:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-26 6:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: More FBC refactoring (rev2)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (25 preceding siblings ...)
2021-11-26 6:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-11-26 7:19 ` Patchwork
2021-11-26 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-26 7:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8516 bytes --]
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/97239/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10929 -> Patchwork_21684
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/index.html
Participating hosts (42 -> 35)
------------------------------
Additional (1): fi-tgl-u2
Missing (8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21684 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
- fi-skl-6700k2: NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-skl-6700k2: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-6700k2: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][8] -> [DMESG-FAIL][9] ([i915#2373])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][10] -> [INCOMPLETE][11] ([i915#3921])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([fdo#109284] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6700k2: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][18] ([i915#3301])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6700k2: [INCOMPLETE][19] ([i915#198]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][21] ([i915#4432]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4375]: https://gitlab.freedesktop.org/drm/intel/issues/4375
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_10929 -> Patchwork_21684
CI-20190529: 20190529
CI_DRM_10929: 59e636eb65235e3b6220ecf1b19da2a6dca76160 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6291: 9ff3844d8c1fee8d8736d888f16223c4789fb69f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21684: 707fe3ea76e0902d881c1b2315a32406c29b92f6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
707fe3ea76e0 drm/i915/fbc: Pimp the FBC debugfs output
265f35c68dfa drm/i915/fbc: No FBC+double wide pipe
1613ba4b582f drm/i915/fbc: s/parms/fbc_state/
0d101081f6ba drm/i915/fbc: Move plane pointer into intel_fbc_state
333fc023eb02 drm/i915/fbc: Nuke state_cache
80232297151f drm/i915/fbc: Disable FBC fully on FIFO underrun
66c429270725 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
17e23c924c3e drm/i915/fbc: Allocate intel_fbc dynamically
fe90fc1caab3 drm/i915/fbc: Introduce intel_fbc_add_plane()
30449365cb8d drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
3a841917eade drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
ff34e90358e2 drm/i915/fbc: Flatten __intel_fbc_pre_update()
2e39a4018470 drm/i915/fbc: Track FBC usage per-plane
8f85614ed262 drm/i915/fbc: Pass around FBC instance instead of crtc
f83f4327755d drm/i915/fbc: Reuse the same struct for the cache and params
c8cc75f5871a drm/i915/fbc: Nuke more FBC state
545993666997 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
efd77e8334c0 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
bed0959cfa5b drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
b0fe40e87a84 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/index.html
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^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: More FBC refactoring (rev2)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (26 preceding siblings ...)
2021-11-26 7:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-11-26 9:01 ` Patchwork
2021-11-28 6:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev3) Patchwork
` (3 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-26 9:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev2)
URL : https://patchwork.freedesktop.org/series/97239/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10929_full -> Patchwork_21684_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21684_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21684_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21684_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
Known issues
------------
Here are the changes found in Patchwork_21684_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063] / [i915#3648])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb3/igt@gem_eio@unwedge-stress.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [PASS][8] -> [SKIP][9] ([fdo#109271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-apl4/igt@gem_exec_fair@basic-none-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb8/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-random:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl9/igt@gem_lmem_swapping@heavy-random.html
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl6/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][21] ([i915#2658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-snb7/igt@gem_pread@exhaustion.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#4270])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-apl6/igt@gem_softpin@noreloc-s3.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#3297])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@gem_userptr_blits@input-checking.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: NOTRUN -> [DMESG-WARN][27] ([i915#180])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@bb-large:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#2856])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@gen9_exec_parse@bb-large.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][29] -> [FAIL][30] ([i915#454])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111644] / [i915#1397] / [i915#2411])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#198])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-skl10/igt@i915_suspend@fence-restore-tiled2untiled.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#404])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][35] ([i915#3743])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#111615])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615] / [i915#3689])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +90 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271]) +11 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-edid-read:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_chamelium@vga-edid-read.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +6 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +10 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@lic:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111828])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_content_protection@lic.html
- shard-kbl: NOTRUN -> [TIMEOUT][51] ([i915#1319])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl1/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3359]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-onscreen:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-512x512-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][54] -> [INCOMPLETE][55] ([i915#2411] / [i915#4211])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_flip@blocking-absolute-wf_vblank@a-edp1:
- shard-skl: [PASS][56] -> [DMESG-WARN][57] ([i915#1982])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-skl3/igt@kms_flip@blocking-absolute-wf_vblank@a-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@kms_flip@blocking-absolute-wf_vblank@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [PASS][58] -> [SKIP][59] ([i915#3701])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2672])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#1226])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-apl7/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl3/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
- shard-kbl: [PASS][63] -> [DMESG-WARN][64] ([i915#1226])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-kbl7/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl7/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-tglb: [PASS][65] -> [INCOMPLETE][66] ([i915#2411] / [i915#2828] / [i915#456])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-snb: NOTRUN -> [SKIP][67] ([fdo#109271]) +13 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-snb7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111825]) +9 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271]) +89 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][70] -> [DMESG-WARN][71] ([i915#180]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
- shard-skl: [PASS][72] -> [FAIL][73] ([i915#1188])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-tglb: [PASS][76] -> [INCOMPLETE][77] ([i915#2828] / [i915#456]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][78] ([i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][80] ([fdo#108145] / [i915#265])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
- shard-skl: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_lowres@pipe-c-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3536])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-x.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][85] -> [SKIP][86] ([fdo#109642] / [fdo#111068] / [i915#658])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][87] -> [SKIP][88] ([fdo#109441]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb4/igt@kms_psr@psr2_primary_blt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][89] -> [DMESG-WARN][90] ([i915#180] / [i915#295])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl8/igt@kms_writeback@writeback-check-output.html
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2437])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-d-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#2530])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@nouveau_crc@pipe-d-source-outp-complete.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][94] ([i915#180])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl1/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][95] ([fdo#109291]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@prime_nv_pcopy@test3_2.html
* igt@sysfs_clients@sema-50:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#2994])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@drm_read@short-buffer-block:
- {shard-rkl}: [SKIP][97] ([i915#4098]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@drm_read@short-buffer-block.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@drm_read@short-buffer-block.html
* igt@fbdev@pan:
- {shard-rkl}: ([SKIP][99], [SKIP][100]) ([i915#2582]) -> [PASS][101]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@fbdev@pan.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-4/igt@fbdev@pan.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@fbdev@pan.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][102] ([i915#2842]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][104] ([i915#2842] / [i915#3468]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][108] ([i915#2842]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-snb: [INCOMPLETE][110] -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-snb2/igt@gem_exec_suspend@basic-s4-devices.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-snb7/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][112] ([i915#1436] / [i915#716]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_backlight@bad-brightness:
- {shard-rkl}: [SKIP][114] ([i915#3012]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@i915_pm_backlight@bad-brightness.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][116] ([i915#1397]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp-stress.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_async_flips@async-flip-with-page-flip-events:
- {shard-rkl}: ([SKIP][118], [SKIP][119]) ([i915#1845]) -> [PASS][120] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_async_flips@async-flip-with-page-flip-events.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][121] ([i915#118]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-glk9/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_color@pipe-a-ctm-0-25:
- {shard-rkl}: [SKIP][123] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_color@pipe-a-ctm-0-25.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement:
- {shard-rkl}: [SKIP][125] ([fdo#112022] / [i915#4070]) -> [PASS][126] +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][127] ([i915#300]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
- {shard-rkl}: ([SKIP][129], [SKIP][130]) ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][131]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge:
- {shard-rkl}: [SKIP][132] ([i915#1849] / [i915#4070]) -> [PASS][133] +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- {shard-rkl}: [SKIP][134] ([fdo#111825] / [i915#4070]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {shard-rkl}: ([PASS][136], [SKIP][137]) ([fdo#111825]) -> [PASS][138]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-4/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- {shard-rkl}: [SKIP][139] ([fdo#111314]) -> [PASS][140] +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-snb: [SKIP][141] ([fdo#109271]) -> [PASS][142] +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10929/shard-snb7/igt@kms_fbcon_fbt@fbc-suspend.html
[142]: https://intel-gfx-ci.01.org/tree/drm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21684/index.html
[-- Attachment #2: Type: text/html, Size: 33378 bytes --]
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev3)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (27 preceding siblings ...)
2021-11-26 9:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-11-28 6:08 ` Patchwork
2021-11-28 6:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-28 6:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev3)
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecef8578b004 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
d3fce6e917a0 drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
d34c28935927 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
9f5b6931ea18 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
54eed564808c drm/i915/fbc: Nuke more FBC state
1acf585d8f7a drm/i915/fbc: Reuse the same struct for the cache and params
61bff1141b24 drm/i915/fbc: Pass around FBC instance instead of crtc
fa1855f35110 drm/i915/fbc: Track FBC usage per-plane
-:427: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:427: WARNING:TABSTOP: Statements should start on a tabstop
#427: FILE: drivers/gpu/drm/i915/i915_trace.h:385:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:447: WARNING:TABSTOP: Statements should start on a tabstop
#447: FILE: drivers/gpu/drm/i915/i915_trace.h:407:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
-:467: WARNING:TABSTOP: Statements should start on a tabstop
#467: FILE: drivers/gpu/drm/i915/i915_trace.h:429:
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(to_i915(plane->base.dev),
total: 0 errors, 6 warnings, 0 checks, 423 lines checked
88636ab19217 drm/i915/fbc: Flatten __intel_fbc_pre_update()
01c5bd8f3273 drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
b9d51c6c3959 drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
aac0390be0a4 drm/i915/fbc: Introduce intel_fbc_add_plane()
39f3617ba35b drm/i915/fbc: Allocate intel_fbc dynamically
5023c9d56830 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
d0e5f415b54b drm/i915/fbc: Disable FBC fully on FIFO underrun
160889a06c69 drm/i915/fbc: Nuke state_cache
c63d4fbb2cac drm/i915/fbc: Move plane pointer into intel_fbc_state
c8fe1882d435 drm/i915/fbc: s/parms/fbc_state/
65cdebed3462 drm/i915/fbc: No FBC+double wide pipe
5076f20a6bda drm/i915/fbc: Pimp the FBC debugfs output
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: More FBC refactoring (rev3)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (28 preceding siblings ...)
2021-11-28 6:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More FBC refactoring (rev3) Patchwork
@ 2021-11-28 6:09 ` Patchwork
2021-11-28 6:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-11-28 8:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-28 6:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev3)
URL : https://patchwork.freedesktop.org/series/97239/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: More FBC refactoring (rev3)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (29 preceding siblings ...)
2021-11-28 6:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-11-28 6:42 ` Patchwork
2021-11-28 8:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-28 6:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6809 bytes --]
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev3)
URL : https://patchwork.freedesktop.org/series/97239/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10934 -> Patchwork_21690
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/index.html
Participating hosts (41 -> 32)
------------------------------
Missing (9): fi-kbl-soraka bat-dg1-6 fi-tgl-u2 bat-dg1-5 bat-adlp-6 bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21690 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4547])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#4432])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-11600: [PASS][7] -> [DMESG-FAIL][8] ([i915#2373])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#4269])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][11] ([i915#3928] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [FAIL][12] ([i915#4547]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][14] ([i915#1886]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [DMESG-FAIL][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [INCOMPLETE][18] ([i915#3921]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
Build changes
-------------
* Linux: CI_DRM_10934 -> Patchwork_21690
CI-20190529: 20190529
CI_DRM_10934: 6a8f90ec433e2f5de5fc16d7a4839771b7027cc0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6293: bf11f87c27ad1cec3e60bd31c23080d19aa093f3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21690: 5076f20a6bda76f23a1b2e87dc4c4f32bd32eeed @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5076f20a6bda drm/i915/fbc: Pimp the FBC debugfs output
65cdebed3462 drm/i915/fbc: No FBC+double wide pipe
c8fe1882d435 drm/i915/fbc: s/parms/fbc_state/
c63d4fbb2cac drm/i915/fbc: Move plane pointer into intel_fbc_state
160889a06c69 drm/i915/fbc: Nuke state_cache
d0e5f415b54b drm/i915/fbc: Disable FBC fully on FIFO underrun
5023c9d56830 drm/i915/fbc: Move stuff from intel_fbc_can_enable() into intel_fbc_check_plane()
39f3617ba35b drm/i915/fbc: Allocate intel_fbc dynamically
aac0390be0a4 drm/i915/fbc: Introduce intel_fbc_add_plane()
b9d51c6c3959 drm/i915/fbc: Move FBC debugfs stuff into intel_fbc.c
01c5bd8f3273 drm/i915/fbc: Pass i915 instead of FBC instance to FBC underrun stuff
88636ab19217 drm/i915/fbc: Flatten __intel_fbc_pre_update()
fa1855f35110 drm/i915/fbc: Track FBC usage per-plane
61bff1141b24 drm/i915/fbc: Pass around FBC instance instead of crtc
1acf585d8f7a drm/i915/fbc: Reuse the same struct for the cache and params
54eed564808c drm/i915/fbc: Nuke more FBC state
9f5b6931ea18 drm/i915/fbc: Relocate intel_fbc_override_cfb_stride()
d34c28935927 drm/i915/fbc: Nuke lots of crap from intel_fbc_state_cache
d3fce6e917a0 drm/i915/fbc: Pass whole plane state to intel_fbc_min_limit()
ecef8578b004 drm/i915/fbc: Eliminate racy intel_fbc_is_active() usage
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/index.html
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^ permalink raw reply [flat|nested] 63+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: More FBC refactoring (rev3)
2021-11-24 11:36 [Intel-gfx] [PATCH 00/20] drm/i915/fbc: More FBC refactoring Ville Syrjala
` (30 preceding siblings ...)
2021-11-28 6:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-11-28 8:22 ` Patchwork
31 siblings, 0 replies; 63+ messages in thread
From: Patchwork @ 2021-11-28 8:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]
== Series Details ==
Series: drm/i915/fbc: More FBC refactoring (rev3)
URL : https://patchwork.freedesktop.org/series/97239/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10934_full -> Patchwork_21690_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21690_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21690_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21690_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_selftest@all@check_plane_state:
- shard-tglb: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@kms_selftest@all@check_plane_state.html
- shard-kbl: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl3/igt@kms_selftest@all@check_plane_state.html
Known issues
------------
Here are the changes found in Patchwork_21690_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [FAIL][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4392]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk1/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk1/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk1/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk3/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk3/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk4/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk4/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk4/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk2/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk2/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk6/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk9/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk9/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#456])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-tglb1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#280])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][56] -> [TIMEOUT][57] ([i915#3063])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-tglb7/igt@gem_eio@in-flight-contexts-1us.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][58] -> [FAIL][59] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][62] -> [SKIP][63] ([fdo#109271]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4613]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#4613])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@smem-oom:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl4/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_media_vme:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#284])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@gem_media_vme.html
* igt@gem_pxp@display-protected-crc:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#4270]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#768])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html
* igt@gem_vm_create@invalid-destroy:
- shard-iclb: [PASS][71] -> [DMESG-WARN][72] ([i915#4391])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb3/igt@gem_vm_create@invalid-destroy.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb7/igt@gem_vm_create@invalid-destroy.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][73] -> [DMESG-WARN][74] ([i915#180]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
- shard-kbl: NOTRUN -> [DMESG-WARN][75] ([i915#180])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gen3_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109289])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@gen3_mixed_blits.html
* igt@gen9_exec_parse@bb-start-param:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#2856])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][78] -> [FAIL][79] ([i915#454])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#1937])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#1937])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#111644] / [i915#1397] / [i915#2411])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-tglb: [PASS][83] -> [INCOMPLETE][84] ([i915#2411] / [i915#456] / [i915#750])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-tglb1/igt@i915_pm_rpm@system-suspend-execbuf.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb7/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3777]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3777]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +14 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-skl9/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#110723])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][90] ([fdo#111615]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278] / [i915#3886])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#3886])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#3886]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#3886]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][95] ([i915#3689])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#111615] / [i915#3689])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-snb: NOTRUN -> [SKIP][97] ([fdo#109271]) +7 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-snb5/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271]) +101 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-frame-dump:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109284] / [fdo#111827]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][100] ([fdo#109271] / [fdo#111827])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-glk: NOTRUN -> [SKIP][101] ([fdo#109271] / [fdo#111827]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-tglb: NOTRUN -> [SKIP][102] ([fdo#109284] / [fdo#111827]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [fdo#111827])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-skl9/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [fdo#111827]) +10 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111827]) +4 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglb: NOTRUN -> [SKIP][107] ([fdo#111828]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#3116])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][109] ([i915#1319])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl3/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#3319]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][111] ([i915#3359]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109278] / [fdo#109279])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_cursor_crc@pipe-c-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][113] -> [DMESG-WARN][114] ([i915#180])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-random:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109278]) +9 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_cursor_crc@pipe-d-cursor-64x64-random.html
* igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271]) +176 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl4/igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-iclb: NOTRUN -> [SKIP][117] ([fdo#109274] / [fdo#109278])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-iclb: [PASS][118] -> [FAIL][119] ([i915#2346])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglb: NOTRUN -> [SKIP][120] ([fdo#111825]) +9 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][121] -> [FAIL][122] ([i915#2122])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [PASS][123] -> [SKIP][124] ([i915#3701])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: [PASS][125] -> [DMESG-WARN][126] ([i915#1226])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-apl8/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
- shard-kbl: [PASS][127] -> [DMESG-WARN][128] ([i915#1226])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-kbl1/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl1/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109280]) +8 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][130] ([fdo#109271]) +35 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-tglb: [PASS][131] -> [INCOMPLETE][132] ([i915#2411] / [i915#456])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-tglb5/igt@kms_frontbuffer_tracking@psr-suspend.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][133] ([fdo#108145] / [i915#265])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][134] ([fdo#108145] / [i915#265]) +2 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
- shard-apl: NOTRUN -> [FAIL][135] ([fdo#108145] / [i915#265])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-iclb: NOTRUN -> [SKIP][136] ([i915#3536])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][137] ([fdo#111615] / [fdo#112054])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb3/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2733])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#658])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-glk7/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#658]) +2 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip:
- shard-apl: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#658]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl8/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][142] ([i915#132] / [i915#3467])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][143] -> [SKIP][144] ([fdo#109441])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][145] ([fdo#109441]) +1 similar issue
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][146] -> [FAIL][147] ([i915#31])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-apl4/igt@kms_setmode@basic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [PASS][148] -> [INCOMPLETE][149] ([i915#3896])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10934/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
* igt@kms_vrr@flipline:
- shard-iclb: NOTRUN -> [SKIP][150] ([fdo#109502])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_vrr@flipline.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][151] ([fdo#109271] / [i915#2437])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl1/igt@kms_writeback@writeback-check-output.html
- shard-kbl: NOTRUN -> [SKIP][152] ([fdo#109271] / [i915#2437])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-kbl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-iclb: NOTRUN -> [SKIP][153] ([i915#2437])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@kms_writeback@writeback-fb-id.html
* igt@prime_nv_test@i915_nv_sharing:
- shard-tglb: NOTRUN -> [SKIP][154] ([fdo#109291]) +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb6/igt@prime_nv_test@i915_nv_sharing.html
* igt@prime_nv_test@nv_write_i915_cpu_mmap_read:
- shard-iclb: NOTRUN -> [SKIP][155] ([fdo#109291])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-iclb3/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html
* igt@prime_vgem@fence-read-hang:
- shard-tglb: NOTRUN -> [SKIP][156] ([fdo#109295])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-tglb5/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][157] ([fdo#109271] / [i915#2994]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/shard-apl2/igt@sysfs_clients@recycl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21690/index.html
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