* [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
@ 2018-03-12 1:50 ` Shunqian Zheng
0 siblings, 0 replies; 6+ messages in thread
From: Shunqian Zheng @ 2018-03-12 1:50 UTC (permalink / raw)
To: heiko
Cc: linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
dianders, Shunqian Zheng
The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++--
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 199a511..7d8d5de 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -580,7 +580,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@@ -588,7 +589,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <800000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
&emmc_phy {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d79e9b3..91ee951 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1259,7 +1259,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1267,7 +1268,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
grf: syscon@ff770000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
@ 2018-03-12 1:50 ` Shunqian Zheng
0 siblings, 0 replies; 6+ messages in thread
From: Shunqian Zheng @ 2018-03-12 1:50 UTC (permalink / raw)
To: linux-arm-kernel
The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++--
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 199a511..7d8d5de 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -580,7 +580,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@@ -588,7 +589,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <800000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
&emmc_phy {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d79e9b3..91ee951 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1259,7 +1259,8 @@
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+ <&cru ACLK_VIO>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@@ -1267,7 +1268,8 @@
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
- <100000000>, <50000000>;
+ <100000000>, <50000000>,
+ <400000000>;
};
grf: syscon at ff770000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
2018-03-12 1:50 ` Shunqian Zheng
@ 2018-03-12 2:14 ` Doug Anderson
-1 siblings, 0 replies; 6+ messages in thread
From: Doug Anderson @ 2018-03-12 2:14 UTC (permalink / raw)
To: Shunqian Zheng
Cc: Heiko Stübner, open list:ARM/Rockchip SoC...,
devicetree, Linux ARM, LKML
Hi,
On Sun, Mar 11, 2018 at 6:50 PM, Shunqian Zheng <zhengsq@rock-chips.com> wrote:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++--
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++--
> 2 files changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
@ 2018-03-12 2:14 ` Doug Anderson
0 siblings, 0 replies; 6+ messages in thread
From: Doug Anderson @ 2018-03-12 2:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Sun, Mar 11, 2018 at 6:50 PM, Shunqian Zheng <zhengsq@rock-chips.com> wrote:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++--
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++--
> 2 files changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
2018-03-12 1:50 ` Shunqian Zheng
@ 2018-03-12 10:52 ` Heiko Stuebner
-1 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2018-03-12 10:52 UTC (permalink / raw)
To: Shunqian Zheng
Cc: linux-rockchip, devicetree, linux-arm-kernel, linux-kernel, dianders
Am Montag, 12. März 2018, 02:50:48 CET schrieb Shunqian Zheng:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
applied for 4.17
Thanks
Heiko
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
@ 2018-03-12 10:52 ` Heiko Stuebner
0 siblings, 0 replies; 6+ messages in thread
From: Heiko Stuebner @ 2018-03-12 10:52 UTC (permalink / raw)
To: linux-arm-kernel
Am Montag, 12. M?rz 2018, 02:50:48 CET schrieb Shunqian Zheng:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
applied for 4.17
Thanks
Heiko
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-12 10:53 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-12 1:50 [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO Shunqian Zheng
2018-03-12 1:50 ` Shunqian Zheng
2018-03-12 2:14 ` Doug Anderson
2018-03-12 2:14 ` Doug Anderson
2018-03-12 10:52 ` Heiko Stuebner
2018-03-12 10:52 ` Heiko Stuebner
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