* [PATCH v10 0/2] Add XYUV format support
@ 2018-10-02 11:15 Stanislav Lisovskiy
2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Stanislav Lisovskiy @ 2018-10-02 11:15 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, martin.peres, dri-devel, juha-pekka.heikkila
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format support for skl+
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
include/uapi/drm/drm_fourcc.h | 1 +
5 files changed, 21 insertions(+), 1 deletion(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-02 11:15 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy @ 2018-10-02 11:15 ` Stanislav Lisovskiy 2018-10-02 15:28 ` Alexandru-Cosmin Gheorghe 2018-10-02 11:15 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy ` (2 subsequent siblings) 3 siblings, 1 reply; 15+ messages in thread From: Stanislav Lisovskiy @ 2018-10-02 11:15 UTC (permalink / raw) To: intel-gfx; +Cc: ville.syrjala, martin.peres, dri-devel, juha-pekka.heikkila v5: This is YUV444 packed format same as AYUV, but without alpha, as supported by i915. v6: Removed unneeded initializer for new XYUV format. v7: Added is_yuv field initialization according to latest drm_fourcc format structure initialization changes. v8: Edited commit message to be more clear about skl+, renamed PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format doesn't support per-pixel alpha. Fixed minor code issues. v9: Moved DRM format check to proper place in intel_framebuffer_init. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/drm_fourcc.c | 1 + include/uapi/drm/drm_fourcc.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index be1d6aaef651..60752d0be9d8 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -190,6 +190,7 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true }, + { .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true }, }; unsigned int i; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 139632b87181..88d2e491f40c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -151,6 +151,7 @@ extern "C" { #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ /* * 2 plane RGB + A -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy @ 2018-10-02 15:28 ` Alexandru-Cosmin Gheorghe 2018-10-03 6:39 ` Lisovskiy, Stanislav 0 siblings, 1 reply; 15+ messages in thread From: Alexandru-Cosmin Gheorghe @ 2018-10-02 15:28 UTC (permalink / raw) To: Stanislav Lisovskiy Cc: ville.syrjala, intel-gfx, martin.peres, dri-devel, juha-pekka.heikkila, nd Hi, On Tue, Oct 02, 2018 at 02:15:42PM +0300, Stanislav Lisovskiy wrote: > v5: This is YUV444 packed format same as AYUV, but without alpha, > as supported by i915. > > v6: Removed unneeded initializer for new XYUV format. > > v7: Added is_yuv field initialization according to latest > drm_fourcc format structure initialization changes. > > v8: Edited commit message to be more clear about skl+, renamed > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > doesn't support per-pixel alpha. Fixed minor code issues. > > v9: Moved DRM format check to proper place in intel_framebuffer_init. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> I'm planning of sending a new version with my series[1], do you think this patch will get merged soon, or is there anything else that needs to be done. [1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html > --- > drivers/gpu/drm/drm_fourcc.c | 1 + > include/uapi/drm/drm_fourcc.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c > index be1d6aaef651..60752d0be9d8 100644 > --- a/drivers/gpu/drm/drm_fourcc.c > +++ b/drivers/gpu/drm/drm_fourcc.c > @@ -190,6 +190,7 @@ const struct drm_format_info *__drm_format_info(u32 format) > { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, > { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, > { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true }, > + { .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true }, > }; > > unsigned int i; > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index 139632b87181..88d2e491f40c 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -151,6 +151,7 @@ extern "C" { > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ > > /* > * 2 plane RGB + A > -- > 2.17.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Cheers, Alex G _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-02 15:28 ` Alexandru-Cosmin Gheorghe @ 2018-10-03 6:39 ` Lisovskiy, Stanislav 2018-10-03 8:07 ` Alexandru-Cosmin Gheorghe 0 siblings, 1 reply; 15+ messages in thread From: Lisovskiy, Stanislav @ 2018-10-03 6:39 UTC (permalink / raw) To: Alexandru-Cosmin.Gheorghe Cc: Syrjala, Ville, intel-gfx, Peres, Martin, dri-devel, Heikkila, Juha-pekka, nd On Tue, 2018-10-02 at 15:28 +0000, Alexandru-Cosmin Gheorghe wrote: > Hi, > > On Tue, Oct 02, 2018 at 02:15:42PM +0300, Stanislav Lisovskiy wrote: > > v5: This is YUV444 packed format same as AYUV, but without alpha, > > as supported by i915. > > > > v6: Removed unneeded initializer for new XYUV format. > > > > v7: Added is_yuv field initialization according to latest > > drm_fourcc format structure initialization changes. > > > > v8: Edited commit message to be more clear about skl+, renamed > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > v9: Moved DRM format check to proper place in > > intel_framebuffer_init. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> > > I'm planning of sending a new version with my series[1], do you think > this patch will get merged soon, or is there anything else that needs > to be done. > > [1] https://lists.freedesktop.org/archives/dri-devel/2018- > August/186963.html Hi, I had to implement IGT test case and xf86-video-intel support for this new format(in order to check that it works with gstreamer as we have userspace requirement for this change), so currently I guess all the requirements are met. I might need to do some minor changes in those patches though, once I get some feedback. > > > --- > > drivers/gpu/drm/drm_fourcc.c | 1 + > > include/uapi/drm/drm_fourcc.h | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_fourcc.c > > b/drivers/gpu/drm/drm_fourcc.c > > index be1d6aaef651..60752d0be9d8 100644 > > --- a/drivers/gpu/drm/drm_fourcc.c > > +++ b/drivers/gpu/drm/drm_fourcc.c > > @@ -190,6 +190,7 @@ const struct drm_format_info > > *__drm_format_info(u32 format) > > { .format = DRM_FORMAT_UYVY, .depth > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, > > .is_yuv = true }, > > { .format = DRM_FORMAT_VYUY, .depth > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, > > .is_yuv = true }, > > { .format = DRM_FORMAT_AYUV, .depth > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, > > .has_alpha = true, .is_yuv = true }, > > + { .format = DRM_FORMAT_XYUV, .depth > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, > > .is_yuv = true }, > > }; > > > > unsigned int i; > > diff --git a/include/uapi/drm/drm_fourcc.h > > b/include/uapi/drm/drm_fourcc.h > > index 139632b87181..88d2e491f40c 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -151,6 +151,7 @@ extern "C" { > > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', > > 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ > > > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', > > 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > > +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', > > 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ > > > > /* > > * 2 plane RGB + A > > -- > > 2.17.1 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- Best Regards, Lisovskiy Stanislav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-03 6:39 ` Lisovskiy, Stanislav @ 2018-10-03 8:07 ` Alexandru-Cosmin Gheorghe 2018-10-04 12:04 ` Lisovskiy, Stanislav 0 siblings, 1 reply; 15+ messages in thread From: Alexandru-Cosmin Gheorghe @ 2018-10-03 8:07 UTC (permalink / raw) To: Lisovskiy, Stanislav Cc: Syrjala, Ville, intel-gfx, Peres, Martin, dri-devel, Heikkila, Juha-pekka, nd On Wed, Oct 03, 2018 at 06:39:00AM +0000, Lisovskiy, Stanislav wrote: > On Tue, 2018-10-02 at 15:28 +0000, Alexandru-Cosmin Gheorghe wrote: > > Hi, > > > > On Tue, Oct 02, 2018 at 02:15:42PM +0300, Stanislav Lisovskiy wrote: > > > v5: This is YUV444 packed format same as AYUV, but without alpha, > > > as supported by i915. > > > > > > v6: Removed unneeded initializer for new XYUV format. > > > > > > v7: Added is_yuv field initialization according to latest > > > drm_fourcc format structure initialization changes. > > > > > > v8: Edited commit message to be more clear about skl+, renamed > > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > > > v9: Moved DRM format check to proper place in > > > intel_framebuffer_init. > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> > > > > I'm planning of sending a new version with my series[1], do you think > > this patch will get merged soon, or is there anything else that needs > > to be done. > > > > [1] https://lists.freedesktop.org/archives/dri-devel/2018- > > August/186963.html > > Hi, > > I had to implement IGT test case and xf86-video-intel support for this > new format(in order to check that it works with gstreamer as we have > userspace requirement for this change), so currently I guess all the > requirements are met. I might need to do some > minor changes in those patches though, once I get some feedback. A bit offtopic do we need userspace for adding a new fourcc as well, I thought those are extempted from "must have userspace rule". > > > > > > --- > > > drivers/gpu/drm/drm_fourcc.c | 1 + > > > include/uapi/drm/drm_fourcc.h | 1 + > > > 2 files changed, 2 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/drm_fourcc.c > > > b/drivers/gpu/drm/drm_fourcc.c > > > index be1d6aaef651..60752d0be9d8 100644 > > > --- a/drivers/gpu/drm/drm_fourcc.c > > > +++ b/drivers/gpu/drm/drm_fourcc.c > > > @@ -190,6 +190,7 @@ const struct drm_format_info > > > *__drm_format_info(u32 format) > > > { .format = DRM_FORMAT_UYVY, .depth > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, > > > .is_yuv = true }, > > > { .format = DRM_FORMAT_VYUY, .depth > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, > > > .is_yuv = true }, > > > { .format = DRM_FORMAT_AYUV, .depth > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, > > > .has_alpha = true, .is_yuv = true }, > > > + { .format = DRM_FORMAT_XYUV, .depth > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, > > > .is_yuv = true }, > > > }; > > > > > > unsigned int i; > > > diff --git a/include/uapi/drm/drm_fourcc.h > > > b/include/uapi/drm/drm_fourcc.h > > > index 139632b87181..88d2e491f40c 100644 > > > --- a/include/uapi/drm/drm_fourcc.h > > > +++ b/include/uapi/drm/drm_fourcc.h > > > @@ -151,6 +151,7 @@ extern "C" { > > > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', > > > 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ > > > > > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', > > > 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > > > +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', > > > 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ > > > > > > /* > > > * 2 plane RGB + A > > > -- > > > 2.17.1 > > > > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > > -- > Best Regards, > > Lisovskiy Stanislav -- Cheers, Alex G _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-03 8:07 ` Alexandru-Cosmin Gheorghe @ 2018-10-04 12:04 ` Lisovskiy, Stanislav 2018-10-04 12:25 ` Alexandru-Cosmin Gheorghe 0 siblings, 1 reply; 15+ messages in thread From: Lisovskiy, Stanislav @ 2018-10-04 12:04 UTC (permalink / raw) To: Alexandru-Cosmin.Gheorghe Cc: Syrjala, Ville, intel-gfx, Peres, Martin, dri-devel, Heikkila, Juha-pekka, nd On Wed, 2018-10-03 at 08:07 +0000, Alexandru-Cosmin Gheorghe wrote: > On Wed, Oct 03, 2018 at 06:39:00AM +0000, Lisovskiy, Stanislav wrote: > > On Tue, 2018-10-02 at 15:28 +0000, Alexandru-Cosmin Gheorghe wrote: > > > Hi, > > > > > > On Tue, Oct 02, 2018 at 02:15:42PM +0300, Stanislav Lisovskiy > > > wrote: > > > > v5: This is YUV444 packed format same as AYUV, but without > > > > alpha, > > > > as supported by i915. > > > > > > > > v6: Removed unneeded initializer for new XYUV format. > > > > > > > > v7: Added is_yuv field initialization according to latest > > > > drm_fourcc format structure initialization changes. > > > > > > > > v8: Edited commit message to be more clear about skl+, renamed > > > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this > > > > format > > > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > > > > > v9: Moved DRM format check to proper place in > > > > intel_framebuffer_init. > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.c > > > > om> > > > > > > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.co > > > m> > > > > > > I'm planning of sending a new version with my series[1], do you > > > think > > > this patch will get merged soon, or is there anything else that > > > needs > > > to be done. > > > > > > [1] https://lists.freedesktop.org/archives/dri-devel/2018- > > > August/186963.html > > > > Hi, > > > > I had to implement IGT test case and xf86-video-intel support for > > this > > new format(in order to check that it works with gstreamer as we > > have > > userspace requirement for this change), so currently I guess all > > the > > requirements are met. I might need to do some > > minor changes in those patches though, once I get some feedback. > > A bit offtopic do we need userspace for adding a new fourcc as well, > I thought those are extempted from "must have userspace rule". Well, at least in my case I was asked to do that. Interesting task though :) Currently I check with GStreamer, so that video works both in textured and sprite format. BTW, I have changed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV8888 so that it is compliant with your change. As I understood we've agreed to have it called that way instead of DRM_FORMAT_XYUV. Are you ok with that? I will then send a new patch for IGT, xf86-video-intel and drm today. > > > > > > > > > --- > > > > drivers/gpu/drm/drm_fourcc.c | 1 + > > > > include/uapi/drm/drm_fourcc.h | 1 + > > > > 2 files changed, 2 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/drm_fourcc.c > > > > b/drivers/gpu/drm/drm_fourcc.c > > > > index be1d6aaef651..60752d0be9d8 100644 > > > > --- a/drivers/gpu/drm/drm_fourcc.c > > > > +++ b/drivers/gpu/drm/drm_fourcc.c > > > > @@ -190,6 +190,7 @@ const struct drm_format_info > > > > *__drm_format_info(u32 format) > > > > { .format = DRM_FORMAT_UYVY, .d > > > > epth > > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = > > > > 1, > > > > .is_yuv = true }, > > > > { .format = DRM_FORMAT_VYUY, .d > > > > epth > > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = > > > > 1, > > > > .is_yuv = true }, > > > > { .format = DRM_FORMAT_AYUV, .d > > > > epth > > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = > > > > 1, > > > > .has_alpha = true, .is_yuv = true }, > > > > + { .format = DRM_FORMAT_XYUV, .d > > > > epth > > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = > > > > 1, > > > > .is_yuv = true }, > > > > }; > > > > > > > > unsigned int i; > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > > > b/include/uapi/drm/drm_fourcc.h > > > > index 139632b87181..88d2e491f40c 100644 > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > @@ -151,6 +151,7 @@ extern "C" { > > > > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', > > > > 'U', > > > > 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ > > > > > > > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', > > > > 'U', > > > > 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > > > > +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', > > > > 'U', > > > > 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ > > > > > > > > /* > > > > * 2 plane RGB + A > > > > -- > > > > 2.17.1 > > > > > > > > _______________________________________________ > > > > dri-devel mailing list > > > > dri-devel@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > > > > > > > -- > > Best Regards, > > > > Lisovskiy Stanislav > > -- Best Regards, Lisovskiy Stanislav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV 2018-10-04 12:04 ` Lisovskiy, Stanislav @ 2018-10-04 12:25 ` Alexandru-Cosmin Gheorghe 0 siblings, 0 replies; 15+ messages in thread From: Alexandru-Cosmin Gheorghe @ 2018-10-04 12:25 UTC (permalink / raw) To: Lisovskiy, Stanislav Cc: Syrjala, Ville, intel-gfx, Peres, Martin, dri-devel, Heikkila, Juha-pekka, nd On Thu, Oct 04, 2018 at 12:04:57PM +0000, Lisovskiy, Stanislav wrote: > On Wed, 2018-10-03 at 08:07 +0000, Alexandru-Cosmin Gheorghe wrote: > > On Wed, Oct 03, 2018 at 06:39:00AM +0000, Lisovskiy, Stanislav wrote: > > > On Tue, 2018-10-02 at 15:28 +0000, Alexandru-Cosmin Gheorghe wrote: > > > > Hi, > > > > > > > > On Tue, Oct 02, 2018 at 02:15:42PM +0300, Stanislav Lisovskiy > > > > wrote: > > > > > v5: This is YUV444 packed format same as AYUV, but without > > > > > alpha, > > > > > as supported by i915. > > > > > > > > > > v6: Removed unneeded initializer for new XYUV format. > > > > > > > > > > v7: Added is_yuv field initialization according to latest > > > > > drm_fourcc format structure initialization changes. > > > > > > > > > > v8: Edited commit message to be more clear about skl+, renamed > > > > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this > > > > > format > > > > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > > > > > > > v9: Moved DRM format check to proper place in > > > > > intel_framebuffer_init. > > > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.c > > > > > om> > > > > > > > > Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.co > > > > m> > > > > > > > > I'm planning of sending a new version with my series[1], do you > > > > think > > > > this patch will get merged soon, or is there anything else that > > > > needs > > > > to be done. > > > > > > > > [1] https://lists.freedesktop.org/archives/dri-devel/2018- > > > > August/186963.html > > > > > > Hi, > > > > > > I had to implement IGT test case and xf86-video-intel support for > > > this > > > new format(in order to check that it works with gstreamer as we > > > have > > > userspace requirement for this change), so currently I guess all > > > the > > > requirements are met. I might need to do some > > > minor changes in those patches though, once I get some feedback. > > > > A bit offtopic do we need userspace for adding a new fourcc as well, > > I thought those are extempted from "must have userspace rule". > > Well, at least in my case I was asked to do that. > Interesting task though :) > Currently I check with GStreamer, so that video works both in textured > and sprite format. > BTW, I have changed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV8888 so that it > is compliant with your change. As I understood we've agreed to have it > called that way instead of DRM_FORMAT_XYUV. Are you ok with that? > Yes DRM_FORMAT_XYUV8888, it's fine by me. Thanks. > I will then send a new patch for IGT, xf86-video-intel and drm today. > > > > > > > > > > > > > --- > > > > > drivers/gpu/drm/drm_fourcc.c | 1 + > > > > > include/uapi/drm/drm_fourcc.h | 1 + > > > > > 2 files changed, 2 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/drm_fourcc.c > > > > > b/drivers/gpu/drm/drm_fourcc.c > > > > > index be1d6aaef651..60752d0be9d8 100644 > > > > > --- a/drivers/gpu/drm/drm_fourcc.c > > > > > +++ b/drivers/gpu/drm/drm_fourcc.c > > > > > @@ -190,6 +190,7 @@ const struct drm_format_info > > > > > *__drm_format_info(u32 format) > > > > > { .format = DRM_FORMAT_UYVY, .d > > > > > epth > > > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = > > > > > 1, > > > > > .is_yuv = true }, > > > > > { .format = DRM_FORMAT_VYUY, .d > > > > > epth > > > > > = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = > > > > > 1, > > > > > .is_yuv = true }, > > > > > { .format = DRM_FORMAT_AYUV, .d > > > > > epth > > > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = > > > > > 1, > > > > > .has_alpha = true, .is_yuv = true }, > > > > > + { .format = DRM_FORMAT_XYUV, .d > > > > > epth > > > > > = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = > > > > > 1, > > > > > .is_yuv = true }, > > > > > }; > > > > > > > > > > unsigned int i; > > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > > > > b/include/uapi/drm/drm_fourcc.h > > > > > index 139632b87181..88d2e491f40c 100644 > > > > > --- a/include/uapi/drm/drm_fourcc.h > > > > > +++ b/include/uapi/drm/drm_fourcc.h > > > > > @@ -151,6 +151,7 @@ extern "C" { > > > > > #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', > > > > > 'U', > > > > > 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ > > > > > > > > > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', > > > > > 'U', > > > > > 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > > > > > +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', > > > > > 'U', > > > > > 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ > > > > > > > > > > /* > > > > > * 2 plane RGB + A > > > > > -- > > > > > 2.17.1 > > > > > > > > > > _______________________________________________ > > > > > dri-devel mailing list > > > > > dri-devel@lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > > > > > > > > > > > -- > > > Best Regards, > > > > > > Lisovskiy Stanislav > > > > > -- > Best Regards, > > Lisovskiy Stanislav -- Cheers, Alex G _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-10-02 11:15 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy 2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy @ 2018-10-02 11:15 ` Stanislav Lisovskiy 2018-10-23 11:39 ` Maarten Lankhorst 2018-10-02 11:42 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev7) Patchwork 2018-10-02 12:01 ` ✗ Fi.CI.BAT: failure " Patchwork 3 siblings, 1 reply; 15+ messages in thread From: Stanislav Lisovskiy @ 2018-10-02 11:15 UTC (permalink / raw) To: intel-gfx; +Cc: ville.syrjala, martin.peres, dri-devel, juha-pekka.heikkila PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification. v2: Edited commit message, removed redundant whitespaces. v3: Fixed fallthrough logic for the format switch cases. v4: Yet again fixed fallthrough logic, to reuse code from other case labels. v5: Started to use XYUV instead of AYUV, as we don't use alpha. v6: Removed unneeded initializer for new XYUV format. v7: Added scaling support for DRM_FORMAT_XYUV v8: Edited commit message to be more clear about skl+, renamed PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format doesn't support per-pixel alpha. Fixed minor code issues. v9: Moved DRM format check to proper place in intel_framebuffer_init. v10: Added missing XYUV format to sprite planes for skl+. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bc8e730ee1..ac24ac4b1d51 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6501,7 +6501,7 @@ enum { #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) -#define PLANE_CTL_FORMAT_AYUV (8 << 24) +#define PLANE_CTL_FORMAT_XYUV (8 << 24) #define PLANE_CTL_FORMAT_INDEXED (12 << 24) #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b2bab57cd113..b11f71b306a3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, }; static const uint32_t skl_pri_planar_formats[] = { @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, DRM_FORMAT_NV12, }; @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_XYUV: + return DRM_FORMAT_XYUV; default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) { @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_XRGB_2101010; case DRM_FORMAT_XBGR2101010: return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; + case DRM_FORMAT_XYUV: + return PLANE_CTL_FORMAT_XYUV; case DRM_FORMAT_YUYV: return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; case DRM_FORMAT_YVYU: @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */ @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err; } break; + case DRM_FORMAT_XYUV: + if (INTEL_GEN(dev_priv) < 9) { + DRM_DEBUG_KMS("unsupported pixel format: %s\n", + drm_get_format_name(mode_cmd->pixel_format, &format_name)); + goto err; + } + break; case DRM_FORMAT_YUYV: case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9600ccfc5b76..54f74a55e3fb 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, }; static uint32_t skl_planar_formats[] = { @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = { DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_NV12, + DRM_FORMAT_XYUV, }; static const uint64_t skl_plane_format_modifiers_noccs[] = { @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */ -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-10-02 11:15 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy @ 2018-10-23 11:39 ` Maarten Lankhorst 2018-10-23 11:55 ` Lisovskiy, Stanislav 2018-10-24 17:17 ` Matt Roper 0 siblings, 2 replies; 15+ messages in thread From: Maarten Lankhorst @ 2018-10-23 11:39 UTC (permalink / raw) To: Stanislav Lisovskiy, intel-gfx Cc: ville.syrjala, martin.peres, dri-devel, juha-pekka.heikkila Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy: > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware > specification. > > v2: Edited commit message, removed redundant whitespaces. > > v3: Fixed fallthrough logic for the format switch cases. > > v4: Yet again fixed fallthrough logic, to reuse code from other case > labels. > > v5: Started to use XYUV instead of AYUV, as we don't use alpha. > > v6: Removed unneeded initializer for new XYUV format. > > v7: Added scaling support for DRM_FORMAT_XYUV > > v8: Edited commit message to be more clear about skl+, renamed > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > doesn't support per-pixel alpha. Fixed minor code issues. > > v9: Moved DRM format check to proper place in intel_framebuffer_init. > > v10: Added missing XYUV format to sprite planes for skl+. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/intel_sprite.c | 3 +++ > 3 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 09bc8e730ee1..ac24ac4b1d51 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6501,7 +6501,7 @@ enum { > #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) > #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) > #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) > -#define PLANE_CTL_FORMAT_AYUV (8 << 24) > +#define PLANE_CTL_FORMAT_XYUV (8 << 24) It's the same format as AYUV, don't add a separate definition here for it. The only difference is we ignore the alpha channel. > #define PLANE_CTL_FORMAT_INDEXED (12 << 24) > #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) > #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b2bab57cd113..b11f71b306a3 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = { > DRM_FORMAT_YVYU, > DRM_FORMAT_UYVY, > DRM_FORMAT_VYUY, > + DRM_FORMAT_XYUV, > }; > > static const uint32_t skl_pri_planar_formats[] = { > @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = { > DRM_FORMAT_YVYU, > DRM_FORMAT_UYVY, > DRM_FORMAT_VYUY, > + DRM_FORMAT_XYUV, > DRM_FORMAT_NV12, I would add AYUV as well, only difference is blending mode used by the alpha channel.. > }; > > @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) > return DRM_FORMAT_RGB565; > case PLANE_CTL_FORMAT_NV12: > return DRM_FORMAT_NV12; > + case PLANE_CTL_FORMAT_XYUV: > + return DRM_FORMAT_XYUV; Use PLANE_CTL_FORMAT_AYUV here. return alpha ? DRM_FORMAT_AYUV : DRM_FORMAT_XYUV8888. > default: > case PLANE_CTL_FORMAT_XRGB_8888: > if (rgb_order) { > @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) > return PLANE_CTL_FORMAT_XRGB_2101010; > case DRM_FORMAT_XBGR2101010: > return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; > + case DRM_FORMAT_XYUV: > + return PLANE_CTL_FORMAT_XYUV; > case DRM_FORMAT_YUYV: > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; > case DRM_FORMAT_YVYU: > @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, > case DRM_FORMAT_UYVY: > case DRM_FORMAT_VYUY: > case DRM_FORMAT_NV12: > + case DRM_FORMAT_XYUV: > break; > default: > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", > @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_UYVY: > case DRM_FORMAT_VYUY: > case DRM_FORMAT_NV12: > + case DRM_FORMAT_XYUV: > if (modifier == I915_FORMAT_MOD_Yf_TILED) > return true; > /* fall through */ > @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > goto err; > } > break; > + case DRM_FORMAT_XYUV: > + if (INTEL_GEN(dev_priv) < 9) { > + DRM_DEBUG_KMS("unsupported pixel format: %s\n", > + drm_get_format_name(mode_cmd->pixel_format, &format_name)); > + goto err; > + } > + break; > case DRM_FORMAT_YUYV: > case DRM_FORMAT_UYVY: > case DRM_FORMAT_YVYU: > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 9600ccfc5b76..54f74a55e3fb 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = { > DRM_FORMAT_YVYU, > DRM_FORMAT_UYVY, > DRM_FORMAT_VYUY, > + DRM_FORMAT_XYUV, > }; > > static uint32_t skl_planar_formats[] = { > @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = { > DRM_FORMAT_UYVY, > DRM_FORMAT_VYUY, > DRM_FORMAT_NV12, > + DRM_FORMAT_XYUV, > }; > > static const uint64_t skl_plane_format_modifiers_noccs[] = { > @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_UYVY: > case DRM_FORMAT_VYUY: > case DRM_FORMAT_NV12: > + case DRM_FORMAT_XYUV: > if (modifier == I915_FORMAT_MOD_Yf_TILED) > return true; > /* fall through */ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-10-23 11:39 ` Maarten Lankhorst @ 2018-10-23 11:55 ` Lisovskiy, Stanislav 2018-10-24 17:17 ` Matt Roper 1 sibling, 0 replies; 15+ messages in thread From: Lisovskiy, Stanislav @ 2018-10-23 11:55 UTC (permalink / raw) To: intel-gfx, maarten.lankhorst Cc: Syrjala, Ville, Heikkila, Juha-pekka, dri-devel, Peres, Martin On Tue, 2018-10-23 at 13:39 +0200, Maarten Lankhorst wrote: > > Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy: > > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware > > specification. > > > > v2: Edited commit message, removed redundant whitespaces. > > > > v3: Fixed fallthrough logic for the format switch cases. > > > > v4: Yet again fixed fallthrough logic, to reuse code from other > > case > > labels. > > > > v5: Started to use XYUV instead of AYUV, as we don't use alpha. > > > > v6: Removed unneeded initializer for new XYUV format. > > > > v7: Added scaling support for DRM_FORMAT_XYUV > > > > v8: Edited commit message to be more clear about skl+, renamed > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > v9: Moved DRM format check to proper place in > > intel_framebuffer_init. > > > > v10: Added missing XYUV format to sprite planes for skl+. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 +- > > drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ > > drivers/gpu/drm/i915/intel_sprite.c | 3 +++ > > 3 files changed, 19 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 09bc8e730ee1..ac24ac4b1d51 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6501,7 +6501,7 @@ enum { > > #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) > > #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) > > #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) > > -#define PLANE_CTL_FORMAT_AYUV (8 << 24) > > +#define PLANE_CTL_FORMAT_XYUV (8 << 24) > > It's the same format as AYUV, don't add a separate definition here > for it. > The only difference is we ignore the alpha channel. Yeah, initially it was that way in my first patches, but then we agreed with Ville that it might make more sense to change it to XYUV as it doesn't have alpha. So probably we should work on some common approach here(personally I'm fine with both). > > #define PLANE_CTL_FORMAT_INDEXED (12 << 24) > > #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) > > #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index b2bab57cd113..b11f71b306a3 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > }; > > > > static const uint32_t skl_pri_planar_formats[] = { > > @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] > > = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > DRM_FORMAT_NV12, > > I would add AYUV as well, only difference is blending mode used by > the alpha channel.. > > }; > > > > @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool > > rgb_order, bool alpha) > > return DRM_FORMAT_RGB565; > > case PLANE_CTL_FORMAT_NV12: > > return DRM_FORMAT_NV12; > > + case PLANE_CTL_FORMAT_XYUV: > > + return DRM_FORMAT_XYUV; > > Use PLANE_CTL_FORMAT_AYUV here. > return alpha ? DRM_FORMAT_AYUV : DRM_FORMAT_XYUV8888. > > > > default: > > case PLANE_CTL_FORMAT_XRGB_8888: > > if (rgb_order) { > > @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t > > pixel_format) > > return PLANE_CTL_FORMAT_XRGB_2101010; > > case DRM_FORMAT_XBGR2101010: > > return PLANE_CTL_ORDER_RGBX | > > PLANE_CTL_FORMAT_XRGB_2101010; > > + case DRM_FORMAT_XYUV: > > + return PLANE_CTL_FORMAT_XYUV; > > case DRM_FORMAT_YUYV: > > return PLANE_CTL_FORMAT_YUV422 | > > PLANE_CTL_YUV422_YUYV; > > case DRM_FORMAT_YVYU: > > @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct > > intel_crtc_state *crtc_state, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > break; > > default: > > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported > > scaling format 0x%x\n", > > @@ -13421,6 +13428,7 @@ static bool > > skl_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > if (modifier == I915_FORMAT_MOD_Yf_TILED) > > return true; > > /* fall through */ > > @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct > > intel_framebuffer *intel_fb, > > goto err; > > } > > break; > > + case DRM_FORMAT_XYUV: > > + if (INTEL_GEN(dev_priv) < 9) { > > + DRM_DEBUG_KMS("unsupported pixel format: > > %s\n", > > + drm_get_format_name(mode_cmd > > ->pixel_format, &format_name)); > > + goto err; > > + } > > + break; > > case DRM_FORMAT_YUYV: > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_YVYU: > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c > > b/drivers/gpu/drm/i915/intel_sprite.c > > index 9600ccfc5b76..54f74a55e3fb 100644 > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > }; > > > > static uint32_t skl_planar_formats[] = { > > @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = { > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > DRM_FORMAT_NV12, > > + DRM_FORMAT_XYUV, > > }; > > > > static const uint64_t skl_plane_format_modifiers_noccs[] = { > > @@ -1420,6 +1422,7 @@ static bool > > skl_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > if (modifier == I915_FORMAT_MOD_Yf_TILED) > > return true; > > /* fall through */ > > -- Best Regards, Lisovskiy Stanislav _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-10-23 11:39 ` Maarten Lankhorst 2018-10-23 11:55 ` Lisovskiy, Stanislav @ 2018-10-24 17:17 ` Matt Roper 2018-10-25 6:21 ` Maarten Lankhorst 1 sibling, 1 reply; 15+ messages in thread From: Matt Roper @ 2018-10-24 17:17 UTC (permalink / raw) To: Maarten Lankhorst Cc: ville.syrjala, intel-gfx, martin.peres, dri-devel, juha-pekka.heikkila On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote: > > > Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy: > > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware > > specification. > > > > v2: Edited commit message, removed redundant whitespaces. > > > > v3: Fixed fallthrough logic for the format switch cases. > > > > v4: Yet again fixed fallthrough logic, to reuse code from other case > > labels. > > > > v5: Started to use XYUV instead of AYUV, as we don't use alpha. > > > > v6: Removed unneeded initializer for new XYUV format. > > > > v7: Added scaling support for DRM_FORMAT_XYUV > > > > v8: Edited commit message to be more clear about skl+, renamed > > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format > > doesn't support per-pixel alpha. Fixed minor code issues. > > > > v9: Moved DRM format check to proper place in intel_framebuffer_init. > > > > v10: Added missing XYUV format to sprite planes for skl+. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 +- > > drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ > > drivers/gpu/drm/i915/intel_sprite.c | 3 +++ > > 3 files changed, 19 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 09bc8e730ee1..ac24ac4b1d51 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6501,7 +6501,7 @@ enum { > > #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) > > #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) > > #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) > > -#define PLANE_CTL_FORMAT_AYUV (8 << 24) > > +#define PLANE_CTL_FORMAT_XYUV (8 << 24) > It's the same format as AYUV, don't add a separate definition here for it. > The only difference is we ignore the alpha channel. I think he's just renaming the format that's already been added to be more consistent with how we name our other PLANE_CTL_FORMAT_ definitions. I.e., all the rgb types use "XRGB" in the name. > > #define PLANE_CTL_FORMAT_INDEXED (12 << 24) > > #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) > > #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index b2bab57cd113..b11f71b306a3 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > }; > > > > static const uint32_t skl_pri_planar_formats[] = { > > @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > DRM_FORMAT_NV12, > I would add AYUV as well, only difference is blending mode used by the alpha channel.. According to the bspec's "Display Features / Surface Formats" matrix, per-pixel alpha isn't supported for this format (and the PLANE_CTL/PLANE_COLOR_CTL descriptions seem to agree that alpha is only supported for RGB formats), so I don't think we want to expose the alpha version of this format in the userspace-visible format lists. Matt > > }; > > > > @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) > > return DRM_FORMAT_RGB565; > > case PLANE_CTL_FORMAT_NV12: > > return DRM_FORMAT_NV12; > > + case PLANE_CTL_FORMAT_XYUV: > > + return DRM_FORMAT_XYUV; > Use PLANE_CTL_FORMAT_AYUV here. > return alpha ? DRM_FORMAT_AYUV : DRM_FORMAT_XYUV8888. > > > > default: > > case PLANE_CTL_FORMAT_XRGB_8888: > > if (rgb_order) { > > @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) > > return PLANE_CTL_FORMAT_XRGB_2101010; > > case DRM_FORMAT_XBGR2101010: > > return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; > > + case DRM_FORMAT_XYUV: > > + return PLANE_CTL_FORMAT_XYUV; > > case DRM_FORMAT_YUYV: > > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; > > case DRM_FORMAT_YVYU: > > @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > break; > > default: > > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", > > @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > if (modifier == I915_FORMAT_MOD_Yf_TILED) > > return true; > > /* fall through */ > > @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > > goto err; > > } > > break; > > + case DRM_FORMAT_XYUV: > > + if (INTEL_GEN(dev_priv) < 9) { > > + DRM_DEBUG_KMS("unsupported pixel format: %s\n", > > + drm_get_format_name(mode_cmd->pixel_format, &format_name)); > > + goto err; > > + } > > + break; > > case DRM_FORMAT_YUYV: > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_YVYU: > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > > index 9600ccfc5b76..54f74a55e3fb 100644 > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = { > > DRM_FORMAT_YVYU, > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > + DRM_FORMAT_XYUV, > > }; > > > > static uint32_t skl_planar_formats[] = { > > @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = { > > DRM_FORMAT_UYVY, > > DRM_FORMAT_VYUY, > > DRM_FORMAT_NV12, > > + DRM_FORMAT_XYUV, > > }; > > > > static const uint64_t skl_plane_format_modifiers_noccs[] = { > > @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_UYVY: > > case DRM_FORMAT_VYUY: > > case DRM_FORMAT_NV12: > > + case DRM_FORMAT_XYUV: > > if (modifier == I915_FORMAT_MOD_Yf_TILED) > > return true; > > /* fall through */ > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-10-24 17:17 ` Matt Roper @ 2018-10-25 6:21 ` Maarten Lankhorst 0 siblings, 0 replies; 15+ messages in thread From: Maarten Lankhorst @ 2018-10-25 6:21 UTC (permalink / raw) To: Matt Roper Cc: ville.syrjala, intel-gfx, martin.peres, dri-devel, juha-pekka.heikkila Op 24-10-18 om 19:17 schreef Matt Roper: > On Tue, Oct 23, 2018 at 01:39:10PM +0200, Maarten Lankhorst wrote: >> >> Op 02-10-18 om 13:15 schreef Stanislav Lisovskiy: >>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware >>> specification. >>> >>> v2: Edited commit message, removed redundant whitespaces. >>> >>> v3: Fixed fallthrough logic for the format switch cases. >>> >>> v4: Yet again fixed fallthrough logic, to reuse code from other case >>> labels. >>> >>> v5: Started to use XYUV instead of AYUV, as we don't use alpha. >>> >>> v6: Removed unneeded initializer for new XYUV format. >>> >>> v7: Added scaling support for DRM_FORMAT_XYUV >>> >>> v8: Edited commit message to be more clear about skl+, renamed >>> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format >>> doesn't support per-pixel alpha. Fixed minor code issues. >>> >>> v9: Moved DRM format check to proper place in intel_framebuffer_init. >>> >>> v10: Added missing XYUV format to sprite planes for skl+. >>> >>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_reg.h | 2 +- >>> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ >>> drivers/gpu/drm/i915/intel_sprite.c | 3 +++ >>> 3 files changed, 19 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >>> index 09bc8e730ee1..ac24ac4b1d51 100644 >>> --- a/drivers/gpu/drm/i915/i915_reg.h >>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>> @@ -6501,7 +6501,7 @@ enum { >>> #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) >>> #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) >>> #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) >>> -#define PLANE_CTL_FORMAT_AYUV (8 << 24) >>> +#define PLANE_CTL_FORMAT_XYUV (8 << 24) >> It's the same format as AYUV, don't add a separate definition here for it. >> The only difference is we ignore the alpha channel. > I think he's just renaming the format that's already been added to be > more consistent with how we name our other PLANE_CTL_FORMAT_ > definitions. I.e., all the rgb types use "XRGB" in the name. > Ah k, with your explanation it makes more sense then. :) Yeah just zap the AYUV if there's no alpha channel. ~Maarten _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev7) 2018-10-02 11:15 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy 2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy 2018-10-02 11:15 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy @ 2018-10-02 11:42 ` Patchwork 2018-10-02 12:01 ` ✗ Fi.CI.BAT: failure " Patchwork 3 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2018-10-02 11:42 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: Add XYUV format support (rev7) URL : https://patchwork.freedesktop.org/series/48007/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7ef74de686fe drm: Introduce new DRM_FORMAT_XYUV -:30: WARNING:LONG_LINE: line over 100 characters #30: FILE: drivers/gpu/drm/drm_fourcc.c:228: + { .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true }, -:42: WARNING:LONG_LINE_COMMENT: line over 100 characters #42: FILE: include/uapi/drm/drm_fourcc.h:154: +#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ total: 0 errors, 2 warnings, 0 checks, 14 lines checked bb1a2cba6c59 drm/i915: Adding YUV444 packed format support for skl+ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: failure for Add XYUV format support (rev7) 2018-10-02 11:15 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy ` (2 preceding siblings ...) 2018-10-02 11:42 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev7) Patchwork @ 2018-10-02 12:01 ` Patchwork 3 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2018-10-02 12:01 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: Add XYUV format support (rev7) URL : https://patchwork.freedesktop.org/series/48007/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4914 -> Patchwork_10322 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10322 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10322, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/7/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10322: === IGT changes === ==== Possible regressions ==== igt@gem_exec_basic@gtt-bsd1: fi-pnv-d510: NOTRUN -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10322 that come from known issues: === IGT changes === ==== Issues hit ==== igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) ==== Possible fixes ==== igt@amdgpu/amd_cs_nop@fork-gfx0: fi-kbl-8809g: DMESG-WARN (fdo#107762) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-skl-guc: FAIL (fdo#103191) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107762 https://bugs.freedesktop.org/show_bug.cgi?id=107762 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 == Participating hosts (44 -> 43) == Additional (2): fi-bdw-samus fi-pnv-d510 Missing (3): fi-bsw-cyan fi-byt-squawks fi-icl-u2 == Build changes == * Linux: CI_DRM_4914 -> Patchwork_10322 CI_DRM_4914: 7bb6a990d5bfa66c62bbdb97ae74c1ce5c828a19 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4660: d0975646c50568e66e65b44b81d28232d059b94e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10322: bb1a2cba6c5960f4ef4e2a444ec731f97c42d8a7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb1a2cba6c59 drm/i915: Adding YUV444 packed format support for skl+ 7ef74de686fe drm: Introduce new DRM_FORMAT_XYUV == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10322/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v10 0/2] Add XYUV format support @ 2018-09-07 8:45 Stanislav Lisovskiy 2018-09-07 8:45 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy 0 siblings, 1 reply; 15+ messages in thread From: Stanislav Lisovskiy @ 2018-09-07 8:45 UTC (permalink / raw) To: intel-gfx; +Cc: stanislav.lisovskiy, ville.syrjala, dri-devel Introduced new XYUV scan-in format for framebuffer and added support for it to i915(SkyLake+). Stanislav Lisovskiy (2): drm: Introduce new DRM_FORMAT_XYUV drm/i915: Adding YUV444 packed format support for skl+ drivers/gpu/drm/drm_fourcc.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 2 ++ include/uapi/drm/drm_fourcc.h | 1 + 5 files changed, 20 insertions(+), 1 deletion(-) -- 2.17.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ 2018-09-07 8:45 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy @ 2018-09-07 8:45 ` Stanislav Lisovskiy 0 siblings, 0 replies; 15+ messages in thread From: Stanislav Lisovskiy @ 2018-09-07 8:45 UTC (permalink / raw) To: intel-gfx; +Cc: stanislav.lisovskiy, ville.syrjala, dri-devel PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification. v2: Edited commit message, removed redundant whitespaces. v3: Fixed fallthrough logic for the format switch cases. v4: Yet again fixed fallthrough logic, to reuse code from other case labels. v5: Started to use XYUV instead of AYUV, as we don't use alpha. v6: Removed unneeded initializer for new XYUV format. v7: Added scaling support for DRM_FORMAT_XYUV v8: Edited commit message to be more clear about skl+, renamed PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format doesn't support per-pixel alpha. Fixed minor code issues. v9: Moved DRM format check to proper place in intel_framebuffer_init. v10: Added missing XYUV format to sprite planes for skl+. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 2 ++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8534f88a60f6..e0c8480aaa02 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6499,7 +6499,7 @@ enum { #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) -#define PLANE_CTL_FORMAT_AYUV (8 << 24) +#define PLANE_CTL_FORMAT_XYUV (8 << 24) #define PLANE_CTL_FORMAT_INDEXED (12 << 24) #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 30fdfd1a3037..9323708db71f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, }; static const uint32_t skl_pri_planar_formats[] = { @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, DRM_FORMAT_NV12, }; @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) return DRM_FORMAT_RGB565; case PLANE_CTL_FORMAT_NV12: return DRM_FORMAT_NV12; + case PLANE_CTL_FORMAT_XYUV: + return DRM_FORMAT_XYUV; default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) { @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_XRGB_2101010; case DRM_FORMAT_XBGR2101010: return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; + case DRM_FORMAT_XYUV: + return PLANE_CTL_FORMAT_XYUV; case DRM_FORMAT_YUYV: return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; case DRM_FORMAT_YVYU: @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */ @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err; } break; + case DRM_FORMAT_XYUV: + if (INTEL_GEN(dev_priv) < 9) { + DRM_DEBUG_KMS("unsupported pixel format: %s\n", + drm_get_format_name(mode_cmd->pixel_format, &format_name)); + goto err; + } + break; case DRM_FORMAT_YUYV: case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index c286dda625e4..5c3931d2c557 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_YVYU, DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + DRM_FORMAT_XYUV, }; static uint32_t skl_planar_formats[] = { @@ -1420,6 +1421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_XYUV: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; /* fall through */ -- 2.17.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-10-25 6:21 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-10-02 11:15 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy 2018-10-02 11:15 ` [PATCH v10 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy 2018-10-02 15:28 ` Alexandru-Cosmin Gheorghe 2018-10-03 6:39 ` Lisovskiy, Stanislav 2018-10-03 8:07 ` Alexandru-Cosmin Gheorghe 2018-10-04 12:04 ` Lisovskiy, Stanislav 2018-10-04 12:25 ` Alexandru-Cosmin Gheorghe 2018-10-02 11:15 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy 2018-10-23 11:39 ` Maarten Lankhorst 2018-10-23 11:55 ` Lisovskiy, Stanislav 2018-10-24 17:17 ` Matt Roper 2018-10-25 6:21 ` Maarten Lankhorst 2018-10-02 11:42 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev7) Patchwork 2018-10-02 12:01 ` ✗ Fi.CI.BAT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2018-09-07 8:45 [PATCH v10 0/2] Add XYUV format support Stanislav Lisovskiy 2018-09-07 8:45 ` [PATCH v10 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
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