* [PATCH v3 1/2] powerpc/32s: automatically allocate BAT in setbat() @ 2019-09-16 20:25 ` Christophe Leroy 0 siblings, 0 replies; 7+ messages in thread From: Christophe Leroy @ 2019-09-16 20:25 UTC (permalink / raw) To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, oss, galak Cc: linux-kernel, linuxppc-dev If no BAT is given to setbat(), select an available BAT. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- v2: no change v3: no change --- arch/powerpc/mm/book3s32/mmu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c index 84d5fab94f8f..69b2419accef 100644 --- a/arch/powerpc/mm/book3s32/mmu.c +++ b/arch/powerpc/mm/book3s32/mmu.c @@ -251,9 +251,18 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys, { unsigned int bl; int wimgxpp; - struct ppc_bat *bat = BATS[index]; + struct ppc_bat *bat; unsigned long flags = pgprot_val(prot); + if (index == -1) + index = find_free_bat(); + if (index == -1) { + pr_err("%s: no BAT available for mapping 0x%llx\n", __func__, + (unsigned long long)phys); + return; + } + bat = BATS[index]; + if ((flags & _PAGE_NO_CACHE) || (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0)) flags &= ~_PAGE_COHERENT; -- 2.13.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 1/2] powerpc/32s: automatically allocate BAT in setbat() @ 2019-09-16 20:25 ` Christophe Leroy 0 siblings, 0 replies; 7+ messages in thread From: Christophe Leroy @ 2019-09-16 20:25 UTC (permalink / raw) To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, oss, galak Cc: linuxppc-dev, linux-kernel If no BAT is given to setbat(), select an available BAT. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- v2: no change v3: no change --- arch/powerpc/mm/book3s32/mmu.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c index 84d5fab94f8f..69b2419accef 100644 --- a/arch/powerpc/mm/book3s32/mmu.c +++ b/arch/powerpc/mm/book3s32/mmu.c @@ -251,9 +251,18 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys, { unsigned int bl; int wimgxpp; - struct ppc_bat *bat = BATS[index]; + struct ppc_bat *bat; unsigned long flags = pgprot_val(prot); + if (index == -1) + index = find_free_bat(); + if (index == -1) { + pr_err("%s: no BAT available for mapping 0x%llx\n", __func__, + (unsigned long long)phys); + return; + } + bat = BATS[index]; + if ((flags & _PAGE_NO_CACHE) || (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0)) flags &= ~_PAGE_COHERENT; -- 2.13.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/2] powerpc/83xx: map IMMR with a BAT. 2019-09-16 20:25 ` Christophe Leroy @ 2019-09-16 20:25 ` Christophe Leroy -1 siblings, 0 replies; 7+ messages in thread From: Christophe Leroy @ 2019-09-16 20:25 UTC (permalink / raw) To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, oss, galak Cc: linux-kernel, linuxppc-dev On mpc83xx with a QE, IMMR is 2Mbytes and aligned on 2Mbytes boundarie. On mpc83xx without a QE, IMMR is 1Mbyte and 1Mbyte aligned. Each driver will map a part of it to access the registers it needs. Some drivers will map the same part of IMMR as other drivers. In order to reduce TLB misses, map the full IMMR with a BAT. If it is 2Mbytes aligned, map 2Mbytes. If there is no QE, the upper part will remain unused, but it doesn't harm as it is mapped as guarded memory. When the IMMR is not aligned on a 2Mbytes boundarie, only map 1Mbyte. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- v2: - use a fixmap area instead of playing with ioremap_bot - always map 2M unless IMMRBAR is only 1M aligned v3: - replaced __fix_to_virt() by fix_to_virt() --- arch/powerpc/include/asm/fixmap.h | 8 ++++++++ arch/powerpc/platforms/83xx/misc.c | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h index 0cfc365d814b..79c3aa55f43d 100644 --- a/arch/powerpc/include/asm/fixmap.h +++ b/arch/powerpc/include/asm/fixmap.h @@ -15,6 +15,7 @@ #define _ASM_FIXMAP_H #ifndef __ASSEMBLY__ +#include <linux/sizes.h> #include <asm/page.h> #include <asm/pgtable.h> #ifdef CONFIG_HIGHMEM @@ -63,6 +64,13 @@ enum fixed_addresses { FIX_IMMR_BASE = __ALIGN_MASK(FIX_IMMR_START, FIX_IMMR_SIZE - 1) - 1 + FIX_IMMR_SIZE, #endif +#ifdef CONFIG_PPC_83xx + /* For IMMR we need an aligned 2M area */ +#define FIX_IMMR_SIZE (SZ_2M / PAGE_SIZE) + FIX_IMMR_START, + FIX_IMMR_BASE = __ALIGN_MASK(FIX_IMMR_START, FIX_IMMR_SIZE - 1) - 1 + + FIX_IMMR_SIZE, +#endif /* FIX_PCIE_MCFG, */ __end_of_fixed_addresses }; diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index f46d7bf3b140..6399865a625e 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -18,6 +18,8 @@ #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> +#include <mm/mmu_decl.h> + #include "mpc83xx.h" static __be32 __iomem *restart_reg_base; @@ -145,6 +147,15 @@ void __init mpc83xx_setup_arch(void) if (ppc_md.progress) ppc_md.progress("mpc83xx_setup_arch()", 0); + if (!__map_without_bats) { + phys_addr_t immrbase = get_immrbase(); + int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M; + unsigned long va = fix_to_virt(FIX_IMMR_BASE); + + setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG); + update_bats(); + } + mpc83xx_setup_pci(); } -- 2.13.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 2/2] powerpc/83xx: map IMMR with a BAT. @ 2019-09-16 20:25 ` Christophe Leroy 0 siblings, 0 replies; 7+ messages in thread From: Christophe Leroy @ 2019-09-16 20:25 UTC (permalink / raw) To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, oss, galak Cc: linuxppc-dev, linux-kernel On mpc83xx with a QE, IMMR is 2Mbytes and aligned on 2Mbytes boundarie. On mpc83xx without a QE, IMMR is 1Mbyte and 1Mbyte aligned. Each driver will map a part of it to access the registers it needs. Some drivers will map the same part of IMMR as other drivers. In order to reduce TLB misses, map the full IMMR with a BAT. If it is 2Mbytes aligned, map 2Mbytes. If there is no QE, the upper part will remain unused, but it doesn't harm as it is mapped as guarded memory. When the IMMR is not aligned on a 2Mbytes boundarie, only map 1Mbyte. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- v2: - use a fixmap area instead of playing with ioremap_bot - always map 2M unless IMMRBAR is only 1M aligned v3: - replaced __fix_to_virt() by fix_to_virt() --- arch/powerpc/include/asm/fixmap.h | 8 ++++++++ arch/powerpc/platforms/83xx/misc.c | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h index 0cfc365d814b..79c3aa55f43d 100644 --- a/arch/powerpc/include/asm/fixmap.h +++ b/arch/powerpc/include/asm/fixmap.h @@ -15,6 +15,7 @@ #define _ASM_FIXMAP_H #ifndef __ASSEMBLY__ +#include <linux/sizes.h> #include <asm/page.h> #include <asm/pgtable.h> #ifdef CONFIG_HIGHMEM @@ -63,6 +64,13 @@ enum fixed_addresses { FIX_IMMR_BASE = __ALIGN_MASK(FIX_IMMR_START, FIX_IMMR_SIZE - 1) - 1 + FIX_IMMR_SIZE, #endif +#ifdef CONFIG_PPC_83xx + /* For IMMR we need an aligned 2M area */ +#define FIX_IMMR_SIZE (SZ_2M / PAGE_SIZE) + FIX_IMMR_START, + FIX_IMMR_BASE = __ALIGN_MASK(FIX_IMMR_START, FIX_IMMR_SIZE - 1) - 1 + + FIX_IMMR_SIZE, +#endif /* FIX_PCIE_MCFG, */ __end_of_fixed_addresses }; diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c index f46d7bf3b140..6399865a625e 100644 --- a/arch/powerpc/platforms/83xx/misc.c +++ b/arch/powerpc/platforms/83xx/misc.c @@ -18,6 +18,8 @@ #include <sysdev/fsl_soc.h> #include <sysdev/fsl_pci.h> +#include <mm/mmu_decl.h> + #include "mpc83xx.h" static __be32 __iomem *restart_reg_base; @@ -145,6 +147,15 @@ void __init mpc83xx_setup_arch(void) if (ppc_md.progress) ppc_md.progress("mpc83xx_setup_arch()", 0); + if (!__map_without_bats) { + phys_addr_t immrbase = get_immrbase(); + int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M; + unsigned long va = fix_to_virt(FIX_IMMR_BASE); + + setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG); + update_bats(); + } + mpc83xx_setup_pci(); } -- 2.13.3 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/2] powerpc/83xx: map IMMR with a BAT. 2019-09-16 20:25 ` Christophe Leroy @ 2019-09-16 20:36 ` Scott Wood -1 siblings, 0 replies; 7+ messages in thread From: Scott Wood @ 2019-09-16 20:36 UTC (permalink / raw) To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, galak Cc: linux-kernel, linuxppc-dev On Mon, 2019-09-16 at 20:25 +0000, Christophe Leroy wrote: > On mpc83xx with a QE, IMMR is 2Mbytes and aligned on 2Mbytes boundarie. > On mpc83xx without a QE, IMMR is 1Mbyte and 1Mbyte aligned. > > Each driver will map a part of it to access the registers it needs. > Some drivers will map the same part of IMMR as other drivers. > > In order to reduce TLB misses, map the full IMMR with a BAT. If it is > 2Mbytes aligned, map 2Mbytes. If there is no QE, the upper part will > remain unused, but it doesn't harm as it is mapped as guarded memory. > > When the IMMR is not aligned on a 2Mbytes boundarie, only map 1Mbyte. > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > > --- > v2: > - use a fixmap area instead of playing with ioremap_bot > - always map 2M unless IMMRBAR is only 1M aligned > > v3: > - replaced __fix_to_virt() by fix_to_virt() > --- > arch/powerpc/include/asm/fixmap.h | 8 ++++++++ > arch/powerpc/platforms/83xx/misc.c | 11 +++++++++++ > 2 files changed, 19 insertions(+) Acked-by: Scott Wood <oss@buserror.net> -Scott ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/2] powerpc/83xx: map IMMR with a BAT. @ 2019-09-16 20:36 ` Scott Wood 0 siblings, 0 replies; 7+ messages in thread From: Scott Wood @ 2019-09-16 20:36 UTC (permalink / raw) To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, galak Cc: linuxppc-dev, linux-kernel On Mon, 2019-09-16 at 20:25 +0000, Christophe Leroy wrote: > On mpc83xx with a QE, IMMR is 2Mbytes and aligned on 2Mbytes boundarie. > On mpc83xx without a QE, IMMR is 1Mbyte and 1Mbyte aligned. > > Each driver will map a part of it to access the registers it needs. > Some drivers will map the same part of IMMR as other drivers. > > In order to reduce TLB misses, map the full IMMR with a BAT. If it is > 2Mbytes aligned, map 2Mbytes. If there is no QE, the upper part will > remain unused, but it doesn't harm as it is mapped as guarded memory. > > When the IMMR is not aligned on a 2Mbytes boundarie, only map 1Mbyte. > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > > --- > v2: > - use a fixmap area instead of playing with ioremap_bot > - always map 2M unless IMMRBAR is only 1M aligned > > v3: > - replaced __fix_to_virt() by fix_to_virt() > --- > arch/powerpc/include/asm/fixmap.h | 8 ++++++++ > arch/powerpc/platforms/83xx/misc.c | 11 +++++++++++ > 2 files changed, 19 insertions(+) Acked-by: Scott Wood <oss@buserror.net> -Scott ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/2] powerpc/32s: automatically allocate BAT in setbat() 2019-09-16 20:25 ` Christophe Leroy (?) (?) @ 2019-11-25 10:47 ` Michael Ellerman -1 siblings, 0 replies; 7+ messages in thread From: Michael Ellerman @ 2019-11-25 10:47 UTC (permalink / raw) To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras, oss, galak Cc: linuxppc-dev, linux-kernel On Mon, 2019-09-16 at 20:25:39 UTC, Christophe Leroy wrote: > If no BAT is given to setbat(), select an available BAT. > > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/cbcaff7d27ad5c5d2c2db113ec489be88adb815a cheers ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-25 10:47 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-09-16 20:25 [PATCH v3 1/2] powerpc/32s: automatically allocate BAT in setbat() Christophe Leroy 2019-09-16 20:25 ` Christophe Leroy 2019-09-16 20:25 ` [PATCH v3 2/2] powerpc/83xx: map IMMR with a BAT Christophe Leroy 2019-09-16 20:25 ` Christophe Leroy 2019-09-16 20:36 ` Scott Wood 2019-09-16 20:36 ` Scott Wood 2019-11-25 10:47 ` [PATCH v3 1/2] powerpc/32s: automatically allocate BAT in setbat() Michael Ellerman
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