From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandre Chartre <alexandre.chartre@oracle.com>,
Robin Murphy <robin.murphy@arm.com>,
Andrew Jones <drjones@redhat.com>,
Russell King <linux@arm.linux.org.uk>,
kernel-team@android.com,
Russell King <rmk+kernel@armlinux.org.uk>
Subject: Re: [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements
Date: Mon, 19 Jul 2021 17:02:01 +0100 [thread overview]
Message-ID: <482a40a8-d190-99d3-ec17-59ee730be0fa@arm.com> (raw)
In-Reply-To: <171834f3198b898d5c2aefa0270b65f2@kernel.org>
Hi Marc,
On 7/19/21 4:56 PM, Marc Zyngier wrote:
> On 2021-07-19 16:55, Alexandru Elisei wrote:
>> Hi Marc,
>>
>> On 7/19/21 1:38 PM, Marc Zyngier wrote:
>>> A number of the PMU sysregs expose reset values that are not
>>> compliant with the architecture (set bits in the RES0 ranges,
>>> for example).
>>>
>>> This in turn has the effect that we need to pointlessly mask
>>> some register fields when using them.
>>>
>>> Let's start by making sure we don't have illegal values in the
>>> shadow registers at reset time. This affects all the registers
>>> that dedicate one bit per counter, the counters themselves,
>>> PMEVTYPERn_EL0 and PMSELR_EL0.
>>>
>>> Reported-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> ---
>>> arch/arm64/kvm/sys_regs.c | 43 ++++++++++++++++++++++++++++++++++++---
>>> 1 file changed, 40 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>> index f6f126eb6ac1..96bdfa0e68b2 100644
>>> --- a/arch/arm64/kvm/sys_regs.c
>>> +++ b/arch/arm64/kvm/sys_regs.c
>>> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct kvm_vcpu
>>> *vcpu,
>>> return REG_HIDDEN;
>>> }
>>>
>>> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>> +{
>>> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
>>> +
>>> + /* No PMU available, any PMU reg may UNDEF... */
>>> + if (!kvm_arm_support_pmu_v3())
>>> + return;
>>> +
>>> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
>>> + n &= ARMV8_PMU_PMCR_N_MASK;
>>> + if (n)
>>> + mask |= GENMASK(n - 1, 0);
>>
>> Hm... seems to be missing the cycle counter.
>
> Check the declaration for 'mask'... :-)
Yeah, sorry for that, I still had in my mind the original function body.
Everything looks alright to me, no changes from the previous version (PMSWINC_EL1
is handled in the last patch) where I had checked that the reset values match the
architecture:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvm@vger.kernel.org, kernel-team@android.com,
Russell King <rmk+kernel@armlinux.org.uk>,
Russell King <linux@arm.linux.org.uk>,
Robin Murphy <robin.murphy@arm.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements
Date: Mon, 19 Jul 2021 17:02:01 +0100 [thread overview]
Message-ID: <482a40a8-d190-99d3-ec17-59ee730be0fa@arm.com> (raw)
In-Reply-To: <171834f3198b898d5c2aefa0270b65f2@kernel.org>
Hi Marc,
On 7/19/21 4:56 PM, Marc Zyngier wrote:
> On 2021-07-19 16:55, Alexandru Elisei wrote:
>> Hi Marc,
>>
>> On 7/19/21 1:38 PM, Marc Zyngier wrote:
>>> A number of the PMU sysregs expose reset values that are not
>>> compliant with the architecture (set bits in the RES0 ranges,
>>> for example).
>>>
>>> This in turn has the effect that we need to pointlessly mask
>>> some register fields when using them.
>>>
>>> Let's start by making sure we don't have illegal values in the
>>> shadow registers at reset time. This affects all the registers
>>> that dedicate one bit per counter, the counters themselves,
>>> PMEVTYPERn_EL0 and PMSELR_EL0.
>>>
>>> Reported-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> ---
>>> arch/arm64/kvm/sys_regs.c | 43 ++++++++++++++++++++++++++++++++++++---
>>> 1 file changed, 40 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>> index f6f126eb6ac1..96bdfa0e68b2 100644
>>> --- a/arch/arm64/kvm/sys_regs.c
>>> +++ b/arch/arm64/kvm/sys_regs.c
>>> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct kvm_vcpu
>>> *vcpu,
>>> return REG_HIDDEN;
>>> }
>>>
>>> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>> +{
>>> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
>>> +
>>> + /* No PMU available, any PMU reg may UNDEF... */
>>> + if (!kvm_arm_support_pmu_v3())
>>> + return;
>>> +
>>> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
>>> + n &= ARMV8_PMU_PMCR_N_MASK;
>>> + if (n)
>>> + mask |= GENMASK(n - 1, 0);
>>
>> Hm... seems to be missing the cycle counter.
>
> Check the declaration for 'mask'... :-)
Yeah, sorry for that, I still had in my mind the original function body.
Everything looks alright to me, no changes from the previous version (PMSWINC_EL1
is handled in the last patch) where I had checked that the reset values match the
architecture:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandre Chartre <alexandre.chartre@oracle.com>,
Robin Murphy <robin.murphy@arm.com>,
Andrew Jones <drjones@redhat.com>,
Russell King <linux@arm.linux.org.uk>,
kernel-team@android.com,
Russell King <rmk+kernel@armlinux.org.uk>
Subject: Re: [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements
Date: Mon, 19 Jul 2021 17:02:01 +0100 [thread overview]
Message-ID: <482a40a8-d190-99d3-ec17-59ee730be0fa@arm.com> (raw)
In-Reply-To: <171834f3198b898d5c2aefa0270b65f2@kernel.org>
Hi Marc,
On 7/19/21 4:56 PM, Marc Zyngier wrote:
> On 2021-07-19 16:55, Alexandru Elisei wrote:
>> Hi Marc,
>>
>> On 7/19/21 1:38 PM, Marc Zyngier wrote:
>>> A number of the PMU sysregs expose reset values that are not
>>> compliant with the architecture (set bits in the RES0 ranges,
>>> for example).
>>>
>>> This in turn has the effect that we need to pointlessly mask
>>> some register fields when using them.
>>>
>>> Let's start by making sure we don't have illegal values in the
>>> shadow registers at reset time. This affects all the registers
>>> that dedicate one bit per counter, the counters themselves,
>>> PMEVTYPERn_EL0 and PMSELR_EL0.
>>>
>>> Reported-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
>>> Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> ---
>>> arch/arm64/kvm/sys_regs.c | 43 ++++++++++++++++++++++++++++++++++++---
>>> 1 file changed, 40 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>> index f6f126eb6ac1..96bdfa0e68b2 100644
>>> --- a/arch/arm64/kvm/sys_regs.c
>>> +++ b/arch/arm64/kvm/sys_regs.c
>>> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct kvm_vcpu
>>> *vcpu,
>>> return REG_HIDDEN;
>>> }
>>>
>>> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>>> +{
>>> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
>>> +
>>> + /* No PMU available, any PMU reg may UNDEF... */
>>> + if (!kvm_arm_support_pmu_v3())
>>> + return;
>>> +
>>> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
>>> + n &= ARMV8_PMU_PMCR_N_MASK;
>>> + if (n)
>>> + mask |= GENMASK(n - 1, 0);
>>
>> Hm... seems to be missing the cycle counter.
>
> Check the declaration for 'mask'... :-)
Yeah, sorry for that, I still had in my mind the original function body.
Everything looks alright to me, no changes from the previous version (PMSWINC_EL1
is handled in the last patch) where I had checked that the reset values match the
architecture:
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Thanks,
Alex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-19 16:10 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-19 12:38 [PATCH v2 0/4] kvm-arm64: Fix PMU reset values (and more) Marc Zyngier
2021-07-19 12:38 ` Marc Zyngier
2021-07-19 12:38 ` Marc Zyngier
2021-07-19 12:38 ` [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements Marc Zyngier
2021-07-19 12:38 ` Marc Zyngier
2021-07-19 12:38 ` Marc Zyngier
2021-07-19 15:55 ` Alexandru Elisei
2021-07-19 15:55 ` Alexandru Elisei
2021-07-19 15:55 ` Alexandru Elisei
2021-07-19 15:56 ` Marc Zyngier
2021-07-19 15:56 ` Marc Zyngier
2021-07-19 15:56 ` Marc Zyngier
2021-07-19 16:02 ` Alexandru Elisei [this message]
2021-07-19 16:02 ` Alexandru Elisei
2021-07-19 16:02 ` Alexandru Elisei
2021-07-19 12:39 ` [PATCH v2 2/4] KVM: arm64: Drop unnecessary masking of PMU registers Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 12:39 ` [PATCH v2 3/4] KVM: arm64: Disabling disabled PMU counters wastes a lot of time Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 12:39 ` [PATCH v2 4/4] KVM: arm64: Remove PMSWINC_EL0 shadow register Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 12:39 ` Marc Zyngier
2021-07-19 16:35 ` Alexandru Elisei
2021-07-19 16:35 ` Alexandru Elisei
2021-07-19 16:35 ` Alexandru Elisei
2021-07-19 16:56 ` Marc Zyngier
2021-07-19 16:56 ` Marc Zyngier
2021-07-19 16:56 ` Marc Zyngier
2021-07-20 16:44 ` Alexandru Elisei
2021-07-20 16:44 ` Alexandru Elisei
2021-07-20 16:44 ` Alexandru Elisei
2021-07-21 9:30 ` Marc Zyngier
2021-07-21 9:30 ` Marc Zyngier
2021-07-21 9:30 ` Marc Zyngier
2021-08-02 13:39 ` [PATCH v2 0/4] kvm-arm64: Fix PMU reset values (and more) Marc Zyngier
2021-08-02 13:39 ` Marc Zyngier
2021-08-02 13:39 ` Marc Zyngier
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