[PATCH 00/12] KIQ support for gfx9

[PATCH 00/12] KIQ support for gfx9

[Alex Deucher]

Basically a port of the recent KIQ work for gfx8 to gfx9.  A couple
of general bug fixes as well.  Can someone with a vega10 board test
this?

Alex Deucher (12):
  drm/amdgpu/gfx9: fix typo in mpd init
  drm/amdgpu/gfx9: add additional MQD initialization
  drm/amdgpu/gfx9: create mqd backups
  drm/amdgpu/gfx9: clear the compute ring on reset
  drm/amdgpu: add KIQ packet defines to soc15d.h
  drm/amdgpu/gfx9: use new KIQ packet defines
  drm/amdgpu/gfx9: wait for completion in KIQ init
  drm/amdgpu: split gfx_v9_0_kiq_init_queue into two
  drm/amdgpu/gfx9: wait once for all KCQs to be created
  drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream
  drm/amdgpu/gfx9: fix resume of KIQ and KCQs
  drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring
    management. (v3)

 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 570 +++++++++++++---------------------
 drivers/gpu/drm/amd/amdgpu/soc15d.h   |  82 +++++
 2 files changed, 292 insertions(+), 360 deletions(-)

-- 
2.5.5

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[PATCH 01/12] drm/amdgpu/gfx9: fix typo in mpd init

[Alex Deucher]

Using the wrong macro for soc15 register access.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 87596e4..6b91805 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1989,12 +1989,12 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 
 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 	ring->wptr = 0;
-	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
+	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
 
 	/* set the vmid for the queue */
 	mqd->cp_hqd_vmid = 0;
 
-	tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
+	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
 	mqd->cp_hqd_persistent_state = tmp;
 
-- 
2.5.5

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[PATCH 02/12] drm/amdgpu/gfx9: add additional MQD initialization

[Alex Deucher]

Need to properly set the ROQ space setting.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6b91805..2f3e516 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1998,6 +1998,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
 	mqd->cp_hqd_persistent_state = tmp;
 
+	/* set MIN_IB_AVAIL_SIZE */
+	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
+	mqd->cp_hqd_ib_control = tmp;
+
 	/* activate the queue */
 	mqd->cp_hqd_active = 1;
 
-- 
2.5.5

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[PATCH 03/12] drm/amdgpu/gfx9: create mqd backups

[Alex Deucher]

And properly synchronize them with the master during
queue init.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2f3e516..98983a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -667,7 +667,10 @@ static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
 			return r;
 		}
 
-		/*TODO: prepare MQD backup */
+		/* prepare MQD backup */
+		adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
+		if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
+			dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 	}
 
 	/* create MQD for each KCQ */
@@ -682,7 +685,10 @@ static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
 				return r;
 			}
 
-			/* TODO: prepare MQD backup */
+			/* prepare MQD backup */
+			adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
+			if (!adev->gfx.mec.mqd_backup[i])
+				dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 		}
 	}
 
@@ -696,10 +702,12 @@ static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
 
 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 		ring = &adev->gfx.compute_ring[i];
+		kfree(adev->gfx.mec.mqd_backup[i]);
 		amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
 	}
 
 	ring = &adev->gfx.kiq.ring;
+	kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 	amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
 }
 
@@ -2138,8 +2146,12 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 		soc15_grbm_select(adev, 0, 0, 0, 0);
 		mutex_unlock(&adev->srbm_mutex);
 
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
 	} else { /* for GPU_RESET case */
 		/* reset MQD to a clean status */
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
 
 		/* reset ring buffer */
 		ring->wptr = 0;
-- 
2.5.5

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[PATCH 04/12] drm/amdgpu/gfx9: clear the compute ring on reset

[Alex Deucher]

To be consistent with gfx8.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 98983a6..189ddbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2155,6 +2155,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 
 		/* reset ring buffer */
 		ring->wptr = 0;
+		amdgpu_ring_clear_ring(ring);
 
 		if (is_kiq) {
 		    mutex_lock(&adev->srbm_mutex);
-- 
2.5.5

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[PATCH 05/12] drm/amdgpu: add KIQ packet defines to soc15d.h

[Alex Deucher]

Will be used in subsequent commits rather rather than
magic numbers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15d.h | 82 +++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index 75403c7..9e1b9e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -260,7 +260,89 @@
 #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
 #define	PACKET3_SWITCH_BUFFER				0x8B
 #define PACKET3_SET_RESOURCES				0xA0
+/* 1. header
+ * 2. CONTROL
+ * 3. QUEUE_MASK_LO [31:0]
+ * 4. QUEUE_MASK_HI [31:0]
+ * 5. GWS_MASK_LO [31:0]
+ * 6. GWS_MASK_HI [31:0]
+ * 7. OAC_MASK [15:0]
+ * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
+ */
+#              define PACKET3_SET_RESOURCES_VMID_MASK(x)     ((x) << 0)
+#              define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
+#              define PACKET3_SET_RESOURCES_QUEUE_TYPE(x)    ((x) << 29)
 #define PACKET3_MAP_QUEUES				0xA2
+/* 1. header
+ * 2. CONTROL
+ * 3. CONTROL2
+ * 4. MQD_ADDR_LO [31:0]
+ * 5. MQD_ADDR_HI [31:0]
+ * 6. WPTR_ADDR_LO [31:0]
+ * 7. WPTR_ADDR_HI [31:0]
+ */
+/* CONTROL */
+#              define PACKET3_MAP_QUEUES_QUEUE_SEL(x)       ((x) << 4)
+#              define PACKET3_MAP_QUEUES_VMID(x)            ((x) << 8)
+#              define PACKET3_MAP_QUEUES_QUEUE(x)           ((x) << 13)
+#              define PACKET3_MAP_QUEUES_PIPE(x)            ((x) << 16)
+#              define PACKET3_MAP_QUEUES_ME(x)              ((x) << 18)
+#              define PACKET3_MAP_QUEUES_QUEUE_TYPE(x)      ((x) << 21)
+#              define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x)    ((x) << 24)
+#              define PACKET3_MAP_QUEUES_ENGINE_SEL(x)      ((x) << 26)
+#              define PACKET3_MAP_QUEUES_NUM_QUEUES(x)      ((x) << 29)
+/* CONTROL2 */
+#              define PACKET3_MAP_QUEUES_CHECK_DISABLE(x)   ((x) << 1)
+#              define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
+#define	PACKET3_UNMAP_QUEUES				0xA3
+/* 1. header
+ * 2. CONTROL
+ * 3. CONTROL2
+ * 4. CONTROL3
+ * 5. CONTROL4
+ * 6. CONTROL5
+ */
+/* CONTROL */
+#              define PACKET3_UNMAP_QUEUES_ACTION(x)           ((x) << 0)
+		/* 0 - PREEMPT_QUEUES
+		 * 1 - RESET_QUEUES
+		 * 2 - DISABLE_PROCESS_QUEUES
+		 * 3 - PREEMPT_QUEUES_NO_UNMAP
+		 */
+#              define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x)        ((x) << 4)
+#              define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x)       ((x) << 26)
+#              define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x)       ((x) << 29)
+/* CONTROL2a */
+#              define PACKET3_UNMAP_QUEUES_PASID(x)            ((x) << 0)
+/* CONTROL2b */
+#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
+/* CONTROL3a */
+#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
+/* CONTROL3b */
+#              define PACKET3_UNMAP_QUEUES_RB_WPTR(x)          ((x) << 0)
+/* CONTROL4 */
+#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
+/* CONTROL5 */
+#              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
+#define	PACKET3_QUERY_STATUS				0xA4
+/* 1. header
+ * 2. CONTROL
+ * 3. CONTROL2
+ * 4. ADDR_LO [31:0]
+ * 5. ADDR_HI [31:0]
+ * 6. DATA_LO [31:0]
+ * 7. DATA_HI [31:0]
+ */
+/* CONTROL */
+#              define PACKET3_QUERY_STATUS_CONTEXT_ID(x)       ((x) << 0)
+#              define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x)    ((x) << 28)
+#              define PACKET3_QUERY_STATUS_COMMAND(x)          ((x) << 30)
+/* CONTROL2a */
+#              define PACKET3_QUERY_STATUS_PASID(x)            ((x) << 0)
+/* CONTROL2b */
+#              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) << 2)
+#              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)
+
 
 #define VCE_CMD_NO_OP		0x00000000
 #define VCE_CMD_END		0x00000001
-- 
2.5.5

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[PATCH 06/12] drm/amdgpu/gfx9: use new KIQ packet defines

[Alex Deucher]

Rather than magic numbers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 189ddbe..20959bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1844,7 +1844,8 @@ static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
 	amdgpu_ring_alloc(ring, 8);
 	/* set resources */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
-	amdgpu_ring_write(ring, 0);	/* vmid_mask:0 queue_type:0 (KIQ) */
+	amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
+			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
 	amdgpu_ring_write(ring, 0x000000FF);	/* queue mask lo */
 	amdgpu_ring_write(ring, 0);	/* queue mask hi */
 	amdgpu_ring_write(ring, 0);	/* gws mask lo */
@@ -1868,16 +1869,16 @@ static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
-			  (0 << 4) | /* Queue_Sel */
-			  (0 << 8) | /* VMID */
-			  (ring->queue << 13 ) |
-			  (ring->pipe << 16) |
-			  ((ring->me == 1 ? 0 : 1) << 18) |
-			  (0 << 21) | /*queue_type: normal compute queue */
-			  (1 << 24) | /* alloc format: all_on_one_pipe */
-			  (0 << 26) | /* engine_sel: compute */
-			  (1 << 29)); /* num_queues: must be 1 */
-	amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2));
+			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
+			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
+			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
+			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
+			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
+			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
+			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
+			  PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
+			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
+	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
-- 
2.5.5

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[PATCH 07/12] drm/amdgpu/gfx9: wait for completion in KIQ init

[Alex Deucher]

We need to make sure the various init sequences submitted
to KIQ complete before testing the rings.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 89 +++++++++++++++++++++++++++++++----
 1 file changed, 79 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 20959bc..097a524 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1839,9 +1839,26 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
 }
 
-static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
+static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
 {
-	amdgpu_ring_alloc(ring, 8);
+	struct amdgpu_device *adev = ring->adev;
+	uint32_t scratch, tmp = 0;
+	int r, i;
+
+	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	if (r) {
+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+
+	r = amdgpu_ring_alloc(ring, 8);
+	if (r) {
+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+		amdgpu_gfx_scratch_free(adev, scratch);
+		return r;
+	}
+	amdgpu_ring_alloc(ring, 11);
 	/* set resources */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 	amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
@@ -1852,19 +1869,52 @@ static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
 	amdgpu_ring_write(ring, 0);	/* gws mask hi */
 	amdgpu_ring_write(ring, 0);	/* oac mask */
 	amdgpu_ring_write(ring, 0);	/* gds heap base:0, gds heap size:0 */
+	/* write to scratch for completion */
+	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(ring, 0xDEADBEEF);
 	amdgpu_ring_commit(ring);
-	udelay(50);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i >= adev->usec_timeout) {
+		DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	amdgpu_gfx_scratch_free(adev, scratch);
+
+	return r;
 }
 
-static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
-				   struct amdgpu_ring *ring)
+static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
+				     struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = kiq_ring->adev;
 	uint64_t mqd_addr, wptr_addr;
+	uint32_t scratch, tmp = 0;
+	int r, i;
+
+	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	if (r) {
+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+
+	r = amdgpu_ring_alloc(kiq_ring, 10);
+	if (r) {
+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+		amdgpu_gfx_scratch_free(adev, scratch);
+		return r;
+	}
 
 	mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 	wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-	amdgpu_ring_alloc(kiq_ring, 8);
 
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
@@ -1883,8 +1933,26 @@ static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+	/* write to scratch for completion */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
 	amdgpu_ring_commit(kiq_ring);
-	udelay(50);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i >= adev->usec_timeout) {
+		DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	amdgpu_gfx_scratch_free(adev, scratch);
+
+	return r;
 }
 
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
@@ -2130,6 +2198,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 	struct v9_mqd *mqd = ring->mqd_ptr;
 	bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
+	int r;
 
 	if (is_kiq) {
 		gfx_v9_0_kiq_setting(&kiq->ring);
@@ -2168,11 +2237,11 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 	}
 
 	if (is_kiq)
-		gfx_v9_0_kiq_enable(ring);
+		r = gfx_v9_0_kiq_enable(ring);
 	else
-		gfx_v9_0_map_queue_enable(&kiq->ring, ring);
+		r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
 
-	return 0;
+	return r;
 }
 
 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
-- 
2.5.5

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[PATCH 08/12] drm/amdgpu: split gfx_v9_0_kiq_init_queue into two

[Alex Deucher]

One for KIQ and one for the KCQ. This simplifies the logic and
allows for future optimizations.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 63 +++++++++++++++++++++++------------
 1 file changed, 42 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 097a524..815f985 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2194,25 +2194,18 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 	struct v9_mqd *mqd = ring->mqd_ptr;
-	bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ);
 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
 	int r;
 
-	if (is_kiq) {
-		gfx_v9_0_kiq_setting(&kiq->ring);
-	} else {
-		mqd_idx = ring - &adev->gfx.compute_ring[0];
-	}
+	gfx_v9_0_kiq_setting(ring);
 
 	if (!adev->gfx.in_reset) {
 		memset((void *)mqd, 0, sizeof(*mqd));
 		mutex_lock(&adev->srbm_mutex);
 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
 		gfx_v9_0_mqd_init(ring);
-		if (is_kiq)
-			gfx_v9_0_kiq_init_register(ring);
+		gfx_v9_0_kiq_init_register(ring);
 		soc15_grbm_select(adev, 0, 0, 0, 0);
 		mutex_unlock(&adev->srbm_mutex);
 
@@ -2227,19 +2220,47 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 		ring->wptr = 0;
 		amdgpu_ring_clear_ring(ring);
 
-		if (is_kiq) {
-		    mutex_lock(&adev->srbm_mutex);
-		    soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-		    gfx_v9_0_kiq_init_register(ring);
-		    soc15_grbm_select(adev, 0, 0, 0, 0);
-		    mutex_unlock(&adev->srbm_mutex);
-		}
+		mutex_lock(&adev->srbm_mutex);
+		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v9_0_kiq_init_register(ring);
+		soc15_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
 	}
 
-	if (is_kiq)
-		r = gfx_v9_0_kiq_enable(ring);
-	else
-		r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
+	r = gfx_v9_0_kiq_enable(ring);
+
+	return r;
+}
+
+static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+	struct v9_mqd *mqd = ring->mqd_ptr;
+	int mqd_idx = ring - &adev->gfx.compute_ring[0];
+	int r;
+
+	if (!adev->gfx.in_reset) {
+		memset((void *)mqd, 0, sizeof(*mqd));
+		mutex_lock(&adev->srbm_mutex);
+		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v9_0_mqd_init(ring);
+		soc15_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
+
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
+	} else { /* for GPU_RESET case */
+		/* reset MQD to a clean status */
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
+
+		/* reset ring buffer */
+		ring->wptr = 0;
+		amdgpu_ring_clear_ring(ring);
+	}
+
+	r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
 
 	return r;
 }
@@ -2275,7 +2296,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
 			goto done;
 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
 		if (!r) {
-			r = gfx_v9_0_kiq_init_queue(ring);
+			r = gfx_v9_0_kcq_init_queue(ring);
 			amdgpu_bo_kunmap(ring->mqd_obj);
 			ring->mqd_ptr = NULL;
 		}
-- 
2.5.5

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[PATCH 09/12] drm/amdgpu/gfx9: wait once for all KCQs to be created

[Alex Deucher]

Rather than waiting for each queue.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 60 +++++++++++++++++------------------
 1 file changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 815f985..10930d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1891,11 +1891,9 @@ static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
 	return r;
 }
 
-static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
-				     struct amdgpu_ring *ring)
+static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
 {
-	struct amdgpu_device *adev = kiq_ring->adev;
-	uint64_t mqd_addr, wptr_addr;
+	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 	uint32_t scratch, tmp = 0;
 	int r, i;
 
@@ -1906,33 +1904,36 @@ static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring,
 	}
 	WREG32(scratch, 0xCAFEDEAD);
 
-	r = amdgpu_ring_alloc(kiq_ring, 10);
+	r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3);
 	if (r) {
 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 		amdgpu_gfx_scratch_free(adev, scratch);
 		return r;
 	}
 
-	mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
-	wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-
-	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
-	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
-	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
-			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
-			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
-			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
-			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
-			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
-			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
-			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
-			  PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
-			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
-	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
-	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
-	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
-	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
-	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
+		uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+		uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+
+		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
+		/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
+		amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+				  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
+				  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
+				  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
+				  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
+				  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
+				  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
+				  PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
+				  PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
+				  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
+		amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
+		amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
+		amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
+		amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
+		amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
+	}
 	/* write to scratch for completion */
 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
@@ -2235,10 +2236,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 	struct v9_mqd *mqd = ring->mqd_ptr;
 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
-	int r;
 
 	if (!adev->gfx.in_reset) {
 		memset((void *)mqd, 0, sizeof(*mqd));
@@ -2260,9 +2259,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 		amdgpu_ring_clear_ring(ring);
 	}
 
-	r = gfx_v9_0_map_queue_enable(&kiq->ring, ring);
-
-	return r;
+	return 0;
 }
 
 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
@@ -2305,13 +2302,14 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
 			goto done;
 	}
 
+	r = gfx_v9_0_map_queues_enable(adev);
 done:
 	return r;
 }
 
 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 {
-	int r,i;
+	int r, i;
 	struct amdgpu_ring *ring;
 
 	if (!(adev->flags & AMD_IS_APU))
-- 
2.5.5

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[PATCH 10/12] drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream

[Alex Deucher]

As the KCQ setup.  This way we only have to wait once for the
entire MEC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 73 +++++++----------------------------
 1 file changed, 14 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 10930d4..d26bad2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1839,59 +1839,7 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
 }
 
-static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-	uint32_t scratch, tmp = 0;
-	int r, i;
-
-	r = amdgpu_gfx_scratch_get(adev, &scratch);
-	if (r) {
-		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-		return r;
-	}
-	WREG32(scratch, 0xCAFEDEAD);
-
-	r = amdgpu_ring_alloc(ring, 8);
-	if (r) {
-		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-		amdgpu_gfx_scratch_free(adev, scratch);
-		return r;
-	}
-	amdgpu_ring_alloc(ring, 11);
-	/* set resources */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
-	amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
-			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
-	amdgpu_ring_write(ring, 0x000000FF);	/* queue mask lo */
-	amdgpu_ring_write(ring, 0);	/* queue mask hi */
-	amdgpu_ring_write(ring, 0);	/* gws mask lo */
-	amdgpu_ring_write(ring, 0);	/* gws mask hi */
-	amdgpu_ring_write(ring, 0);	/* oac mask */
-	amdgpu_ring_write(ring, 0);	/* gds heap base:0, gds heap size:0 */
-	/* write to scratch for completion */
-	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-	amdgpu_ring_write(ring, 0xDEADBEEF);
-	amdgpu_ring_commit(ring);
-
-	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32(scratch);
-		if (tmp == 0xDEADBEEF)
-			break;
-		DRM_UDELAY(1);
-	}
-	if (i >= adev->usec_timeout) {
-		DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n",
-			  scratch, tmp);
-		r = -EINVAL;
-	}
-	amdgpu_gfx_scratch_free(adev, scratch);
-
-	return r;
-}
-
-static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
+static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
 {
 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 	uint32_t scratch, tmp = 0;
@@ -1904,13 +1852,23 @@ static int gfx_v9_0_map_queues_enable(struct amdgpu_device *adev)
 	}
 	WREG32(scratch, 0xCAFEDEAD);
 
-	r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 3);
+	r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
 	if (r) {
 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 		amdgpu_gfx_scratch_free(adev, scratch);
 		return r;
 	}
 
+	/* set resources */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
+	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
+			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
+	amdgpu_ring_write(kiq_ring, 0x000000FF);	/* queue mask lo */
+	amdgpu_ring_write(kiq_ring, 0);	/* queue mask hi */
+	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
+	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
+	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
+	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
 		uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
@@ -2197,7 +2155,6 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 	struct v9_mqd *mqd = ring->mqd_ptr;
 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
-	int r;
 
 	gfx_v9_0_kiq_setting(ring);
 
@@ -2228,9 +2185,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 		mutex_unlock(&adev->srbm_mutex);
 	}
 
-	r = gfx_v9_0_kiq_enable(ring);
-
-	return r;
+	return 0;
 }
 
 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
@@ -2302,7 +2257,7 @@ static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
 			goto done;
 	}
 
-	r = gfx_v9_0_map_queues_enable(adev);
+	r = gfx_v9_0_kiq_kcq_enable(adev);
 done:
 	return r;
 }
-- 
2.5.5

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[PATCH 11/12] drm/amdgpu/gfx9: fix resume of KIQ and KCQs

[Alex Deucher]

No need to reset the wptr and clear the rings.  The UNMAP_QUEUES
packet writes the current MQD state back the MQD on suspend,
so there is no need to reset it as well.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d26bad2..f86a7f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2158,18 +2158,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 
 	gfx_v9_0_kiq_setting(ring);
 
-	if (!adev->gfx.in_reset) {
-		memset((void *)mqd, 0, sizeof(*mqd));
-		mutex_lock(&adev->srbm_mutex);
-		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-		gfx_v9_0_mqd_init(ring);
-		gfx_v9_0_kiq_init_register(ring);
-		soc15_grbm_select(adev, 0, 0, 0, 0);
-		mutex_unlock(&adev->srbm_mutex);
-
-		if (adev->gfx.mec.mqd_backup[mqd_idx])
-			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-	} else { /* for GPU_RESET case */
+	if (adev->gfx.in_reset) { /* for GPU_RESET case */
 		/* reset MQD to a clean status */
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
@@ -2183,6 +2172,17 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 		gfx_v9_0_kiq_init_register(ring);
 		soc15_grbm_select(adev, 0, 0, 0, 0);
 		mutex_unlock(&adev->srbm_mutex);
+	} else {
+		memset((void *)mqd, 0, sizeof(*mqd));
+		mutex_lock(&adev->srbm_mutex);
+		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v9_0_mqd_init(ring);
+		gfx_v9_0_kiq_init_register(ring);
+		soc15_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
+
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
 	}
 
 	return 0;
@@ -2204,7 +2204,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-	} else { /* for GPU_RESET case */
+	} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
 		/* reset MQD to a clean status */
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
-- 
2.5.5

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Alex Deucher]

KIQ is the Kernel Interface Queue for managing the MEC.  Rather than setting
up rings via direct MMIO of ring registers, the rings are configured via
special packets sent to the KIQ.  The allows the MEC to better manage shared
resources and certain power events. It also reduces the code paths in the
driver to support and is required for MEC powergating.

v2: drop gfx_v9_0_cp_compute_fini() as well
v3: rebase on latest changes derived from gfx8, add unmap queues on
hw_fini

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 374 ++++++++--------------------------
 1 file changed, 81 insertions(+), 293 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f86a7f6..ef7a3ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1113,23 +1113,21 @@ static int gfx_v9_0_sw_init(void *handle)
 			return r;
 	}
 
-	if (amdgpu_sriov_vf(adev)) {
-		r = gfx_v9_0_kiq_init(adev);
-		if (r) {
-			DRM_ERROR("Failed to init KIQ BOs!\n");
-			return r;
-		}
+	r = gfx_v9_0_kiq_init(adev);
+	if (r) {
+		DRM_ERROR("Failed to init KIQ BOs!\n");
+		return r;
+	}
 
-		kiq = &adev->gfx.kiq;
-		r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
-		if (r)
-			return r;
+	kiq = &adev->gfx.kiq;
+	r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
+	if (r)
+		return r;
 
-		/* create MQD for all compute queues as wel as KIQ for SRIOV case */
-		r = gfx_v9_0_compute_mqd_sw_init(adev);
-		if (r)
-			return r;
-	}
+	/* create MQD for all compute queues as wel as KIQ for SRIOV case */
+	r = gfx_v9_0_compute_mqd_sw_init(adev);
+	if (r)
+		return r;
 
 	/* reserve GDS, GWS and OA resource for gfx */
 	r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
@@ -1176,11 +1174,9 @@ static int gfx_v9_0_sw_fini(void *handle)
 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
-	if (amdgpu_sriov_vf(adev)) {
-		gfx_v9_0_compute_mqd_sw_fini(adev);
-		gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
-		gfx_v9_0_kiq_fini(adev);
-	}
+	gfx_v9_0_compute_mqd_sw_fini(adev);
+	gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+	gfx_v9_0_kiq_fini(adev);
 
 	gfx_v9_0_mec_fini(adev);
 	gfx_v9_0_ngg_fini(adev);
@@ -1736,13 +1732,6 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 	udelay(50);
 }
 
-static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
-{
-	gfx_v9_0_cp_compute_enable(adev, true);
-
-	return 0;
-}
-
 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 {
 	const struct gfx_firmware_header_v1_0 *mec_hdr;
@@ -1785,45 +1774,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 	return 0;
 }
 
-static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
-{
-	int i, r;
-
-	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-
-		if (ring->mqd_obj) {
-			r = amdgpu_bo_reserve(ring->mqd_obj, false);
-			if (unlikely(r != 0))
-				dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
-
-			amdgpu_bo_unpin(ring->mqd_obj);
-			amdgpu_bo_unreserve(ring->mqd_obj);
-
-			amdgpu_bo_unref(&ring->mqd_obj);
-			ring->mqd_obj = NULL;
-		}
-	}
-}
-
-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
-
-static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
-{
-	int i, r;
-	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-		if (gfx_v9_0_init_queue(ring))
-			dev_warn(adev->dev, "compute queue %d init failed!\n", i);
-	}
-
-	r = gfx_v9_0_cp_compute_start(adev);
-	if (r)
-		return r;
-
-	return 0;
-}
-
 /* KIQ functions */
 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 {
@@ -1914,6 +1864,56 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
 	return r;
 }
 
+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
+{
+	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+	uint32_t scratch, tmp = 0;
+	int r, i;
+
+	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	if (r) {
+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+
+	r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
+	if (r) {
+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+		amdgpu_gfx_scratch_free(adev, scratch);
+		return r;
+	}
+	/* unmap queues */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+	amdgpu_ring_write(kiq_ring,
+			  PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
+			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	/* write to scratch for completion */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+	amdgpu_ring_commit(kiq_ring);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i >= adev->usec_timeout) {
+		DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
+			  scratch, tmp);
+		r = -EINVAL;
+	}
+	amdgpu_gfx_scratch_free(adev, scratch);
+
+	return r;
+}
+
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
@@ -2194,7 +2194,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 	struct v9_mqd *mqd = ring->mqd_ptr;
 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
 
-	if (!adev->gfx.in_reset) {
+	if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
 		memset((void *)mqd, 0, sizeof(*mqd));
 		mutex_lock(&adev->srbm_mutex);
 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
@@ -2285,10 +2285,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 	if (r)
 		return r;
 
-	if (amdgpu_sriov_vf(adev))
-		r = gfx_v9_0_kiq_resume(adev);
-	else
-		r = gfx_v9_0_cp_compute_resume(adev);
+	r = gfx_v9_0_kiq_resume(adev);
 	if (r)
 		return r;
 
@@ -2298,6 +2295,13 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 		ring->ready = false;
 		return r;
 	}
+
+	ring = &adev->gfx.kiq.ring;
+	ring->ready = true;
+	r = amdgpu_ring_test_ring(ring);
+	if (r)
+		ring->ready = false;
+
 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 		ring = &adev->gfx.compute_ring[i];
 
@@ -2307,14 +2311,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
 			ring->ready = false;
 	}
 
-	if (amdgpu_sriov_vf(adev)) {
-		ring = &adev->gfx.kiq.ring;
-		ring->ready = true;
-		r = amdgpu_ring_test_ring(ring);
-		if (r)
-			ring->ready = false;
-	}
-
 	gfx_v9_0_enable_gui_idle_interrupt(adev, true);
 
 	return 0;
@@ -2360,9 +2356,9 @@ static int gfx_v9_0_hw_fini(void *handle)
 		pr_debug("For SRIOV client, shouldn't do anything.\n");
 		return 0;
 	}
+	gfx_v9_0_kiq_kcq_disable(adev);
 	gfx_v9_0_cp_enable(adev, false);
 	gfx_v9_0_rlc_stop(adev);
-	gfx_v9_0_cp_compute_fini(adev);
 
 	return 0;
 }
@@ -2371,14 +2367,18 @@ static int gfx_v9_0_suspend(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	adev->gfx.in_suspend = true;
 	return gfx_v9_0_hw_fini(adev);
 }
 
 static int gfx_v9_0_resume(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int r;
 
-	return gfx_v9_0_hw_init(adev);
+	r = gfx_v9_0_hw_init(adev);
+	adev->gfx.in_suspend = false;
+	return r;
 }
 
 static bool gfx_v9_0_is_idle(void *handle)
@@ -3753,218 +3753,6 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
-{
-	int r, j;
-	u32 tmp;
-	bool use_doorbell = true;
-	u64 hqd_gpu_addr;
-	u64 mqd_gpu_addr;
-	u64 eop_gpu_addr;
-	u64 wb_gpu_addr;
-	u32 *buf;
-	struct v9_mqd *mqd;
-	struct amdgpu_device *adev;
-
-	adev = ring->adev;
-	if (ring->mqd_obj == NULL) {
-		r = amdgpu_bo_create(adev,
-				sizeof(struct v9_mqd),
-				PAGE_SIZE,true,
-				AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
-				NULL, &ring->mqd_obj);
-		if (r) {
-			dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
-			return r;
-		}
-	}
-
-	r = amdgpu_bo_reserve(ring->mqd_obj, false);
-	if (unlikely(r != 0)) {
-		gfx_v9_0_cp_compute_fini(adev);
-		return r;
-	}
-
-	r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
-				  &mqd_gpu_addr);
-	if (r) {
-		dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
-		gfx_v9_0_cp_compute_fini(adev);
-		return r;
-	}
-	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
-	if (r) {
-		dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
-		gfx_v9_0_cp_compute_fini(adev);
-		return r;
-	}
-
-	/* init the mqd struct */
-	memset(buf, 0, sizeof(struct v9_mqd));
-
-	mqd = (struct v9_mqd *)buf;
-	mqd->header = 0xC0310800;
-	mqd->compute_pipelinestat_enable = 0x00000001;
-	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
-	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
-	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
-	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
-	mqd->compute_misc_reserved = 0x00000003;
-	mutex_lock(&adev->srbm_mutex);
-	soc15_grbm_select(adev, ring->me,
-			       ring->pipe,
-			       ring->queue, 0);
-	/* disable wptr polling */
-	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-
-	/* write the EOP addr */
-	BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
-	eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
-	eop_gpu_addr >>= 8;
-
-	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
-	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
-	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
-	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
-
-	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
-				    (order_base_2(MEC_HPD_SIZE / 4) - 1));
-	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
-
-	/* enable doorbell? */
-	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-	if (use_doorbell)
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-	else
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
-
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
-	mqd->cp_hqd_pq_doorbell_control = tmp;
-
-	/* disable the queue if it's active */
-	ring->wptr = 0;
-	mqd->cp_hqd_dequeue_request = 0;
-	mqd->cp_hqd_pq_rptr = 0;
-	mqd->cp_hqd_pq_wptr_lo = 0;
-	mqd->cp_hqd_pq_wptr_hi = 0;
-	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
-		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
-		for (j = 0; j < adev->usec_timeout; j++) {
-			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
-				break;
-			udelay(1);
-		}
-		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
-		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
-		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-	}
-
-	/* set the pointer to the MQD */
-	mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
-	mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
-	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
-	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
-
-	/* set MQD vmid to 0 */
-	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
-	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
-	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
-	mqd->cp_mqd_control = tmp;
-
-	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
-	hqd_gpu_addr = ring->gpu_addr >> 8;
-	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
-	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
-
-	/* set up the HQD, this is similar to CP_RB0_CNTL */
-	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
-		(order_base_2(ring->ring_size / 4) - 1));
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
-		((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
-#ifdef __BIG_ENDIAN
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
-#endif
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
-	mqd->cp_hqd_pq_control = tmp;
-
-	/* set the wb address wether it's enabled or not */
-	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
-	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
-	mqd->cp_hqd_pq_rptr_report_addr_hi =
-	upper_32_bits(wb_gpu_addr) & 0xffff;
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
-		mqd->cp_hqd_pq_rptr_report_addr_lo);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
-		mqd->cp_hqd_pq_rptr_report_addr_hi);
-
-	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
-	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
-		mqd->cp_hqd_pq_wptr_poll_addr_lo);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
-		mqd->cp_hqd_pq_wptr_poll_addr_hi);
-
-	/* enable the doorbell if requested */
-	if (use_doorbell) {
-		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
-			(AMDGPU_DOORBELL64_KIQ * 2) << 2);
-		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-			(AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
-		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-			DOORBELL_OFFSET, ring->doorbell_index);
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
-		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
-		mqd->cp_hqd_pq_doorbell_control = tmp;
-
-	} else {
-		mqd->cp_hqd_pq_doorbell_control = 0;
-	}
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
-		mqd->cp_hqd_pq_doorbell_control);
-
-	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-
-	/* set the vmid for the queue */
-	mqd->cp_hqd_vmid = 0;
-	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
-
-	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
-	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
-	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
-	mqd->cp_hqd_persistent_state = tmp;
-
-	/* activate the queue */
-	mqd->cp_hqd_active = 1;
-	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
-
-	soc15_grbm_select(adev, 0, 0, 0, 0);
-	mutex_unlock(&adev->srbm_mutex);
-
-	amdgpu_bo_kunmap(ring->mqd_obj);
-	amdgpu_bo_unreserve(ring->mqd_obj);
-
-	if (use_doorbell)
-		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-
-	return 0;
-}
-
 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
 {
 	.type = AMD_IP_BLOCK_TYPE_GFX,
-- 
2.5.5

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 20223 bytes --]

+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)

...............

+               DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",


should be disable here.


Best Regards

Rex


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Tuesday, April 18, 2017 6:00:47 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander
Subject: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

KIQ is the Kernel Interface Queue for managing the MEC.  Rather than setting
up rings via direct MMIO of ring registers, the rings are configured via
special packets sent to the KIQ.  The allows the MEC to better manage shared
resources and certain power events. It also reduces the code paths in the
driver to support and is required for MEC powergating.

v2: drop gfx_v9_0_cp_compute_fini() as well
v3: rebase on latest changes derived from gfx8, add unmap queues on
hw_fini

Signed-off-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 374 ++++++++--------------------------
 1 file changed, 81 insertions(+), 293 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f86a7f6..ef7a3ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1113,23 +1113,21 @@ static int gfx_v9_0_sw_init(void *handle)
                         return r;
         }

-       if (amdgpu_sriov_vf(adev)) {
-               r = gfx_v9_0_kiq_init(adev);
-               if (r) {
-                       DRM_ERROR("Failed to init KIQ BOs!\n");
-                       return r;
-               }
+       r = gfx_v9_0_kiq_init(adev);
+       if (r) {
+               DRM_ERROR("Failed to init KIQ BOs!\n");
+               return r;
+       }

-               kiq = &adev->gfx.kiq;
-               r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
-               if (r)
-                       return r;
+       kiq = &adev->gfx.kiq;
+       r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
+       if (r)
+               return r;

-               /* create MQD for all compute queues as wel as KIQ for SRIOV case */
-               r = gfx_v9_0_compute_mqd_sw_init(adev);
-               if (r)
-                       return r;
-       }
+       /* create MQD for all compute queues as wel as KIQ for SRIOV case */
+       r = gfx_v9_0_compute_mqd_sw_init(adev);
+       if (r)
+               return r;

         /* reserve GDS, GWS and OA resource for gfx */
         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
@@ -1176,11 +1174,9 @@ static int gfx_v9_0_sw_fini(void *handle)
         for (i = 0; i < adev->gfx.num_compute_rings; i++)
                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);

-       if (amdgpu_sriov_vf(adev)) {
-               gfx_v9_0_compute_mqd_sw_fini(adev);
-               gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
-               gfx_v9_0_kiq_fini(adev);
-       }
+       gfx_v9_0_compute_mqd_sw_fini(adev);
+       gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+       gfx_v9_0_kiq_fini(adev);

         gfx_v9_0_mec_fini(adev);
         gfx_v9_0_ngg_fini(adev);
@@ -1736,13 +1732,6 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
         udelay(50);
 }

-static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
-{
-       gfx_v9_0_cp_compute_enable(adev, true);
-
-       return 0;
-}
-
 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 {
         const struct gfx_firmware_header_v1_0 *mec_hdr;
@@ -1785,45 +1774,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
         return 0;
 }

-static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
-{
-       int i, r;
-
-       for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-               struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-
-               if (ring->mqd_obj) {
-                       r = amdgpu_bo_reserve(ring->mqd_obj, false);
-                       if (unlikely(r != 0))
-                               dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
-
-                       amdgpu_bo_unpin(ring->mqd_obj);
-                       amdgpu_bo_unreserve(ring->mqd_obj);
-
-                       amdgpu_bo_unref(&ring->mqd_obj);
-                       ring->mqd_obj = NULL;
-               }
-       }
-}
-
-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
-
-static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
-{
-       int i, r;
-       for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-               struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-               if (gfx_v9_0_init_queue(ring))
-                       dev_warn(adev->dev, "compute queue %d init failed!\n", i);
-       }
-
-       r = gfx_v9_0_cp_compute_start(adev);
-       if (r)
-               return r;
-
-       return 0;
-}
-
 /* KIQ functions */
 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 {
@@ -1914,6 +1864,56 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
         return r;
 }

+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
+{
+       struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+       uint32_t scratch, tmp = 0;
+       int r, i;
+
+       r = amdgpu_gfx_scratch_get(adev, &scratch);
+       if (r) {
+               DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+               return r;
+       }
+       WREG32(scratch, 0xCAFEDEAD);
+
+       r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
+       if (r) {
+               DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+               amdgpu_gfx_scratch_free(adev, scratch);
+               return r;
+       }
+       /* unmap queues */
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+       amdgpu_ring_write(kiq_ring,
+                         PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
+                         PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       /* write to scratch for completion */
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+       amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+       amdgpu_ring_commit(kiq_ring);
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               tmp = RREG32(scratch);
+               if (tmp == 0xDEADBEEF)
+                       break;
+               DRM_UDELAY(1);
+       }
+       if (i >= adev->usec_timeout) {
+               DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
+                         scratch, tmp);
+               r = -EINVAL;
+       }
+       amdgpu_gfx_scratch_free(adev, scratch);
+
+       return r;
+}
+
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
@@ -2194,7 +2194,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
         struct v9_mqd *mqd = ring->mqd_ptr;
         int mqd_idx = ring - &adev->gfx.compute_ring[0];

-       if (!adev->gfx.in_reset) {
+       if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
                 memset((void *)mqd, 0, sizeof(*mqd));
                 mutex_lock(&adev->srbm_mutex);
                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
@@ -2285,10 +2285,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
         if (r)
                 return r;

-       if (amdgpu_sriov_vf(adev))
-               r = gfx_v9_0_kiq_resume(adev);
-       else
-               r = gfx_v9_0_cp_compute_resume(adev);
+       r = gfx_v9_0_kiq_resume(adev);
         if (r)
                 return r;

@@ -2298,6 +2295,13 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
                 ring->ready = false;
                 return r;
         }
+
+       ring = &adev->gfx.kiq.ring;
+       ring->ready = true;
+       r = amdgpu_ring_test_ring(ring);
+       if (r)
+               ring->ready = false;
+
         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                 ring = &adev->gfx.compute_ring[i];

@@ -2307,14 +2311,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
                         ring->ready = false;
         }

-       if (amdgpu_sriov_vf(adev)) {
-               ring = &adev->gfx.kiq.ring;
-               ring->ready = true;
-               r = amdgpu_ring_test_ring(ring);
-               if (r)
-                       ring->ready = false;
-       }
-
         gfx_v9_0_enable_gui_idle_interrupt(adev, true);

         return 0;
@@ -2360,9 +2356,9 @@ static int gfx_v9_0_hw_fini(void *handle)
                 pr_debug("For SRIOV client, shouldn't do anything.\n");
                 return 0;
         }
+       gfx_v9_0_kiq_kcq_disable(adev);
         gfx_v9_0_cp_enable(adev, false);
         gfx_v9_0_rlc_stop(adev);
-       gfx_v9_0_cp_compute_fini(adev);

         return 0;
 }
@@ -2371,14 +2367,18 @@ static int gfx_v9_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+       adev->gfx.in_suspend = true;
         return gfx_v9_0_hw_fini(adev);
 }

 static int gfx_v9_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int r;

-       return gfx_v9_0_hw_init(adev);
+       r = gfx_v9_0_hw_init(adev);
+       adev->gfx.in_suspend = false;
+       return r;
 }

 static bool gfx_v9_0_is_idle(void *handle)
@@ -3753,218 +3753,6 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
         return 0;
 }

-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
-{
-       int r, j;
-       u32 tmp;
-       bool use_doorbell = true;
-       u64 hqd_gpu_addr;
-       u64 mqd_gpu_addr;
-       u64 eop_gpu_addr;
-       u64 wb_gpu_addr;
-       u32 *buf;
-       struct v9_mqd *mqd;
-       struct amdgpu_device *adev;
-
-       adev = ring->adev;
-       if (ring->mqd_obj == NULL) {
-               r = amdgpu_bo_create(adev,
-                               sizeof(struct v9_mqd),
-                               PAGE_SIZE,true,
-                               AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
-                               NULL, &ring->mqd_obj);
-               if (r) {
-                       dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
-                       return r;
-               }
-       }
-
-       r = amdgpu_bo_reserve(ring->mqd_obj, false);
-       if (unlikely(r != 0)) {
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-
-       r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
-                                 &mqd_gpu_addr);
-       if (r) {
-               dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
-       if (r) {
-               dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-
-       /* init the mqd struct */
-       memset(buf, 0, sizeof(struct v9_mqd));
-
-       mqd = (struct v9_mqd *)buf;
-       mqd->header = 0xC0310800;
-       mqd->compute_pipelinestat_enable = 0x00000001;
-       mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
-       mqd->compute_misc_reserved = 0x00000003;
-       mutex_lock(&adev->srbm_mutex);
-       soc15_grbm_select(adev, ring->me,
-                              ring->pipe,
-                              ring->queue, 0);
-       /* disable wptr polling */
-       WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-
-       /* write the EOP addr */
-       BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
-       eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
-       eop_gpu_addr >>= 8;
-
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
-       mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
-       mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
-
-       /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
-                                   (order_base_2(MEC_HPD_SIZE / 4) - 1));
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
-
-       /* enable doorbell? */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-       if (use_doorbell)
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-       else
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
-
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
-       mqd->cp_hqd_pq_doorbell_control = tmp;
-
-       /* disable the queue if it's active */
-       ring->wptr = 0;
-       mqd->cp_hqd_dequeue_request = 0;
-       mqd->cp_hqd_pq_rptr = 0;
-       mqd->cp_hqd_pq_wptr_lo = 0;
-       mqd->cp_hqd_pq_wptr_hi = 0;
-       if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
-               WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
-               for (j = 0; j < adev->usec_timeout; j++) {
-                       if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
-                               break;
-                       udelay(1);
-               }
-               WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-       }
-
-       /* set the pointer to the MQD */
-       mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
-       mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
-
-       /* set MQD vmid to 0 */
-       tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
-       WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
-       mqd->cp_mqd_control = tmp;
-
-       /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
-       hqd_gpu_addr = ring->gpu_addr >> 8;
-       mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
-       mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
-
-       /* set up the HQD, this is similar to CP_RB0_CNTL */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
-               (order_base_2(ring->ring_size / 4) - 1));
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
-               ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
-#ifdef __BIG_ENDIAN
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
-#endif
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
-       mqd->cp_hqd_pq_control = tmp;
-
-       /* set the wb address wether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
-       mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
-       mqd->cp_hqd_pq_rptr_report_addr_hi =
-       upper_32_bits(wb_gpu_addr) & 0xffff;
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
-               mqd->cp_hqd_pq_rptr_report_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
-               mqd->cp_hqd_pq_rptr_report_addr_hi);
-
-       /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-       mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
-       mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
-               mqd->cp_hqd_pq_wptr_poll_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
-               mqd->cp_hqd_pq_wptr_poll_addr_hi);
-
-       /* enable the doorbell if requested */
-       if (use_doorbell) {
-               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
-                       (AMDGPU_DOORBELL64_KIQ * 2) << 2);
-               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-                       (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
-               tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                       DOORBELL_OFFSET, ring->doorbell_index);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
-               mqd->cp_hqd_pq_doorbell_control = tmp;
-
-       } else {
-               mqd->cp_hqd_pq_doorbell_control = 0;
-       }
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
-               mqd->cp_hqd_pq_doorbell_control);
-
-       /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-
-       /* set the vmid for the queue */
-       mqd->cp_hqd_vmid = 0;
-       WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
-
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
-       mqd->cp_hqd_persistent_state = tmp;
-
-       /* activate the queue */
-       mqd->cp_hqd_active = 1;
-       WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
-
-       soc15_grbm_select(adev, 0, 0, 0, 0);
-       mutex_unlock(&adev->srbm_mutex);
-
-       amdgpu_bo_kunmap(ring->mqd_obj);
-       amdgpu_bo_unreserve(ring->mqd_obj);
-
-       if (use_doorbell)
-               WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-
-       return 0;
-}
-
 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
 {
         .type = AMD_IP_BLOCK_TYPE_GFX,
--
2.5.5

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RE: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Deucher, Alexander]

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Thanks.  Updated patch sent out.

Alex

From: Zhu, Rex
Sent: Tuesday, April 18, 2017 2:11 AM
To: Alex Deucher; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander
Subject: Re: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)


+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)

...............

+               DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",



should be disable here.



Best Regards

Rex



________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org<mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
Sent: Tuesday, April 18, 2017 6:00:47 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander
Subject: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

KIQ is the Kernel Interface Queue for managing the MEC.  Rather than setting
up rings via direct MMIO of ring registers, the rings are configured via
special packets sent to the KIQ.  The allows the MEC to better manage shared
resources and certain power events. It also reduces the code paths in the
driver to support and is required for MEC powergating.

v2: drop gfx_v9_0_cp_compute_fini() as well
v3: rebase on latest changes derived from gfx8, add unmap queues on
hw_fini

Signed-off-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org<mailto:alexander.deucher-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 374 ++++++++--------------------------
 1 file changed, 81 insertions(+), 293 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f86a7f6..ef7a3ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1113,23 +1113,21 @@ static int gfx_v9_0_sw_init(void *handle)
                         return r;
         }

-       if (amdgpu_sriov_vf(adev)) {
-               r = gfx_v9_0_kiq_init(adev);
-               if (r) {
-                       DRM_ERROR("Failed to init KIQ BOs!\n");
-                       return r;
-               }
+       r = gfx_v9_0_kiq_init(adev);
+       if (r) {
+               DRM_ERROR("Failed to init KIQ BOs!\n");
+               return r;
+       }

-               kiq = &adev->gfx.kiq;
-               r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
-               if (r)
-                       return r;
+       kiq = &adev->gfx.kiq;
+       r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
+       if (r)
+               return r;

-               /* create MQD for all compute queues as wel as KIQ for SRIOV case */
-               r = gfx_v9_0_compute_mqd_sw_init(adev);
-               if (r)
-                       return r;
-       }
+       /* create MQD for all compute queues as wel as KIQ for SRIOV case */
+       r = gfx_v9_0_compute_mqd_sw_init(adev);
+       if (r)
+               return r;

         /* reserve GDS, GWS and OA resource for gfx */
         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
@@ -1176,11 +1174,9 @@ static int gfx_v9_0_sw_fini(void *handle)
         for (i = 0; i < adev->gfx.num_compute_rings; i++)
                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);

-       if (amdgpu_sriov_vf(adev)) {
-               gfx_v9_0_compute_mqd_sw_fini(adev);
-               gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
-               gfx_v9_0_kiq_fini(adev);
-       }
+       gfx_v9_0_compute_mqd_sw_fini(adev);
+       gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+       gfx_v9_0_kiq_fini(adev);

         gfx_v9_0_mec_fini(adev);
         gfx_v9_0_ngg_fini(adev);
@@ -1736,13 +1732,6 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
         udelay(50);
 }

-static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
-{
-       gfx_v9_0_cp_compute_enable(adev, true);
-
-       return 0;
-}
-
 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 {
         const struct gfx_firmware_header_v1_0 *mec_hdr;
@@ -1785,45 +1774,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
         return 0;
 }

-static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
-{
-       int i, r;
-
-       for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-               struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-
-               if (ring->mqd_obj) {
-                       r = amdgpu_bo_reserve(ring->mqd_obj, false);
-                       if (unlikely(r != 0))
-                               dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
-
-                       amdgpu_bo_unpin(ring->mqd_obj);
-                       amdgpu_bo_unreserve(ring->mqd_obj);
-
-                       amdgpu_bo_unref(&ring->mqd_obj);
-                       ring->mqd_obj = NULL;
-               }
-       }
-}
-
-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
-
-static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
-{
-       int i, r;
-       for (i = 0; i < adev->gfx.num_compute_rings; i++) {
-               struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
-               if (gfx_v9_0_init_queue(ring))
-                       dev_warn(adev->dev, "compute queue %d init failed!\n", i);
-       }
-
-       r = gfx_v9_0_cp_compute_start(adev);
-       if (r)
-               return r;
-
-       return 0;
-}
-
 /* KIQ functions */
 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 {
@@ -1914,6 +1864,56 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
         return r;
 }

+static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
+{
+       struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
+       uint32_t scratch, tmp = 0;
+       int r, i;
+
+       r = amdgpu_gfx_scratch_get(adev, &scratch);
+       if (r) {
+               DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+               return r;
+       }
+       WREG32(scratch, 0xCAFEDEAD);
+
+       r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
+       if (r) {
+               DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+               amdgpu_gfx_scratch_free(adev, scratch);
+               return r;
+       }
+       /* unmap queues */
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+       amdgpu_ring_write(kiq_ring,
+                         PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
+                         PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       amdgpu_ring_write(kiq_ring, 0);
+       /* write to scratch for completion */
+       amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+       amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+       amdgpu_ring_commit(kiq_ring);
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               tmp = RREG32(scratch);
+               if (tmp == 0xDEADBEEF)
+                       break;
+               DRM_UDELAY(1);
+       }
+       if (i >= adev->usec_timeout) {
+               DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
+                         scratch, tmp);
+               r = -EINVAL;
+       }
+       amdgpu_gfx_scratch_free(adev, scratch);
+
+       return r;
+}
+
 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
@@ -2194,7 +2194,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
         struct v9_mqd *mqd = ring->mqd_ptr;
         int mqd_idx = ring - &adev->gfx.compute_ring[0];

-       if (!adev->gfx.in_reset) {
+       if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
                 memset((void *)mqd, 0, sizeof(*mqd));
                 mutex_lock(&adev->srbm_mutex);
                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
@@ -2285,10 +2285,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
         if (r)
                 return r;

-       if (amdgpu_sriov_vf(adev))
-               r = gfx_v9_0_kiq_resume(adev);
-       else
-               r = gfx_v9_0_cp_compute_resume(adev);
+       r = gfx_v9_0_kiq_resume(adev);
         if (r)
                 return r;

@@ -2298,6 +2295,13 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
                 ring->ready = false;
                 return r;
         }
+
+       ring = &adev->gfx.kiq.ring;
+       ring->ready = true;
+       r = amdgpu_ring_test_ring(ring);
+       if (r)
+               ring->ready = false;
+
         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                 ring = &adev->gfx.compute_ring[i];

@@ -2307,14 +2311,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
                         ring->ready = false;
         }

-       if (amdgpu_sriov_vf(adev)) {
-               ring = &adev->gfx.kiq.ring;
-               ring->ready = true;
-               r = amdgpu_ring_test_ring(ring);
-               if (r)
-                       ring->ready = false;
-       }
-
         gfx_v9_0_enable_gui_idle_interrupt(adev, true);

         return 0;
@@ -2360,9 +2356,9 @@ static int gfx_v9_0_hw_fini(void *handle)
                 pr_debug("For SRIOV client, shouldn't do anything.\n");
                 return 0;
         }
+       gfx_v9_0_kiq_kcq_disable(adev);
         gfx_v9_0_cp_enable(adev, false);
         gfx_v9_0_rlc_stop(adev);
-       gfx_v9_0_cp_compute_fini(adev);

         return 0;
 }
@@ -2371,14 +2367,18 @@ static int gfx_v9_0_suspend(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+       adev->gfx.in_suspend = true;
         return gfx_v9_0_hw_fini(adev);
 }

 static int gfx_v9_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int r;

-       return gfx_v9_0_hw_init(adev);
+       r = gfx_v9_0_hw_init(adev);
+       adev->gfx.in_suspend = false;
+       return r;
 }

 static bool gfx_v9_0_is_idle(void *handle)
@@ -3753,218 +3753,6 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
         return 0;
 }

-static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
-{
-       int r, j;
-       u32 tmp;
-       bool use_doorbell = true;
-       u64 hqd_gpu_addr;
-       u64 mqd_gpu_addr;
-       u64 eop_gpu_addr;
-       u64 wb_gpu_addr;
-       u32 *buf;
-       struct v9_mqd *mqd;
-       struct amdgpu_device *adev;
-
-       adev = ring->adev;
-       if (ring->mqd_obj == NULL) {
-               r = amdgpu_bo_create(adev,
-                               sizeof(struct v9_mqd),
-                               PAGE_SIZE,true,
-                               AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
-                               NULL, &ring->mqd_obj);
-               if (r) {
-                       dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
-                       return r;
-               }
-       }
-
-       r = amdgpu_bo_reserve(ring->mqd_obj, false);
-       if (unlikely(r != 0)) {
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-
-       r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
-                                 &mqd_gpu_addr);
-       if (r) {
-               dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-       r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
-       if (r) {
-               dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
-               gfx_v9_0_cp_compute_fini(adev);
-               return r;
-       }
-
-       /* init the mqd struct */
-       memset(buf, 0, sizeof(struct v9_mqd));
-
-       mqd = (struct v9_mqd *)buf;
-       mqd->header = 0xC0310800;
-       mqd->compute_pipelinestat_enable = 0x00000001;
-       mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
-       mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
-       mqd->compute_misc_reserved = 0x00000003;
-       mutex_lock(&adev->srbm_mutex);
-       soc15_grbm_select(adev, ring->me,
-                              ring->pipe,
-                              ring->queue, 0);
-       /* disable wptr polling */
-       WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-
-       /* write the EOP addr */
-       BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
-       eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
-       eop_gpu_addr >>= 8;
-
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
-       mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
-       mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
-
-       /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
-                                   (order_base_2(MEC_HPD_SIZE / 4) - 1));
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
-
-       /* enable doorbell? */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-       if (use_doorbell)
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-       else
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
-
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
-       mqd->cp_hqd_pq_doorbell_control = tmp;
-
-       /* disable the queue if it's active */
-       ring->wptr = 0;
-       mqd->cp_hqd_dequeue_request = 0;
-       mqd->cp_hqd_pq_rptr = 0;
-       mqd->cp_hqd_pq_wptr_lo = 0;
-       mqd->cp_hqd_pq_wptr_hi = 0;
-       if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
-               WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
-               for (j = 0; j < adev->usec_timeout; j++) {
-                       if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
-                               break;
-                       udelay(1);
-               }
-               WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-               WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-       }
-
-       /* set the pointer to the MQD */
-       mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
-       mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
-
-       /* set MQD vmid to 0 */
-       tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
-       WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
-       mqd->cp_mqd_control = tmp;
-
-       /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
-       hqd_gpu_addr = ring->gpu_addr >> 8;
-       mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
-       mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
-
-       /* set up the HQD, this is similar to CP_RB0_CNTL */
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
-               (order_base_2(ring->ring_size / 4) - 1));
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
-               ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
-#ifdef __BIG_ENDIAN
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
-#endif
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
-       mqd->cp_hqd_pq_control = tmp;
-
-       /* set the wb address wether it's enabled or not */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
-       mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
-       mqd->cp_hqd_pq_rptr_report_addr_hi =
-       upper_32_bits(wb_gpu_addr) & 0xffff;
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
-               mqd->cp_hqd_pq_rptr_report_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
-               mqd->cp_hqd_pq_rptr_report_addr_hi);
-
-       /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
-       wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-       mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
-       mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
-               mqd->cp_hqd_pq_wptr_poll_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
-               mqd->cp_hqd_pq_wptr_poll_addr_hi);
-
-       /* enable the doorbell if requested */
-       if (use_doorbell) {
-               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
-                       (AMDGPU_DOORBELL64_KIQ * 2) << 2);
-               WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-                       (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
-               tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                       DOORBELL_OFFSET, ring->doorbell_index);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
-               mqd->cp_hqd_pq_doorbell_control = tmp;
-
-       } else {
-               mqd->cp_hqd_pq_doorbell_control = 0;
-       }
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
-               mqd->cp_hqd_pq_doorbell_control);
-
-       /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
-
-       /* set the vmid for the queue */
-       mqd->cp_hqd_vmid = 0;
-       WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
-
-       tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
-       tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
-       WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
-       mqd->cp_hqd_persistent_state = tmp;
-
-       /* activate the queue */
-       mqd->cp_hqd_active = 1;
-       WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
-
-       soc15_grbm_select(adev, 0, 0, 0, 0);
-       mutex_unlock(&adev->srbm_mutex);
-
-       amdgpu_bo_kunmap(ring->mqd_obj);
-       amdgpu_bo_unreserve(ring->mqd_obj);
-
-       if (use_doorbell)
-               WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-
-       return 0;
-}
-
 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
 {
         .type = AMD_IP_BLOCK_TYPE_GFX,
--
2.5.5

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Re: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Andres Rodriguez]

On 2017-04-17 06:00 PM, Alex Deucher wrote:
> KIQ is the Kernel Interface Queue for managing the MEC.  Rather than setting
> up rings via direct MMIO of ring registers, the rings are configured via
> special packets sent to the KIQ.  The allows the MEC to better manage shared
> resources and certain power events. It also reduces the code paths in the
> driver to support and is required for MEC powergating.
>
> v2: drop gfx_v9_0_cp_compute_fini() as well
> v3: rebase on latest changes derived from gfx8, add unmap queues on
> hw_fini
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 374 ++++++++--------------------------
>  1 file changed, 81 insertions(+), 293 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f86a7f6..ef7a3ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1113,23 +1113,21 @@ static int gfx_v9_0_sw_init(void *handle)
>  			return r;
>  	}
>
> -	if (amdgpu_sriov_vf(adev)) {
> -		r = gfx_v9_0_kiq_init(adev);
> -		if (r) {
> -			DRM_ERROR("Failed to init KIQ BOs!\n");
> -			return r;
> -		}
> +	r = gfx_v9_0_kiq_init(adev);
> +	if (r) {
> +		DRM_ERROR("Failed to init KIQ BOs!\n");
> +		return r;
> +	}
>
> -		kiq = &adev->gfx.kiq;
> -		r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
> -		if (r)
> -			return r;
> +	kiq = &adev->gfx.kiq;
> +	r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
> +	if (r)
> +		return r;
>
> -		/* create MQD for all compute queues as wel as KIQ for SRIOV case */
> -		r = gfx_v9_0_compute_mqd_sw_init(adev);
> -		if (r)
> -			return r;
> -	}
> +	/* create MQD for all compute queues as wel as KIQ for SRIOV case */

s/wel/well

Typo was there before, but a good change to fix it.

> +	r = gfx_v9_0_compute_mqd_sw_init(adev);
> +	if (r)
> +		return r;
>
>  	/* reserve GDS, GWS and OA resource for gfx */
>  	r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
> @@ -1176,11 +1174,9 @@ static int gfx_v9_0_sw_fini(void *handle)
>  	for (i = 0; i < adev->gfx.num_compute_rings; i++)
>  		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
>
> -	if (amdgpu_sriov_vf(adev)) {
> -		gfx_v9_0_compute_mqd_sw_fini(adev);
> -		gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
> -		gfx_v9_0_kiq_fini(adev);
> -	}
> +	gfx_v9_0_compute_mqd_sw_fini(adev);
> +	gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
> +	gfx_v9_0_kiq_fini(adev);
>
>  	gfx_v9_0_mec_fini(adev);
>  	gfx_v9_0_ngg_fini(adev);
> @@ -1736,13 +1732,6 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
>  	udelay(50);
>  }
>
> -static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev)
> -{
> -	gfx_v9_0_cp_compute_enable(adev, true);
> -
> -	return 0;
> -}
> -
>  static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
>  {
>  	const struct gfx_firmware_header_v1_0 *mec_hdr;
> @@ -1785,45 +1774,6 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
>  	return 0;
>  }
>
> -static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev)
> -{
> -	int i, r;
> -
> -	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> -		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
> -
> -		if (ring->mqd_obj) {
> -			r = amdgpu_bo_reserve(ring->mqd_obj, false);
> -			if (unlikely(r != 0))
> -				dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
> -
> -			amdgpu_bo_unpin(ring->mqd_obj);
> -			amdgpu_bo_unreserve(ring->mqd_obj);
> -
> -			amdgpu_bo_unref(&ring->mqd_obj);
> -			ring->mqd_obj = NULL;
> -		}
> -	}
> -}
> -
> -static int gfx_v9_0_init_queue(struct amdgpu_ring *ring);
> -
> -static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev)
> -{
> -	int i, r;
> -	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> -		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
> -		if (gfx_v9_0_init_queue(ring))
> -			dev_warn(adev->dev, "compute queue %d init failed!\n", i);
> -	}
> -
> -	r = gfx_v9_0_cp_compute_start(adev);
> -	if (r)
> -		return r;
> -
> -	return 0;
> -}
> -
>  /* KIQ functions */
>  static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
>  {
> @@ -1914,6 +1864,56 @@ static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
>  	return r;
>  }
>
> +static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
> +{
> +	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
> +	uint32_t scratch, tmp = 0;
> +	int r, i;
> +
> +	r = amdgpu_gfx_scratch_get(adev, &scratch);
> +	if (r) {
> +		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
> +		return r;
> +	}
> +	WREG32(scratch, 0xCAFEDEAD);

WREG32_SOC15 needed here I think

> +
> +	r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
> +	if (r) {
> +		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
> +		amdgpu_gfx_scratch_free(adev, scratch);
> +		return r;
> +	}
> +	/* unmap queues */
> +	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
> +	amdgpu_ring_write(kiq_ring,
> +			  PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
> +			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	/* write to scratch for completion */
> +	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> +	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
> +	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
> +	amdgpu_ring_commit(kiq_ring);
> +
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		tmp = RREG32(scratch);
> +		if (tmp == 0xDEADBEEF)
> +			break;
> +		DRM_UDELAY(1);
> +	}
> +	if (i >= adev->usec_timeout) {
> +		DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
> +			  scratch, tmp);
> +		r = -EINVAL;
> +	}
> +	amdgpu_gfx_scratch_free(adev, scratch);
> +
> +	return r;
> +}
> +
>  static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>  {
>  	struct amdgpu_device *adev = ring->adev;
> @@ -2194,7 +2194,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
>  	struct v9_mqd *mqd = ring->mqd_ptr;
>  	int mqd_idx = ring - &adev->gfx.compute_ring[0];
>
> -	if (!adev->gfx.in_reset) {
> +	if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
>  		memset((void *)mqd, 0, sizeof(*mqd));
>  		mutex_lock(&adev->srbm_mutex);
>  		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
> @@ -2285,10 +2285,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>  	if (r)
>  		return r;
>
> -	if (amdgpu_sriov_vf(adev))
> -		r = gfx_v9_0_kiq_resume(adev);
> -	else
> -		r = gfx_v9_0_cp_compute_resume(adev);
> +	r = gfx_v9_0_kiq_resume(adev);
>  	if (r)
>  		return r;
>
> @@ -2298,6 +2295,13 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>  		ring->ready = false;
>  		return r;
>  	}
> +
> +	ring = &adev->gfx.kiq.ring;
> +	ring->ready = true;
> +	r = amdgpu_ring_test_ring(ring);
> +	if (r)
> +		ring->ready = false;
> +
>  	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>  		ring = &adev->gfx.compute_ring[i];
>
> @@ -2307,14 +2311,6 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
>  			ring->ready = false;
>  	}
>
> -	if (amdgpu_sriov_vf(adev)) {
> -		ring = &adev->gfx.kiq.ring;
> -		ring->ready = true;
> -		r = amdgpu_ring_test_ring(ring);
> -		if (r)
> -			ring->ready = false;
> -	}
> -
>  	gfx_v9_0_enable_gui_idle_interrupt(adev, true);
>
>  	return 0;
> @@ -2360,9 +2356,9 @@ static int gfx_v9_0_hw_fini(void *handle)
>  		pr_debug("For SRIOV client, shouldn't do anything.\n");
>  		return 0;
>  	}
> +	gfx_v9_0_kiq_kcq_disable(adev);
>  	gfx_v9_0_cp_enable(adev, false);
>  	gfx_v9_0_rlc_stop(adev);
> -	gfx_v9_0_cp_compute_fini(adev);
>
>  	return 0;
>  }
> @@ -2371,14 +2367,18 @@ static int gfx_v9_0_suspend(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +	adev->gfx.in_suspend = true;
>  	return gfx_v9_0_hw_fini(adev);
>  }
>
>  static int gfx_v9_0_resume(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	int r;
>
> -	return gfx_v9_0_hw_init(adev);
> +	r = gfx_v9_0_hw_init(adev);
> +	adev->gfx.in_suspend = false;
> +	return r;
>  }
>
>  static bool gfx_v9_0_is_idle(void *handle)
> @@ -3753,218 +3753,6 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
>  	return 0;
>  }
>
> -static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
> -{
> -	int r, j;
> -	u32 tmp;
> -	bool use_doorbell = true;
> -	u64 hqd_gpu_addr;
> -	u64 mqd_gpu_addr;
> -	u64 eop_gpu_addr;
> -	u64 wb_gpu_addr;
> -	u32 *buf;
> -	struct v9_mqd *mqd;
> -	struct amdgpu_device *adev;
> -
> -	adev = ring->adev;
> -	if (ring->mqd_obj == NULL) {
> -		r = amdgpu_bo_create(adev,
> -				sizeof(struct v9_mqd),
> -				PAGE_SIZE,true,
> -				AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
> -				NULL, &ring->mqd_obj);
> -		if (r) {
> -			dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
> -			return r;
> -		}
> -	}
> -
> -	r = amdgpu_bo_reserve(ring->mqd_obj, false);
> -	if (unlikely(r != 0)) {
> -		gfx_v9_0_cp_compute_fini(adev);
> -		return r;
> -	}
> -
> -	r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
> -				  &mqd_gpu_addr);
> -	if (r) {
> -		dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
> -		gfx_v9_0_cp_compute_fini(adev);
> -		return r;
> -	}
> -	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
> -	if (r) {
> -		dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
> -		gfx_v9_0_cp_compute_fini(adev);
> -		return r;
> -	}
> -
> -	/* init the mqd struct */
> -	memset(buf, 0, sizeof(struct v9_mqd));
> -
> -	mqd = (struct v9_mqd *)buf;
> -	mqd->header = 0xC0310800;
> -	mqd->compute_pipelinestat_enable = 0x00000001;
> -	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
> -	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
> -	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
> -	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
> -	mqd->compute_misc_reserved = 0x00000003;
> -	mutex_lock(&adev->srbm_mutex);
> -	soc15_grbm_select(adev, ring->me,
> -			       ring->pipe,
> -			       ring->queue, 0);
> -	/* disable wptr polling */
> -	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
> -
> -	/* write the EOP addr */
> -	BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
> -	eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE);
> -	eop_gpu_addr >>= 8;
> -
> -	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr));
> -	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
> -	mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr);
> -	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr);
> -
> -	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
> -	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
> -				    (order_base_2(MEC_HPD_SIZE / 4) - 1));
> -	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp);
> -
> -	/* enable doorbell? */
> -	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
> -	if (use_doorbell)
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
> -	else
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
> -
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
> -	mqd->cp_hqd_pq_doorbell_control = tmp;
> -
> -	/* disable the queue if it's active */
> -	ring->wptr = 0;
> -	mqd->cp_hqd_dequeue_request = 0;
> -	mqd->cp_hqd_pq_rptr = 0;
> -	mqd->cp_hqd_pq_wptr_lo = 0;
> -	mqd->cp_hqd_pq_wptr_hi = 0;
> -	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
> -		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
> -		for (j = 0; j < adev->usec_timeout; j++) {
> -			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
> -				break;
> -			udelay(1);
> -		}
> -		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
> -		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
> -		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
> -		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
> -	}
> -
> -	/* set the pointer to the MQD */
> -	mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
> -	mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
> -	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
> -	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
> -
> -	/* set MQD vmid to 0 */
> -	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
> -	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
> -	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp);
> -	mqd->cp_mqd_control = tmp;
> -
> -	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
> -	hqd_gpu_addr = ring->gpu_addr >> 8;
> -	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
> -	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
> -
> -	/* set up the HQD, this is similar to CP_RB0_CNTL */
> -	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
> -		(order_base_2(ring->ring_size / 4) - 1));
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> -		((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
> -#ifdef __BIG_ENDIAN
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
> -#endif
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp);
> -	mqd->cp_hqd_pq_control = tmp;
> -
> -	/* set the wb address wether it's enabled or not */
> -	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
> -	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
> -	mqd->cp_hqd_pq_rptr_report_addr_hi =
> -	upper_32_bits(wb_gpu_addr) & 0xffff;
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
> -		mqd->cp_hqd_pq_rptr_report_addr_lo);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
> -		mqd->cp_hqd_pq_rptr_report_addr_hi);
> -
> -	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
> -	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> -	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
> -	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
> -		mqd->cp_hqd_pq_wptr_poll_addr_lo);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
> -		mqd->cp_hqd_pq_wptr_poll_addr_hi);
> -
> -	/* enable the doorbell if requested */
> -	if (use_doorbell) {
> -		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
> -			(AMDGPU_DOORBELL64_KIQ * 2) << 2);
> -		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
> -			(AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2);
> -		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -			DOORBELL_OFFSET, ring->doorbell_index);
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
> -		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
> -		mqd->cp_hqd_pq_doorbell_control = tmp;
> -
> -	} else {
> -		mqd->cp_hqd_pq_doorbell_control = 0;
> -	}
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
> -		mqd->cp_hqd_pq_doorbell_control);
> -
> -	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi);
> -
> -	/* set the vmid for the queue */
> -	mqd->cp_hqd_vmid = 0;
> -	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
> -
> -	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
> -	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
> -	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp);
> -	mqd->cp_hqd_persistent_state = tmp;
> -
> -	/* activate the queue */
> -	mqd->cp_hqd_active = 1;
> -	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
> -
> -	soc15_grbm_select(adev, 0, 0, 0, 0);
> -	mutex_unlock(&adev->srbm_mutex);
> -
> -	amdgpu_bo_kunmap(ring->mqd_obj);
> -	amdgpu_bo_unreserve(ring->mqd_obj);
> -
> -	if (use_doorbell)
> -		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
> -
> -	return 0;
> -}
> -
>  const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
>  {
>  	.type = AMD_IP_BLOCK_TYPE_GFX,
>
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Re: [PATCH 01/12] drm/amdgpu/gfx9: fix typo in mpd init

[Andres Rodriguez]

s/mpd/mqd in subject

On 2017-04-17 06:00 PM, Alex Deucher wrote:
> Using the wrong macro for soc15 register access.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 87596e4..6b91805 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1989,12 +1989,12 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>
>  	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
>  	ring->wptr = 0;
> -	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
> +	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
>
>  	/* set the vmid for the queue */
>  	mqd->cp_hqd_vmid = 0;
>
> -	tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
> +	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
>  	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
>  	mqd->cp_hqd_persistent_state = tmp;
>
>
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Re: [PATCH 00/12] KIQ support for gfx9

[Andres Rodriguez]

One comment and two typo nitpicks on the emails.

With those fixed the series is:
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>

Regards,
Andres

On 2017-04-17 06:00 PM, Alex Deucher wrote:
> Basically a port of the recent KIQ work for gfx8 to gfx9.  A couple
> of general bug fixes as well.  Can someone with a vega10 board test
> this?
>
> Alex Deucher (12):
>   drm/amdgpu/gfx9: fix typo in mpd init
>   drm/amdgpu/gfx9: add additional MQD initialization
>   drm/amdgpu/gfx9: create mqd backups
>   drm/amdgpu/gfx9: clear the compute ring on reset
>   drm/amdgpu: add KIQ packet defines to soc15d.h
>   drm/amdgpu/gfx9: use new KIQ packet defines
>   drm/amdgpu/gfx9: wait for completion in KIQ init
>   drm/amdgpu: split gfx_v9_0_kiq_init_queue into two
>   drm/amdgpu/gfx9: wait once for all KCQs to be created
>   drm/amdgpu/gfx9: move SET_RESOURCES into the same command stream
>   drm/amdgpu/gfx9: fix resume of KIQ and KCQs
>   drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring
>     management. (v3)
>
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 570 +++++++++++++---------------------
>  drivers/gpu/drm/amd/amdgpu/soc15d.h   |  82 +++++
>  2 files changed, 292 insertions(+), 360 deletions(-)
>
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Re: [PATCH 12/12] drm/amdgpu/gfx9: Switch baremetal to use KIQ for compute ring management. (v3)

[Tom St Denis]

On 18/04/17 01:00 PM, Andres Rodriguez wrote:

>> +static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
>> +{
>> +    struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
>> +    uint32_t scratch, tmp = 0;
>> +    int r, i;
>> +
>> +    r = amdgpu_gfx_scratch_get(adev, &scratch);
>> +    if (r) {
>> +        DRM_ERROR("Failed to get scratch reg (%d).\n", r);
>> +        return r;
>> +    }
>> +    WREG32(scratch, 0xCAFEDEAD);
> 
> WREG32_SOC15 needed here I think

In the function gfx_v9_0_scratch_init() the offset is initialized with 
GC/0 using a SOC15 macro.  After that you can use normal WREG32/RREG32 
on it.

Tom
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