* One reg interface for Timer register
[not found] <9F6FE96B71CF29479FF1CDC8046E1503545D18@039-SN1MPN1-003.039d.mgd.msft.net>
@ 2013-02-04 6:12 ` Bhushan Bharat-R65777
0 siblings, 0 replies; 4+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-02-04 6:12 UTC (permalink / raw)
To: Yoder Stuart-B08248, Wood Scott-B07421, Alexander Graf; +Cc: kvm-ppc, kvm
Hi Alex/Scott,
Below is my understanding about the ONE_REG interface requirement for timer registers.
Define the below 2 ONE_REG interface for TSR access:
KVM_REG_SET_TSR, // Set the specified bits in TSR
KVM_REG_CLEAR_TSR, // Clear the specified bits in TSR
QEMU will use the above ioctl call to selectively set/clear bits of TSR.
We do not need the similar interface for TCR as there is no race issue with TCR. So for TCR QEMU will keep on using the SREGS interface.
Thanks
-Bharat
^ permalink raw reply [flat|nested] 4+ messages in thread
* One reg interface for Timer register
@ 2013-02-04 6:12 ` Bhushan Bharat-R65777
0 siblings, 0 replies; 4+ messages in thread
From: Bhushan Bharat-R65777 @ 2013-02-04 6:12 UTC (permalink / raw)
To: Yoder Stuart-B08248, Wood Scott-B07421, Alexander Graf; +Cc: kvm-ppc, kvm
Hi Alex/Scott,
Below is my understanding about the ONE_REG interface requirement for timer registers.
Define the below 2 ONE_REG interface for TSR access:
KVM_REG_SET_TSR, // Set the specified bits in TSR
KVM_REG_CLEAR_TSR, // Clear the specified bits in TSR
QEMU will use the above ioctl call to selectively set/clear bits of TSR.
We do not need the similar interface for TCR as there is no race issue with TCR. So for TCR QEMU will keep on using the SREGS interface.
Thanks
-Bharat
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: One reg interface for Timer register
2013-02-04 6:12 ` Bhushan Bharat-R65777
@ 2013-02-07 14:34 ` Alexander Graf
-1 siblings, 0 replies; 4+ messages in thread
From: Alexander Graf @ 2013-02-07 14:34 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Yoder Stuart-B08248, Wood Scott-B07421, kvm-ppc, kvm
On 04.02.2013, at 07:12, Bhushan Bharat-R65777 wrote:
> Hi Alex/Scott,
>
> Below is my understanding about the ONE_REG interface requirement for timer registers.
>
> Define the below 2 ONE_REG interface for TSR access:
> KVM_REG_SET_TSR, // Set the specified bits in TSR
s/SET/OR/
> KVM_REG_CLEAR_TSR, // Clear the specified bits in TSR
>
> QEMU will use the above ioctl call to selectively set/clear bits of TSR.
Exactly :).
> We do not need the similar interface for TCR as there is no race issue with TCR. So for TCR QEMU will keep on using the SREGS interface.
Good point, yes :).
Alex
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: One reg interface for Timer register
@ 2013-02-07 14:34 ` Alexander Graf
0 siblings, 0 replies; 4+ messages in thread
From: Alexander Graf @ 2013-02-07 14:34 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Yoder Stuart-B08248, Wood Scott-B07421, kvm-ppc, kvm
On 04.02.2013, at 07:12, Bhushan Bharat-R65777 wrote:
> Hi Alex/Scott,
>
> Below is my understanding about the ONE_REG interface requirement for timer registers.
>
> Define the below 2 ONE_REG interface for TSR access:
> KVM_REG_SET_TSR, // Set the specified bits in TSR
s/SET/OR/
> KVM_REG_CLEAR_TSR, // Clear the specified bits in TSR
>
> QEMU will use the above ioctl call to selectively set/clear bits of TSR.
Exactly :).
> We do not need the similar interface for TCR as there is no race issue with TCR. So for TCR QEMU will keep on using the SREGS interface.
Good point, yes :).
Alex
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-02-07 14:34 UTC | newest]
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[not found] <9F6FE96B71CF29479FF1CDC8046E1503545D18@039-SN1MPN1-003.039d.mgd.msft.net>
2013-02-04 6:12 ` One reg interface for Timer register Bhushan Bharat-R65777
2013-02-04 6:12 ` Bhushan Bharat-R65777
2013-02-07 14:34 ` Alexander Graf
2013-02-07 14:34 ` Alexander Graf
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