From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
devicetree@vger.kernel.org
Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 08/12] ARM: dts: r8a7792: add [H]SCIF support
Date: Mon, 13 Jun 2016 00:09:42 +0300 [thread overview]
Message-ID: <4960519.xV8itPzGGv@wasted.cogentembedded.com> (raw)
In-Reply-To: <14666252.G84Ipxe6EL@wasted.cogentembedded.com>
Describe [H]SCIFs in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- resolved reject, indenting the device nodes that are now under the "soc" node;
- added Geert's tag.
arch/arm/boot/dts/r8a7792.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -152,6 +152,96 @@
dma-channels = <15>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
WARNING: multiple messages have this Message-ID (diff)
From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 08/12] ARM: dts: r8a7792: add [H]SCIF support
Date: Mon, 13 Jun 2016 00:09:42 +0300 [thread overview]
Message-ID: <4960519.xV8itPzGGv@wasted.cogentembedded.com> (raw)
In-Reply-To: <14666252.G84Ipxe6EL@wasted.cogentembedded.com>
Describe [H]SCIFs in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 3:
- refreshed the patch.
Changes in version 2:
- resolved reject, indenting the device nodes that are now under the "soc" node;
- added Geert's tag.
arch/arm/boot/dts/r8a7792.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -152,6 +152,96 @@
dma-channels = <15>;
};
+ scif0: serial at e6e60000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial at e6e68000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial at e6e58000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 64>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial at e6ea8000 {
+ compatible = "renesas,scif-r8a7792",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial at e62c0000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 96>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial at e62c8000 {
+ compatible = "renesas,hscif-r8a7792",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
/* Special CPG clocks */
cpg_clocks: cpg_clocks at e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
next prev parent reply other threads:[~2016-06-12 21:09 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-12 20:47 [PATCH v5 00/12] Add R8A7792/Blanche board support Sergei Shtylyov
2016-06-12 20:47 ` Sergei Shtylyov
2016-06-12 20:53 ` [PATCH v5 01/12] ARM: shmobile: r8a7792: add clock index macros Sergei Shtylyov
2016-06-12 20:54 ` [PATCH v5 02/12] ARM: shmobile: r8a7792: add power domain " Sergei Shtylyov
2016-06-12 20:56 ` [PATCH v5 03/12] soc: renesas: rcar-sysc: add R8A7792 support Sergei Shtylyov
2016-06-12 21:01 ` [PATCH v5 04/12] ARM: shmobile: r8a7792: basic SoC support Sergei Shtylyov
2016-06-12 21:01 ` Sergei Shtylyov
2016-06-12 21:04 ` [PATCH v5 05/12] ARM: shmobile: r8a7792: add SMP support Sergei Shtylyov
2016-06-12 21:04 ` Sergei Shtylyov
2016-06-15 2:30 ` Simon Horman
2016-06-15 2:30 ` Simon Horman
2016-06-15 10:43 ` Sergei Shtylyov
2016-06-15 10:43 ` Sergei Shtylyov
2016-06-16 5:19 ` Simon Horman
2016-06-16 5:19 ` Simon Horman
2016-06-12 21:06 ` [PATCH v5 06/12] ARM: dts: r8a7792: initial SoC device tree Sergei Shtylyov
2016-06-12 21:06 ` Sergei Shtylyov
2016-06-12 21:08 ` [PATCH v5 07/12] ARM: dts: r8a7792: add SYS-DMAC support Sergei Shtylyov
2016-06-12 21:08 ` Sergei Shtylyov
2016-06-12 21:09 ` Sergei Shtylyov [this message]
2016-06-12 21:09 ` [PATCH v5 08/12] ARM: dts: r8a7792: add [H]SCIF support Sergei Shtylyov
2016-06-12 21:12 ` [PATCH v5 09/12] ARM: dts: r8a7792: add IRQC support Sergei Shtylyov
2016-06-12 21:12 ` Sergei Shtylyov
2016-06-12 21:14 ` [PATCH v5 10/12] DT: arm: shmobile: document Blanche board Sergei Shtylyov
2016-06-12 21:15 ` [PATCH v5 11/12] ARM: dts: blanche: initial device tree Sergei Shtylyov
2016-06-12 21:15 ` Sergei Shtylyov
2016-06-12 21:17 ` [PATCH v5 12/12] ARM: dts: blanche: add Ethernet support Sergei Shtylyov
2016-06-12 21:17 ` Sergei Shtylyov
2016-06-20 22:31 ` [PATCH] ARM: dts: r8a7792: add SMP support Sergei Shtylyov
2016-06-20 22:31 ` Sergei Shtylyov
2016-06-20 22:31 ` Sergei Shtylyov
[not found] ` <1627631.X1bJtVQHBF-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-06-21 7:10 ` Geert Uytterhoeven
2016-06-21 7:10 ` Geert Uytterhoeven
2016-06-21 7:10 ` Geert Uytterhoeven
2016-06-29 16:46 ` Sergei Shtylyov
2016-06-29 16:46 ` Sergei Shtylyov
2016-06-30 12:27 ` Simon Horman
2016-06-30 12:27 ` Simon Horman
2016-06-30 17:52 ` Sergei Shtylyov
2016-06-30 17:52 ` Sergei Shtylyov
2016-06-21 22:03 ` [PATCH] ARM: dts: r8a7794: " Sergei Shtylyov
2016-06-21 22:03 ` Sergei Shtylyov
2016-06-21 22:03 ` Sergei Shtylyov
[not found] ` <27171008.uuY7altQup-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-06-22 7:20 ` Geert Uytterhoeven
2016-06-22 7:20 ` Geert Uytterhoeven
2016-06-22 7:20 ` Geert Uytterhoeven
2016-06-22 10:08 ` Sergei Shtylyov
2016-06-22 10:08 ` Sergei Shtylyov
2016-06-22 10:08 ` Sergei Shtylyov
2016-06-22 10:20 ` Geert Uytterhoeven
2016-06-22 10:20 ` Geert Uytterhoeven
2016-06-23 8:11 ` Geert Uytterhoeven
2016-06-23 8:11 ` Geert Uytterhoeven
2018-05-08 16:39 ` [PATCH] arm64: dts: renesas: r8a77970: " Sergei Shtylyov
2018-05-08 16:39 ` Sergei Shtylyov
2018-05-08 18:40 ` Geert Uytterhoeven
2018-05-08 18:40 ` Geert Uytterhoeven
2018-05-08 18:40 ` Geert Uytterhoeven
2018-05-08 18:47 ` Sergei Shtylyov
2018-05-08 18:47 ` Sergei Shtylyov
2018-05-08 18:47 ` Sergei Shtylyov
2018-05-09 19:05 ` Simon Horman
2018-05-09 19:05 ` Simon Horman
2018-05-09 19:05 ` Simon Horman
2018-05-10 16:43 ` Sergei Shtylyov
2018-05-10 16:43 ` Sergei Shtylyov
2018-05-10 16:43 ` Sergei Shtylyov
2018-05-12 14:08 ` Simon Horman
2018-05-12 14:08 ` Simon Horman
2018-05-12 14:08 ` Simon Horman
2018-05-17 20:19 ` [PATCH] arm64: dts: renesas: r8a77980: " Sergei Shtylyov
2018-05-17 20:19 ` Sergei Shtylyov
2018-05-17 20:23 ` Geert Uytterhoeven
2018-05-17 20:23 ` Geert Uytterhoeven
2018-05-17 20:23 ` Geert Uytterhoeven
2018-05-19 17:38 ` Sergei Shtylyov
2018-05-19 17:38 ` Sergei Shtylyov
2018-05-19 17:38 ` Sergei Shtylyov
2018-05-22 8:54 ` Simon Horman
2018-05-22 8:54 ` Simon Horman
2018-05-22 8:54 ` Simon Horman
2018-05-22 9:49 ` Geert Uytterhoeven
2018-05-22 9:49 ` Geert Uytterhoeven
2018-05-22 9:49 ` Geert Uytterhoeven
2018-05-23 8:30 ` Simon Horman
2018-05-23 8:30 ` Simon Horman
2018-05-23 8:30 ` Simon Horman
2018-05-22 8:54 ` Simon Horman
2018-05-22 8:54 ` Simon Horman
2018-05-22 8:54 ` Simon Horman
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