[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Sanjeev Premi]

The function display_board_info() displays incorrect
silicon revision - based on the return value from
function get_cpu_rev().

This patch fixes the problem.

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 cpu/arm_cortexa8/cpu.c             |    4 ++--
 cpu/arm_cortexa8/omap3/clock.c     |    5 +++--
 cpu/arm_cortexa8/omap3/sys_info.c  |   30 ++++++++++++++++++++++--------
 include/asm-arm/arch-omap3/omap3.h |   10 ++++++++--
 4 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 5e7b935..3e1780b 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -101,7 +101,7 @@ void l2cache_enable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -131,7 +131,7 @@ void l2cache_disable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 8ac31be..d035677 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -132,7 +132,7 @@ void prcm_init(void)
 	void (*f_lock_pll) (u32, u32, u32, u32);
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
-	u32 clk_index, sil_index;
+	u32 clk_index, sil_index = 0;
 	prm_t *prm_base = (prm_t *)PRM_BASE;
 	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
 	dpll_param *dpll_param_p;
@@ -170,7 +170,8 @@ void prcm_init(void)
 	 * and sil_index will get the values for that SysClk for the
 	 * appropriate silicon rev.
 	 */
-	sil_index = get_cpu_rev() - 1;
+	if (get_cpu_rev())
+		sil_index = 1;
 
 	/* Unlock MPU DPLL (slows things down, and needed later) */
 	sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index 80f6e5e..9246790 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo;
 static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
 static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
 static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static char *rev_s[CPU_3XX_MAX_REV] = {
+				"1.0",
+				"2.0",
+				"2.1",
+				"3.0",
+				"3.1"};
 
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
@@ -76,18 +82,27 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
+	ctrl_id_t *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4
-	 * so using CPU ID to differentiate
-	 * between ES2.0 and ES1.0.
+	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 	 */
 	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 	if ((cpuid & 0xf) == 0x0)
-		return CPU_3430_ES1;
-	else
-		return CPU_3430_ES2;
+		return CPU_3XX_ES10;
+	else {
+		/* Decode the IDs on > ES1.0 */
+		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+
+		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xff;
+
+		/* Some early ES2.0 seem to report ID 0, fix this */
+		if(cpuid == 0)
+			cpuid = CPU_3XX_ES20;
 
+		return cpuid;
+	}
 }
 
 /****************************************************
@@ -215,9 +230,8 @@ void display_board_info(void)
 		sec_s = "?";
 	}
 
-
-	printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
-	       sec_s, get_cpu_rev());
+	printf("OMAP%s-%s [ES%s], CPU-OPP2 L3-165MHz\n", cpu_s,
+	       sec_s, rev_s[get_cpu_rev()]);
 	printf("%s + %s/%s\n", sysinfo.board_string,
 	       mem_s, sysinfo.nand_string);
 
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index d0d2737..8cce18b 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -171,8 +171,14 @@ typedef struct gpio {
  * ES1     = 0+1 = 1
  * ES1     = 1+1 = 1
  */
-#define CPU_3430_ES1		1
-#define CPU_3430_ES2		2
+#define CPU_3XX_ES10		0
+#define CPU_3XX_ES20		1
+#define CPU_3XX_ES21		2
+#define CPU_3XX_ES30		3
+#define CPU_3XX_ES31		4
+#define CPU_3XX_MAX_REV		(CPU_3XX_ES31 + 1)
+
+#define CPU_3XX_ID_SHIFT	28
 
 #define WIDTH_8BIT		0x0000
 #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
-- 
1.6.2.1

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Jean-Christophe PLAGNIOL-VILLARD]

On 20:22 Fri 24 Apr     , Sanjeev Premi wrote:
> The function display_board_info() displays incorrect
> silicon revision - based on the return value from
> function get_cpu_rev().
> 
> This patch fixes the problem.

two comment on the omap3
first for the cp15 we have the get/set_cr API it will be nice to use it
and the omap3 specific l2 cache management need to be moved to the soc no the
arch as currenty

Best Regards,
J.

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Dirk Behme]

Sanjeev Premi wrote:
> The function display_board_info() displays incorrect
> silicon revision - based on the return value from
> function get_cpu_rev().
> 
> This patch fixes the problem.
> 
> Signed-off-by: Sanjeev Premi <premi@ti.com>

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Tested-by: Dirk Behme <dirk.behme@googlemail.com>

> ---
>  cpu/arm_cortexa8/cpu.c             |    4 ++--
>  cpu/arm_cortexa8/omap3/clock.c     |    5 +++--
>  cpu/arm_cortexa8/omap3/sys_info.c  |   30 ++++++++++++++++++++++--------
>  include/asm-arm/arch-omap3/omap3.h |   10 ++++++++--
>  4 files changed, 35 insertions(+), 14 deletions(-)
> 
> diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
> index 5e7b935..3e1780b 100644
> --- a/cpu/arm_cortexa8/cpu.c
> +++ b/cpu/arm_cortexa8/cpu.c
> @@ -101,7 +101,7 @@ void l2cache_enable()
>  	volatile unsigned int j;
>  
>  	/* ES2 onwards we can disable/enable L2 ourselves */
> -	if (get_cpu_rev() == CPU_3430_ES2) {
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
>  		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
>  		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
>  		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> @@ -131,7 +131,7 @@ void l2cache_disable()
>  	volatile unsigned int j;
>  
>  	/* ES2 onwards we can disable/enable L2 ourselves */
> -	if (get_cpu_rev() == CPU_3430_ES2) {
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
>  		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
>  		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
>  		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
> index 8ac31be..d035677 100644
> --- a/cpu/arm_cortexa8/omap3/clock.c
> +++ b/cpu/arm_cortexa8/omap3/clock.c
> @@ -132,7 +132,7 @@ void prcm_init(void)
>  	void (*f_lock_pll) (u32, u32, u32, u32);
>  	int xip_safe, p0, p1, p2, p3;
>  	u32 osc_clk = 0, sys_clkin_sel;
> -	u32 clk_index, sil_index;
> +	u32 clk_index, sil_index = 0;
>  	prm_t *prm_base = (prm_t *)PRM_BASE;
>  	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
>  	dpll_param *dpll_param_p;
> @@ -170,7 +170,8 @@ void prcm_init(void)
>  	 * and sil_index will get the values for that SysClk for the
>  	 * appropriate silicon rev.
>  	 */
> -	sil_index = get_cpu_rev() - 1;
> +	if (get_cpu_rev())
> +		sil_index = 1;
>  
>  	/* Unlock MPU DPLL (slows things down, and needed later) */
>  	sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
> diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
> index 80f6e5e..9246790 100644
> --- a/cpu/arm_cortexa8/omap3/sys_info.c
> +++ b/cpu/arm_cortexa8/omap3/sys_info.c
> @@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo;
>  static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
>  static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
>  static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
> +static char *rev_s[CPU_3XX_MAX_REV] = {
> +				"1.0",
> +				"2.0",
> +				"2.1",
> +				"3.0",
> +				"3.1"};
>  
>  /*****************************************************************
>   * dieid_num_r(void) - read and set die ID
> @@ -76,18 +82,27 @@ u32 get_cpu_type(void)
>  u32 get_cpu_rev(void)
>  {
>  	u32 cpuid = 0;
> +	ctrl_id_t *id_base;
>  
>  	/*
>  	 * On ES1.0 the IDCODE register is not exposed on L4
> -	 * so using CPU ID to differentiate
> -	 * between ES2.0 and ES1.0.
> +	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
>  	 */
>  	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
>  	if ((cpuid & 0xf) == 0x0)
> -		return CPU_3430_ES1;
> -	else
> -		return CPU_3430_ES2;
> +		return CPU_3XX_ES10;
> +	else {
> +		/* Decode the IDs on > ES1.0 */
> +		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
> +
> +		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xff;
> +
> +		/* Some early ES2.0 seem to report ID 0, fix this */
> +		if(cpuid == 0)
> +			cpuid = CPU_3XX_ES20;
>  
> +		return cpuid;
> +	}
>  }
>  
>  /****************************************************
> @@ -215,9 +230,8 @@ void display_board_info(void)
>  		sec_s = "?";
>  	}
>  
> -
> -	printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
> -	       sec_s, get_cpu_rev());
> +	printf("OMAP%s-%s [ES%s], CPU-OPP2 L3-165MHz\n", cpu_s,
> +	       sec_s, rev_s[get_cpu_rev()]);
>  	printf("%s + %s/%s\n", sysinfo.board_string,
>  	       mem_s, sysinfo.nand_string);
>  
> diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
> index d0d2737..8cce18b 100644
> --- a/include/asm-arm/arch-omap3/omap3.h
> +++ b/include/asm-arm/arch-omap3/omap3.h
> @@ -171,8 +171,14 @@ typedef struct gpio {
>   * ES1     = 0+1 = 1
>   * ES1     = 1+1 = 1
>   */
> -#define CPU_3430_ES1		1
> -#define CPU_3430_ES2		2
> +#define CPU_3XX_ES10		0
> +#define CPU_3XX_ES20		1
> +#define CPU_3XX_ES21		2
> +#define CPU_3XX_ES30		3
> +#define CPU_3XX_ES31		4
> +#define CPU_3XX_MAX_REV		(CPU_3XX_ES31 + 1)
> +
> +#define CPU_3XX_ID_SHIFT	28
>  
>  #define WIDTH_8BIT		0x0000
>  #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Wolfgang Denk]

Dear Jean-Christophe PLAGNIOL-VILLARD,

In message <20090424164644.GC2953@game.jcrosoft.org> you wrote:
> On 20:22 Fri 24 Apr     , Sanjeev Premi wrote:
> > The function display_board_info() displays incorrect
> > silicon revision - based on the return value from
> > function get_cpu_rev().
> > 
> > This patch fixes the problem.
> 
> two comment on the omap3
> first for the cp15 we have the get/set_cr API it will be nice to use it
> and the omap3 specific l2 cache management need to be moved to the soc no the
> arch as currenty

But this is outside the scope of this patch, isn;t it?

I mean, you will apply this patch, right?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Wenn das dann in die Hose geht, nehme ich es auf meine Kappe.
                                         -- Rudi V?ller, 15. Nov 2003

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:49 Fri 24 Apr     , Dirk Behme wrote:
> Sanjeev Premi wrote:
> > The function display_board_info() displays incorrect
> > silicon revision - based on the return value from
> > function get_cpu_rev().
> > 
> > This patch fixes the problem.
> > 
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> 
> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
> Tested-by: Dirk Behme <dirk.behme@googlemail.com>

why the twice?

Best Regards,
J.

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Dirk Behme]

Dear Jean-Christophe,

Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:49 Fri 24 Apr     , Dirk Behme wrote:
>> Sanjeev Premi wrote:
>>> The function display_board_info() displays incorrect
>>> silicon revision - based on the return value from
>>> function get_cpu_rev().
>>>
>>> This patch fixes the problem.
>>>
>>> Signed-off-by: Sanjeev Premi <premi@ti.com>
>> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
>> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
> 
> why the twice?

I wanted to mention that I helped developing these patches and that I 
tested them on real HW.

http://kerneltrap.org/node/8329:

"The Signed-off-by: tag implies that the signer was involved in the 
development of the patch"

"Tested-by ... it's very useful information to have. For a start, it 
tells you who has the hardware and knows how to build ..."

If you think one is enough, remove what you don't like ;)

Dirk

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Jean-Christophe PLAGNIOL-VILLARD]

On 22:40 Fri 24 Apr     , Dirk Behme wrote:
> Dear Jean-Christophe,
>
> Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 18:49 Fri 24 Apr     , Dirk Behme wrote:
>>> Sanjeev Premi wrote:
>>>> The function display_board_info() displays incorrect
>>>> silicon revision - based on the return value from
>>>> function get_cpu_rev().
>>>>
>>>> This patch fixes the problem.
>>>>
>>>> Signed-off-by: Sanjeev Premi <premi@ti.com>
>>> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
>>> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
>>
>> why the twice?
>
> I wanted to mention that I helped developing these patches and that I  
> tested them on real HW.
what do you mean by help?
review or dev?
if it's review I do not think the sob is correct

Best Regards,
J.

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Ben Warren]

Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:40 Fri 24 Apr     , Dirk Behme wrote:
>   
>> Dear Jean-Christophe,
>>
>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>     
>>> On 18:49 Fri 24 Apr     , Dirk Behme wrote:
>>>       
>>>> Sanjeev Premi wrote:
>>>>         
>>>>> The function display_board_info() displays incorrect
>>>>> silicon revision - based on the return value from
>>>>> function get_cpu_rev().
>>>>>
>>>>> This patch fixes the problem.
>>>>>
>>>>> Signed-off-by: Sanjeev Premi <premi@ti.com>
>>>>>           
>>>> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
>>>> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
>>>>         
>>> why the twice?
>>>       
>> I wanted to mention that I helped developing these patches and that I  
>> tested them on real HW.
>>     
> what do you mean by help?
> review or dev?
> if it's review I do not think the sob is correct
>
>   
Seriously, who cares?  This extra information doesn't hurt anything so 
let it pass.

--Ben

[U-Boot] Using Signed-off-by, was: OMAP3: Print correct silicon revision

[Dirk Behme]

Dear Jean-Christophe,

Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 22:40 Fri 24 Apr     , Dirk Behme wrote:
>> Dear Jean-Christophe,
>>
>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 18:49 Fri 24 Apr     , Dirk Behme wrote:
>>>> Sanjeev Premi wrote:
>>>>> The function display_board_info() displays incorrect
>>>>> silicon revision - based on the return value from
>>>>> function get_cpu_rev().
>>>>>
>>>>> This patch fixes the problem.
>>>>>
>>>>> Signed-off-by: Sanjeev Premi <premi@ti.com>
>>>> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
>>>> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
>>> why the twice?
>> I wanted to mention that I helped developing these patches and that I  
>> tested them on real HW.
> what do you mean by help?
> review or dev?

Sorry, but I can't see what might be unclear with the string 'helped 
developing' I used regarding your question.

> if it's review I do not think the sob is correct

Please elaborate more why in review case you think sob is not correct?

Dirk

[U-Boot] [PATCH 2/2] OMAP3: Print correct silicon revision

[Dirk Behme]

Ben Warren wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 22:40 Fri 24 Apr     , Dirk Behme wrote:
>>  
>>> Dear Jean-Christophe,
>>>
>>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>    
>>>> On 18:49 Fri 24 Apr     , Dirk Behme wrote:
>>>>      
>>>>> Sanjeev Premi wrote:
>>>>>        
>>>>>> The function display_board_info() displays incorrect
>>>>>> silicon revision - based on the return value from
>>>>>> function get_cpu_rev().
>>>>>>
>>>>>> This patch fixes the problem.
>>>>>>
>>>>>> Signed-off-by: Sanjeev Premi <premi@ti.com>
>>>>>>           
>>>>> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
>>>>> Tested-by: Dirk Behme <dirk.behme@googlemail.com>
>>>>>         
>>>> why the twice?
>>>>       
>>> I wanted to mention that I helped developing these patches and that 
>>> I  tested them on real HW.
>>>     
>> what do you mean by help?
>> review or dev?
>> if it's review I do not think the sob is correct
>>
>>   
> Seriously, who cares?  This extra information doesn't hurt anything so 
> let it pass.

Yes, totally agreed. Thanks.

Best regards

Dirk