From: Samuel Holland <samuel@sholland.org>
To: Andre Przywara <andre.przywara@arm.com>,
Jagan Teki <jagan@amarulasolutions.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 1/2] clk: sunxi: add PIO bus gate clocks
Date: Fri, 6 May 2022 20:47:07 -0500 [thread overview]
Message-ID: <49a100f1-9bd8-9334-b58e-6288209906bf@sholland.org> (raw)
In-Reply-To: <20220506003301.13194-2-andre.przywara@arm.com>
On 5/5/22 7:33 PM, Andre Przywara wrote:
> The introduction of the DM pinctrl driver made its probe function enable
> all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
> variations) gate clock, but also CLK_PLL_PERIPH0. So far we didn't
I believe the use of CLK_PLL_PERIPH0 is from the R_CCU driver, so it is not
directly related to the introduction of DM pinctrl.
> describe those clocks in our clock driver.
> As we enable them already in the SPL, the devices happen to work, but
> the clock driver still complains about not finding those clocks:
> =========
> sunxi_set_gate: (CLK#58) unhandled
> =========
>
> Add the one-liners that are needed to announce the gate bit for those
> clocks, to silence that message on the console.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
next prev parent reply other threads:[~2022-05-07 1:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-06 0:32 [PATCH 0/2] sunxi: clk: fix unhandled clocks warnings Andre Przywara
2022-05-06 0:33 ` [PATCH 1/2] clk: sunxi: add PIO bus gate clocks Andre Przywara
2022-05-07 1:47 ` Samuel Holland [this message]
2022-05-24 16:12 ` Andre Przywara
2022-05-06 0:33 ` [PATCH 2/2] clk: sunxi: add and use dummy " Andre Przywara
2022-05-09 5:00 ` Samuel Holland
2022-05-24 16:13 ` Andre Przywara
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