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* [OpenRISC] ORPSoC in ISE project navigator/Quartus
@ 2016-12-14 10:17 Masoud Man
  2016-12-14 14:05 ` Olof Kindgren
  0 siblings, 1 reply; 3+ messages in thread
From: Masoud Man @ 2016-12-14 10:17 UTC (permalink / raw)
  To: openrisc


Hello friends,
Has anyone used openRISC design in Xilinx ISE project Navigator or Quartus softwares (GUI based not with makefile)?
I have some small questions, thanks.

Best Regards
Masoud



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* [OpenRISC] ORPSoC in ISE project navigator/Quartus
  2016-12-14 10:17 [OpenRISC] ORPSoC in ISE project navigator/Quartus Masoud Man
@ 2016-12-14 14:05 ` Olof Kindgren
  2016-12-14 14:54   ` Masoud Man
  0 siblings, 1 reply; 3+ messages in thread
From: Olof Kindgren @ 2016-12-14 14:05 UTC (permalink / raw)
  To: openrisc

On Wed, Dec 14, 2016 at 11:17 AM, Masoud Man <masoud.mansouryar@gmail.com>
wrote:

>
> Hello friends,
> Has anyone used openRISC design in Xilinx ISE project Navigator or Quartus
> softwares (GUI based not with makefile)?
> I have some small questions, thanks.
>
> Best Regards
> Masoud
>
>
>
>
> _______________________________________________
> OpenRISC mailing list
> OpenRISC at lists.librecores.org
> https://lists.librecores.org/listinfo/openrisc
>
>
What kind of questions?

If you're using FuseSoC, it will automatically generate project files for
you. I sometimes use the GUI to do the implementation, but mostly let
FuseSoC build the whole thing

//Oof
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* [OpenRISC] ORPSoC in ISE project navigator/Quartus
  2016-12-14 14:05 ` Olof Kindgren
@ 2016-12-14 14:54   ` Masoud Man
  0 siblings, 0 replies; 3+ messages in thread
From: Masoud Man @ 2016-12-14 14:54 UTC (permalink / raw)
  To: openrisc


Dear Olof,
Thank you for your suggestion. I am actually working on a modification of ORPSoC design, and following this workflow (OpenRISC 1200):
http://www.rte.se/blog/blogg-modesty-corex/index <http://www.rte.se/blog/blogg-modesty-corex/index>

But in the simulation part when I use Fuse command, I get errors which I cannot solve. That’s why I want to try GUI since it’s easier to simulate and debug.
Would you tell me the Verilog sources needed to add in my ISE hierarchy for synthesis please?

Thanks
Masoud





> On 14 Dec 2016, at 15:05, Olof Kindgren <olof.kindgren@gmail.com> wrote:
> 
> FuseSoC

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