[U-Boot] [PATCH RFC 0/2] dcache on ARM

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Alessandro Rubini]

These patches enable the dcache for ARM9.  It's mainly an RFC, as some
details are still to be sorted out, but they work fine (and the speed
increase is noticeable for kernel boots and cp.b -- didn't make more
tests.

I tested the code on at91sam9263ek and nhk8815. No makeall at this
point, as I'm mainly interested in comments here.

This is based on the cache-cp15.c infrastructure set up by
Jean-Christophe for icache enabling.

I'm sure Drasko Draskovic has better code, but since he has sent
no a patch yet (asked in Mar 2009, and then again and again),
here is my approach.

Alessandro Rubini (2):
  flush cache for arm926
  arm cp15: setup mmu and enable dcache

 lib_arm/cache-cp15.c |   37 +++++++++++++++++++++++++++++++++++++
 lib_arm/cache.c      |    6 ++++++
 2 files changed, 43 insertions(+), 0 deletions(-)

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Nick Thompson]

On 26/01/10 16:16, Alessandro Rubini wrote:
> These patches enable the dcache for ARM9.  It's mainly an RFC, as some
> details are still to be sorted out, but they work fine (and the speed
> increase is noticeable for kernel boots and cp.b -- didn't make more
> tests.

I'm all for speed increases :-)

On TI DA830, the 1.0 & 1.1 revision of the silicon have a data caching
bug. You can use data caching, but only in write thru' mode. This is
fixed in the very latest 2.0 silicon. Even still it is better than
no caching as proved in Linux.

Is it simple for you to enable different levels of caching by config?

Nick.

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Armando VISCONTI]

Alessandro,

I don't see the flush_cache() call inside cmd_bootm.c.
Don't you think it is necessary before jumping to Linux?
Or am I missing something?

Rgds,
Arm

Alessandro Rubini wrote:
> These patches enable the dcache for ARM9.  It's mainly an RFC, as some
> details are still to be sorted out, but they work fine (and the speed
> increase is noticeable for kernel boots and cp.b -- didn't make more
> tests.
>
> I tested the code on at91sam9263ek and nhk8815. No makeall at this
> point, as I'm mainly interested in comments here.
>
> This is based on the cache-cp15.c infrastructure set up by
> Jean-Christophe for icache enabling.
>
> I'm sure Drasko Draskovic has better code, but since he has sent
> no a patch yet (asked in Mar 2009, and then again and again),
> here is my approach.
>
> Alessandro Rubini (2):
>   flush cache for arm926
>   arm cp15: setup mmu and enable dcache
>
>  lib_arm/cache-cp15.c |   37 +++++++++++++++++++++++++++++++++++++
>  lib_arm/cache.c      |    6 ++++++
>  2 files changed, 43 insertions(+), 0 deletions(-)
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>   


-- 
-- "Every step appears to be the unavoidable consequence of the
-- preceding one." (A. Einstein) 
-- 
Armando Visconti                  Mobile: (+39) 346 8879146
Senior SW Engineer                Fax:    (+39) 02 93519290
CPG                               Work:   (+39) 02 93519683
Computer System Division          e-mail: armando.visconti at st.com
ST Microelectronics               TINA:   051  4683
                                    
 

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Alessandro Rubini]

> I don't see the flush_cache() call inside cmd_bootm.c.
> Don't you think it is necessary before jumping to Linux?

Yes, definitely. Actually, I checked it, but re-checking now I see
I've been tricked by '[id]cache_disable' being grepped successfully in
common/cmd_bootm.c . However, it's inside a false ifdef.

I'm booting through the network, so that's probably why it works
reliably for me (netboot_common does the propre flushing).

> Or am I missing something?

Not at all, thanks for catching this.

/alessandro

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Armando VISCONTI]

>
>> I don't see the flush_cache() call inside cmd_bootm.c.
>> Don't you think it is necessary before jumping to Linux?
>>     
>
> Yes, definitely. Actually, I checked it, but re-checking now I see
> I've been tricked by '[id]cache_disable' being grepped successfully in
> common/cmd_bootm.c . However, it's inside a false ifdef.
>
> I'm booting through the network, so that's probably why it works
> reliably for me (netboot_common does the propre flushing).
>   
Right, cache_disable() should be called to do the proper
job, i.e. cache disabling and flushing.

OK, we can wait for more comments but if there are no other architectural
drawbacks I can't think of I'm willing to test it on
SPEAr achitecture as well. Actually I have always thought about
enabling dcache, but too lazy to implement/verify it :-(

Thx,
Arm



-- 
-- "Every step appears to be the unavoidable consequence of the
-- preceding one." (A. Einstein) 
-- 
Armando Visconti                  Mobile: (+39) 346 8879146
Senior SW Engineer                Fax:    (+39) 02 93519290
CPG                               Work:   (+39) 02 93519683
Computer System Division          e-mail: armando.visconti at st.com
ST Microelectronics               TINA:   051  4683
                                    
 

[U-Boot] [PATCH RFC 0/2] dcache on ARM

[Alessandro Rubini]

Hello Nick.

> On TI DA830, the 1.0 & 1.1 revision of the silicon have a data caching
> bug. You can use data caching, but only in write thru' mode.

I see. So instead of both C and B you just need to C bit set in the
page table, and no B.

I propose to allow an extra option for write-back, leaving
write-through as the default. This matches the blackfin, which has
CONFIG_DCACHE_WB as an option, and leaves a safer default for those
who won't explicitly require WB policy.

Could you please confirm my patch works on that board after changing
the magic bits from 0x1e to 0x1a ? (I'll use symbolic constants
anyways in V2, this was just a quick RFC to see if the approach is
acceptable).

/alessandro