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* [U-Boot] [PATCH 1/5] nios2: add nios2-generic board
@ 2010-03-31  0:50 Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
                   ` (6 more replies)
  0 siblings, 7 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  0:50 UTC (permalink / raw)
  To: u-boot

This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot

In order to better support MMU and NOMMU targets, we will use
virtual addressing in the config file. All references to devices
except for the main memory (sdram), should be mapped to uncached
(bypass), IO region. While the main memory should use cached,
kernel region.

In stead of editing the hex number of base address, we will use
the resource header file generated with Altera SOPC tools.

For example the SMC device def will become,
#define CONFIG_SMC91111_BASE	((LAN91C111_BASE + \
  LAN91C111_LAN91C111_REGISTERS_OFFSET) \
 | IO_REGION_BASE) /* Base addr	*/
where the LAN91C111_xxx will be defined in the SOPC generated
header file.

Then when you reassign the base address or turn on/off the MMU,
you will only need to regenerate the resource header file.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
 board/altera/nios2-generic/Makefile        |   60 ++++++++++++
 board/altera/nios2-generic/config.mk       |   32 +++++++
 board/altera/nios2-generic/nios2-generic.c |   73 +++++++++++++++
 board/altera/nios2-generic/text_base.S     |   21 +++++
 board/altera/nios2-generic/u-boot.lds      |  136 ++++++++++++++++++++++++++++
 5 files changed, 322 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/Makefile
 create mode 100644 board/altera/nios2-generic/config.mk
 create mode 100644 board/altera/nios2-generic/nios2-generic.c
 create mode 100644 board/altera/nios2-generic/text_base.S
 create mode 100644 board/altera/nios2-generic/u-boot.lds

diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..2a6f69b
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..cb7c68e
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..703836c
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+	rc = dm9000_initialize(bis);
+#endif
+
+#ifdef CONFIG_ALTERA_TSE
+	altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS);
+#endif
+
+#ifdef CONFIG_ETHOC
+	rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
+
+int board_late_init(void)
+{
+	return 0;
+}
diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..fa7ed30
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
@ 2010-03-31  0:50 ` Thomas Chou
  2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
                     ` (3 more replies)
  2010-03-31  0:50 ` [U-Boot] [PATCH 3/5] nios2: add Altera EP3C120 board Thomas Chou
                   ` (5 subsequent siblings)
  6 siblings, 4 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  0:50 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera CycloneII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
 MAINTAINERS                          |    1 +
 MAKEALL                              |    1 +
 Makefile                             |    6 +
 board/altera/nios2-generic/2c35_cf.h |  757 ++++++++++++++++++++++++++++++++++
 include/configs/EP2C35.h             |  372 +++++++++++++++++
 5 files changed, 1137 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/2c35_cf.h
 create mode 100644 include/configs/EP2C35.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bb03f17..1f33146 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	EP2C35		Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index a88c31e..8ab3358 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -823,6 +823,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	EP2C35		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index f5b556c..a27b002 100644
--- a/Makefile
+++ b/Makefile
@@ -3533,6 +3533,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = EP2C35
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/2c35_cf.h b/board/altera/nios2-generic/2c35_cf.h
new file mode 100644
index 0000000..a08b35c
--- /dev/null
+++ b/board/altera/nios2-generic/2c35_cf.h
@@ -0,0 +1,757 @@
+#ifndef _ALTERA_2C35_CF_FPGA_H_
+#define _ALTERA_2C35_CF_FPGA_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in
+ * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate macro names.
+ * Instead, use the system header file which has macros with unique names.
+ */
+
+/*
+ * Macros for module 'cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define BIG_ENDIAN 0
+#define CPU_FREQ 85000000
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 4096
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 2048
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 10
+#define TLB_NUM_WAYS 16
+#define TLB_NUM_WAYS_LOG2 4
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc8000000
+#define EXCEPTION_ADDR 0xc6000020
+#define RESET_ADDR 0xc0000000
+#define BREAK_ADDR 0xc2120020
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 0
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 28
+#define DATA_ADDR_WIDTH 28
+#define NUM_OF_SHADOW_REG_SETS 0
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'EXT_FLASH_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define EXT_FLASH_COMPONENT_NAME ext_flash
+#define EXT_FLASH_BASE 0x0
+#define EXT_FLASH_SPAN 16777216
+#define EXT_FLASH_END 0xffffff
+#define EXT_FLASH_SETUP_VALUE 45
+#define EXT_FLASH_WAIT_VALUE 160
+#define EXT_FLASH_HOLD_VALUE 35
+#define EXT_FLASH_TIMING_UNITS "ns"
+#define EXT_FLASH_SIZE 16777216
+#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'cf_ctl', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_CTL_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_CTL_COMPONENT_TYPE altera_avalon_cf
+#define CF_CTL_COMPONENT_NAME cf
+#define CF_CTL_BASE 0x1000000
+#define CF_CTL_SPAN 16
+#define CF_CTL_END 0x100000f
+#define CF_CTL_IRQ 8
+
+/*
+ * Macros for device 'pll', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLL_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x1000020
+#define PLL_SPAN 32
+#define PLL_END 0x100003f
+#define PLL_ARESET "None"
+#define PLL_PFDENA "None"
+#define PLL_LOCKED "None"
+#define PLL_PLLENA "None"
+#define PLL_SCANCLK "None"
+#define PLL_SCANDATA "None"
+#define PLL_SCANREAD "None"
+#define PLL_SCANWRITE "None"
+#define PLL_SCANCLKENA "None"
+#define PLL_SCANACLR "None"
+#define PLL_SCANDATAOUT "None"
+#define PLL_SCANDONE "None"
+#define PLL_CONFIGUPDATE "None"
+#define PLL_PHASECOUNTERSELECT "None"
+#define PLL_PHASEDONE "None"
+#define PLL_PHASEUPDOWN "None"
+#define PLL_PHASESTEP "None"
+
+/*
+ * Macros for device 'pllsysx2', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLLSYSX2_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLLSYSX2_COMPONENT_TYPE altera_avalon_pll
+#define PLLSYSX2_COMPONENT_NAME pllsysx2
+#define PLLSYSX2_BASE 0x1000040
+#define PLLSYSX2_SPAN 32
+#define PLLSYSX2_END 0x100005f
+#define PLLSYSX2_ARESET "None"
+#define PLLSYSX2_PFDENA "None"
+#define PLLSYSX2_LOCKED "None"
+#define PLLSYSX2_PLLENA "None"
+#define PLLSYSX2_SCANCLK "None"
+#define PLLSYSX2_SCANDATA "None"
+#define PLLSYSX2_SCANREAD "None"
+#define PLLSYSX2_SCANWRITE "None"
+#define PLLSYSX2_SCANCLKENA "None"
+#define PLLSYSX2_SCANACLR "None"
+#define PLLSYSX2_SCANDATAOUT "None"
+#define PLLSYSX2_SCANDONE "None"
+#define PLLSYSX2_CONFIGUPDATE "None"
+#define PLLSYSX2_PHASECOUNTERSELECT "None"
+#define PLLSYSX2_PHASEDONE "None"
+#define PLLSYSX2_PHASEUPDOWN "None"
+#define PLLSYSX2_PHASESTEP "None"
+
+/*
+ * Macros for device 'cf_ide', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_IDE_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_IDE_COMPONENT_TYPE altera_avalon_cf
+#define CF_IDE_COMPONENT_NAME cf
+#define CF_IDE_BASE 0x1000080
+#define CF_IDE_SPAN 64
+#define CF_IDE_END 0x10000bf
+#define CF_IDE_IRQ 9
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * The macros are prefixed with 'EXT_SSRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define EXT_SSRAM_BASE 0x1400000
+#define EXT_SSRAM_SPAN 2097152
+#define EXT_SSRAM_END 0x15fffff
+#define EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * The macros are prefixed with 'LAN91C111_'.
+ * The prefix is the slave descriptor.
+ */
+#define LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define LAN91C111_COMPONENT_NAME lan91c111
+#define LAN91C111_BASE 0x2110000
+#define LAN91C111_SPAN 65536
+#define LAN91C111_END 0x211ffff
+#define LAN91C111_IRQ 6
+#define LAN91C111_IS_ETHERNET_MAC 1
+#define LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'sys_clk_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'SYS_CLK_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYS_CLK_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define SYS_CLK_TIMER_COMPONENT_NAME sys_clk_timer
+#define SYS_CLK_TIMER_BASE 0x2120800
+#define SYS_CLK_TIMER_SPAN 32
+#define SYS_CLK_TIMER_END 0x212081f
+#define SYS_CLK_TIMER_IRQ 0
+#define SYS_CLK_TIMER_ALWAYS_RUN 0
+#define SYS_CLK_TIMER_FIXED_PERIOD 0
+#define SYS_CLK_TIMER_SNAPSHOT 1
+#define SYS_CLK_TIMER_PERIOD 10.0
+#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
+#define SYS_CLK_TIMER_RESET_OUTPUT 0
+#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define SYS_CLK_TIMER_FREQ 85000000
+#define SYS_CLK_TIMER_LOAD_VALUE 849999ULL
+#define SYS_CLK_TIMER_COUNTER_SIZE 32
+#define SYS_CLK_TIMER_MULT 0.0010
+#define SYS_CLK_TIMER_TICKS_PER_SEC 100
+
+/*
+ * Macros for device 'high_res_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'HIGH_RES_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define HIGH_RES_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define HIGH_RES_TIMER_COMPONENT_NAME high_res_timer
+#define HIGH_RES_TIMER_BASE 0x2120820
+#define HIGH_RES_TIMER_SPAN 32
+#define HIGH_RES_TIMER_END 0x212083f
+#define HIGH_RES_TIMER_IRQ 3
+#define HIGH_RES_TIMER_ALWAYS_RUN 0
+#define HIGH_RES_TIMER_FIXED_PERIOD 0
+#define HIGH_RES_TIMER_SNAPSHOT 1
+#define HIGH_RES_TIMER_PERIOD 10.0
+#define HIGH_RES_TIMER_PERIOD_UNITS "us"
+#define HIGH_RES_TIMER_RESET_OUTPUT 0
+#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define HIGH_RES_TIMER_FREQ 85000000
+#define HIGH_RES_TIMER_LOAD_VALUE 849ULL
+#define HIGH_RES_TIMER_COUNTER_SIZE 32
+#define HIGH_RES_TIMER_MULT 1.0E-6
+#define HIGH_RES_TIMER_TICKS_PER_SEC 100000
+
+/*
+ * Macros for device 'uart1', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART1_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART1_COMPONENT_TYPE altera_avalon_uart
+#define UART1_COMPONENT_NAME uart1
+#define UART1_BASE 0x2120840
+#define UART1_SPAN 32
+#define UART1_END 0x212085f
+#define UART1_IRQ 4
+#define UART1_BAUD 115200
+#define UART1_DATA_BITS 8
+#define UART1_FIXED_BAUD 1
+#define UART1_PARITY 'N'
+#define UART1_STOP_BITS 1
+#define UART1_SYNC_REG_DEPTH 2
+#define UART1_USE_CTS_RTS 0
+#define UART1_USE_EOP_REGISTER 0
+#define UART1_SIM_TRUE_BAUD 0
+#define UART1_SIM_CHAR_STREAM ""
+#define UART1_FREQ 85000000
+
+/*
+ * Macros for device 'button_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'BUTTON_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
+#define BUTTON_PIO_COMPONENT_NAME button_pio
+#define BUTTON_PIO_BASE 0x2120860
+#define BUTTON_PIO_SPAN 16
+#define BUTTON_PIO_END 0x212086f
+#define BUTTON_PIO_IRQ 2
+#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1
+#define BUTTON_PIO_DRIVEN_SIM_VALUE 0xf
+#define BUTTON_PIO_HAS_TRI 0
+#define BUTTON_PIO_HAS_OUT 0
+#define BUTTON_PIO_HAS_IN 1
+#define BUTTON_PIO_CAPTURE 1
+#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define BUTTON_PIO_DATA_WIDTH 4
+#define BUTTON_PIO_RESET_VALUE 0x0
+#define BUTTON_PIO_EDGE_TYPE "ANY"
+#define BUTTON_PIO_IRQ_TYPE "EDGE"
+#define BUTTON_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'led_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'LED_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
+#define LED_PIO_COMPONENT_NAME led_pio
+#define LED_PIO_BASE 0x2120870
+#define LED_PIO_SPAN 16
+#define LED_PIO_END 0x212087f
+#define LED_PIO_DO_TEST_BENCH_WIRING 0
+#define LED_PIO_DRIVEN_SIM_VALUE 0x0
+#define LED_PIO_HAS_TRI 0
+#define LED_PIO_HAS_OUT 1
+#define LED_PIO_HAS_IN 0
+#define LED_PIO_CAPTURE 0
+#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define LED_PIO_DATA_WIDTH 8
+#define LED_PIO_RESET_VALUE 0x0
+#define LED_PIO_EDGE_TYPE "NONE"
+#define LED_PIO_IRQ_TYPE "NONE"
+#define LED_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'lcd_display', class 'altera_avalon_lcd_16207'
+ * The macros are prefixed with 'LCD_DISPLAY_'.
+ * The prefix is the slave descriptor.
+ */
+#define LCD_DISPLAY_COMPONENT_TYPE altera_avalon_lcd_16207
+#define LCD_DISPLAY_COMPONENT_NAME lcd_display
+#define LCD_DISPLAY_BASE 0x2120880
+#define LCD_DISPLAY_SPAN 16
+#define LCD_DISPLAY_END 0x212088f
+
+/*
+ * Macros for device 'seven_seg_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'SEVEN_SEG_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define SEVEN_SEG_PIO_COMPONENT_TYPE altera_avalon_pio
+#define SEVEN_SEG_PIO_COMPONENT_NAME seven_seg_pio
+#define SEVEN_SEG_PIO_BASE 0x2120890
+#define SEVEN_SEG_PIO_SPAN 16
+#define SEVEN_SEG_PIO_END 0x212089f
+#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0
+#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0
+#define SEVEN_SEG_PIO_HAS_TRI 0
+#define SEVEN_SEG_PIO_HAS_OUT 1
+#define SEVEN_SEG_PIO_HAS_IN 0
+#define SEVEN_SEG_PIO_CAPTURE 0
+#define SEVEN_SEG_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define SEVEN_SEG_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define SEVEN_SEG_PIO_DATA_WIDTH 16
+#define SEVEN_SEG_PIO_RESET_VALUE 0x0
+#define SEVEN_SEG_PIO_EDGE_TYPE "NONE"
+#define SEVEN_SEG_PIO_IRQ_TYPE "NONE"
+#define SEVEN_SEG_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'reconfig_request_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'RECONFIG_REQUEST_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define RECONFIG_REQUEST_PIO_COMPONENT_TYPE altera_avalon_pio
+#define RECONFIG_REQUEST_PIO_COMPONENT_NAME reconfig_request_pio
+#define RECONFIG_REQUEST_PIO_BASE 0x21208a0
+#define RECONFIG_REQUEST_PIO_SPAN 16
+#define RECONFIG_REQUEST_PIO_END 0x21208af
+#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0
+#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_HAS_TRI 1
+#define RECONFIG_REQUEST_PIO_HAS_OUT 0
+#define RECONFIG_REQUEST_PIO_HAS_IN 0
+#define RECONFIG_REQUEST_PIO_CAPTURE 0
+#define RECONFIG_REQUEST_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define RECONFIG_REQUEST_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define RECONFIG_REQUEST_PIO_DATA_WIDTH 1
+#define RECONFIG_REQUEST_PIO_RESET_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x21208b0
+#define JTAG_UART_SPAN 8
+#define JTAG_UART_END 0x21208b7
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_COMPONENT_TYPE altera_avalon_sysid
+#define SYSID_COMPONENT_NAME sysid
+#define SYSID_BASE 0x21208b8
+#define SYSID_SPAN 8
+#define SYSID_END 0x21208bf
+#define SYSID_ID 1003732523
+#define SYSID_TIMESTAMP 1268227126
+
+/*
+ * Macros for device 'performance_counter', class 'altera_avalon_performance_counter'
+ * The macros are prefixed with 'PERFORMANCE_COUNTER_'.
+ * The prefix is the slave descriptor.
+ */
+#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter
+#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter
+#define PERFORMANCE_COUNTER_BASE 0x2120900
+#define PERFORMANCE_COUNTER_SPAN 64
+#define PERFORMANCE_COUNTER_END 0x212093f
+#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 3
+
+/*
+ * Macros for device 'dma', class 'altera_avalon_dma'
+ * The macros are prefixed with 'DMA_'.
+ * The prefix is the slave descriptor.
+ */
+#define DMA_COMPONENT_TYPE altera_avalon_dma
+#define DMA_COMPONENT_NAME dma
+#define DMA_BASE 0x2120a00
+#define DMA_SPAN 32
+#define DMA_END 0x2120a1f
+#define DMA_IRQ 7
+#define DMA_LENGTHWIDTH 13
+#define DMA_ALLOW_BYTE_TRANSACTIONS 1
+#define DMA_ALLOW_HW_TRANSACTIONS 1
+#define DMA_ALLOW_WORD_TRANSACTIONS 1
+#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1
+#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1
+#define DMA_MAX_BURST_SIZE 128
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_READ_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_READ_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_READ_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_READ_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_READ_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_READ_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_READ_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_READ_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_READ_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_READ_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_READ_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_READ_MASTER_LAN91C111_SPAN 65536
+#define DMA_READ_MASTER_LAN91C111_END 0x211ffff
+#define DMA_READ_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_READ_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_READ_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_READ_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_WRITE_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_WRITE_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_WRITE_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_WRITE_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_WRITE_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_WRITE_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_WRITE_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_WRITE_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_WRITE_MASTER_LAN91C111_SPAN 65536
+#define DMA_WRITE_MASTER_LAN91C111_END 0x211ffff
+#define DMA_WRITE_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'epcs_controller', class 'altera_avalon_epcs_flash_controller'
+ * The macros are prefixed with 'EPCS_CONTROLLER_'.
+ * The prefix is the slave descriptor.
+ */
+#define EPCS_CONTROLLER_COMPONENT_TYPE altera_avalon_epcs_flash_controller
+#define EPCS_CONTROLLER_COMPONENT_NAME epcs_controller
+#define EPCS_CONTROLLER_BASE 0x3200000
+#define EPCS_CONTROLLER_SPAN 2048
+#define EPCS_CONTROLLER_END 0x32007ff
+#define EPCS_CONTROLLER_IRQ 5
+#define EPCS_CONTROLLER_REGISTER_OFFSET 512
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_FILENAME epcs_controller_boot_rom
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_EPCS 1
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_HEX 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_HEX_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * The macros are prefixed with 'DDR_SDRAM_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DDR_SDRAM_0_BASE 0x6000000
+#define DDR_SDRAM_0_SPAN 33554432
+#define DDR_SDRAM_0_END 0x7ffffff
+#define DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_instruction_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_INSTRUCTION_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_NAME tightly_coupled_instruction_memory
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_BASE 0x8000000
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SPAN 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_END 0x8000fff
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_instruction_memory"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_VALUE 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+
+#endif /* _ALTERA_2C35_CF_FPGA_H_ */
diff --git a/include/configs/EP2C35.h b/include/configs/EP2C35.h
new file mode 100644
index 0000000..a973913
--- /dev/null
+++ b/include/configs/EP2C35.h
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/2c35_cf.h"
+#define CONFIG_BOARD_NAME "EP2C35"
+#define CONFIG_EP2C35
+
+#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE		(DDR_SDRAM_0_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR_SDRAM_0_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0
+# define CONFIG_SYS_GPIO_SCL 1
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(EXT_FLASH_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ALTERA_SPI
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART1_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART1_FREQ
+#define CONFIG_BAUDRATE		UART1_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART1_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(SYS_CLK_TIMER_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		SYS_CLK_TIMER_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((SYS_CLK_TIMER_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_HZ			100
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		(LED_PIO_BASE | IO_REGION_BASE)
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2) /* 500 mS */
+
+/*
+ * IDE support
+ */
+#define CONFIG_CMD_IDE
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE	((LAN91C111_BASE + \
+				  LAN91C111_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_CMD_MII */
+#define CONFIG_ETHPRIME "tse0"
+#undef	CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_SERVERIP	192.168.1.254
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/* #define CONFIG_CMD_SAVES */
+/* #define CONFIG_CMD_JFFS2 */
+/* #define CONFIG_JFFS2_CMDLINE */
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=nor0\0"						\
+	"mtdparts=mtdparts=nor0:2m(boot),6m(romfs),4m(user),4m(factory)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 3/5] nios2: add Altera EP3C120 board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
@ 2010-03-31  0:50 ` Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 4/5] nios2: add Altera NEEK board Thomas Chou
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  0:50 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera CycloneIII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
 MAINTAINERS                              |    1 +
 MAKEALL                                  |    1 +
 Makefile                                 |    2 +-
 board/altera/nios2-generic/default_mmu.h |  371 ++++++++++++++++++++++++++++
 include/configs/EP3C120.h                |  394 ++++++++++++++++++++++++++++++
 5 files changed, 768 insertions(+), 1 deletions(-)
 create mode 100644 board/altera/nios2-generic/default_mmu.h
 create mode 100644 include/configs/EP3C120.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 1f33146..30ac451 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -851,6 +851,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1S10		Nios-II
 	EP1S40		Nios-II
 	EP2C35		Nios-II
+	EP3C120	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index 8ab3358..886d608 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2="		\
 	PCI5441		\
 	PK1C20		\
 	EP2C35		\
+	EP3C120	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index a27b002..5b3c589 100644
--- a/Makefile
+++ b/Makefile
@@ -3534,7 +3534,7 @@ PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
 # nios2 generic boards
-NIOS2_GENERIC = EP2C35
+NIOS2_GENERIC = EP2C35 EP3C120
 
 $(NIOS2_GENERIC:%=%_config) : unconfig
 	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h
new file mode 100644
index 0000000..dc14dc2
--- /dev/null
+++ b/board/altera/nios2-generic/default_mmu.h
@@ -0,0 +1,371 @@
+#ifndef _ALTERA_LINUX_CPU_H_
+#define _ALTERA_LINUX_CPU_H_
+
+/* Note, this file was manually edited after generation
+ * since the multiple inclusion proctetion macro above collides with
+ * include/linux/cpu.h
+ */
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
+ * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'linux_cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not #include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate #defines.
+ * Instead, use the system header file which has #defines with unique names.
+ */
+
+/*
+ * Macros for module 'linux_cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 32768
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 32768
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 8
+#define TLB_NUM_WAYS 16
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc7fff400
+#define EXCEPTION_ADDR 0xd0000020
+#define RESET_ADDR 0xc2800000
+#define BREAK_ADDR 0xc7fff820
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 1
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 29
+#define DATA_ADDR_WIDTH 29
+
+/*
+ * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'CFI_FLASH_64M_'.
+ * The prefix is the slave descriptor.
+ */
+#define CFI_FLASH_64M_BASE 0x0
+#define CFI_FLASH_64M_SPAN 67108864u
+#define CFI_FLASH_64M_SETUP_VALUE 75
+#define CFI_FLASH_64M_WAIT_VALUE 35
+#define CFI_FLASH_64M_HOLD_VALUE 1
+#define CFI_FLASH_64M_TIMING_UNITS "ns"
+#define CFI_FLASH_64M_SIZE 67108864u
+
+/*
+ * Macros for device 'fast_tlb_miss_ram_1k', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'FAST_TLB_MISS_RAM_1K_'.
+ * The prefix is the slave descriptor.
+ */
+#define FAST_TLB_MISS_RAM_1K_BASE 0x7fff400
+#define FAST_TLB_MISS_RAM_1K_SPAN 1024u
+#define FAST_TLB_MISS_RAM_1K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define FAST_TLB_MISS_RAM_1K_INIT_CONTENTS_FILE "fast_tlb_miss_ram_1k"
+#define FAST_TLB_MISS_RAM_1K_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define FAST_TLB_MISS_RAM_1K_GUI_RAM_BLOCK_TYPE "Automatic"
+#define FAST_TLB_MISS_RAM_1K_WRITABLE 1
+#define FAST_TLB_MISS_RAM_1K_DUAL_PORT 1
+#define FAST_TLB_MISS_RAM_1K_SIZE_VALUE 1024u
+#define FAST_TLB_MISS_RAM_1K_SIZE_MULTIPLE 1
+#define FAST_TLB_MISS_RAM_1K_CONTENTS_INFO ""
+#define FAST_TLB_MISS_RAM_1K_RAM_BLOCK_TYPE "Auto"
+#define FAST_TLB_MISS_RAM_1K_INIT_MEM_CONTENT 1
+#define FAST_TLB_MISS_RAM_1K_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define FAST_TLB_MISS_RAM_1K_INSTANCE_ID "NONE"
+#define FAST_TLB_MISS_RAM_1K_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define DESCRIPTOR_MEMORY_BASE 0x8002000
+#define DESCRIPTOR_MEMORY_SPAN 8192u
+#define DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "descriptor_memory"
+#define DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DESCRIPTOR_MEMORY_WRITABLE 1
+#define DESCRIPTOR_MEMORY_DUAL_PORT 0
+#define DESCRIPTOR_MEMORY_SIZE_VALUE 8192u
+#define DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1
+#define DESCRIPTOR_MEMORY_CONTENTS_INFO ""
+#define DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 1
+#define DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DESCRIPTOR_MEMORY_INSTANCE_ID "NONE"
+#define DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'tse_mac', class 'triple_speed_ethernet'
+ * The macros are prefixed with 'TSE_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define TSE_MAC_BASE 0x8004000
+#define TSE_MAC_SPAN 1024u
+#define TSE_MAC_TRANSMIT "sgdma_tx"
+#define TSE_MAC_RECEIVE "sgdma_rx"
+#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
+#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
+#define TSE_MAC_FIFO_WIDTH 32
+#define TSE_MAC_ENABLE_MACLITE 0
+#define TSE_MAC_MACLITE_GIGE 0
+#define TSE_MAC_USE_MDIO 1
+#define TSE_MAC_NUMBER_OF_CHANNEL 0
+#define TSE_MAC_NUMBER_OF_MAC_MDIO_SHARED 0
+#define TSE_MAC_IS_MULTICHANNEL_MAC 0
+#define TSE_MAC_MDIO_SHARED 0
+#define TSE_MAC_REGISTER_SHARED 0
+#define TSE_MAC_PCS 0
+#define TSE_MAC_PCS_SGMII 0
+#define TSE_MAC_PCS_ID 0u
+
+/*
+ * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_RX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_RX_BASE 0x8004400
+#define SGDMA_RX_SPAN 1024u
+#define SGDMA_RX_IRQ 2
+#define SGDMA_RX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_STREAM_DATA_WIDTH 32
+#define SGDMA_RX_ADDRESS_WIDTH 32
+#define SGDMA_RX_HAS_READ_BLOCK 0
+#define SGDMA_RX_HAS_WRITE_BLOCK 1
+#define SGDMA_RX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_BURST_TRANSFER 0
+#define SGDMA_RX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_RX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_RX_UNALIGNED_TRANSFER 0
+#define SGDMA_RX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_RX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_RX_DESC_DATA_WIDTH 32
+#define SGDMA_RX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_RX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_RX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_RX_BURST_DATA_WIDTH 8
+#define SGDMA_RX_CONTROL_DATA_WIDTH 8
+#define SGDMA_RX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_RX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_RX_SYMBOLS_PER_BEAT 4
+#define SGDMA_RX_IN_ERROR_WIDTH 6
+#define SGDMA_RX_OUT_ERROR_WIDTH 0
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_rx_m_write'.
+ * The macros are prefixed with 'SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_TX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_TX_BASE 0x8004800
+#define SGDMA_TX_SPAN 1024u
+#define SGDMA_TX_IRQ 3
+#define SGDMA_TX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_STREAM_DATA_WIDTH 32
+#define SGDMA_TX_ADDRESS_WIDTH 32
+#define SGDMA_TX_HAS_READ_BLOCK 1
+#define SGDMA_TX_HAS_WRITE_BLOCK 0
+#define SGDMA_TX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_BURST_TRANSFER 0
+#define SGDMA_TX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_TX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_TX_UNALIGNED_TRANSFER 0
+#define SGDMA_TX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_TX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_TX_DESC_DATA_WIDTH 32
+#define SGDMA_TX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_TX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_TX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_TX_BURST_DATA_WIDTH 8
+#define SGDMA_TX_CONTROL_DATA_WIDTH 8
+#define SGDMA_TX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_TX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_TX_SYMBOLS_PER_BEAT 4
+#define SGDMA_TX_IN_ERROR_WIDTH 0
+#define SGDMA_TX_OUT_ERROR_WIDTH 1
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_tx_m_read'.
+ * The macros are prefixed with 'SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_BASE 0x8004c80
+#define UART_SPAN 32u
+#define UART_IRQ 10
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 0
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 62500000u
+
+/*
+ * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_LED_PIO_8OUT_BASE 0x8004cc0
+#define USER_LED_PIO_8OUT_SPAN 16u
+#define USER_LED_PIO_8OUT_DO_TEST_BENCH_WIRING 0
+#define USER_LED_PIO_8OUT_DRIVEN_SIM_VALUE 0x0
+#define USER_LED_PIO_8OUT_HAS_TRI 0
+#define USER_LED_PIO_8OUT_HAS_OUT 1
+#define USER_LED_PIO_8OUT_HAS_IN 0
+#define USER_LED_PIO_8OUT_CAPTURE 0
+#define USER_LED_PIO_8OUT_BIT_CLEARING_EDGE_REGISTER 0
+#define USER_LED_PIO_8OUT_DATA_WIDTH 8
+#define USER_LED_PIO_8OUT_RESET_VALUE 0xff
+#define USER_LED_PIO_8OUT_EDGE_TYPE "NONE"
+#define USER_LED_PIO_8OUT_IRQ_TYPE "NONE"
+#define USER_LED_PIO_8OUT_FREQ 62500000u
+
+/*
+ * Macros for device 'user_dipsw_pio_8in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_DIPSW_PIO_8IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_DIPSW_PIO_8IN_BASE 0x8004ce0
+#define USER_DIPSW_PIO_8IN_SPAN 16u
+#define USER_DIPSW_PIO_8IN_IRQ 8
+#define USER_DIPSW_PIO_8IN_DO_TEST_BENCH_WIRING 0
+#define USER_DIPSW_PIO_8IN_DRIVEN_SIM_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_HAS_TRI 0
+#define USER_DIPSW_PIO_8IN_HAS_OUT 0
+#define USER_DIPSW_PIO_8IN_HAS_IN 1
+#define USER_DIPSW_PIO_8IN_CAPTURE 1
+#define USER_DIPSW_PIO_8IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_DIPSW_PIO_8IN_DATA_WIDTH 8
+#define USER_DIPSW_PIO_8IN_RESET_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_EDGE_TYPE "ANY"
+#define USER_DIPSW_PIO_8IN_IRQ_TYPE "EDGE"
+#define USER_DIPSW_PIO_8IN_FREQ 62500000u
+
+/*
+ * Macros for device 'user_pb_pio_4in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_PB_PIO_4IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_PB_PIO_4IN_BASE 0x8004d00
+#define USER_PB_PIO_4IN_SPAN 16u
+#define USER_PB_PIO_4IN_IRQ 9
+#define USER_PB_PIO_4IN_DO_TEST_BENCH_WIRING 0
+#define USER_PB_PIO_4IN_DRIVEN_SIM_VALUE 0x0
+#define USER_PB_PIO_4IN_HAS_TRI 0
+#define USER_PB_PIO_4IN_HAS_OUT 0
+#define USER_PB_PIO_4IN_HAS_IN 1
+#define USER_PB_PIO_4IN_CAPTURE 1
+#define USER_PB_PIO_4IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_PB_PIO_4IN_DATA_WIDTH 4
+#define USER_PB_PIO_4IN_RESET_VALUE 0x0
+#define USER_PB_PIO_4IN_EDGE_TYPE "ANY"
+#define USER_PB_PIO_4IN_IRQ_TYPE "EDGE"
+#define USER_PB_PIO_4IN_FREQ 62500000u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_BASE 0x8004d40
+#define SYSID_SPAN 8u
+#define SYSID_ID 1174346794u
+#define SYSID_TIMESTAMP 1233287581u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_BASE 0x8004d50
+#define JTAG_UART_SPAN 8u
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
+ * The macros are prefixed with 'LINUX_TIMER_1MS_'.
+ * The prefix is the slave descriptor.
+ */
+#define LINUX_TIMER_1MS_BASE 0x8400000
+#define LINUX_TIMER_1MS_SPAN 32u
+#define LINUX_TIMER_1MS_IRQ 11
+#define LINUX_TIMER_1MS_ALWAYS_RUN 0
+#define LINUX_TIMER_1MS_FIXED_PERIOD 0
+#define LINUX_TIMER_1MS_SNAPSHOT 1
+#define LINUX_TIMER_1MS_PERIOD 1
+#define LINUX_TIMER_1MS_PERIOD_UNITS "ms"
+#define LINUX_TIMER_1MS_RESET_OUTPUT 0
+#define LINUX_TIMER_1MS_TIMEOUT_PULSE_OUTPUT 0
+#define LINUX_TIMER_1MS_FREQ 125000000u
+#define LINUX_TIMER_1MS_LOAD_VALUE 124999ULL
+#define LINUX_TIMER_1MS_COUNTER_SIZE 32
+#define LINUX_TIMER_1MS_MULT 0.0010
+#define LINUX_TIMER_1MS_TICKS_PER_SEC 1000u
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define DDR2_LO_LATENCY_128M_SPAN 134217728
+
+
+#endif /* _ALTERA_LINUX_CPU_H_ */
diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
new file mode 100644
index 0000000..4624102
--- /dev/null
+++ b/include/configs/EP3C120.h
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/default_mmu.h"
+#define CONFIG_BOARD_NAME "EP3C120"
+#define CONFIG_EP3C120
+
+#define CONFIG_SYS_CLK_FREQ		125000000
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR2_LO_LATENCY_128M_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0
+# define CONFIG_SYS_GPIO_SCL 1
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(CFI_FLASH_64M_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART_FREQ
+#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		LINUX_TIMER_1MS_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((LINUX_TIMER_1MS_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_HZ			100
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		(USER_LED_PIO_8OUT_BASE | \
+					 IO_REGION_BASE)
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2) /* 500 mS */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+#define CONFIG_ALTERA_TSE
+#define CONFIG_MII		1
+#define CONFIG_CMD_MII
+#define CONFIG_ETHPRIME "tse0"
+#undef  CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_GWADDR		192.168.1.1
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_BOOTDELAY	10
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=ep3c120-flash\0"					\
+	"mtdparts=mtdparts=ep3c120-flash:40m(JFFS),1M(U-Boot),4m(uImage1)," \
+	"4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
+	"3584k(USER_IMAGE),512k(options-bits)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS \
+	"autoload=no\0"						\
+	"autostart=no\0"						\
+	"bootcmd=run tftp_program_flash\0"				\
+	"ipaddr_cmd="							\
+		"echo 'Getting ethaddr from flash';"			\
+		"altera ethaddr;"					\
+		"echo 'DHCP Address';"					\
+		"dhcp;"						\
+		"run set_serverip\0"					\
+	"tftp_program_flash="						\
+		"echo 'TFTP Program Flash';"				\
+		"run ipaddr_cmd;"					\
+		"tftp 0xd1000000 ${serverip}:tftp_program_flash_script.img;" \
+		"iminfo ${fileaddr};"					\
+		"autoscr ${fileaddr};\0"				\
+		"set_serverip=setenv serverip ${tftpserverip}\0"	\
+	"tftpserverip=137.57.185.173\0"				\
+	""
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 4/5] nios2: add Altera NEEK board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 3/5] nios2: add Altera EP3C120 board Thomas Chou
@ 2010-03-31  0:50 ` Thomas Chou
  2010-03-31  0:50 ` [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c Thomas Chou
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  0:50 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera Nios2 Embedded Evaluation Kit using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
 MAINTAINERS                                   |    1 +
 MAKEALL                                       |    1 +
 Makefile                                      |    2 +-
 board/altera/nios2-generic/neek_ocm_spi_mmu.h |  406 +++++++++++++++++++++++++
 include/configs/NEEK.h                        |  366 ++++++++++++++++++++++
 5 files changed, 775 insertions(+), 1 deletions(-)
 create mode 100644 board/altera/nios2-generic/neek_ocm_spi_mmu.h
 create mode 100644 include/configs/NEEK.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 30ac451..9c0707d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1S40		Nios-II
 	EP2C35		Nios-II
 	EP3C120	Nios-II
+	NEEK		Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index 886d608..694b20e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -825,6 +825,7 @@ LIST_nios2="		\
 	PK1C20		\
 	EP2C35		\
 	EP3C120	\
+	NEEK		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 5b3c589..ab708a0 100644
--- a/Makefile
+++ b/Makefile
@@ -3534,7 +3534,7 @@ PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
 # nios2 generic boards
-NIOS2_GENERIC = EP2C35 EP3C120
+NIOS2_GENERIC = EP2C35 EP3C120 NEEK
 
 $(NIOS2_GENERIC:%=%_config) : unconfig
 	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
diff --git a/board/altera/nios2-generic/neek_ocm_spi_mmu.h b/board/altera/nios2-generic/neek_ocm_spi_mmu.h
new file mode 100644
index 0000000..5e62059
--- /dev/null
+++ b/board/altera/nios2-generic/neek_ocm_spi_mmu.h
@@ -0,0 +1,406 @@
+#ifndef _ALTERA_CPU_H_
+#define _ALTERA_CPU_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'cycloneIII_embedded_evaluation_kit_standard_sopc' in
+ * file './cycloneIII_embedded_evaluation_kit_standard_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not #include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate #defines.
+ * Instead, use the system header file which has #defines with unique names.
+ */
+
+/*
+ * Macros for module 'cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define CPU_FREQ 100000000u
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 8192
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 4096
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 10
+#define TLB_NUM_WAYS 16
+#define TLB_NUM_WAYS_LOG2 4
+#define TLB_PTR_SZ 8
+#define TLB_NUM_ENTRIES 256
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc9000000
+#define EXCEPTION_ADDR 0xc0000020
+#define RESET_ADDR 0xc4000000
+#define BREAK_ADDR 0xc6000020
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 0
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 28
+#define DATA_ADDR_WIDTH 28
+
+/*
+ * Macros for device 'ddr_sdram', class 'altmemddr'
+ * The macros are prefixed with 'DDR_SDRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR_SDRAM_COMPONENT_TYPE altmemddr
+#define DDR_SDRAM_COMPONENT_NAME ddr_sdram
+#define DDR_SDRAM_BASE 0x0
+#define DDR_SDRAM_SPAN 33554432
+
+/*
+ * Macros for device 'lcd_sgdma', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'LCD_SGDMA_'.
+ * The prefix is the slave descriptor.
+ */
+#define LCD_SGDMA_COMPONENT_TYPE altera_avalon_sgdma
+#define LCD_SGDMA_COMPONENT_NAME lcd_sgdma
+#define LCD_SGDMA_BASE 0x2000000
+#define LCD_SGDMA_SPAN 1024u
+#define LCD_SGDMA_IRQ 5
+#define LCD_SGDMA_READ_BLOCK_DATA_WIDTH 64
+#define LCD_SGDMA_WRITE_BLOCK_DATA_WIDTH 64
+#define LCD_SGDMA_STREAM_DATA_WIDTH 64
+#define LCD_SGDMA_ADDRESS_WIDTH 32
+#define LCD_SGDMA_HAS_READ_BLOCK 1
+#define LCD_SGDMA_HAS_WRITE_BLOCK 0
+#define LCD_SGDMA_READ_BURSTCOUNT_WIDTH 4
+#define LCD_SGDMA_WRITE_BURSTCOUNT_WIDTH 4
+#define LCD_SGDMA_BURST_TRANSFER 0
+#define LCD_SGDMA_ALWAYS_DO_MAX_BURST 1
+#define LCD_SGDMA_DESCRIPTOR_READ_BURST 0
+#define LCD_SGDMA_UNALIGNED_TRANSFER 0
+#define LCD_SGDMA_CONTROL_SLAVE_DATA_WIDTH 32
+#define LCD_SGDMA_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define LCD_SGDMA_DESC_DATA_WIDTH 32
+#define LCD_SGDMA_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define LCD_SGDMA_STATUS_TOKEN_DATA_WIDTH 24
+#define LCD_SGDMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define LCD_SGDMA_BURST_DATA_WIDTH 8
+#define LCD_SGDMA_CONTROL_DATA_WIDTH 8
+#define LCD_SGDMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define LCD_SGDMA_COMMAND_FIFO_DATA_WIDTH 104
+#define LCD_SGDMA_SYMBOLS_PER_BEAT 8
+#define LCD_SGDMA_IN_ERROR_WIDTH 0
+#define LCD_SGDMA_OUT_ERROR_WIDTH 0
+
+/*
+ * Macros for device 'ddr_sdram', class 'altmemddr'
+ * Path to the device is from the master group 'lcd_sgdma_m_read'.
+ * The macros are prefixed with 'LCD_SGDMA_M_READ_DDR_SDRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define LCD_SGDMA_M_READ_DDR_SDRAM_COMPONENT_TYPE altmemddr
+#define LCD_SGDMA_M_READ_DDR_SDRAM_COMPONENT_NAME ddr_sdram
+#define LCD_SGDMA_M_READ_DDR_SDRAM_BASE 0x0
+#define LCD_SGDMA_M_READ_DDR_SDRAM_SPAN 33554432u
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'EXT_FLASH_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define EXT_FLASH_COMPONENT_NAME ext_flash
+#define EXT_FLASH_BASE 0x4000000
+#define EXT_FLASH_SPAN 16777216u
+#define EXT_FLASH_SETUP_VALUE 25
+#define EXT_FLASH_WAIT_VALUE 100
+#define EXT_FLASH_HOLD_VALUE 20
+#define EXT_FLASH_TIMING_UNITS "ns"
+#define EXT_FLASH_SIZE 16777216u
+
+/*
+ * Macros for device 'ssram', class 'altera_avalon_cy7c1380_ssram'
+ * The macros are prefixed with 'SSRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define SSRAM_COMPONENT_NAME ssram
+#define SSRAM_BASE 0x5000000
+#define SSRAM_SPAN 1048576u
+#define SSRAM_SRAM_MEMORY_SIZE 1
+#define SSRAM_SRAM_MEMORY_UNITS 1048576
+#define SSRAM_SSRAM_DATA_WIDTH 32
+#define SSRAM_SSRAM_READ_LATENCY 2
+
+/*
+ * Macros for device 'igor_mac', class 'eth_ocm'
+ * The macros are prefixed with 'IGOR_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define IGOR_MAC_COMPONENT_TYPE eth_ocm
+#define IGOR_MAC_COMPONENT_NAME igor_mac
+#define IGOR_MAC_BASE 0x8000000
+#define IGOR_MAC_SPAN 4096u
+#define IGOR_MAC_IRQ 1
+
+/*
+ * Macros for device 'remote_update', class 'altera_avalon_remote_update_cycloneiii'
+ * The macros are prefixed with 'REMOTE_UPDATE_'.
+ * The prefix is the slave descriptor.
+ */
+#define REMOTE_UPDATE_COMPONENT_TYPE altera_avalon_remote_update_cycloneiii
+#define REMOTE_UPDATE_COMPONENT_NAME remote_update
+#define REMOTE_UPDATE_BASE 0x8001000
+#define REMOTE_UPDATE_SPAN 512u
+
+/*
+ * Macros for device 'pll', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLL_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x8001200
+#define PLL_SPAN 64u
+#define PLL_ARESET "None"
+#define PLL_PFDENA "None"
+#define PLL_LOCKED "None"
+#define PLL_PLLENA "None"
+#define PLL_SCANCLK "None"
+#define PLL_SCANDATA "None"
+#define PLL_SCANREAD "None"
+#define PLL_SCANWRITE "None"
+#define PLL_SCANCLKENA "None"
+#define PLL_SCANACLR "None"
+#define PLL_SCANDATAOUT "None"
+#define PLL_SCANDONE "None"
+#define PLL_CONFIGUPDATE "None"
+#define PLL_PHASECOUNTERSELECT "None"
+#define PLL_PHASEDONE "None"
+#define PLL_PHASEUPDOWN "None"
+#define PLL_PHASESTEP "None"
+
+/*
+ * Macros for device 'sys_clk_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'SYS_CLK_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYS_CLK_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define SYS_CLK_TIMER_COMPONENT_NAME sys_clk_timer
+#define SYS_CLK_TIMER_BASE 0x8001240
+#define SYS_CLK_TIMER_SPAN 64u
+#define SYS_CLK_TIMER_IRQ 0
+#define SYS_CLK_TIMER_ALWAYS_RUN 0
+#define SYS_CLK_TIMER_FIXED_PERIOD 0
+#define SYS_CLK_TIMER_SNAPSHOT 1
+#define SYS_CLK_TIMER_PERIOD 10.0
+#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
+#define SYS_CLK_TIMER_RESET_OUTPUT 0
+#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define SYS_CLK_TIMER_FREQ 60000000u
+#define SYS_CLK_TIMER_LOAD_VALUE 599999ULL
+#define SYS_CLK_TIMER_COUNTER_SIZE 32
+#define SYS_CLK_TIMER_MULT 0.0010
+#define SYS_CLK_TIMER_TICKS_PER_SEC 100u
+
+/*
+ * Macros for device 'performance_counter', class 'altera_avalon_performance_counter'
+ * The macros are prefixed with 'PERFORMANCE_COUNTER_'.
+ * The prefix is the slave descriptor.
+ */
+#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter
+#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter
+#define PERFORMANCE_COUNTER_BASE 0x8001280
+#define PERFORMANCE_COUNTER_SPAN 64u
+#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 1
+
+/*
+ * Macros for device 'touch_panel_spi', class 'altera_avalon_spi'
+ * The macros are prefixed with 'TOUCH_PANEL_SPI_'.
+ * The prefix is the slave descriptor.
+ */
+#define TOUCH_PANEL_SPI_COMPONENT_TYPE altera_avalon_spi
+#define TOUCH_PANEL_SPI_COMPONENT_NAME touch_panel_spi
+#define TOUCH_PANEL_SPI_BASE 0x80012c0
+#define TOUCH_PANEL_SPI_SPAN 64u
+#define TOUCH_PANEL_SPI_IRQ 3
+#define TOUCH_PANEL_SPI_DATABITS 8
+#define TOUCH_PANEL_SPI_DATAWIDTH 16
+#define TOUCH_PANEL_SPI_TARGETCLOCK 32000u
+#define TOUCH_PANEL_SPI_CLOCKUNITS "Hz"
+#define TOUCH_PANEL_SPI_CLOCKMULT 1
+#define TOUCH_PANEL_SPI_NUMSLAVES 1
+#define TOUCH_PANEL_SPI_ISMASTER 1
+#define TOUCH_PANEL_SPI_CLOCKPOLARITY 0
+#define TOUCH_PANEL_SPI_CLOCKPHASE 0
+#define TOUCH_PANEL_SPI_LSBFIRST 0
+#define TOUCH_PANEL_SPI_EXTRADELAY 0
+#define TOUCH_PANEL_SPI_TARGETSSDELAY "0.0"
+#define TOUCH_PANEL_SPI_DELAYUNITS "ns"
+#define TOUCH_PANEL_SPI_DELAYMULT "1.0E-9"
+#define TOUCH_PANEL_SPI_PREFIX "spi_"
+
+/*
+ * Macros for device 'mmc_spi', class 'altera_avalon_spi'
+ * The macros are prefixed with 'MMC_SPI_'.
+ * The prefix is the slave descriptor.
+ */
+#define MMC_SPI_COMPONENT_TYPE altera_avalon_spi
+#define MMC_SPI_COMPONENT_NAME mmc_spi
+#define MMC_SPI_BASE 0x8001300
+#define MMC_SPI_SPAN 64u
+#define MMC_SPI_IRQ 8
+#define MMC_SPI_DATABITS 8
+#define MMC_SPI_DATAWIDTH 16
+#define MMC_SPI_TARGETCLOCK 20000000u
+#define MMC_SPI_CLOCKUNITS "Hz"
+#define MMC_SPI_CLOCKMULT 1
+#define MMC_SPI_NUMSLAVES 1
+#define MMC_SPI_ISMASTER 1
+#define MMC_SPI_CLOCKPOLARITY 0
+#define MMC_SPI_CLOCKPHASE 0
+#define MMC_SPI_LSBFIRST 0
+#define MMC_SPI_EXTRADELAY 0
+#define MMC_SPI_TARGETSSDELAY "0.0"
+#define MMC_SPI_DELAYUNITS "ns"
+#define MMC_SPI_DELAYMULT "1.0E-9"
+#define MMC_SPI_PREFIX "spi_"
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_COMPONENT_TYPE altera_avalon_uart
+#define UART_COMPONENT_NAME uart
+#define UART_BASE 0x8001340
+#define UART_SPAN 64u
+#define UART_IRQ 6
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 1
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_SYNC_REG_DEPTH 2
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 66500000u
+
+/*
+ * Macros for device 'touch_panel_pen_irq_n', class 'altera_avalon_pio'
+ * The macros are prefixed with 'TOUCH_PANEL_PEN_IRQ_N_'.
+ * The prefix is the slave descriptor.
+ */
+#define TOUCH_PANEL_PEN_IRQ_N_COMPONENT_TYPE altera_avalon_pio
+#define TOUCH_PANEL_PEN_IRQ_N_COMPONENT_NAME touch_panel_pen_irq_n
+#define TOUCH_PANEL_PEN_IRQ_N_BASE 0x80013e0
+#define TOUCH_PANEL_PEN_IRQ_N_SPAN 32u
+#define TOUCH_PANEL_PEN_IRQ_N_IRQ 4
+#define TOUCH_PANEL_PEN_IRQ_N_DO_TEST_BENCH_WIRING 0
+#define TOUCH_PANEL_PEN_IRQ_N_DRIVEN_SIM_VALUE 0x0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_TRI 0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_OUT 0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_IN 1
+#define TOUCH_PANEL_PEN_IRQ_N_CAPTURE 1
+#define TOUCH_PANEL_PEN_IRQ_N_BIT_CLEARING_EDGE_REGISTER 0
+#define TOUCH_PANEL_PEN_IRQ_N_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define TOUCH_PANEL_PEN_IRQ_N_DATA_WIDTH 1
+#define TOUCH_PANEL_PEN_IRQ_N_RESET_VALUE 0x0
+#define TOUCH_PANEL_PEN_IRQ_N_EDGE_TYPE "FALLING"
+#define TOUCH_PANEL_PEN_IRQ_N_IRQ_TYPE "EDGE"
+#define TOUCH_PANEL_PEN_IRQ_N_FREQ 60000000u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_COMPONENT_TYPE altera_avalon_sysid
+#define SYSID_COMPONENT_NAME sysid
+#define SYSID_BASE 0x8001400
+#define SYSID_SPAN 16u
+#define SYSID_ID 1597074984u
+#define SYSID_TIMESTAMP 1254740213u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x8001410
+#define JTAG_UART_SPAN 16u
+#define JTAG_UART_IRQ 7
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'ps2_0', class 'altera_up_avalon_ps2_classic'
+ * The macros are prefixed with 'PS2_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define PS2_0_COMPONENT_TYPE altera_up_avalon_ps2_classic
+#define PS2_0_COMPONENT_NAME ps2_0
+#define PS2_0_BASE 0x8001420
+#define PS2_0_SPAN 8u
+#define PS2_0_IRQ 9
+
+/*
+ * Macros for device 'gpio_0', class 'gpio'
+ * The macros are prefixed with 'GPIO_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define GPIO_0_COMPONENT_TYPE gpio
+#define GPIO_0_COMPONENT_NAME gpio_0
+#define GPIO_0_BASE 0x8001500
+#define GPIO_0_SPAN 128u
+
+/*
+ * Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
+#define ONCHIP_MEMORY2_0_BASE 0x9000000
+#define ONCHIP_MEMORY2_0_SPAN 512u
+#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "onchip_memory2_0"
+#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "Automatic"
+#define ONCHIP_MEMORY2_0_WRITABLE 1
+#define ONCHIP_MEMORY2_0_DUAL_PORT 1
+#define ONCHIP_MEMORY2_0_SIZE_VALUE 512u
+#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
+#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
+#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "Auto"
+#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
+#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
+#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
+
+
+#endif /* _ALTERA_CPU_H_ */
diff --git a/include/configs/NEEK.h b/include/configs/NEEK.h
new file mode 100644
index 0000000..491fe01
--- /dev/null
+++ b/include/configs/NEEK.h
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/neek_ocm_spi_mmu.h"
+#define CONFIG_BOARD_NAME "NEEK"
+#define CONFIG_NEEK
+
+#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE		(DDR_SDRAM_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR_SDRAM_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_0_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_HBT 2		/* heartbeat status LED */
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(EXT_FLASH_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART_FREQ
+#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(SYS_CLK_TIMER_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		SYS_CLK_TIMER_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((SYS_CLK_TIMER_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_HZ			100
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED			/* Enable status driver */
+#define CONFIG_GPIOLED				/* Enable gpioled driver */
+
+#define STATUS_LED_BIT		CONFIG_SYS_GPIO_HBT
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)	/* 500 mS */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_CMD_MII */
+#define CONFIG_ETHPRIME "tse0"
+#undef	CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+#define CONFIG_ETHOC
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_SERVERIP	192.168.1.254
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/* #define CONFIG_CMD_SAVES */
+/* #define CONFIG_CMD_JFFS2 */
+/* #define CONFIG_JFFS2_CMDLINE */
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+/* save the env in unused space of NEEK, please refer to the user guide */
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=boot\0"						\
+	"mtdparts=mtdparts=boot:128k(cat),1408k(sel),11776k(app),-(user)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
                   ` (2 preceding siblings ...)
  2010-03-31  0:50 ` [U-Boot] [PATCH 4/5] nios2: add Altera NEEK board Thomas Chou
@ 2010-03-31  0:50 ` Thomas Chou
  2010-04-17 15:20   ` [U-Boot] [PATCH 5/5 v2] " Thomas Chou
  2010-04-22  9:27   ` [U-Boot] [PATCH 5/5 v3] " Thomas Chou
  2010-04-15 14:55 ` [U-Boot] [PATCH v2] nios2: add nios2-generic board Thomas Chou
                   ` (2 subsequent siblings)
  6 siblings, 2 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  0:50 UTC (permalink / raw)
  To: u-boot

This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization,

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
 lib_nios2/board.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index 311d66c..d5f6c14 100644
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c
@@ -100,7 +100,9 @@ void board_init (void)
 	bd = gd->bd;
 	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
 #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
 	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
 	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
@@ -119,8 +121,20 @@ void board_init (void)
 	/* The Malloc area is immediately below the monitor copy in RAM */
 	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
+#ifndef CONFIG_SYS_NO_FLASH
 	WATCHDOG_RESET ();
 	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
 
 	WATCHDOG_RESET ();
 	env_relocate();
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5 v2] nios2: add Altera EP2C35 board
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
@ 2010-03-31  4:03   ` Thomas Chou
  2010-04-01 12:26     ` Thomas Chou
  2010-04-05  5:48     ` Ben Warren
  2010-03-31  4:03   ` [U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board Thomas Chou
                     ` (2 subsequent siblings)
  3 siblings, 2 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  4:03 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera CycloneII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
change CONFIG_SYS_HZ to 1000.

 MAINTAINERS                          |    1 +
 MAKEALL                              |    1 +
 Makefile                             |    6 +
 board/altera/nios2-generic/2c35_cf.h |  757 ++++++++++++++++++++++++++++++++++
 include/configs/EP2C35.h             |  373 +++++++++++++++++
 5 files changed, 1138 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/2c35_cf.h
 create mode 100644 include/configs/EP2C35.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bb03f17..1f33146 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	EP2C35		Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index a88c31e..8ab3358 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -823,6 +823,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	EP2C35		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index f5b556c..a27b002 100644
--- a/Makefile
+++ b/Makefile
@@ -3533,6 +3533,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = EP2C35
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/2c35_cf.h b/board/altera/nios2-generic/2c35_cf.h
new file mode 100644
index 0000000..a08b35c
--- /dev/null
+++ b/board/altera/nios2-generic/2c35_cf.h
@@ -0,0 +1,757 @@
+#ifndef _ALTERA_2C35_CF_FPGA_H_
+#define _ALTERA_2C35_CF_FPGA_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in
+ * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate macro names.
+ * Instead, use the system header file which has macros with unique names.
+ */
+
+/*
+ * Macros for module 'cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define BIG_ENDIAN 0
+#define CPU_FREQ 85000000
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 4096
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 2048
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 10
+#define TLB_NUM_WAYS 16
+#define TLB_NUM_WAYS_LOG2 4
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc8000000
+#define EXCEPTION_ADDR 0xc6000020
+#define RESET_ADDR 0xc0000000
+#define BREAK_ADDR 0xc2120020
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 0
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 28
+#define DATA_ADDR_WIDTH 28
+#define NUM_OF_SHADOW_REG_SETS 0
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'EXT_FLASH_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define EXT_FLASH_COMPONENT_NAME ext_flash
+#define EXT_FLASH_BASE 0x0
+#define EXT_FLASH_SPAN 16777216
+#define EXT_FLASH_END 0xffffff
+#define EXT_FLASH_SETUP_VALUE 45
+#define EXT_FLASH_WAIT_VALUE 160
+#define EXT_FLASH_HOLD_VALUE 35
+#define EXT_FLASH_TIMING_UNITS "ns"
+#define EXT_FLASH_SIZE 16777216
+#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'cf_ctl', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_CTL_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_CTL_COMPONENT_TYPE altera_avalon_cf
+#define CF_CTL_COMPONENT_NAME cf
+#define CF_CTL_BASE 0x1000000
+#define CF_CTL_SPAN 16
+#define CF_CTL_END 0x100000f
+#define CF_CTL_IRQ 8
+
+/*
+ * Macros for device 'pll', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLL_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x1000020
+#define PLL_SPAN 32
+#define PLL_END 0x100003f
+#define PLL_ARESET "None"
+#define PLL_PFDENA "None"
+#define PLL_LOCKED "None"
+#define PLL_PLLENA "None"
+#define PLL_SCANCLK "None"
+#define PLL_SCANDATA "None"
+#define PLL_SCANREAD "None"
+#define PLL_SCANWRITE "None"
+#define PLL_SCANCLKENA "None"
+#define PLL_SCANACLR "None"
+#define PLL_SCANDATAOUT "None"
+#define PLL_SCANDONE "None"
+#define PLL_CONFIGUPDATE "None"
+#define PLL_PHASECOUNTERSELECT "None"
+#define PLL_PHASEDONE "None"
+#define PLL_PHASEUPDOWN "None"
+#define PLL_PHASESTEP "None"
+
+/*
+ * Macros for device 'pllsysx2', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLLSYSX2_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLLSYSX2_COMPONENT_TYPE altera_avalon_pll
+#define PLLSYSX2_COMPONENT_NAME pllsysx2
+#define PLLSYSX2_BASE 0x1000040
+#define PLLSYSX2_SPAN 32
+#define PLLSYSX2_END 0x100005f
+#define PLLSYSX2_ARESET "None"
+#define PLLSYSX2_PFDENA "None"
+#define PLLSYSX2_LOCKED "None"
+#define PLLSYSX2_PLLENA "None"
+#define PLLSYSX2_SCANCLK "None"
+#define PLLSYSX2_SCANDATA "None"
+#define PLLSYSX2_SCANREAD "None"
+#define PLLSYSX2_SCANWRITE "None"
+#define PLLSYSX2_SCANCLKENA "None"
+#define PLLSYSX2_SCANACLR "None"
+#define PLLSYSX2_SCANDATAOUT "None"
+#define PLLSYSX2_SCANDONE "None"
+#define PLLSYSX2_CONFIGUPDATE "None"
+#define PLLSYSX2_PHASECOUNTERSELECT "None"
+#define PLLSYSX2_PHASEDONE "None"
+#define PLLSYSX2_PHASEUPDOWN "None"
+#define PLLSYSX2_PHASESTEP "None"
+
+/*
+ * Macros for device 'cf_ide', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_IDE_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_IDE_COMPONENT_TYPE altera_avalon_cf
+#define CF_IDE_COMPONENT_NAME cf
+#define CF_IDE_BASE 0x1000080
+#define CF_IDE_SPAN 64
+#define CF_IDE_END 0x10000bf
+#define CF_IDE_IRQ 9
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * The macros are prefixed with 'EXT_SSRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define EXT_SSRAM_BASE 0x1400000
+#define EXT_SSRAM_SPAN 2097152
+#define EXT_SSRAM_END 0x15fffff
+#define EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * The macros are prefixed with 'LAN91C111_'.
+ * The prefix is the slave descriptor.
+ */
+#define LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define LAN91C111_COMPONENT_NAME lan91c111
+#define LAN91C111_BASE 0x2110000
+#define LAN91C111_SPAN 65536
+#define LAN91C111_END 0x211ffff
+#define LAN91C111_IRQ 6
+#define LAN91C111_IS_ETHERNET_MAC 1
+#define LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'sys_clk_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'SYS_CLK_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYS_CLK_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define SYS_CLK_TIMER_COMPONENT_NAME sys_clk_timer
+#define SYS_CLK_TIMER_BASE 0x2120800
+#define SYS_CLK_TIMER_SPAN 32
+#define SYS_CLK_TIMER_END 0x212081f
+#define SYS_CLK_TIMER_IRQ 0
+#define SYS_CLK_TIMER_ALWAYS_RUN 0
+#define SYS_CLK_TIMER_FIXED_PERIOD 0
+#define SYS_CLK_TIMER_SNAPSHOT 1
+#define SYS_CLK_TIMER_PERIOD 10.0
+#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
+#define SYS_CLK_TIMER_RESET_OUTPUT 0
+#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define SYS_CLK_TIMER_FREQ 85000000
+#define SYS_CLK_TIMER_LOAD_VALUE 849999ULL
+#define SYS_CLK_TIMER_COUNTER_SIZE 32
+#define SYS_CLK_TIMER_MULT 0.0010
+#define SYS_CLK_TIMER_TICKS_PER_SEC 100
+
+/*
+ * Macros for device 'high_res_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'HIGH_RES_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define HIGH_RES_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define HIGH_RES_TIMER_COMPONENT_NAME high_res_timer
+#define HIGH_RES_TIMER_BASE 0x2120820
+#define HIGH_RES_TIMER_SPAN 32
+#define HIGH_RES_TIMER_END 0x212083f
+#define HIGH_RES_TIMER_IRQ 3
+#define HIGH_RES_TIMER_ALWAYS_RUN 0
+#define HIGH_RES_TIMER_FIXED_PERIOD 0
+#define HIGH_RES_TIMER_SNAPSHOT 1
+#define HIGH_RES_TIMER_PERIOD 10.0
+#define HIGH_RES_TIMER_PERIOD_UNITS "us"
+#define HIGH_RES_TIMER_RESET_OUTPUT 0
+#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define HIGH_RES_TIMER_FREQ 85000000
+#define HIGH_RES_TIMER_LOAD_VALUE 849ULL
+#define HIGH_RES_TIMER_COUNTER_SIZE 32
+#define HIGH_RES_TIMER_MULT 1.0E-6
+#define HIGH_RES_TIMER_TICKS_PER_SEC 100000
+
+/*
+ * Macros for device 'uart1', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART1_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART1_COMPONENT_TYPE altera_avalon_uart
+#define UART1_COMPONENT_NAME uart1
+#define UART1_BASE 0x2120840
+#define UART1_SPAN 32
+#define UART1_END 0x212085f
+#define UART1_IRQ 4
+#define UART1_BAUD 115200
+#define UART1_DATA_BITS 8
+#define UART1_FIXED_BAUD 1
+#define UART1_PARITY 'N'
+#define UART1_STOP_BITS 1
+#define UART1_SYNC_REG_DEPTH 2
+#define UART1_USE_CTS_RTS 0
+#define UART1_USE_EOP_REGISTER 0
+#define UART1_SIM_TRUE_BAUD 0
+#define UART1_SIM_CHAR_STREAM ""
+#define UART1_FREQ 85000000
+
+/*
+ * Macros for device 'button_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'BUTTON_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
+#define BUTTON_PIO_COMPONENT_NAME button_pio
+#define BUTTON_PIO_BASE 0x2120860
+#define BUTTON_PIO_SPAN 16
+#define BUTTON_PIO_END 0x212086f
+#define BUTTON_PIO_IRQ 2
+#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1
+#define BUTTON_PIO_DRIVEN_SIM_VALUE 0xf
+#define BUTTON_PIO_HAS_TRI 0
+#define BUTTON_PIO_HAS_OUT 0
+#define BUTTON_PIO_HAS_IN 1
+#define BUTTON_PIO_CAPTURE 1
+#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define BUTTON_PIO_DATA_WIDTH 4
+#define BUTTON_PIO_RESET_VALUE 0x0
+#define BUTTON_PIO_EDGE_TYPE "ANY"
+#define BUTTON_PIO_IRQ_TYPE "EDGE"
+#define BUTTON_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'led_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'LED_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
+#define LED_PIO_COMPONENT_NAME led_pio
+#define LED_PIO_BASE 0x2120870
+#define LED_PIO_SPAN 16
+#define LED_PIO_END 0x212087f
+#define LED_PIO_DO_TEST_BENCH_WIRING 0
+#define LED_PIO_DRIVEN_SIM_VALUE 0x0
+#define LED_PIO_HAS_TRI 0
+#define LED_PIO_HAS_OUT 1
+#define LED_PIO_HAS_IN 0
+#define LED_PIO_CAPTURE 0
+#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define LED_PIO_DATA_WIDTH 8
+#define LED_PIO_RESET_VALUE 0x0
+#define LED_PIO_EDGE_TYPE "NONE"
+#define LED_PIO_IRQ_TYPE "NONE"
+#define LED_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'lcd_display', class 'altera_avalon_lcd_16207'
+ * The macros are prefixed with 'LCD_DISPLAY_'.
+ * The prefix is the slave descriptor.
+ */
+#define LCD_DISPLAY_COMPONENT_TYPE altera_avalon_lcd_16207
+#define LCD_DISPLAY_COMPONENT_NAME lcd_display
+#define LCD_DISPLAY_BASE 0x2120880
+#define LCD_DISPLAY_SPAN 16
+#define LCD_DISPLAY_END 0x212088f
+
+/*
+ * Macros for device 'seven_seg_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'SEVEN_SEG_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define SEVEN_SEG_PIO_COMPONENT_TYPE altera_avalon_pio
+#define SEVEN_SEG_PIO_COMPONENT_NAME seven_seg_pio
+#define SEVEN_SEG_PIO_BASE 0x2120890
+#define SEVEN_SEG_PIO_SPAN 16
+#define SEVEN_SEG_PIO_END 0x212089f
+#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0
+#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0
+#define SEVEN_SEG_PIO_HAS_TRI 0
+#define SEVEN_SEG_PIO_HAS_OUT 1
+#define SEVEN_SEG_PIO_HAS_IN 0
+#define SEVEN_SEG_PIO_CAPTURE 0
+#define SEVEN_SEG_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define SEVEN_SEG_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define SEVEN_SEG_PIO_DATA_WIDTH 16
+#define SEVEN_SEG_PIO_RESET_VALUE 0x0
+#define SEVEN_SEG_PIO_EDGE_TYPE "NONE"
+#define SEVEN_SEG_PIO_IRQ_TYPE "NONE"
+#define SEVEN_SEG_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'reconfig_request_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'RECONFIG_REQUEST_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define RECONFIG_REQUEST_PIO_COMPONENT_TYPE altera_avalon_pio
+#define RECONFIG_REQUEST_PIO_COMPONENT_NAME reconfig_request_pio
+#define RECONFIG_REQUEST_PIO_BASE 0x21208a0
+#define RECONFIG_REQUEST_PIO_SPAN 16
+#define RECONFIG_REQUEST_PIO_END 0x21208af
+#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0
+#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_HAS_TRI 1
+#define RECONFIG_REQUEST_PIO_HAS_OUT 0
+#define RECONFIG_REQUEST_PIO_HAS_IN 0
+#define RECONFIG_REQUEST_PIO_CAPTURE 0
+#define RECONFIG_REQUEST_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define RECONFIG_REQUEST_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define RECONFIG_REQUEST_PIO_DATA_WIDTH 1
+#define RECONFIG_REQUEST_PIO_RESET_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x21208b0
+#define JTAG_UART_SPAN 8
+#define JTAG_UART_END 0x21208b7
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_COMPONENT_TYPE altera_avalon_sysid
+#define SYSID_COMPONENT_NAME sysid
+#define SYSID_BASE 0x21208b8
+#define SYSID_SPAN 8
+#define SYSID_END 0x21208bf
+#define SYSID_ID 1003732523
+#define SYSID_TIMESTAMP 1268227126
+
+/*
+ * Macros for device 'performance_counter', class 'altera_avalon_performance_counter'
+ * The macros are prefixed with 'PERFORMANCE_COUNTER_'.
+ * The prefix is the slave descriptor.
+ */
+#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter
+#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter
+#define PERFORMANCE_COUNTER_BASE 0x2120900
+#define PERFORMANCE_COUNTER_SPAN 64
+#define PERFORMANCE_COUNTER_END 0x212093f
+#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 3
+
+/*
+ * Macros for device 'dma', class 'altera_avalon_dma'
+ * The macros are prefixed with 'DMA_'.
+ * The prefix is the slave descriptor.
+ */
+#define DMA_COMPONENT_TYPE altera_avalon_dma
+#define DMA_COMPONENT_NAME dma
+#define DMA_BASE 0x2120a00
+#define DMA_SPAN 32
+#define DMA_END 0x2120a1f
+#define DMA_IRQ 7
+#define DMA_LENGTHWIDTH 13
+#define DMA_ALLOW_BYTE_TRANSACTIONS 1
+#define DMA_ALLOW_HW_TRANSACTIONS 1
+#define DMA_ALLOW_WORD_TRANSACTIONS 1
+#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1
+#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1
+#define DMA_MAX_BURST_SIZE 128
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_READ_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_READ_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_READ_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_READ_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_READ_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_READ_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_READ_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_READ_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_READ_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_READ_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_READ_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_READ_MASTER_LAN91C111_SPAN 65536
+#define DMA_READ_MASTER_LAN91C111_END 0x211ffff
+#define DMA_READ_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_READ_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_READ_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_READ_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_WRITE_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_WRITE_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_WRITE_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_WRITE_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_WRITE_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_WRITE_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_WRITE_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_WRITE_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_WRITE_MASTER_LAN91C111_SPAN 65536
+#define DMA_WRITE_MASTER_LAN91C111_END 0x211ffff
+#define DMA_WRITE_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'epcs_controller', class 'altera_avalon_epcs_flash_controller'
+ * The macros are prefixed with 'EPCS_CONTROLLER_'.
+ * The prefix is the slave descriptor.
+ */
+#define EPCS_CONTROLLER_COMPONENT_TYPE altera_avalon_epcs_flash_controller
+#define EPCS_CONTROLLER_COMPONENT_NAME epcs_controller
+#define EPCS_CONTROLLER_BASE 0x3200000
+#define EPCS_CONTROLLER_SPAN 2048
+#define EPCS_CONTROLLER_END 0x32007ff
+#define EPCS_CONTROLLER_IRQ 5
+#define EPCS_CONTROLLER_REGISTER_OFFSET 512
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_FILENAME epcs_controller_boot_rom
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_EPCS 1
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_HEX 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_HEX_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * The macros are prefixed with 'DDR_SDRAM_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DDR_SDRAM_0_BASE 0x6000000
+#define DDR_SDRAM_0_SPAN 33554432
+#define DDR_SDRAM_0_END 0x7ffffff
+#define DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_instruction_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_INSTRUCTION_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_NAME tightly_coupled_instruction_memory
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_BASE 0x8000000
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SPAN 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_END 0x8000fff
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_instruction_memory"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_VALUE 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+
+#endif /* _ALTERA_2C35_CF_FPGA_H_ */
diff --git a/include/configs/EP2C35.h b/include/configs/EP2C35.h
new file mode 100644
index 0000000..bb85741
--- /dev/null
+++ b/include/configs/EP2C35.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/2c35_cf.h"
+#define CONFIG_BOARD_NAME "EP2C35"
+#define CONFIG_EP2C35
+
+#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE		(DDR_SDRAM_0_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR_SDRAM_0_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0
+# define CONFIG_SYS_GPIO_SCL 1
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(EXT_FLASH_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ALTERA_SPI
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART1_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART1_FREQ
+#define CONFIG_BAUDRATE		UART1_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART1_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(SYS_CLK_TIMER_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		SYS_CLK_TIMER_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((SYS_CLK_TIMER_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_NIOS_TMRMS		1	/* Must be one */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		(LED_PIO_BASE | IO_REGION_BASE)
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2) /* 500 mS */
+
+/*
+ * IDE support
+ */
+#define CONFIG_CMD_IDE
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE	((LAN91C111_BASE + \
+				  LAN91C111_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_CMD_MII */
+#define CONFIG_ETHPRIME "tse0"
+#undef	CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_SERVERIP	192.168.1.254
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/* #define CONFIG_CMD_SAVES */
+/* #define CONFIG_CMD_JFFS2 */
+/* #define CONFIG_JFFS2_CMDLINE */
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=nor0\0"						\
+	"mtdparts=mtdparts=nor0:2m(boot),6m(romfs),4m(user),4m(factory)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
  2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
@ 2010-03-31  4:03   ` Thomas Chou
  2010-04-02  1:33     ` [U-Boot] [PATCH 3/5 v3] " Thomas Chou
  2010-03-31  4:03   ` [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board Thomas Chou
  2010-04-01  7:17   ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Michal Simek
  3 siblings, 1 reply; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  4:03 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera CycloneIII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
change CONFIG_SYS_HZ to	1000.

 MAINTAINERS                              |    1 +
 MAKEALL                                  |    1 +
 Makefile                                 |    2 +-
 board/altera/nios2-generic/default_mmu.h |  371 ++++++++++++++++++++++++++++
 include/configs/EP3C120.h                |  395 ++++++++++++++++++++++++++++++
 5 files changed, 769 insertions(+), 1 deletions(-)
 create mode 100644 board/altera/nios2-generic/default_mmu.h
 create mode 100644 include/configs/EP3C120.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 1f33146..30ac451 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -851,6 +851,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1S10		Nios-II
 	EP1S40		Nios-II
 	EP2C35		Nios-II
+	EP3C120	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index 8ab3358..886d608 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2="		\
 	PCI5441		\
 	PK1C20		\
 	EP2C35		\
+	EP3C120	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index a27b002..5b3c589 100644
--- a/Makefile
+++ b/Makefile
@@ -3534,7 +3534,7 @@ PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
 # nios2 generic boards
-NIOS2_GENERIC = EP2C35
+NIOS2_GENERIC = EP2C35 EP3C120
 
 $(NIOS2_GENERIC:%=%_config) : unconfig
 	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h
new file mode 100644
index 0000000..dc14dc2
--- /dev/null
+++ b/board/altera/nios2-generic/default_mmu.h
@@ -0,0 +1,371 @@
+#ifndef _ALTERA_LINUX_CPU_H_
+#define _ALTERA_LINUX_CPU_H_
+
+/* Note, this file was manually edited after generation
+ * since the multiple inclusion proctetion macro above collides with
+ * include/linux/cpu.h
+ */
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
+ * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'linux_cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not #include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate #defines.
+ * Instead, use the system header file which has #defines with unique names.
+ */
+
+/*
+ * Macros for module 'linux_cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 32768
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 32768
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 8
+#define TLB_NUM_WAYS 16
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc7fff400
+#define EXCEPTION_ADDR 0xd0000020
+#define RESET_ADDR 0xc2800000
+#define BREAK_ADDR 0xc7fff820
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 1
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 29
+#define DATA_ADDR_WIDTH 29
+
+/*
+ * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'CFI_FLASH_64M_'.
+ * The prefix is the slave descriptor.
+ */
+#define CFI_FLASH_64M_BASE 0x0
+#define CFI_FLASH_64M_SPAN 67108864u
+#define CFI_FLASH_64M_SETUP_VALUE 75
+#define CFI_FLASH_64M_WAIT_VALUE 35
+#define CFI_FLASH_64M_HOLD_VALUE 1
+#define CFI_FLASH_64M_TIMING_UNITS "ns"
+#define CFI_FLASH_64M_SIZE 67108864u
+
+/*
+ * Macros for device 'fast_tlb_miss_ram_1k', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'FAST_TLB_MISS_RAM_1K_'.
+ * The prefix is the slave descriptor.
+ */
+#define FAST_TLB_MISS_RAM_1K_BASE 0x7fff400
+#define FAST_TLB_MISS_RAM_1K_SPAN 1024u
+#define FAST_TLB_MISS_RAM_1K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define FAST_TLB_MISS_RAM_1K_INIT_CONTENTS_FILE "fast_tlb_miss_ram_1k"
+#define FAST_TLB_MISS_RAM_1K_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define FAST_TLB_MISS_RAM_1K_GUI_RAM_BLOCK_TYPE "Automatic"
+#define FAST_TLB_MISS_RAM_1K_WRITABLE 1
+#define FAST_TLB_MISS_RAM_1K_DUAL_PORT 1
+#define FAST_TLB_MISS_RAM_1K_SIZE_VALUE 1024u
+#define FAST_TLB_MISS_RAM_1K_SIZE_MULTIPLE 1
+#define FAST_TLB_MISS_RAM_1K_CONTENTS_INFO ""
+#define FAST_TLB_MISS_RAM_1K_RAM_BLOCK_TYPE "Auto"
+#define FAST_TLB_MISS_RAM_1K_INIT_MEM_CONTENT 1
+#define FAST_TLB_MISS_RAM_1K_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define FAST_TLB_MISS_RAM_1K_INSTANCE_ID "NONE"
+#define FAST_TLB_MISS_RAM_1K_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define DESCRIPTOR_MEMORY_BASE 0x8002000
+#define DESCRIPTOR_MEMORY_SPAN 8192u
+#define DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "descriptor_memory"
+#define DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DESCRIPTOR_MEMORY_WRITABLE 1
+#define DESCRIPTOR_MEMORY_DUAL_PORT 0
+#define DESCRIPTOR_MEMORY_SIZE_VALUE 8192u
+#define DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1
+#define DESCRIPTOR_MEMORY_CONTENTS_INFO ""
+#define DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 1
+#define DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DESCRIPTOR_MEMORY_INSTANCE_ID "NONE"
+#define DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'tse_mac', class 'triple_speed_ethernet'
+ * The macros are prefixed with 'TSE_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define TSE_MAC_BASE 0x8004000
+#define TSE_MAC_SPAN 1024u
+#define TSE_MAC_TRANSMIT "sgdma_tx"
+#define TSE_MAC_RECEIVE "sgdma_rx"
+#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
+#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
+#define TSE_MAC_FIFO_WIDTH 32
+#define TSE_MAC_ENABLE_MACLITE 0
+#define TSE_MAC_MACLITE_GIGE 0
+#define TSE_MAC_USE_MDIO 1
+#define TSE_MAC_NUMBER_OF_CHANNEL 0
+#define TSE_MAC_NUMBER_OF_MAC_MDIO_SHARED 0
+#define TSE_MAC_IS_MULTICHANNEL_MAC 0
+#define TSE_MAC_MDIO_SHARED 0
+#define TSE_MAC_REGISTER_SHARED 0
+#define TSE_MAC_PCS 0
+#define TSE_MAC_PCS_SGMII 0
+#define TSE_MAC_PCS_ID 0u
+
+/*
+ * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_RX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_RX_BASE 0x8004400
+#define SGDMA_RX_SPAN 1024u
+#define SGDMA_RX_IRQ 2
+#define SGDMA_RX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_STREAM_DATA_WIDTH 32
+#define SGDMA_RX_ADDRESS_WIDTH 32
+#define SGDMA_RX_HAS_READ_BLOCK 0
+#define SGDMA_RX_HAS_WRITE_BLOCK 1
+#define SGDMA_RX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_BURST_TRANSFER 0
+#define SGDMA_RX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_RX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_RX_UNALIGNED_TRANSFER 0
+#define SGDMA_RX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_RX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_RX_DESC_DATA_WIDTH 32
+#define SGDMA_RX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_RX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_RX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_RX_BURST_DATA_WIDTH 8
+#define SGDMA_RX_CONTROL_DATA_WIDTH 8
+#define SGDMA_RX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_RX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_RX_SYMBOLS_PER_BEAT 4
+#define SGDMA_RX_IN_ERROR_WIDTH 6
+#define SGDMA_RX_OUT_ERROR_WIDTH 0
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_rx_m_write'.
+ * The macros are prefixed with 'SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_TX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_TX_BASE 0x8004800
+#define SGDMA_TX_SPAN 1024u
+#define SGDMA_TX_IRQ 3
+#define SGDMA_TX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_STREAM_DATA_WIDTH 32
+#define SGDMA_TX_ADDRESS_WIDTH 32
+#define SGDMA_TX_HAS_READ_BLOCK 1
+#define SGDMA_TX_HAS_WRITE_BLOCK 0
+#define SGDMA_TX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_BURST_TRANSFER 0
+#define SGDMA_TX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_TX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_TX_UNALIGNED_TRANSFER 0
+#define SGDMA_TX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_TX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_TX_DESC_DATA_WIDTH 32
+#define SGDMA_TX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_TX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_TX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_TX_BURST_DATA_WIDTH 8
+#define SGDMA_TX_CONTROL_DATA_WIDTH 8
+#define SGDMA_TX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_TX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_TX_SYMBOLS_PER_BEAT 4
+#define SGDMA_TX_IN_ERROR_WIDTH 0
+#define SGDMA_TX_OUT_ERROR_WIDTH 1
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_tx_m_read'.
+ * The macros are prefixed with 'SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_BASE 0x8004c80
+#define UART_SPAN 32u
+#define UART_IRQ 10
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 0
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 62500000u
+
+/*
+ * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_LED_PIO_8OUT_BASE 0x8004cc0
+#define USER_LED_PIO_8OUT_SPAN 16u
+#define USER_LED_PIO_8OUT_DO_TEST_BENCH_WIRING 0
+#define USER_LED_PIO_8OUT_DRIVEN_SIM_VALUE 0x0
+#define USER_LED_PIO_8OUT_HAS_TRI 0
+#define USER_LED_PIO_8OUT_HAS_OUT 1
+#define USER_LED_PIO_8OUT_HAS_IN 0
+#define USER_LED_PIO_8OUT_CAPTURE 0
+#define USER_LED_PIO_8OUT_BIT_CLEARING_EDGE_REGISTER 0
+#define USER_LED_PIO_8OUT_DATA_WIDTH 8
+#define USER_LED_PIO_8OUT_RESET_VALUE 0xff
+#define USER_LED_PIO_8OUT_EDGE_TYPE "NONE"
+#define USER_LED_PIO_8OUT_IRQ_TYPE "NONE"
+#define USER_LED_PIO_8OUT_FREQ 62500000u
+
+/*
+ * Macros for device 'user_dipsw_pio_8in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_DIPSW_PIO_8IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_DIPSW_PIO_8IN_BASE 0x8004ce0
+#define USER_DIPSW_PIO_8IN_SPAN 16u
+#define USER_DIPSW_PIO_8IN_IRQ 8
+#define USER_DIPSW_PIO_8IN_DO_TEST_BENCH_WIRING 0
+#define USER_DIPSW_PIO_8IN_DRIVEN_SIM_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_HAS_TRI 0
+#define USER_DIPSW_PIO_8IN_HAS_OUT 0
+#define USER_DIPSW_PIO_8IN_HAS_IN 1
+#define USER_DIPSW_PIO_8IN_CAPTURE 1
+#define USER_DIPSW_PIO_8IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_DIPSW_PIO_8IN_DATA_WIDTH 8
+#define USER_DIPSW_PIO_8IN_RESET_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_EDGE_TYPE "ANY"
+#define USER_DIPSW_PIO_8IN_IRQ_TYPE "EDGE"
+#define USER_DIPSW_PIO_8IN_FREQ 62500000u
+
+/*
+ * Macros for device 'user_pb_pio_4in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_PB_PIO_4IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_PB_PIO_4IN_BASE 0x8004d00
+#define USER_PB_PIO_4IN_SPAN 16u
+#define USER_PB_PIO_4IN_IRQ 9
+#define USER_PB_PIO_4IN_DO_TEST_BENCH_WIRING 0
+#define USER_PB_PIO_4IN_DRIVEN_SIM_VALUE 0x0
+#define USER_PB_PIO_4IN_HAS_TRI 0
+#define USER_PB_PIO_4IN_HAS_OUT 0
+#define USER_PB_PIO_4IN_HAS_IN 1
+#define USER_PB_PIO_4IN_CAPTURE 1
+#define USER_PB_PIO_4IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_PB_PIO_4IN_DATA_WIDTH 4
+#define USER_PB_PIO_4IN_RESET_VALUE 0x0
+#define USER_PB_PIO_4IN_EDGE_TYPE "ANY"
+#define USER_PB_PIO_4IN_IRQ_TYPE "EDGE"
+#define USER_PB_PIO_4IN_FREQ 62500000u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_BASE 0x8004d40
+#define SYSID_SPAN 8u
+#define SYSID_ID 1174346794u
+#define SYSID_TIMESTAMP 1233287581u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_BASE 0x8004d50
+#define JTAG_UART_SPAN 8u
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
+ * The macros are prefixed with 'LINUX_TIMER_1MS_'.
+ * The prefix is the slave descriptor.
+ */
+#define LINUX_TIMER_1MS_BASE 0x8400000
+#define LINUX_TIMER_1MS_SPAN 32u
+#define LINUX_TIMER_1MS_IRQ 11
+#define LINUX_TIMER_1MS_ALWAYS_RUN 0
+#define LINUX_TIMER_1MS_FIXED_PERIOD 0
+#define LINUX_TIMER_1MS_SNAPSHOT 1
+#define LINUX_TIMER_1MS_PERIOD 1
+#define LINUX_TIMER_1MS_PERIOD_UNITS "ms"
+#define LINUX_TIMER_1MS_RESET_OUTPUT 0
+#define LINUX_TIMER_1MS_TIMEOUT_PULSE_OUTPUT 0
+#define LINUX_TIMER_1MS_FREQ 125000000u
+#define LINUX_TIMER_1MS_LOAD_VALUE 124999ULL
+#define LINUX_TIMER_1MS_COUNTER_SIZE 32
+#define LINUX_TIMER_1MS_MULT 0.0010
+#define LINUX_TIMER_1MS_TICKS_PER_SEC 1000u
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define DDR2_LO_LATENCY_128M_SPAN 134217728
+
+
+#endif /* _ALTERA_LINUX_CPU_H_ */
diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
new file mode 100644
index 0000000..cfd5569
--- /dev/null
+++ b/include/configs/EP3C120.h
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/default_mmu.h"
+#define CONFIG_BOARD_NAME "EP3C120"
+#define CONFIG_EP3C120
+
+#define CONFIG_SYS_CLK_FREQ		125000000
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR2_LO_LATENCY_128M_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0
+# define CONFIG_SYS_GPIO_SCL 1
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(CFI_FLASH_64M_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART_FREQ
+#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		LINUX_TIMER_1MS_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((LINUX_TIMER_1MS_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_NIOS_TMRMS		1	/* Must be one */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		(USER_LED_PIO_8OUT_BASE | \
+					 IO_REGION_BASE)
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2) /* 500 mS */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+#define CONFIG_ALTERA_TSE
+#define CONFIG_MII		1
+#define CONFIG_CMD_MII
+#define CONFIG_ETHPRIME "tse0"
+#undef  CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_GWADDR		192.168.1.1
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_BOOTDELAY	10
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=ep3c120-flash\0"					\
+	"mtdparts=mtdparts=ep3c120-flash:40m(JFFS),1M(U-Boot),4m(uImage1)," \
+	"4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
+	"3584k(USER_IMAGE),512k(options-bits)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS \
+	"autoload=no\0"						\
+	"autostart=no\0"						\
+	"bootcmd=run tftp_program_flash\0"				\
+	"ipaddr_cmd="							\
+		"echo 'Getting ethaddr from flash';"			\
+		"altera ethaddr;"					\
+		"echo 'DHCP Address';"					\
+		"dhcp;"						\
+		"run set_serverip\0"					\
+	"tftp_program_flash="						\
+		"echo 'TFTP Program Flash';"				\
+		"run ipaddr_cmd;"					\
+		"tftp 0xd1000000 ${serverip}:tftp_program_flash_script.img;" \
+		"iminfo ${fileaddr};"					\
+		"autoscr ${fileaddr};\0"				\
+		"set_serverip=setenv serverip ${tftpserverip}\0"	\
+	"tftpserverip=137.57.185.173\0"				\
+	""
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
  2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
  2010-03-31  4:03   ` [U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board Thomas Chou
@ 2010-03-31  4:03   ` Thomas Chou
  2010-04-01 12:26     ` Thomas Chou
  2010-04-05  5:50     ` Ben Warren
  2010-04-01  7:17   ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Michal Simek
  3 siblings, 2 replies; 24+ messages in thread
From: Thomas Chou @ 2010-03-31  4:03 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera Nios2 Embedded Evaluation Kit using
the example FPGA design at http://nioswiki.com/Linux.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
change CONFIG_SYS_HZ to	1000.

 MAINTAINERS                                   |    1 +
 MAKEALL                                       |    1 +
 Makefile                                      |    2 +-
 board/altera/nios2-generic/neek_ocm_spi_mmu.h |  406 +++++++++++++++++++++++++
 include/configs/NEEK.h                        |  367 ++++++++++++++++++++++
 5 files changed, 776 insertions(+), 1 deletions(-)
 create mode 100644 board/altera/nios2-generic/neek_ocm_spi_mmu.h
 create mode 100644 include/configs/NEEK.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 30ac451..9c0707d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -852,6 +852,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1S40		Nios-II
 	EP2C35		Nios-II
 	EP3C120	Nios-II
+	NEEK		Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index 886d608..694b20e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -825,6 +825,7 @@ LIST_nios2="		\
 	PK1C20		\
 	EP2C35		\
 	EP3C120	\
+	NEEK		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 5b3c589..ab708a0 100644
--- a/Makefile
+++ b/Makefile
@@ -3534,7 +3534,7 @@ PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
 # nios2 generic boards
-NIOS2_GENERIC = EP2C35 EP3C120
+NIOS2_GENERIC = EP2C35 EP3C120 NEEK
 
 $(NIOS2_GENERIC:%=%_config) : unconfig
 	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
diff --git a/board/altera/nios2-generic/neek_ocm_spi_mmu.h b/board/altera/nios2-generic/neek_ocm_spi_mmu.h
new file mode 100644
index 0000000..5e62059
--- /dev/null
+++ b/board/altera/nios2-generic/neek_ocm_spi_mmu.h
@@ -0,0 +1,406 @@
+#ifndef _ALTERA_CPU_H_
+#define _ALTERA_CPU_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'cycloneIII_embedded_evaluation_kit_standard_sopc' in
+ * file './cycloneIII_embedded_evaluation_kit_standard_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'cpu' and devices
+ * connected to the following masters:
+ *   instruction_master
+ *   tightly_coupled_instruction_master_0
+ *   data_master
+ *   tightly_coupled_data_master_0
+ *
+ * Do not #include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate #defines.
+ * Instead, use the system header file which has #defines with unique names.
+ */
+
+/*
+ * Macros for module 'cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define CPU_FREQ 100000000u
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 8192
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 4096
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 10
+#define TLB_NUM_WAYS 16
+#define TLB_NUM_WAYS_LOG2 4
+#define TLB_PTR_SZ 8
+#define TLB_NUM_ENTRIES 256
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc9000000
+#define EXCEPTION_ADDR 0xc0000020
+#define RESET_ADDR 0xc4000000
+#define BREAK_ADDR 0xc6000020
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 0
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 28
+#define DATA_ADDR_WIDTH 28
+
+/*
+ * Macros for device 'ddr_sdram', class 'altmemddr'
+ * The macros are prefixed with 'DDR_SDRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR_SDRAM_COMPONENT_TYPE altmemddr
+#define DDR_SDRAM_COMPONENT_NAME ddr_sdram
+#define DDR_SDRAM_BASE 0x0
+#define DDR_SDRAM_SPAN 33554432
+
+/*
+ * Macros for device 'lcd_sgdma', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'LCD_SGDMA_'.
+ * The prefix is the slave descriptor.
+ */
+#define LCD_SGDMA_COMPONENT_TYPE altera_avalon_sgdma
+#define LCD_SGDMA_COMPONENT_NAME lcd_sgdma
+#define LCD_SGDMA_BASE 0x2000000
+#define LCD_SGDMA_SPAN 1024u
+#define LCD_SGDMA_IRQ 5
+#define LCD_SGDMA_READ_BLOCK_DATA_WIDTH 64
+#define LCD_SGDMA_WRITE_BLOCK_DATA_WIDTH 64
+#define LCD_SGDMA_STREAM_DATA_WIDTH 64
+#define LCD_SGDMA_ADDRESS_WIDTH 32
+#define LCD_SGDMA_HAS_READ_BLOCK 1
+#define LCD_SGDMA_HAS_WRITE_BLOCK 0
+#define LCD_SGDMA_READ_BURSTCOUNT_WIDTH 4
+#define LCD_SGDMA_WRITE_BURSTCOUNT_WIDTH 4
+#define LCD_SGDMA_BURST_TRANSFER 0
+#define LCD_SGDMA_ALWAYS_DO_MAX_BURST 1
+#define LCD_SGDMA_DESCRIPTOR_READ_BURST 0
+#define LCD_SGDMA_UNALIGNED_TRANSFER 0
+#define LCD_SGDMA_CONTROL_SLAVE_DATA_WIDTH 32
+#define LCD_SGDMA_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define LCD_SGDMA_DESC_DATA_WIDTH 32
+#define LCD_SGDMA_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define LCD_SGDMA_STATUS_TOKEN_DATA_WIDTH 24
+#define LCD_SGDMA_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define LCD_SGDMA_BURST_DATA_WIDTH 8
+#define LCD_SGDMA_CONTROL_DATA_WIDTH 8
+#define LCD_SGDMA_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define LCD_SGDMA_COMMAND_FIFO_DATA_WIDTH 104
+#define LCD_SGDMA_SYMBOLS_PER_BEAT 8
+#define LCD_SGDMA_IN_ERROR_WIDTH 0
+#define LCD_SGDMA_OUT_ERROR_WIDTH 0
+
+/*
+ * Macros for device 'ddr_sdram', class 'altmemddr'
+ * Path to the device is from the master group 'lcd_sgdma_m_read'.
+ * The macros are prefixed with 'LCD_SGDMA_M_READ_DDR_SDRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define LCD_SGDMA_M_READ_DDR_SDRAM_COMPONENT_TYPE altmemddr
+#define LCD_SGDMA_M_READ_DDR_SDRAM_COMPONENT_NAME ddr_sdram
+#define LCD_SGDMA_M_READ_DDR_SDRAM_BASE 0x0
+#define LCD_SGDMA_M_READ_DDR_SDRAM_SPAN 33554432u
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'EXT_FLASH_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define EXT_FLASH_COMPONENT_NAME ext_flash
+#define EXT_FLASH_BASE 0x4000000
+#define EXT_FLASH_SPAN 16777216u
+#define EXT_FLASH_SETUP_VALUE 25
+#define EXT_FLASH_WAIT_VALUE 100
+#define EXT_FLASH_HOLD_VALUE 20
+#define EXT_FLASH_TIMING_UNITS "ns"
+#define EXT_FLASH_SIZE 16777216u
+
+/*
+ * Macros for device 'ssram', class 'altera_avalon_cy7c1380_ssram'
+ * The macros are prefixed with 'SSRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define SSRAM_COMPONENT_NAME ssram
+#define SSRAM_BASE 0x5000000
+#define SSRAM_SPAN 1048576u
+#define SSRAM_SRAM_MEMORY_SIZE 1
+#define SSRAM_SRAM_MEMORY_UNITS 1048576
+#define SSRAM_SSRAM_DATA_WIDTH 32
+#define SSRAM_SSRAM_READ_LATENCY 2
+
+/*
+ * Macros for device 'igor_mac', class 'eth_ocm'
+ * The macros are prefixed with 'IGOR_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define IGOR_MAC_COMPONENT_TYPE eth_ocm
+#define IGOR_MAC_COMPONENT_NAME igor_mac
+#define IGOR_MAC_BASE 0x8000000
+#define IGOR_MAC_SPAN 4096u
+#define IGOR_MAC_IRQ 1
+
+/*
+ * Macros for device 'remote_update', class 'altera_avalon_remote_update_cycloneiii'
+ * The macros are prefixed with 'REMOTE_UPDATE_'.
+ * The prefix is the slave descriptor.
+ */
+#define REMOTE_UPDATE_COMPONENT_TYPE altera_avalon_remote_update_cycloneiii
+#define REMOTE_UPDATE_COMPONENT_NAME remote_update
+#define REMOTE_UPDATE_BASE 0x8001000
+#define REMOTE_UPDATE_SPAN 512u
+
+/*
+ * Macros for device 'pll', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLL_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x8001200
+#define PLL_SPAN 64u
+#define PLL_ARESET "None"
+#define PLL_PFDENA "None"
+#define PLL_LOCKED "None"
+#define PLL_PLLENA "None"
+#define PLL_SCANCLK "None"
+#define PLL_SCANDATA "None"
+#define PLL_SCANREAD "None"
+#define PLL_SCANWRITE "None"
+#define PLL_SCANCLKENA "None"
+#define PLL_SCANACLR "None"
+#define PLL_SCANDATAOUT "None"
+#define PLL_SCANDONE "None"
+#define PLL_CONFIGUPDATE "None"
+#define PLL_PHASECOUNTERSELECT "None"
+#define PLL_PHASEDONE "None"
+#define PLL_PHASEUPDOWN "None"
+#define PLL_PHASESTEP "None"
+
+/*
+ * Macros for device 'sys_clk_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'SYS_CLK_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYS_CLK_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define SYS_CLK_TIMER_COMPONENT_NAME sys_clk_timer
+#define SYS_CLK_TIMER_BASE 0x8001240
+#define SYS_CLK_TIMER_SPAN 64u
+#define SYS_CLK_TIMER_IRQ 0
+#define SYS_CLK_TIMER_ALWAYS_RUN 0
+#define SYS_CLK_TIMER_FIXED_PERIOD 0
+#define SYS_CLK_TIMER_SNAPSHOT 1
+#define SYS_CLK_TIMER_PERIOD 10.0
+#define SYS_CLK_TIMER_PERIOD_UNITS "ms"
+#define SYS_CLK_TIMER_RESET_OUTPUT 0
+#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define SYS_CLK_TIMER_FREQ 60000000u
+#define SYS_CLK_TIMER_LOAD_VALUE 599999ULL
+#define SYS_CLK_TIMER_COUNTER_SIZE 32
+#define SYS_CLK_TIMER_MULT 0.0010
+#define SYS_CLK_TIMER_TICKS_PER_SEC 100u
+
+/*
+ * Macros for device 'performance_counter', class 'altera_avalon_performance_counter'
+ * The macros are prefixed with 'PERFORMANCE_COUNTER_'.
+ * The prefix is the slave descriptor.
+ */
+#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter
+#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter
+#define PERFORMANCE_COUNTER_BASE 0x8001280
+#define PERFORMANCE_COUNTER_SPAN 64u
+#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 1
+
+/*
+ * Macros for device 'touch_panel_spi', class 'altera_avalon_spi'
+ * The macros are prefixed with 'TOUCH_PANEL_SPI_'.
+ * The prefix is the slave descriptor.
+ */
+#define TOUCH_PANEL_SPI_COMPONENT_TYPE altera_avalon_spi
+#define TOUCH_PANEL_SPI_COMPONENT_NAME touch_panel_spi
+#define TOUCH_PANEL_SPI_BASE 0x80012c0
+#define TOUCH_PANEL_SPI_SPAN 64u
+#define TOUCH_PANEL_SPI_IRQ 3
+#define TOUCH_PANEL_SPI_DATABITS 8
+#define TOUCH_PANEL_SPI_DATAWIDTH 16
+#define TOUCH_PANEL_SPI_TARGETCLOCK 32000u
+#define TOUCH_PANEL_SPI_CLOCKUNITS "Hz"
+#define TOUCH_PANEL_SPI_CLOCKMULT 1
+#define TOUCH_PANEL_SPI_NUMSLAVES 1
+#define TOUCH_PANEL_SPI_ISMASTER 1
+#define TOUCH_PANEL_SPI_CLOCKPOLARITY 0
+#define TOUCH_PANEL_SPI_CLOCKPHASE 0
+#define TOUCH_PANEL_SPI_LSBFIRST 0
+#define TOUCH_PANEL_SPI_EXTRADELAY 0
+#define TOUCH_PANEL_SPI_TARGETSSDELAY "0.0"
+#define TOUCH_PANEL_SPI_DELAYUNITS "ns"
+#define TOUCH_PANEL_SPI_DELAYMULT "1.0E-9"
+#define TOUCH_PANEL_SPI_PREFIX "spi_"
+
+/*
+ * Macros for device 'mmc_spi', class 'altera_avalon_spi'
+ * The macros are prefixed with 'MMC_SPI_'.
+ * The prefix is the slave descriptor.
+ */
+#define MMC_SPI_COMPONENT_TYPE altera_avalon_spi
+#define MMC_SPI_COMPONENT_NAME mmc_spi
+#define MMC_SPI_BASE 0x8001300
+#define MMC_SPI_SPAN 64u
+#define MMC_SPI_IRQ 8
+#define MMC_SPI_DATABITS 8
+#define MMC_SPI_DATAWIDTH 16
+#define MMC_SPI_TARGETCLOCK 20000000u
+#define MMC_SPI_CLOCKUNITS "Hz"
+#define MMC_SPI_CLOCKMULT 1
+#define MMC_SPI_NUMSLAVES 1
+#define MMC_SPI_ISMASTER 1
+#define MMC_SPI_CLOCKPOLARITY 0
+#define MMC_SPI_CLOCKPHASE 0
+#define MMC_SPI_LSBFIRST 0
+#define MMC_SPI_EXTRADELAY 0
+#define MMC_SPI_TARGETSSDELAY "0.0"
+#define MMC_SPI_DELAYUNITS "ns"
+#define MMC_SPI_DELAYMULT "1.0E-9"
+#define MMC_SPI_PREFIX "spi_"
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_COMPONENT_TYPE altera_avalon_uart
+#define UART_COMPONENT_NAME uart
+#define UART_BASE 0x8001340
+#define UART_SPAN 64u
+#define UART_IRQ 6
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 1
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_SYNC_REG_DEPTH 2
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 66500000u
+
+/*
+ * Macros for device 'touch_panel_pen_irq_n', class 'altera_avalon_pio'
+ * The macros are prefixed with 'TOUCH_PANEL_PEN_IRQ_N_'.
+ * The prefix is the slave descriptor.
+ */
+#define TOUCH_PANEL_PEN_IRQ_N_COMPONENT_TYPE altera_avalon_pio
+#define TOUCH_PANEL_PEN_IRQ_N_COMPONENT_NAME touch_panel_pen_irq_n
+#define TOUCH_PANEL_PEN_IRQ_N_BASE 0x80013e0
+#define TOUCH_PANEL_PEN_IRQ_N_SPAN 32u
+#define TOUCH_PANEL_PEN_IRQ_N_IRQ 4
+#define TOUCH_PANEL_PEN_IRQ_N_DO_TEST_BENCH_WIRING 0
+#define TOUCH_PANEL_PEN_IRQ_N_DRIVEN_SIM_VALUE 0x0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_TRI 0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_OUT 0
+#define TOUCH_PANEL_PEN_IRQ_N_HAS_IN 1
+#define TOUCH_PANEL_PEN_IRQ_N_CAPTURE 1
+#define TOUCH_PANEL_PEN_IRQ_N_BIT_CLEARING_EDGE_REGISTER 0
+#define TOUCH_PANEL_PEN_IRQ_N_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define TOUCH_PANEL_PEN_IRQ_N_DATA_WIDTH 1
+#define TOUCH_PANEL_PEN_IRQ_N_RESET_VALUE 0x0
+#define TOUCH_PANEL_PEN_IRQ_N_EDGE_TYPE "FALLING"
+#define TOUCH_PANEL_PEN_IRQ_N_IRQ_TYPE "EDGE"
+#define TOUCH_PANEL_PEN_IRQ_N_FREQ 60000000u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_COMPONENT_TYPE altera_avalon_sysid
+#define SYSID_COMPONENT_NAME sysid
+#define SYSID_BASE 0x8001400
+#define SYSID_SPAN 16u
+#define SYSID_ID 1597074984u
+#define SYSID_TIMESTAMP 1254740213u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x8001410
+#define JTAG_UART_SPAN 16u
+#define JTAG_UART_IRQ 7
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'ps2_0', class 'altera_up_avalon_ps2_classic'
+ * The macros are prefixed with 'PS2_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define PS2_0_COMPONENT_TYPE altera_up_avalon_ps2_classic
+#define PS2_0_COMPONENT_NAME ps2_0
+#define PS2_0_BASE 0x8001420
+#define PS2_0_SPAN 8u
+#define PS2_0_IRQ 9
+
+/*
+ * Macros for device 'gpio_0', class 'gpio'
+ * The macros are prefixed with 'GPIO_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define GPIO_0_COMPONENT_TYPE gpio
+#define GPIO_0_COMPONENT_NAME gpio_0
+#define GPIO_0_BASE 0x8001500
+#define GPIO_0_SPAN 128u
+
+/*
+ * Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
+ * The prefix is the slave descriptor.
+ */
+#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
+#define ONCHIP_MEMORY2_0_BASE 0x9000000
+#define ONCHIP_MEMORY2_0_SPAN 512u
+#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "onchip_memory2_0"
+#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "Automatic"
+#define ONCHIP_MEMORY2_0_WRITABLE 1
+#define ONCHIP_MEMORY2_0_DUAL_PORT 1
+#define ONCHIP_MEMORY2_0_SIZE_VALUE 512u
+#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
+#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
+#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "Auto"
+#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
+#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
+#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
+
+
+#endif /* _ALTERA_CPU_H_ */
diff --git a/include/configs/NEEK.h b/include/configs/NEEK.h
new file mode 100644
index 0000000..f42701e
--- /dev/null
+++ b/include/configs/NEEK.h
@@ -0,0 +1,367 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/neek_ocm_spi_mmu.h"
+#define CONFIG_BOARD_NAME "NEEK"
+#define CONFIG_NEEK
+
+#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE		(DDR_SDRAM_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR_SDRAM_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_0_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_HBT 2		/* heartbeat status LED */
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(EXT_FLASH_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART_FREQ
+#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(SYS_CLK_TIMER_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		SYS_CLK_TIMER_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT		((SYS_CLK_TIMER_FREQ / \
+					  CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_NIOS_TMRMS		1	/* Must be one */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED			/* Enable status driver */
+#define CONFIG_GPIOLED				/* Enable gpioled driver */
+
+#define STATUS_LED_BIT		CONFIG_SYS_GPIO_HBT
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)	/* 500 mS */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_CMD_MII */
+#define CONFIG_ETHPRIME "tse0"
+#undef	CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+#define CONFIG_ETHOC
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_SERVERIP	192.168.1.254
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/* #define CONFIG_CMD_SAVES */
+/* #define CONFIG_CMD_JFFS2 */
+/* #define CONFIG_JFFS2_CMDLINE */
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+/* save the env in unused space of NEEK, please refer to the user guide */
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=boot\0"						\
+	"mtdparts=mtdparts=boot:128k(cat),1408k(sel),11776k(app),-(user)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board
  2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
                     ` (2 preceding siblings ...)
  2010-03-31  4:03   ` [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board Thomas Chou
@ 2010-04-01  7:17   ` Michal Simek
  2010-04-01 12:24     ` Thomas Chou
  3 siblings, 1 reply; 24+ messages in thread
From: Michal Simek @ 2010-04-01  7:17 UTC (permalink / raw)
  To: u-boot

Thomas Chou wrote:
> This patch supports the Altera CycloneII Nios dev board using
> the example FPGA design at http://nioswiki.com/Linux.
> 
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
>  MAINTAINERS                          |    1 +
>  MAKEALL                              |    1 +
>  Makefile                             |    6 +
>  board/altera/nios2-generic/2c35_cf.h |  757 ++++++++++++++++++++++++++++++++++
>  include/configs/EP2C35.h             |  372 +++++++++++++++++
>  5 files changed, 1137 insertions(+), 0 deletions(-)
>  create mode 100644 board/altera/nios2-generic/2c35_cf.h
>  create mode 100644 include/configs/EP2C35.h

I am strongly against this style of adding any specific nios board to 
U-BOOT.

1. I am not convinced that all information from 2c35_cf.h are important 
for U-BOOT.
What connection has for example "#define KERNEL_REGION_BASE 0xc0000000"?
or others.
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x1000020
+#define PLL_SPAN 32

It is the same situation as we solved for Xilinx boards.
Create generic nios board and then generate only parameters which are 
necessary for U-BOOT itself.
For example I am using only one microblaze generic board to cover all 
microblaze boards.
Look at Microblaze or ppc405/440 solution. board/xilinx is good start 
for you.

Wolfgang: Please reject these patches.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board
  2010-04-01  7:17   ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Michal Simek
@ 2010-04-01 12:24     ` Thomas Chou
  0 siblings, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-01 12:24 UTC (permalink / raw)
  To: u-boot

On 04/01/2010 03:17 PM, Michal Simek wrote:
>
> I am strongly against this style of adding any specific nios board to 
> U-BOOT.
>
> 1. I am not convinced that all information from 2c35_cf.h are 
> important for U-BOOT.
> What connection has for example "#define KERNEL_REGION_BASE 0xc0000000"?
> or others.
> +#define PLL_COMPONENT_TYPE altera_avalon_pll
> +#define PLL_COMPONENT_NAME pll
> +#define PLL_BASE 0x1000020
> +#define PLL_SPAN 32
>
> It is the same situation as we solved for Xilinx boards.
> Create generic nios board and then generate only parameters which are 
> necessary for U-BOOT itself.
> For example I am using only one microblaze generic board to cover all 
> microblaze boards.
> Look at Microblaze or ppc405/440 solution. board/xilinx is good start 
> for you.
>
>

Hi Michal,

Thank you very much for the suggestions. Your experiences are invaluable 
to us.

I will trim down the fpga parameter file. I will keep only one board 
configuration to serve as nios2-generic template, and remove other two.

Best regards,
Thomas

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5 v2] nios2: add Altera EP2C35 board
  2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
@ 2010-04-01 12:26     ` Thomas Chou
  2010-04-05  5:48     ` Ben Warren
  1 sibling, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-01 12:26 UTC (permalink / raw)
  To: u-boot

On 03/31/2010 12:03 PM, Thomas Chou wrote:
> This patch supports the Altera CycloneII Nios dev board using
>    
Please drop this patch.

- Thomas

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board
  2010-03-31  4:03   ` [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board Thomas Chou
@ 2010-04-01 12:26     ` Thomas Chou
  2010-04-05  5:50     ` Ben Warren
  1 sibling, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-01 12:26 UTC (permalink / raw)
  To: u-boot

On 03/31/2010 12:03 PM, Thomas Chou wrote:
> This patch supports the Altera Nios2 Embedded Evaluation Kit using
>    
Please drop this patch.

- Thomas

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 3/5 v3] nios2: add Altera EP3C120 board
  2010-03-31  4:03   ` [U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board Thomas Chou
@ 2010-04-02  1:33     ` Thomas Chou
  2010-04-02  6:57       ` Michal Simek
  2010-04-15 14:40       ` Thomas Chou
  0 siblings, 2 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-02  1:33 UTC (permalink / raw)
  To: u-boot

This patch supports the Altera CycloneIII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.

This board servers as a configuration template for nios2-generic
approach. Since each fpga board can have different designs, we
will refer them as designs rather than boards. All designs can
share the same nios2-generic board directory.

To support a new design,
1. add a configuration file based on EP3C120.h.
2. include the fpga header file
3. add an entry to the NIOS2_GENERIC list in the top Makefile

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
trim down fpga header.
merge timer patch from Scott.
disable altera_tse to cut the dependency.
change mtdparts device name.

After nios2 next merged, this patch is only depended on
1. nios2: Fix outx/writex parameter order in io.h (from Scott)
2. nios2: add nios2-generic board (patch 1/5 in this series)

 MAINTAINERS                              |    1 +
 MAKEALL                                  |    1 +
 Makefile                                 |    6 +
 board/altera/nios2-generic/default_mmu.h |  131 +++++++++++
 include/configs/EP3C120.h                |  376 ++++++++++++++++++++++++++++++
 5 files changed, 515 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/default_mmu.h
 create mode 100644 include/configs/EP3C120.h

diff --git a/MAINTAINERS b/MAINTAINERS
index bb03f17..b26aa22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -850,6 +850,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	EP3C120	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index a88c31e..01a4d2f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -823,6 +823,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	EP3C120	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 4532550..2139333 100644
--- a/Makefile
+++ b/Makefile
@@ -3533,6 +3533,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = EP3C120
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h
new file mode 100644
index 0000000..5637ae4
--- /dev/null
+++ b/board/altera/nios2-generic/default_mmu.h
@@ -0,0 +1,131 @@
+#ifndef _ALTERA_LINUX_CPU_H_
+#define _ALTERA_LINUX_CPU_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
+ * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
+ */
+
+/*
+ * Macros for module 'linux_cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define CPU_FREQ 125000000u
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_SIZE 32768
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_SIZE 32768
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define EXCEPTION_ADDR 0xd0000020
+#define RESET_ADDR 0xc2800000
+#define BREAK_ADDR 0xc7fff820
+
+/*
+ * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'CFI_FLASH_64M_'.
+ * The prefix is the slave descriptor.
+ */
+#define CFI_FLASH_64M_BASE 0x0
+#define CFI_FLASH_64M_SPAN 67108864u
+
+/*
+ * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define DESCRIPTOR_MEMORY_BASE 0x8002000
+#define DESCRIPTOR_MEMORY_SPAN 8192u
+
+/*
+ * Macros for device 'tse_mac', class 'triple_speed_ethernet'
+ * The macros are prefixed with 'TSE_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define TSE_MAC_BASE 0x8004000
+#define TSE_MAC_SPAN 1024u
+#define TSE_MAC_TRANSMIT "sgdma_tx"
+#define TSE_MAC_RECEIVE "sgdma_rx"
+#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
+#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
+
+/*
+ * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_RX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_RX_BASE 0x8004400
+#define SGDMA_RX_SPAN 1024u
+#define SGDMA_RX_IRQ 2
+
+/*
+ * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_TX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_TX_BASE 0x8004800
+#define SGDMA_TX_SPAN 1024u
+#define SGDMA_TX_IRQ 3
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_BASE 0x8004c80
+#define UART_SPAN 32u
+#define UART_IRQ 10
+#define UART_BAUD 115200
+#define UART_FREQ 62500000u
+
+/*
+ * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_LED_PIO_8OUT_BASE 0x8004cc0
+#define USER_LED_PIO_8OUT_SPAN 16u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_BASE 0x8004d40
+#define SYSID_SPAN 8u
+#define SYSID_ID 1174346794u
+#define SYSID_TIMESTAMP 1233287581u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_BASE 0x8004d50
+#define JTAG_UART_SPAN 8u
+#define JTAG_UART_IRQ 1
+
+/*
+ * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
+ * The macros are prefixed with 'LINUX_TIMER_1MS_'.
+ * The prefix is the slave descriptor.
+ */
+#define LINUX_TIMER_1MS_BASE 0x8400000
+#define LINUX_TIMER_1MS_SPAN 32u
+#define LINUX_TIMER_1MS_IRQ 11
+#define LINUX_TIMER_1MS_FREQ 125000000u
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define DDR2_LO_LATENCY_128M_SPAN 134217728
+
+
+#endif /* _ALTERA_LINUX_CPU_H_ */
diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
new file mode 100644
index 0000000..83f9e09
--- /dev/null
+++ b/include/configs/EP3C120.h
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/default_mmu.h"
+#define CONFIG_BOARD_NAME "EP3C120"
+#define CONFIG_EP3C120
+
+#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
+#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE		0		/* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE		0x80000000	/* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(DDR2_LO_LATENCY_128M_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE		(CFI_FLASH_64M_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ		30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
+					  EPCS_CONTROLLER_REGISTER_OFFSET) \
+					 | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE		2
+#define NIOS2_NAND_PLAT_ALE		3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+	       (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ		UART_FREQ
+#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	(LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ		LINUX_TIMER_1MS_IRQ
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS		1	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (LINUX_TIMER_1MS_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		(USER_LED_PIO_8OUT_BASE | \
+					 IO_REGION_BASE)
+/* #define CONFIG_GPIOLED */
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+				 | IO_REGION_BASE) /* Base addr	*/
+#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT	1
+#define CONFIG_DM9000_NO_SROM		1
+/* #define CONFIG_NET_RETRY_COUNT		20 */
+/* #define CONFIG_RESET_PHY_R		1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_CMD_MII */
+/* #define CONFIG_ETHPRIME "tse0" */
+#undef  CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS			1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
+						 IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18
+
+/* TSE Supported modes */
+/* GMII/MII	= 0 */
+/* RGMII	= 1 */
+/* RGMII_ID	= 2 */
+/* RGMII_TXID	= 3 */
+/* RGMII_RXID	= 4 */
+/* SGMII	= 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_GWADDR		192.168.1.1
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_BOOTDELAY	5
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
+# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
+# define CONFIG_ENV_SECT_SIZE		0x20000
+# define CONFIG_ENV_SPI_BUS		0
+# define CONFIG_ENV_SPI_CS		0
+# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET		0x40000
+# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+# define CONFIG_ENV_SIZE		0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+	"mtdids=nor0=physmap-flash.0\0"				\
+	"mtdparts=mtdparts=physmap-flash.0:40m(JFFS),1M(U-Boot),4m(uImage1)," \
+	"4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
+	"3584k(USER_IMAGE),512k(options-bits)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 3/5 v3] nios2: add Altera EP3C120 board
  2010-04-02  1:33     ` [U-Boot] [PATCH 3/5 v3] " Thomas Chou
@ 2010-04-02  6:57       ` Michal Simek
  2010-04-15 14:40       ` Thomas Chou
  1 sibling, 0 replies; 24+ messages in thread
From: Michal Simek @ 2010-04-02  6:57 UTC (permalink / raw)
  To: u-boot

Thomas Chou wrote:
> This patch supports the Altera CycloneIII Nios dev board using
> the example FPGA design at http://nioswiki.com/Linux.
> 
> This board servers as a configuration template for nios2-generic
> approach. Since each fpga board can have different designs, we
> will refer them as designs rather than boards. All designs can
> share the same nios2-generic board directory.

First of all. This patch is nicer than previous one.

Some my other comments below.

> 
> To support a new design,
> 1. add a configuration file based on EP3C120.h.
> 2. include the fpga header file
> 3. add an entry to the NIOS2_GENERIC list in the top Makefile
> 
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
> trim down fpga header.
> merge timer patch from Scott.
> disable altera_tse to cut the dependency.
> change mtdparts device name.
> 
> After nios2 next merged, this patch is only depended on
> 1. nios2: Fix outx/writex parameter order in io.h (from Scott)
> 2. nios2: add nios2-generic board (patch 1/5 in this series)
> 
>  MAINTAINERS                              |    1 +
>  MAKEALL                                  |    1 +
>  Makefile                                 |    6 +
>  board/altera/nios2-generic/default_mmu.h |  131 +++++++++++
>  include/configs/EP3C120.h                |  376 ++++++++++++++++++++++++++++++
>  5 files changed, 515 insertions(+), 0 deletions(-)
>  create mode 100644 board/altera/nios2-generic/default_mmu.h
>  create mode 100644 include/configs/EP3C120.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bb03f17..b26aa22 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -850,6 +850,7 @@ Scott McNutt <smcnutt@psyent.com>
>  	EP1C20		Nios-II
>  	EP1S10		Nios-II
>  	EP1S40		Nios-II
> +	EP3C120	Nios-II
>  
>  #########################################################################
>  # MicroBlaze Systems:							#
> diff --git a/MAKEALL b/MAKEALL
> index a88c31e..01a4d2f 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -823,6 +823,7 @@ LIST_nios2="		\
>  	EP1S40		\
>  	PCI5441		\
>  	PK1C20		\
> +	EP3C120	\
>  "
>  
>  #########################################################################
> diff --git a/Makefile b/Makefile
> index 4532550..2139333 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3533,6 +3533,12 @@ PK1C20_config : unconfig
>  PCI5441_config : unconfig
>  	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
>  
> +# nios2 generic boards
> +NIOS2_GENERIC = EP3C120
> +
> +$(NIOS2_GENERIC:%=%_config) : unconfig
> +	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
> +
>  #========================================================================
>  ## Microblaze
>  #========================================================================
> diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h

IMHO this name is confusing but I am OK if make sense in altera world.

> new file mode 100644
> index 0000000..5637ae4
> --- /dev/null
> +++ b/board/altera/nios2-generic/default_mmu.h
> @@ -0,0 +1,131 @@
> +#ifndef _ALTERA_LINUX_CPU_H_
> +#define _ALTERA_LINUX_CPU_H_

Is it any reason why should be LINUX here? I expect that you will boot 
Linux but U-BOOT is not just about LINUX. IMHO _ALTERA_DEFAULT_MMU_H_ is 
better.

> +
> +/*
> + * This file was automatically generated by the swinfo2header utility.

Can you explain me how is this file generated?
Is there any connection with HW design?
What is the input for that swinfo2header utility?
Is it program which you can change?

I created for Microblaze one BSP which is directly called from design 
tools which generates unified names which are used in U-BOOT. This is 
IMHO the best way how to handle it.

> + *
> + * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
> + * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
> + */

As you wrote above your configuration depends on hw design which is the 
same problem as we faced for Microblaze and PPC.
If you connect board with any HW design, you will have troubles when you 
have to upgrade it. You will do upgrade and then you will send patch to 
U-BOOT. If you do it properly right now, you won't send any patch to U-BOOT.

> +
> +/*
> + * Macros for module 'linux_cpu', class 'altera_nios2'.
> + * The macros have no prefix.
> + */
> +#define CPU_IMPLEMENTATION "fast"

Is it use somewhere?

> +#define CPU_FREQ 125000000u
> +#define ICACHE_LINE_SIZE 32
> +#define ICACHE_SIZE 32768
> +#define DCACHE_LINE_SIZE 32
> +#define DCACHE_SIZE 32768
> +#define MMU_PRESENT

the same? Do you use MMU for U-BOOT or not?

> +#define KERNEL_REGION_BASE 0xc0000000

This parameter name is confusing.

> +#define IO_REGION_BASE 0xe0000000
> +#define EXCEPTION_ADDR 0xd0000020
> +#define RESET_ADDR 0xc2800000
> +#define BREAK_ADDR 0xc7fff820

the same

> +
> +/*
> + * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
> + * The macros are prefixed with 'CFI_FLASH_64M_'.
> + * The prefix is the slave descriptor.
> + */
> +#define CFI_FLASH_64M_BASE 0x0
> +#define CFI_FLASH_64M_SPAN 67108864u

How will look like parameters for 128M flash?
Will be good to use unified names.


> +
> +/*
> + * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
> + * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
> + * The prefix is the slave descriptor.
> + */
> +#define DESCRIPTOR_MEMORY_BASE 0x8002000
> +#define DESCRIPTOR_MEMORY_SPAN 8192u
> +
> +/*
> + * Macros for device 'tse_mac', class 'triple_speed_ethernet'
> + * The macros are prefixed with 'TSE_MAC_'.
> + * The prefix is the slave descriptor.
> + */
> +#define TSE_MAC_BASE 0x8004000
> +#define TSE_MAC_SPAN 1024u
> +#define TSE_MAC_TRANSMIT "sgdma_tx"
> +#define TSE_MAC_RECEIVE "sgdma_rx"

Is it use anywhere?

> +#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
> +#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
> +
> +/*
> + * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
> + * The macros are prefixed with 'SGDMA_RX_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SGDMA_RX_BASE 0x8004400
> +#define SGDMA_RX_SPAN 1024u
> +#define SGDMA_RX_IRQ 2

Do you use network driver with IRQ or polled mode?

> +
> +/*
> + * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
> + * The macros are prefixed with 'SGDMA_TX_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SGDMA_TX_BASE 0x8004800
> +#define SGDMA_TX_SPAN 1024u
> +#define SGDMA_TX_IRQ 3
> +
> +/*
> + * Macros for device 'uart', class 'altera_avalon_uart'
> + * The macros are prefixed with 'UART_'.
> + * The prefix is the slave descriptor.
> + */
> +#define UART_BASE 0x8004c80
> +#define UART_SPAN 32u
> +#define UART_IRQ 10

The same here. Do you use uart driver with IRQ support?

> +#define UART_BAUD 115200
> +#define UART_FREQ 62500000u
> +
> +/*
> + * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
> + * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
> + * The prefix is the slave descriptor.
> + */
> +#define USER_LED_PIO_8OUT_BASE 0x8004cc0
> +#define USER_LED_PIO_8OUT_SPAN 16u

IMHO unified name - what about name for 16 outputs?


> +
> +/*
> + * Macros for device 'sysid', class 'altera_avalon_sysid'
> + * The macros are prefixed with 'SYSID_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SYSID_BASE 0x8004d40
> +#define SYSID_SPAN 8u
> +#define SYSID_ID 1174346794u
> +#define SYSID_TIMESTAMP 1233287581u
> +
> +/*
> + * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
> + * The macros are prefixed with 'JTAG_UART_'.
> + * The prefix is the slave descriptor.
> + */
> +#define JTAG_UART_BASE 0x8004d50
> +#define JTAG_UART_SPAN 8u
> +#define JTAG_UART_IRQ 1
> +
> +/*
> + * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
> + * The macros are prefixed with 'LINUX_TIMER_1MS_'.
> + * The prefix is the slave descriptor.
> + */
> +#define LINUX_TIMER_1MS_BASE 0x8400000
> +#define LINUX_TIMER_1MS_SPAN 32u
> +#define LINUX_TIMER_1MS_IRQ 11
> +#define LINUX_TIMER_1MS_FREQ 125000000u

Unified name TIMER_BASE will be nice. I think that the name of timer is 
LINUX_TIMER_1MS and the tool generate this nice name. If someone change 
that name then have to change U-BOOT config file too.

> +
> +/*
> + * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
> + * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
> + * The prefix is the slave descriptor.
> + */
> +#define DDR2_LO_LATENCY_128M_BASE 0x10000000
> +#define DDR2_LO_LATENCY_128M_SPAN 134217728

MEMORY_BASE?

> +
> +
> +#endif /* _ALTERA_LINUX_CPU_H_ */
> diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
> new file mode 100644
> index 0000000..83f9e09
> --- /dev/null
> +++ b/include/configs/EP3C120.h
> @@ -0,0 +1,376 @@
> +/*
> + * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
> + * Scott McNutt <smcnutt@psyent.com>
> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * BOARD/CPU
> + */
> +#include "../board/altera/nios2-generic/default_mmu.h"
> +#define CONFIG_BOARD_NAME "EP3C120"
> +#define CONFIG_EP3C120

Is it use anywhere?

> +
> +#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
> +#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
> +#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
> +#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
> +#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
> +
> +#ifndef KERNEL_REGION_BASE
> +# define KERNEL_REGION_BASE		0		/* NOMMU */
> +#endif
> +
> +#ifndef IO_REGION_BASE
> +# define IO_REGION_BASE		0x80000000	/* NOMMU */
> +#endif

What does it mean? Do you use MMU for U-BOOT or not?
I am not sure about all CPU but I think that most of them not using MMU.

> +
> +/*
> + * CACHE -- the following will support II/s and II/f. The II/s does not
> + * have dcache, so the cache instructions will behave as NOPs.
> + */
> +#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
> +#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
> +#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
> +#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
> +
> +/*
> + * MEMORY BASE ADDRESSES
> + */
> +#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
> +#define CONFIG_SYS_SDRAM_SIZE		(DDR2_LO_LATENCY_128M_SPAN)
> +
> +/*
> + * GPIO
> + */
> +#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
> +#ifdef CONFIG_SYS_GPIO_BASE
> +# define CONFIG_SYS_GPIO_NRB 2
> +# define CONFIG_SYS_GPIO_HBT 3
> +#endif
> +
> +/*
> + * Flash Settings
> + */
> +/* #define CONFIG_SYS_NO_FLASH */
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_FLASH_CFI_MTD
> +
> +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
> +#define CONFIG_SYS_FLASH_BASE		(CFI_FLASH_64M_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_PROTECTION
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1
> +#define CONFIG_SYS_MAX_FLASH_SECT	512
> +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> +
> +/*
> + * SPI FLash,EPCS Settings
> + */
> +/* #define CONFIG_CMD_SPI */
> +/* #define CONFIG_CMD_SF */
> +/* #define CONFIG_SPI_FLASH */
> +/* #define CONFIG_ALTERA_SPI */
> +
> +#define CONFIG_ENV_SPI_MAX_HZ		30000000
> +#define CONFIG_SF_DEFAULT_SPEED	30000000
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
> +					  EPCS_CONTROLLER_REGISTER_OFFSET) \
> +					 | IO_REGION_BASE)
> +
> +/*
> + * NAND Flash
> + */
> +/* #define CONFIG_CMD_NAND */
> +/* #define CONFIG_NAND_PLAT */
> +
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
> +#define NIOS2_NAND_PLAT_CLE		2
> +#define NIOS2_NAND_PLAT_ALE		3
> +#define NAND_PLAT_WRITE_CMD(chip, cmd) \
> +	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
> +	       (1 << NIOS2_NAND_PLAT_CLE))
> +#define NAND_PLAT_WRITE_ADR(chip, cmd) \
> +	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
> +	       (1 << NIOS2_NAND_PLAT_ALE))
> +#define NAND_PLAT_INIT() {}
> +#ifdef CONFIG_SYS_GPIO_NRB
> +# define NAND_PLAT_DEV_READY(chip) \
> +	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
> +#endif
> +
> +/*
> + * SERIAL
> + */
> +/* #define CONFIG_ALTERA_UART */
> +#define CONFIG_ALTERA_JTAG_UART
> +
> +#if defined(CONFIG_ALTERA_JTAG_UART)
> +#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
> +#else
> +#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
> +#endif
> +
> +#define CONFIG_ALTERA_JTAG_UART_BYPASS
> +#define CONFIG_SYS_UART_FREQ		UART_FREQ
> +#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
> +#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
> +
> +/*
> + * SYSID
> + */
> +#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
> +
> +/*
> + * TIMER
> + */
> +#define CONFIG_SYS_NIOS_TMRBASE	(LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_NIOS_TMRIRQ		LINUX_TIMER_1MS_IRQ
> +#define CONFIG_SYS_HZ			1000	/* Always 1000 */
> +#define CONFIG_SYS_NIOS_TMRMS		1	/* Desired period (msec)*/
> +#define CONFIG_SYS_NIOS_TMRCNT \
> +	(CONFIG_SYS_NIOS_TMRMS * (LINUX_TIMER_1MS_FREQ / 1000) - 1)
> +
> +/*
> + * STATUS LED
> + */
> +#define CONFIG_STATUS_LED		/* Enable status driver */
> +#define CONFIG_EPLED			/* Enable LED PIO driver */
> +#define CONFIG_SYS_LEDPIO_ADDR		(USER_LED_PIO_8OUT_BASE | \
> +					 IO_REGION_BASE)
> +/* #define CONFIG_GPIOLED */
> +
> +#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
> +#define STATUS_LED_STATE		1	/* Blinking */
> +#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
> +
> +/*
> + * IDE support
> + */
> +/* #define CONFIG_CMD_IDE */
> +
> +#define CONFIG_SYS_PIO_MODE		1
> +#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
> +#define CONFIG_SYS_IDE_MAXDEVICE	1
> +#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
> +#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
> +#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
> +#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
> +#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
> +#define CONFIG_IDE_RESET
> +
> +/*
> + * ETHERNET
> + */
> +/* #define CONFIG_SMC91111 */
> +#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
> +				 | IO_REGION_BASE) /* Base addr	*/
> +#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
> +#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
> +
> +/* #define CONFIG_DRIVER_DM9000 */
> +#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
> +#define DM9000_IO			CONFIG_DM9000_BASE
> +#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
> +#define CONFIG_DM9000_USE_16BIT	1
> +#define CONFIG_DM9000_NO_SROM		1
> +/* #define CONFIG_NET_RETRY_COUNT		20 */
> +/* #define CONFIG_RESET_PHY_R		1 */
> +
> +/* #define CONFIG_ALTERA_TSE */
> +/* #define CONFIG_MII		1 */
> +/* #define CONFIG_CMD_MII */
> +/* #define CONFIG_ETHPRIME "tse0" */
> +#undef  CONFIG_PCI
> +
> +#define CONFIG_SYS_NUM_TSE_MACS			1
> +#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
> +#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
> +#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
> +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
> +						 IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
> +#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
> +#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
 > +#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18

This is nice example. Why don't move these values to default_mmu.h and
directly fill that values?

For example:
/* TSE: <IP name> */
#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	0xXXXXXXX
#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	2048
#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	2048

Look more straight forward and none have to look for it.

I briefly look at the rest. There are the same thing as above.

Regards,
Michal


> +
> +/* TSE Supported modes */
> +/* GMII/MII	= 0 */
> +/* RGMII	= 1 */
> +/* RGMII_ID	= 2 */
> +/* RGMII_TXID	= 3 */
> +/* RGMII_RXID	= 4 */
> +/* SGMII	= 5 */
> +#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
> +
> +/* #define CONFIG_ETHOC */
> +#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
> +
> +#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
> +#define CONFIG_NETMASK		255.255.255.0
> +#define CONFIG_IPADDR		192.168.1.10
> +#define CONFIG_GWADDR		192.168.1.1
> +#define CONFIG_SERVERIP	192.168.1.1
> +#define CONFIG_BOOTDELAY	5
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BOOTD
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_ITEST
> +#undef CONFIG_CMD_NFS
> +#undef CONFIG_CMD_SETGETDCR
> +#undef CONFIG_CMD_XIMG
> +
> +#ifdef CONFIG_CMD_NET
> +# define CONFIG_NET_MULTI
> +# define CONFIG_CMD_DHCP
> +# define CONFIG_CMD_PING
> +#endif
> +
> +#define CONFIG_CMD_SAVES
> +#define CONFIG_CMD_JFFS2
> +#define CONFIG_JFFS2_CMDLINE
> +/* #define CONFIG_CMD_FAT */
> +/* #define CONFIG_DOS_PARTITION */
> +/* #define CONFIG_CMD_UBI */
> +/* #define CONFIG_CMD_UBIFS */
> +/* #define CONFIG_RBTREE */
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_CMD_MTDPARTS
> +/* #define CONFIG_LZO */
> +
> +/*
> + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
> + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
> + * reset address, no? This will keep the environment in user region
> + * of flash. NOTE: the monitor length must be multiple of sector size
> + * (which is common practice).
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
> +/* #define CONFIG_ENV_IS_IN_NAND */
> +
> +#if defined(CONFIG_ENV_IS_IN_FLASH)
> +# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
> +# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
> +# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
> +					  CONFIG_SYS_MONITOR_LEN) | \
> +					 IO_REGION_BASE)
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
> +# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
> +# define CONFIG_ENV_SECT_SIZE		0x20000
> +# define CONFIG_ENV_SPI_BUS		0
> +# define CONFIG_ENV_SPI_CS		0
> +# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
> +#elif defined(CONFIG_ENV_IS_IN_NAND)
> +# define CONFIG_ENV_OFFSET		0x40000
> +# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
> +#else
> +# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
> +# define CONFIG_ENV_SIZE		0x20000
> +#endif
> +
> +/*
> + * MEMORY ORGANIZATION
> + *	-Monitor at top of sdram.
> + *	-The heap is placed below the monitor
> + *	-Global data is placed below the heap.
> + *	-The stack is placed below global data (&grows down).
> + */
> +#define CONFIG_MONITOR_IS_IN_RAM
> +#ifdef CONFIG_CMD_UBI
> +# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
> +#else
> +# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
> +#endif
> +#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
> +					 CONFIG_SYS_SDRAM_SIZE - \
> +					 CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
> +#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
> +# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
> +#else
> +# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
> +#endif
> +#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
> +					 CONFIG_SYS_MALLOC_LEN)
> +#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
> +					 CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
> +
> +/*
> + * MISC
> + */
> +#define CONFIG_SYS_LONGHELP		/* Provide extended help */
> +#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
> +#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + \
> +					 16)	/* Print buf size */
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
> +
> +#if defined(CONFIG_NAND_PLAT)
> +# define MTD_ENV_SETTINGS \
> +	"mtdids=nand0=nand0\0"						\
> +	"mtdparts=mtdparts=nand0:-(data)\0"
> +#elif defined(CONFIG_FLASH_CFI_DRIVER)
> +# define MTD_ENV_SETTINGS \
> +	"mtdids=nor0=physmap-flash.0\0"				\
> +	"mtdparts=mtdparts=physmap-flash.0:40m(JFFS),1M(U-Boot),4m(uImage1)," \
> +	"4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
> +	"3584k(USER_IMAGE),512k(options-bits)\0"
> +#else
> +# define MTD_ENV_SETTINGS
> +#endif
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	MTD_ENV_SETTINGS
> +
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER
> +#ifdef CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +#endif /* __CONFIG_H */


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 2/5 v2] nios2: add Altera EP2C35 board
  2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
  2010-04-01 12:26     ` Thomas Chou
@ 2010-04-05  5:48     ` Ben Warren
  1 sibling, 0 replies; 24+ messages in thread
From: Ben Warren @ 2010-04-05  5:48 UTC (permalink / raw)
  To: u-boot

Hi Thomas,

On 3/30/2010 9:03 PM, Thomas Chou wrote:
> This patch supports the Altera CycloneII Nios dev board using
> the example FPGA design at http://nioswiki.com/Linux.
>
> Signed-off-by: Thomas Chou<thomas@wytron.com.tw>
> ---
> +/* #define CONFIG_ETHOC */
> +#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
> +
> +#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
> +#define CONFIG_NETMASK		255.255.255.0
> +#define CONFIG_IPADDR		192.168.1.10
> +#define CONFIG_SERVERIP	192.168.1.254
> +
>    
Please remove these definitions.

regards,
Ben

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board
  2010-03-31  4:03   ` [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board Thomas Chou
  2010-04-01 12:26     ` Thomas Chou
@ 2010-04-05  5:50     ` Ben Warren
  1 sibling, 0 replies; 24+ messages in thread
From: Ben Warren @ 2010-04-05  5:50 UTC (permalink / raw)
  To: u-boot

Hi Thomas,

On 3/30/2010 9:03 PM, Thomas Chou wrote:
> This patch supports the Altera Nios2 Embedded Evaluation Kit using
> the example FPGA design at http://nioswiki.com/Linux.
>
> Signed-off-by: Thomas Chou<thomas@wytron.com.tw>
> ---
> +#define CONFIG_ETHOC
> +#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
> +
> +#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
> +#define CONFIG_NETMASK		255.255.255.0
> +#define CONFIG_IPADDR		192.168.1.10
> +#define CONFIG_SERVERIP	192.168.1.254
> +
>    
Please remove these definitions

regards,
Ben

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 3/5 v3] nios2: add Altera EP3C120 board
  2010-04-02  1:33     ` [U-Boot] [PATCH 3/5 v3] " Thomas Chou
  2010-04-02  6:57       ` Michal Simek
@ 2010-04-15 14:40       ` Thomas Chou
  1 sibling, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-15 14:40 UTC (permalink / raw)
  To: u-boot

On 04/02/2010 09:33 AM, Thomas Chou wrote:
> This patch supports the Altera CycloneIII Nios dev board using
> the example FPGA design at http://nioswiki.com/Linux.
>
> This board servers as a configuration template for nios2-generic
> approach. Since each fpga board can have different designs, we
> will refer them as designs rather than boards. All designs can
> share the same nios2-generic board directory.
>
> To support a new design,
> 1. add a configuration file based on EP3C120.h.
> 2. include the fpga header file
> 3. add an entry to the NIOS2_GENERIC list in the top Makefile
>
> Signed-off-by: Thomas Chou<thomas@wytron.com.tw>
> ---
>    
Please drop this patch. A nios2-generic board is fold into patch 1/5.

- Thomas

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH v2] nios2: add nios2-generic board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
                   ` (3 preceding siblings ...)
  2010-03-31  0:50 ` [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c Thomas Chou
@ 2010-04-15 14:55 ` Thomas Chou
  2010-04-16 10:40   ` Michal Simek
  2010-04-17  9:53 ` [U-Boot] [PATCH 1/5 v3] " Thomas Chou
  2010-04-21  0:40 ` [U-Boot] [PATCH 1/5 v4] " Thomas Chou
  6 siblings, 1 reply; 24+ messages in thread
From: Thomas Chou @ 2010-04-15 14:55 UTC (permalink / raw)
  To: u-boot

This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot

A fpga parameter file, which contains base address information
and drivers declaration, is generated from Altera's hardware system
description sopc file using tools.

The example fpga parameter file is compatible with EP1C20, EP1S10
and EP1S40 boards. So these boards can be removed after this commit.
Though epcs controller is not included to cut the dependency of 
altera_spi driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
fix board_eth_init() return.
add nios2-generic board template.

The fpga parameter file is generated with a script at
 http://sopc.et.ntust.edu.tw/?p=toolchain-build.git;
a=blob_plain;f=tools/sopc-create-config-files;hb=HEAD

 MAINTAINERS                                |    1 +
 MAKEALL                                    |    1 +
 Makefile                                   |    6 +
 board/altera/nios2-generic/Makefile        |   60 +++++++++++
 board/altera/nios2-generic/config.mk       |   32 ++++++
 board/altera/nios2-generic/custom_fpga.h   |   66 ++++++++++++
 board/altera/nios2-generic/nios2-generic.c |   68 ++++++++++++
 board/altera/nios2-generic/text_base.S     |   21 ++++
 board/altera/nios2-generic/u-boot.lds      |  136 ++++++++++++++++++++++++
 include/configs/nios2-generic.h            |  153 ++++++++++++++++++++++++++++
 10 files changed, 544 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/Makefile
 create mode 100644 board/altera/nios2-generic/config.mk
 create mode 100644 board/altera/nios2-generic/custom_fpga.h
 create mode 100644 board/altera/nios2-generic/nios2-generic.c
 create mode 100644 board/altera/nios2-generic/text_base.S
 create mode 100644 board/altera/nios2-generic/u-boot.lds
 create mode 100644 include/configs/nios2-generic.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 04c8730..46e051b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -858,6 +858,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index fb1f7a3..216b89b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 5d314c6..752f529 100644
--- a/Makefile
+++ b/Makefile
@@ -3538,6 +3538,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = nios2-generic
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..2a6f69b
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..cb7c68e
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..761f605
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..89848cf
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+	rc += altera_tse_initialize(0,
+				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..fa7ed30
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
new file mode 100644
index 0000000..e83e1e3
--- /dev/null
+++ b/include/configs/nios2-generic.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		LED_PIO_BASE
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH v2] nios2: add nios2-generic board
  2010-04-15 14:55 ` [U-Boot] [PATCH v2] nios2: add nios2-generic board Thomas Chou
@ 2010-04-16 10:40   ` Michal Simek
  0 siblings, 0 replies; 24+ messages in thread
From: Michal Simek @ 2010-04-16 10:40 UTC (permalink / raw)
  To: u-boot

Thomas Chou wrote:
> This is a generic approach to port u-boot for nios2 boards.
> You may find the usage of this approach on the nioswiki,
> http://nioswiki.com/DasUBoot
> 
> A fpga parameter file, which contains base address information
> and drivers declaration, is generated from Altera's hardware system
> description sopc file using tools.

It is much nicer than previous solution. I like it.

> The example fpga parameter file is compatible with EP1C20, EP1S10
> and EP1S40 boards. So these boards can be removed after this commit.
> Though epcs controller is not included to cut the dependency of 
> altera_spi driver.

If is possible to remove it that will be good to create patches and 
clean the code.

> 
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

Acked-by: Michal Simek <monstr@monstr.eu>

Thanks,
Michal


> ---
> fix board_eth_init() return.
> add nios2-generic board template.
> 
> The fpga parameter file is generated with a script at
>  http://sopc.et.ntust.edu.tw/?p=toolchain-build.git;
> a=blob_plain;f=tools/sopc-create-config-files;hb=HEAD
> 
>  MAINTAINERS                                |    1 +
>  MAKEALL                                    |    1 +
>  Makefile                                   |    6 +
>  board/altera/nios2-generic/Makefile        |   60 +++++++++++
>  board/altera/nios2-generic/config.mk       |   32 ++++++
>  board/altera/nios2-generic/custom_fpga.h   |   66 ++++++++++++
>  board/altera/nios2-generic/nios2-generic.c |   68 ++++++++++++
>  board/altera/nios2-generic/text_base.S     |   21 ++++
>  board/altera/nios2-generic/u-boot.lds      |  136 ++++++++++++++++++++++++
>  include/configs/nios2-generic.h            |  153 ++++++++++++++++++++++++++++
>  10 files changed, 544 insertions(+), 0 deletions(-)
>  create mode 100644 board/altera/nios2-generic/Makefile
>  create mode 100644 board/altera/nios2-generic/config.mk
>  create mode 100644 board/altera/nios2-generic/custom_fpga.h
>  create mode 100644 board/altera/nios2-generic/nios2-generic.c
>  create mode 100644 board/altera/nios2-generic/text_base.S
>  create mode 100644 board/altera/nios2-generic/u-boot.lds
>  create mode 100644 include/configs/nios2-generic.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 04c8730..46e051b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -858,6 +858,7 @@ Scott McNutt <smcnutt@psyent.com>
>  	EP1C20		Nios-II
>  	EP1S10		Nios-II
>  	EP1S40		Nios-II
> +	nios2-generic	Nios-II
>  
>  #########################################################################
>  # MicroBlaze Systems:							#
> diff --git a/MAKEALL b/MAKEALL
> index fb1f7a3..216b89b 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -824,6 +824,7 @@ LIST_nios2="		\
>  	EP1S40		\
>  	PCI5441		\
>  	PK1C20		\
> +	nios2-generic	\
>  "
>  
>  #########################################################################
> diff --git a/Makefile b/Makefile
> index 5d314c6..752f529 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3538,6 +3538,12 @@ PK1C20_config : unconfig
>  PCI5441_config : unconfig
>  	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
>  
> +# nios2 generic boards
> +NIOS2_GENERIC = nios2-generic
> +
> +$(NIOS2_GENERIC:%=%_config) : unconfig
> +	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
> +
>  #========================================================================
>  ## Microblaze
>  #========================================================================
> diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
> new file mode 100644
> index 0000000..2a6f69b
> --- /dev/null
> +++ b/board/altera/nios2-generic/Makefile
> @@ -0,0 +1,60 @@
> +#
> +# (C) Copyright 2001-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +ifneq ($(OBJTREE),$(SRCTREE))
> +$(shell mkdir -p $(obj)../common)
> +endif
> +
> +LIB	= $(obj)lib$(BOARD).a
> +
> +COBJS-y	:= $(BOARD).o
> +COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
> +COBJS-$(CONFIG_EPLED) += ../common/epled.o
> +COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o
> +COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
> +
> +SOBJS-y	:= text_base.o
> +
> +SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS-y))
> +SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
> +
> +$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
> +	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> +	rm -f $(SOBJS) $(OBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
> new file mode 100644
> index 0000000..cb7c68e
> --- /dev/null
> +++ b/board/altera/nios2-generic/config.mk
> @@ -0,0 +1,32 @@
> +#
> +# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
> +# Scott McNutt <smcnutt@psyent.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +# we get text_base from board config header, so do not use this
> +#TEXT_BASE = do-not-use-me
> +
> +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
> +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
> +
> +ifeq ($(debug),1)
> +PLATFORM_CPPFLAGS += -DDEBUG
> +endif
> diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
> new file mode 100644
> index 0000000..761f605
> --- /dev/null
> +++ b/board/altera/nios2-generic/custom_fpga.h
> @@ -0,0 +1,66 @@
> +/*
> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This file is generated by sopc-create-config-files.
> + */
> +#ifndef _CUSTOM_FPGA_H_
> +#define _CUSTOM_FPGA_H_
> +
> +/* generated from std_1c20.sopc */
> +
> +/* cpu.data_master is a altera_nios2 */
> +#define CONFIG_SYS_CLK_FREQ 50000000
> +#define CONFIG_SYS_RESET_ADDR 0x00000000
> +#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
> +#define CONFIG_SYS_ICACHE_SIZE 4096
> +#define CONFIG_SYS_ICACHELINE_SIZE 32
> +#define CONFIG_SYS_DCACHE_SIZE 2048
> +#define CONFIG_SYS_DCACHELINE_SIZE 4
> +
> +/* sdram.s1 is a altera_avalon_new_sdram_controller */
> +#define CONFIG_SYS_SDRAM_BASE 0x01000000
> +#define CONFIG_SYS_SDRAM_SIZE 0x01000000
> +
> +/* uart1.s1 is a altera_avalon_uart */
> +#define CONFIG_SYS_UART_BASE 0x82120840
> +#define CONFIG_SYS_UART_FREQ 50000000
> +#define CONFIG_SYS_UART_BAUD 115200
> +
> +/* lan91c111.s1 is a altera_avalon_lan91c111 */
> +#define CONFIG_SMC91111_BASE 0x82110300
> +#define CONFIG_SMC91111
> +#define CONFIG_SMC_USE_32_BIT
> +
> +/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
> +#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
> +
> +/* led_pio.s1 is a altera_avalon_pio */
> +#define LED_PIO_BASE 0x82120870
> +
> +/* high_res_timer.s1 is a altera_avalon_timer */
> +#define CONFIG_SYS_TIMER_BASE 0x82120820
> +#define CONFIG_SYS_TIMER_IRQ 3
> +#define CONFIG_SYS_TIMER_FREQ 50000000
> +
> +/* ext_flash.s1 is a altera_avalon_cfi_flash */
> +#define CONFIG_SYS_FLASH_BASE 0x80000000
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> +#define CONFIG_SYS_FLASH_PROTECTION
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +#define CONFIG_SYS_MAX_FLASH_SECT 1024
> +
> +/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
> +#define CONFIG_SYS_SRAM_BASE 0x02000000
> +#define CONFIG_SYS_SRAM_SIZE 0x00100000
> +
> +/* sysid.control_slave is a altera_avalon_sysid */
> +#define CONFIG_SYS_SYSID_BASE 0x821208b8
> +
> +#endif /* _CUSTOM_FPGA_H_ */
> diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
> new file mode 100644
> index 0000000..89848cf
> --- /dev/null
> +++ b/board/altera/nios2-generic/nios2-generic.c
> @@ -0,0 +1,68 @@
> +/*
> + * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
> + * Scott McNutt <smcnutt@psyent.com>
> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +
> +void text_base_hook(void); /* nop hook for text_base.S */
> +
> +int board_early_init_f(void)
> +{
> +	text_base_hook();
> +	return 0;
> +}
> +
> +int checkboard(void)
> +{
> +	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
> +	return 0;
> +}
> +
> +phys_size_t initdram(int board_type)
> +{
> +	return 0;
> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int board_eth_init(bd_t *bis)
> +{
> +	int rc = 0;
> +#ifdef CONFIG_SMC91111
> +	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
> +#endif
> +#ifdef CONFIG_DRIVER_DM9000
> +	rc += dm9000_initialize(bis);
> +#endif
> +#ifdef CONFIG_ALTERA_TSE
> +	rc += altera_tse_initialize(0,
> +				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
> +				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
> +				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
> +#endif
> +#ifdef CONFIG_ETHOC
> +	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
> +#endif
> +	return rc;
> +}
> +#endif
> diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
> new file mode 100644
> index 0000000..f236db1
> --- /dev/null
> +++ b/board/altera/nios2-generic/text_base.S
> @@ -0,0 +1,21 @@
> +/*
> + * text_base
> + *
> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <config.h>
> +
> +#ifdef CONFIG_SYS_MONITOR_BASE
> +	.text
> +	/* text base used in link script u-boot.lds */
> +	.global text_base
> +	.equ text_base,CONFIG_SYS_MONITOR_BASE
> +	/* dummy func to let linker include this file */
> +	.global text_base_hook
> +text_base_hook:
> +	ret
> +#endif
> diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
> new file mode 100644
> index 0000000..fa7ed30
> --- /dev/null
> +++ b/board/altera/nios2-generic/u-boot.lds
> @@ -0,0 +1,136 @@
> +/*
> + * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
> + * Scott McNutt <smcnutt@psyent.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +
> +OUTPUT_FORMAT("elf32-littlenios2")
> +OUTPUT_ARCH(nios2)
> +ENTRY(_start)
> +
> +SECTIONS
> +{
> +	. = text_base;
> +	.text :
> +	{
> +	  cpu/nios2/start.o (.text)
> +	  *(.text)
> +	  *(.text.*)
> +	  *(.gnu.linkonce.t*)
> +	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
> +	  *(.gnu.linkonce.r*)
> +	}
> +	. = ALIGN (4);
> +	_etext = .;
> +	PROVIDE (etext = .);
> +
> +	/* CMD TABLE - sandwich this in between text and data so
> +	 * the initialization code relocates the command table as
> +	 * well -- admittedly, this is just pure laziness ;-)
> +	 */
> +	__u_boot_cmd_start = .;
> +	.u_boot_cmd :
> +	{
> +	  *(.u_boot_cmd)
> +	}
> +	. = ALIGN(4);
> +	__u_boot_cmd_end = .;
> +
> +	/* INIT DATA sections - "Small" data (see the gcc -G option)
> +	 * is always gp-relative. Here we make all init data sections
> +	 * adjacent to simplify the startup code -- and provide
> +	 * the global pointer for gp-relative access.
> +	 */
> +	_data = .;
> +	.data :
> +	{
> +	  *(.data)
> +	  *(.data.*)
> +	  *(.gnu.linkonce.d*)
> +	}
> +
> +	. = ALIGN(16);
> +	_gp = .;			/* Global pointer addr */
> +	PROVIDE (gp = .);
> +
> +	.sdata :
> +	{
> +	  *(.sdata)
> +	  *(.sdata.*)
> +	  *(.gnu.linkonce.s.*)
> +	}
> +	. = ALIGN(4);
> +
> +	_edata = .;
> +	PROVIDE (edata = .);
> +
> +	/* UNINIT DATA - Small uninitialized data is first so it's
> +	 * adjacent to sdata and can be referenced via gp. The normal
> +	 * bss follows. We keep it adjacent to simplify init code.
> +	 */
> +	__bss_start = .;
> +	.sbss (NOLOAD) :
> +	{
> +	  *(.sbss)
> +	  *(.sbss.*)
> +	  *(.gnu.linkonce.sb.*)
> +	  *(.scommon)
> +	}
> +	. = ALIGN(4);
> +	.bss (NOLOAD) :
> +	{
> +	  *(.bss)
> +	  *(.bss.*)
> +	  *(.dynbss)
> +	  *(COMMON)
> +	  *(.scommon)
> +	}
> +	. = ALIGN(4);
> +	_end = .;
> +	PROVIDE (end = .);
> +
> +	/* DEBUG -- symbol table, string table, etc. etc.
> +	 */
> +	.stab 0 : { *(.stab) }
> +	.stabstr 0 : { *(.stabstr) }
> +	.stab.excl 0 : { *(.stab.excl) }
> +	.stab.exclstr 0 : { *(.stab.exclstr) }
> +	.stab.index 0 : { *(.stab.index) }
> +	.stab.indexstr 0 : { *(.stab.indexstr) }
> +	.comment 0 : { *(.comment) }
> +	.debug		0 : { *(.debug) }
> +	.line		0 : { *(.line) }
> +	.debug_srcinfo	0 : { *(.debug_srcinfo) }
> +	.debug_sfnames	0 : { *(.debug_sfnames) }
> +	.debug_aranges	0 : { *(.debug_aranges) }
> +	.debug_pubnames 0 : { *(.debug_pubnames) }
> +	.debug_info	0 : { *(.debug_info) }
> +	.debug_abbrev	0 : { *(.debug_abbrev) }
> +	.debug_line	0 : { *(.debug_line) }
> +	.debug_frame	0 : { *(.debug_frame) }
> +	.debug_str	0 : { *(.debug_str) }
> +	.debug_loc	0 : { *(.debug_loc) }
> +	.debug_macinfo	0 : { *(.debug_macinfo) }
> +	.debug_weaknames 0 : { *(.debug_weaknames) }
> +	.debug_funcnames 0 : { *(.debug_funcnames) }
> +	.debug_typenames 0 : { *(.debug_typenames) }
> +	.debug_varnames	 0 : { *(.debug_varnames) }
> +}
> diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
> new file mode 100644
> index 0000000..e83e1e3
> --- /dev/null
> +++ b/include/configs/nios2-generic.h
> @@ -0,0 +1,153 @@
> +/*
> + * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
> + * Scott McNutt <smcnutt@psyent.com>
> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * BOARD/CPU
> + */
> +#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
> +#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
> +#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
> +#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
> +
> +/*
> + * SERIAL
> + */
> +#define CONFIG_ALTERA_UART
> +#if defined(CONFIG_ALTERA_JTAG_UART)
> +# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
> +#else
> +# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
> +#endif
> +
> +#define CONFIG_ALTERA_JTAG_UART_BYPASS
> +#define CONFIG_SYS_NIOS_FIXEDBAUD
> +#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
> +#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
> +
> +/*
> + * TIMER
> + */
> +#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
> +#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
> +#define CONFIG_SYS_HZ			1000	/* Always 1000 */
> +#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
> +#define CONFIG_SYS_NIOS_TMRCNT \
> +	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
> +
> +/*
> + * STATUS LED
> + */
> +#define CONFIG_STATUS_LED		/* Enable status driver */
> +#define CONFIG_EPLED			/* Enable LED PIO driver */
> +#define CONFIG_SYS_LEDPIO_ADDR		LED_PIO_BASE
> +
> +#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
> +#define STATUS_LED_STATE		1	/* Blinking */
> +#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BOOTD
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_ITEST
> +#undef CONFIG_CMD_NFS
> +#undef CONFIG_CMD_SETGETDCR
> +#undef CONFIG_CMD_XIMG
> +
> +#ifdef CONFIG_CMD_NET
> +# define CONFIG_NET_MULTI
> +# define CONFIG_CMD_DHCP
> +# define CONFIG_CMD_PING
> +#endif
> +
> +/*
> + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
> + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
> + * reset address, no? This will keep the environment in user region
> + * of flash. NOTE: the monitor length must be multiple of sector size
> + * (which is common practice).
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +
> +#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
> +#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
> +#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
> +					  CONFIG_SYS_MONITOR_LEN) | \
> +					 CONFIG_SYS_FLASH_BASE)
> +
> +/*
> + * MEMORY ORGANIZATION
> + *	-Monitor at top of sdram.
> + *	-The heap is placed below the monitor
> + *	-Global data is placed below the heap.
> + *	-The stack is placed below global data (&grows down).
> + */
> +#define CONFIG_MONITOR_IS_IN_RAM
> +#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
> +#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
> +					 CONFIG_SYS_SDRAM_SIZE - \
> +					 CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
> +#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
> +					 CONFIG_SYS_MALLOC_LEN)
> +#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
> +					 CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
> +
> +/*
> + * MISC
> + */
> +#define CONFIG_SYS_LONGHELP		/* Provide extended help */
> +#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
> +#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + \
> +					 16)	/* Print buf size */
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
> +#define CONFIG_CMDLINE_EDITING
> +
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +
> +#endif /* __CONFIG_H */


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian

^ permalink raw reply	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 1/5 v3] nios2: add nios2-generic board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
                   ` (4 preceding siblings ...)
  2010-04-15 14:55 ` [U-Boot] [PATCH v2] nios2: add nios2-generic board Thomas Chou
@ 2010-04-17  9:53 ` Thomas Chou
  2010-04-21  0:40 ` [U-Boot] [PATCH 1/5 v4] " Thomas Chou
  6 siblings, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-17  9:53 UTC (permalink / raw)
  To: u-boot

This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot

A fpga parameter file, which contains base address information
and drivers declaration, is generated from Altera's hardware system
description sopc file using tools.

The example fpga parameter file is compatible with EP1C20, EP1S10
and EP1S40 boards. So these boards can be removed after this commit.
Though epcs controller is removed to cut the dependency of altera_spi
driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
change link script location.

 MAINTAINERS                                |    1 +
 MAKEALL                                    |    1 +
 Makefile                                   |    6 +
 board/altera/nios2-generic/Makefile        |   60 +++++++++++
 board/altera/nios2-generic/config.mk       |   34 ++++++
 board/altera/nios2-generic/custom_fpga.h   |   66 ++++++++++++
 board/altera/nios2-generic/nios2-generic.c |   68 ++++++++++++
 board/altera/nios2-generic/text_base.S     |   21 ++++
 board/altera/nios2-generic/u-boot.lds      |  136 ++++++++++++++++++++++++
 include/configs/nios2-generic.h            |  153 ++++++++++++++++++++++++++++
 10 files changed, 546 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/Makefile
 create mode 100644 board/altera/nios2-generic/config.mk
 create mode 100644 board/altera/nios2-generic/custom_fpga.h
 create mode 100644 board/altera/nios2-generic/nios2-generic.c
 create mode 100644 board/altera/nios2-generic/text_base.S
 create mode 100644 board/altera/nios2-generic/u-boot.lds
 create mode 100644 include/configs/nios2-generic.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 04c8730..46e051b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -858,6 +858,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index fb1f7a3..216b89b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 0381c81..af6e1ee 100644
--- a/Makefile
+++ b/Makefile
@@ -3538,6 +3538,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = nios2-generic
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..2a6f69b
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..d500133
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..761f605
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..89848cf
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+	rc += altera_tse_initialize(0,
+				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..d4be077
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  arch/nios2/cpu/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
new file mode 100644
index 0000000..e83e1e3
--- /dev/null
+++ b/include/configs/nios2-generic.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		LED_PIO_BASE
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 5/5 v2] nios2: fix no flash, add nand and mmc init in board.c
  2010-03-31  0:50 ` [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c Thomas Chou
@ 2010-04-17 15:20   ` Thomas Chou
  2010-04-22  9:27   ` [U-Boot] [PATCH 5/5 v3] " Thomas Chou
  1 sibling, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-17 15:20 UTC (permalink / raw)
  To: u-boot

This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
arch dir reorganized.

 arch/nios2/lib/board.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index 8ec66a3..f17bb37 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -100,7 +100,9 @@ void board_init (void)
 	bd = gd->bd;
 	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
 #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
 	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
 	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
@@ -119,8 +121,20 @@ void board_init (void)
 	/* The Malloc area is immediately below the monitor copy in RAM */
 	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
+#ifndef CONFIG_SYS_NO_FLASH
 	WATCHDOG_RESET ();
 	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
 
 	WATCHDOG_RESET ();
 	env_relocate();
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 1/5 v4] nios2: add nios2-generic board
  2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
                   ` (5 preceding siblings ...)
  2010-04-17  9:53 ` [U-Boot] [PATCH 1/5 v3] " Thomas Chou
@ 2010-04-21  0:40 ` Thomas Chou
  6 siblings, 0 replies; 24+ messages in thread
From: Thomas Chou @ 2010-04-21  0:40 UTC (permalink / raw)
  To: u-boot

This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot

A fpga parameter file, which contains base address information
and drivers declaration, is generated from Altera's hardware system
description sopc file using tools.

The example fpga parameter file is compatible with EP1C20, EP1S10
and EP1S40 boards. So these boards can be removed after this commit.
Though epcs controller is removed to cut the dependency of altera_spi
driver.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
Remove gpio led from board Makefile.

 MAINTAINERS                                |    1 +
 MAKEALL                                    |    1 +
 Makefile                                   |    6 +
 board/altera/nios2-generic/Makefile        |   59 +++++++++++
 board/altera/nios2-generic/config.mk       |   34 ++++++
 board/altera/nios2-generic/custom_fpga.h   |   66 ++++++++++++
 board/altera/nios2-generic/nios2-generic.c |   68 ++++++++++++
 board/altera/nios2-generic/text_base.S     |   21 ++++
 board/altera/nios2-generic/u-boot.lds      |  136 ++++++++++++++++++++++++
 include/configs/nios2-generic.h            |  153 ++++++++++++++++++++++++++++
 10 files changed, 545 insertions(+), 0 deletions(-)
 create mode 100644 board/altera/nios2-generic/Makefile
 create mode 100644 board/altera/nios2-generic/config.mk
 create mode 100644 board/altera/nios2-generic/custom_fpga.h
 create mode 100644 board/altera/nios2-generic/nios2-generic.c
 create mode 100644 board/altera/nios2-generic/text_base.S
 create mode 100644 board/altera/nios2-generic/u-boot.lds
 create mode 100644 include/configs/nios2-generic.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 04c8730..46e051b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -858,6 +858,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index fb1f7a3..216b89b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 0381c81..af6e1ee 100644
--- a/Makefile
+++ b/Makefile
@@ -3538,6 +3538,12 @@ PK1C20_config : unconfig
 PCI5441_config : unconfig
 	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
 
+# nios2 generic boards
+NIOS2_GENERIC = nios2-generic
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
 #========================================================================
 ## Microblaze
 #========================================================================
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..6780872
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y	:= text_base.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..d500133
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..761f605
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..89848cf
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+	text_base_hook();
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+	rc += altera_tse_initialize(0,
+				    CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+				    CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+	return rc;
+}
+#endif
diff --git a/board/altera/nios2-generic/text_base.S b/board/altera/nios2-generic/text_base.S
new file mode 100644
index 0000000..f236db1
--- /dev/null
+++ b/board/altera/nios2-generic/text_base.S
@@ -0,0 +1,21 @@
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+	.text
+	/* text base used in link script u-boot.lds */
+	.global text_base
+	.equ text_base,CONFIG_SYS_MONITOR_BASE
+	/* dummy func to let linker include this file */
+	.global text_base_hook
+text_base_hook:
+	ret
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..d4be077
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = text_base;
+	.text :
+	{
+	  arch/nios2/cpu/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss (NOLOAD) :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss (NOLOAD) :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
new file mode 100644
index 0000000..e83e1e3
--- /dev/null
+++ b/include/configs/nios2-generic.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_EPLED			/* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR		LED_PIO_BASE
+
+#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ *	-Monitor at top of sdram.
+ *	-The heap is placed below the monitor
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif /* __CONFIG_H */
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 5/5 v3] nios2: fix no flash, add nand and mmc init in board.c
  2010-03-31  0:50 ` [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c Thomas Chou
  2010-04-17 15:20   ` [U-Boot] [PATCH 5/5 v2] " Thomas Chou
@ 2010-04-22  9:27   ` Thomas Chou
  2010-04-23  2:22     ` Scott McNutt
  1 sibling, 1 reply; 24+ messages in thread
From: Thomas Chou @ 2010-04-22  9:27 UTC (permalink / raw)
  To: u-boot

This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
nand flash and mmc initialization, which should go before
env initialization.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
---
v3 include mmc.h and nand.h.
v2 arch dir reorganized.

 arch/nios2/lib/board.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index 8ec66a3..f83e691 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -28,6 +28,7 @@
 #include <stdio_dev.h>
 #include <watchdog.h>
 #include <malloc.h>
+#include <mmc.h>
 #include <net.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -35,6 +36,9 @@
 #if defined(CONFIG_SYS_NIOS_EPCSBASE)
 #include <nios2-epcs.h>
 #endif
+#ifdef CONFIG_CMD_NAND
+#include <nand.h>	/* cannot even include nand.h if it isnt configured */
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -100,7 +104,9 @@ void board_init (void)
 	bd = gd->bd;
 	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
 	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
 #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
 	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
 	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
@@ -119,8 +125,20 @@ void board_init (void)
 	/* The Malloc area is immediately below the monitor copy in RAM */
 	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
+#ifndef CONFIG_SYS_NO_FLASH
 	WATCHDOG_RESET ();
 	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
 
 	WATCHDOG_RESET ();
 	env_relocate();
-- 
1.6.6.1

^ permalink raw reply related	[flat|nested] 24+ messages in thread

* [U-Boot] [PATCH 5/5 v3] nios2: fix no flash, add nand and mmc init in board.c
  2010-04-22  9:27   ` [U-Boot] [PATCH 5/5 v3] " Thomas Chou
@ 2010-04-23  2:22     ` Scott McNutt
  0 siblings, 0 replies; 24+ messages in thread
From: Scott McNutt @ 2010-04-23  2:22 UTC (permalink / raw)
  To: u-boot

Applied. Thanks.
--Scott

Thomas Chou wrote:
> This patch fixes error when CONFIG_SYS_NO_FLASH. And adds
> nand flash and mmc initialization, which should go before
> env initialization.
> 
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
> v3 include mmc.h and nand.h.
> v2 arch dir reorganized.
> 
>  arch/nios2/lib/board.c |   18 ++++++++++++++++++
>  1 files changed, 18 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
> index 8ec66a3..f83e691 100644
> --- a/arch/nios2/lib/board.c
> +++ b/arch/nios2/lib/board.c
> @@ -28,6 +28,7 @@
>  #include <stdio_dev.h>
>  #include <watchdog.h>
>  #include <malloc.h>
> +#include <mmc.h>
>  #include <net.h>
>  #ifdef CONFIG_STATUS_LED
>  #include <status_led.h>
> @@ -35,6 +36,9 @@
>  #if defined(CONFIG_SYS_NIOS_EPCSBASE)
>  #include <nios2-epcs.h>
>  #endif
> +#ifdef CONFIG_CMD_NAND
> +#include <nand.h>	/* cannot even include nand.h if it isnt configured */
> +#endif
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -100,7 +104,9 @@ void board_init (void)
>  	bd = gd->bd;
>  	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
>  	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
> +#ifndef CONFIG_SYS_NO_FLASH
>  	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
> +#endif
>  #if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
>  	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
>  	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
> @@ -119,8 +125,20 @@ void board_init (void)
>  	/* The Malloc area is immediately below the monitor copy in RAM */
>  	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
>  
> +#ifndef CONFIG_SYS_NO_FLASH
>  	WATCHDOG_RESET ();
>  	bd->bi_flashsize = flash_init();
> +#endif
> +
> +#ifdef CONFIG_CMD_NAND
> +	puts("NAND:  ");
> +	nand_init();
> +#endif
> +
> +#ifdef CONFIG_GENERIC_MMC
> +	puts("MMC:   ");
> +	mmc_initialize(bd);
> +#endif
>  
>  	WATCHDOG_RESET ();
>  	env_relocate();

^ permalink raw reply	[flat|nested] 24+ messages in thread

end of thread, other threads:[~2010-04-23  2:22 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-03-31  0:50 [U-Boot] [PATCH 1/5] nios2: add nios2-generic board Thomas Chou
2010-03-31  0:50 ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Thomas Chou
2010-03-31  4:03   ` [U-Boot] [PATCH 2/5 v2] " Thomas Chou
2010-04-01 12:26     ` Thomas Chou
2010-04-05  5:48     ` Ben Warren
2010-03-31  4:03   ` [U-Boot] [PATCH 3/5 v2] nios2: add Altera EP3C120 board Thomas Chou
2010-04-02  1:33     ` [U-Boot] [PATCH 3/5 v3] " Thomas Chou
2010-04-02  6:57       ` Michal Simek
2010-04-15 14:40       ` Thomas Chou
2010-03-31  4:03   ` [U-Boot] [PATCH 4/5 v2] nios2: add Altera NEEK board Thomas Chou
2010-04-01 12:26     ` Thomas Chou
2010-04-05  5:50     ` Ben Warren
2010-04-01  7:17   ` [U-Boot] [PATCH 2/5] nios2: add Altera EP2C35 board Michal Simek
2010-04-01 12:24     ` Thomas Chou
2010-03-31  0:50 ` [U-Boot] [PATCH 3/5] nios2: add Altera EP3C120 board Thomas Chou
2010-03-31  0:50 ` [U-Boot] [PATCH 4/5] nios2: add Altera NEEK board Thomas Chou
2010-03-31  0:50 ` [U-Boot] [PATCH 5/5] nios2: fix no flash, add nand and mmc init in board.c Thomas Chou
2010-04-17 15:20   ` [U-Boot] [PATCH 5/5 v2] " Thomas Chou
2010-04-22  9:27   ` [U-Boot] [PATCH 5/5 v3] " Thomas Chou
2010-04-23  2:22     ` Scott McNutt
2010-04-15 14:55 ` [U-Boot] [PATCH v2] nios2: add nios2-generic board Thomas Chou
2010-04-16 10:40   ` Michal Simek
2010-04-17  9:53 ` [U-Boot] [PATCH 1/5 v3] " Thomas Chou
2010-04-21  0:40 ` [U-Boot] [PATCH 1/5 v4] " Thomas Chou

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