Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[David Daney]

On 04/26/2010 06:25 PM, post@pfrst.de wrote:
>
>
> Hi David,
>
> please excuse me, i just couldn't resist to comment on this :-)
>
> Some time ago we needed to handle multiple (virtual) address-spaces
> (in TO_CAC/TO_UNCAC as well as in virt_to_phys and the like) for
> SGI's Indigo2/R10k and Octane (neither could run a 32bit kernel).
> So in addrspace.h we provided
> 	#ifdef CONFIG_64BIT
> 	static inline unsigned long kernel_physaddr(unsigned long kva)
> 	{
> 		if((kva&0xffffffff80000000UL)==0xffffffff80000000UL)
> 			return CPHYSADDR(kva);
> 		return XPHYSADDR(kva);
> 	}
> 	#else
> 	#define kernel_physaddr CPHYSADDR
> 	#endif
> while mach-ipXX/spaces.h defined
> 	#define TO_PHYS(x)	(             kernel_physaddr(x))
> 	#define TO_CAC(x)	(CAC_BASE   | kernel_physaddr(x))
> 	#define TO_UNCAC(x)	(UNCAC_BASE | kernel_physaddr(x))
> which did the job.
> But at that time these defines didn't meet much acceptance for general
> use in 64bit kernels.  Now, to my amusement, some modern processor
> (and/or system) seems to urge this kind of address-handling again  ;-)
>
>

FWIW, that seems cleaner than what I did (actually I didn't try my 
code).  That should be the default definition for 64-bit kernels I think.

David Daney

> Good luck!
>
>
>
> On Mon, 26 Apr 2010, David Daney wrote:
>
>> Date: Mon, 26 Apr 2010 10:19:04 -0700
>> From: David Daney<ddaney@caviumnetworks.com>
>> To: wuzhangjin@gmail.com
>> Cc: Ralf Baechle<ralf@linux-mips.org>,
>>       Thomas Bogendoerfer<tsbogend@alpha.franken.de>,
>>       linux-mips@linux-mips.org
>> Subject: Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels
>>
>> ...
>> I don't think so.  We should fix TO_UNCAC() so that it works with CKSEG0
>> addresses.  It should be at physical address 0.  So
>> TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000
>>
>>
>> #define TO_UNCAC(x) ({ \
>> 	u64 a = (u64)(x);     \
>> 	if (a&  0xffffffffc000000 == 0xffffffff80000000) \
>> 		a = UNCAC_BASE | (a&  0x30000000); \
>> 	else \
>> 		a = UNCAC_BASE | (a&  TO_PHYS_MASK) \
>> 	a; \
>> })
>>
>> David Daney
>>
>> ...
>

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Wu Zhangjin]

On Mon, 2010-04-26 at 17:22 -0700, David Daney wrote:
[...]
> > Some time ago we needed to handle multiple (virtual) address-spaces
> > (in TO_CAC/TO_UNCAC as well as in virt_to_phys and the like) for
> > SGI's Indigo2/R10k and Octane (neither could run a 32bit kernel).
> > So in addrspace.h we provided
> > 	#ifdef CONFIG_64BIT
> > 	static inline unsigned long kernel_physaddr(unsigned long kva)
> > 	{
> > 		if((kva&0xffffffff80000000UL)==0xffffffff80000000UL)
> > 			return CPHYSADDR(kva);
> > 		return XPHYSADDR(kva);
> > 	}
> > 	#else
> > 	#define kernel_physaddr CPHYSADDR
> > 	#endif
> > while mach-ipXX/spaces.h defined
> > 	#define TO_PHYS(x)	(             kernel_physaddr(x))
> > 	#define TO_CAC(x)	(CAC_BASE   | kernel_physaddr(x))
> > 	#define TO_UNCAC(x)	(UNCAC_BASE | kernel_physaddr(x))
> > which did the job.
> > But at that time these defines didn't meet much acceptance for general
> > use in 64bit kernels.  Now, to my amusement, some modern processor
> > (and/or system) seems to urge this kind of address-handling again  ;-)
> >
> >
> 
> FWIW, that seems cleaner than what I did (actually I didn't try my 
> code).  That should be the default definition for 64-bit kernels I think.

Should we let this stuff be a common implementation? then we can also
provide the TO_CAC(), TO_PHYS(), TO_UNCAC() to the 32bit kernel and
remove some #ifdef from the kernel, for example:

> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 1a4dd65..fb8cd40 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1557,12 +1557,7 @@ static char panic_null_cerr[] __cpuinitdata =
>  void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
>         unsigned long size)
>  {
> -#ifdef CONFIG_32BIT
> -       unsigned long uncached_ebase = KSEG1ADDR(ebase);
> -#endif
> -#ifdef CONFIG_64BIT
>         unsigned long uncached_ebase = TO_UNCAC(ebase);
> -#endif
> 

And I have found lots of places have used KSEG1ADDR() in the kernel source code,
If the TO_UNCAC() for 32bit is provided, then we can also replace it by TO_UNCAC().

I will try to make a patch for it.

Regards,
	Wu Zhangjin

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Maciej W. Rozycki]

On Mon, 26 Apr 2010, David Daney wrote:

> > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
> > then we get the address: 0x97ffffff80000100, is this address ok?
> 
> I don't think so.  We should fix TO_UNCAC() so that it works with CKSEG0
> addresses.  It should be at physical address 0.  So
> TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000

 A 0xffffffff80000000 -> 0xffffffffa0000000 translation would make more 
sense IMHO.  Of course the use of XKPHYS addresses rather than CKSEG ones 
is preferable for 64-bit kernels in the first place, but then if the 
compatibility address space has been chosen for some reason (perhaps a 
virtual address stored in a structure defined by a peripheral is limited 
to 32 bits; I've seen such cases in DMA descriptor rings for example (not 
that code doing such things couldn't be converted to use cookies of some 
sort)), then I think it'll be safer to stick to the space.

  Maciej

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Wu Zhangjin]

On Mon, 2010-04-26 at 10:19 -0700, David Daney wrote:
> On 04/14/2010 01:03 AM, Wu Zhangjin wrote:
> > On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote:
> >> On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote:
> >>
> >>> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
> >>>> This patch have broken the support to the MIPS variants whose
> >>>> cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
> >>>> in these MIPSs.
> >>>
> >>> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
> >>> about CPU we are talking ? And wouldn't it make for senso to have
> >>> an extra define for the exception base then ?
> >>
> >> C0_ebase's design was a short-sigthed only considering 32-bit processors.
> >> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
> >> older.  So yes, there is a bug as I've verified by testing but the patch
> >> is unfortunately incorrect.
> >
> > Just debugged it via PMON:
> >
> > loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash"
> > to start the kernel, there was a bad address exception.
> >
> > the kernel stopped at:
> >
> > Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c
> > ...
> > BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000
> > ...
> > ...
> > __copy_user+0x48  ... sd  t0,0(a0)  # addr = 0x80000100 rt=0x401a8000
> >
> > Seems the a0 argument of __copy_user is _bad_.
> >
> > And tried to set a break pointer to trap_init() and per_cpu_trap_init(),
> > and then cpu_cache_init() ... r4k_cache_init() and at last found that
> > set_uncached_handler(0x100,&except_vec2_generic, 0x80);
> >
> > /*
> >   * Install uncached CPU exception handler.
> >   * This is suitable only for the cache error exception which is the only
> >   * exception handler that is being run uncached.
> >   */
> > void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
> >          unsigned long size)
> > {
> > #ifdef CONFIG_32BIT
> >          unsigned long uncached_ebase = KSEG1ADDR(ebase);
> > #endif
> > #ifdef CONFIG_64BIT
> >          unsigned long uncached_ebase = TO_UNCAC(ebase);
> > #endif
> >
> >          if (!addr)
> >                  panic(panic_null_cerr);
> >
> >          memcpy((void *)(uncached_ebase + offset), addr, size);
> > }
> >
> > memcpy() called __copy_user... and the a0 is uncached_ebase + offset,
> > and uncached_ebase is defined by TO_UNCAC:
> >
> > #define TO_UNCAC(x)             (UNCAC_BASE | ((x)&  TO_PHYS_MASK))
> > #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
> > #define UNCAC_BASE _AC(0x9000000000000000, UL)
> >
> > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
> > then we get the address: 0x97ffffff80000100, is this address ok?
> 
> I don't think so.  We should fix TO_UNCAC() so that it works with CKSEG0 
> addresses.  It should be at physical address 0.  So 
> TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000
> 
> 
> #define TO_UNCAC(x) ({ \
> 	u64 a = (u64)(x);     \
> 	if (a & 0xffffffffc000000 == 0xffffffff80000000) \
> 		a = UNCAC_BASE | (a & 0x30000000); \
> 	else \
> 		a = UNCAC_BASE | (a & TO_PHYS_MASK) \
> 	a; \
> })

Thanks, This works with few of changes:

> diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
> index c9fa4b1..b49f381 100644
> --- a/arch/mips/include/asm/mach-generic/spaces.h
> +++ b/arch/mips/include/asm/mach-generic/spaces.h
> @@ -71,7 +71,14 @@
>  
>  #define TO_PHYS(x)             (             ((x) & TO_PHYS_MASK))
>  #define TO_CAC(x)              (CAC_BASE   | ((x) & TO_PHYS_MASK))
> -#define TO_UNCAC(x)            (UNCAC_BASE | ((x) & TO_PHYS_MASK))
> +#define TO_UNCAC(x)            ({ \
> +       u64 a = (u64)(x);     \
> +       if ((a & 0xffffffffc0000000UL) == 0xffffffff80000000UL) \
> +               a = UNCAC_BASE | (a & 0x30000000); \
> +       else \
> +               a = UNCAC_BASE | (a & TO_PHYS_MASK); \
> +       a; \
> +})
>  
>  #endif /* CONFIG_64BIT */

I will send it out later.

Regards,
	Wu Zhangjin

> 
> David Daney
> 
> 
> >
> > And before, we have used the CAC_BASE as the ebase, the CAC_BASE is
> > defined as following:
> >
> > #ifndef CAC_BASE
> > #ifdef CONFIG_DMA_NONCOHERENT
> > #define CAC_BASE                _AC(0x9800000000000000, UL)
> > #else
> > #define CAC_BASE                _AC(0xa800000000000000, UL)
> > #endif
> > #endif
> >
> > So, before, the uncached_base is 0x9000000000000000.
> >
> > Regards,
> > 	Wu Zhangjin
> >
> >
> 

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[David Daney]

On 04/14/2010 01:03 AM, Wu Zhangjin wrote:
> On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote:
>> On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote:
>>
>>> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
>>>> This patch have broken the support to the MIPS variants whose
>>>> cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
>>>> in these MIPSs.
>>>
>>> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
>>> about CPU we are talking ? And wouldn't it make for senso to have
>>> an extra define for the exception base then ?
>>
>> C0_ebase's design was a short-sigthed only considering 32-bit processors.
>> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
>> older.  So yes, there is a bug as I've verified by testing but the patch
>> is unfortunately incorrect.
>
> Just debugged it via PMON:
>
> loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash"
> to start the kernel, there was a bad address exception.
>
> the kernel stopped at:
>
> Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c
> ...
> BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000
> ...
> ...
> __copy_user+0x48  ... sd  t0,0(a0)  # addr = 0x80000100 rt=0x401a8000
>
> Seems the a0 argument of __copy_user is _bad_.
>
> And tried to set a break pointer to trap_init() and per_cpu_trap_init(),
> and then cpu_cache_init() ... r4k_cache_init() and at last found that
> set_uncached_handler(0x100,&except_vec2_generic, 0x80);
>
> /*
>   * Install uncached CPU exception handler.
>   * This is suitable only for the cache error exception which is the only
>   * exception handler that is being run uncached.
>   */
> void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
>          unsigned long size)
> {
> #ifdef CONFIG_32BIT
>          unsigned long uncached_ebase = KSEG1ADDR(ebase);
> #endif
> #ifdef CONFIG_64BIT
>          unsigned long uncached_ebase = TO_UNCAC(ebase);
> #endif
>
>          if (!addr)
>                  panic(panic_null_cerr);
>
>          memcpy((void *)(uncached_ebase + offset), addr, size);
> }
>
> memcpy() called __copy_user... and the a0 is uncached_ebase + offset,
> and uncached_ebase is defined by TO_UNCAC:
>
> #define TO_UNCAC(x)             (UNCAC_BASE | ((x)&  TO_PHYS_MASK))
> #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
> #define UNCAC_BASE _AC(0x9000000000000000, UL)
>
> If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
> then we get the address: 0x97ffffff80000100, is this address ok?

I don't think so.  We should fix TO_UNCAC() so that it works with CKSEG0 
addresses.  It should be at physical address 0.  So 
TO_UNCAC(0xffffffff80000000), should yield 0x9000000000000000


#define TO_UNCAC(x) ({ \
	u64 a = (u64)(x);     \
	if (a & 0xffffffffc000000 == 0xffffffff80000000) \
		a = UNCAC_BASE | (a & 0x30000000); \
	else \
		a = UNCAC_BASE | (a & TO_PHYS_MASK) \
	a; \
})

David Daney


>
> And before, we have used the CAC_BASE as the ebase, the CAC_BASE is
> defined as following:
>
> #ifndef CAC_BASE
> #ifdef CONFIG_DMA_NONCOHERENT
> #define CAC_BASE                _AC(0x9800000000000000, UL)
> #else
> #define CAC_BASE                _AC(0xa800000000000000, UL)
> #endif
> #endif
>
> So, before, the uncached_base is 0x9000000000000000.
>
> Regards,
> 	Wu Zhangjin
>
>

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Wu Zhangjin]

On Wed, 2010-04-14 at 13:24 +0200, Thomas Bogendoerfer wrote:
> On Wed, Apr 14, 2010 at 04:03:05PM +0800, Wu Zhangjin wrote:
> > If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
> > then we get the address: 0x97ffffff80000100, is this address ok?
> 
> the address is broken TO_UNCAC doesn't work properly for CKSEG0 addresses.
> And that's IMHO the real bug... I'm wondering whether this 
> set_uncached_handler() stunt is even needed. Is there a machine
> where CKSEG0 and CKSEG1 address different memory ? If not, we could
> just use the normal set_handler() function and be done with it.
> 

Hi, all

I'm not familiar with this part, is there any fixup/workaround for this
bug? otherwise, we will get a broken support for the r4k machines(at
least the loongson machines).

Regards,
	Wu Zhangjin

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Thomas Bogendoerfer]

On Wed, Apr 14, 2010 at 04:03:05PM +0800, Wu Zhangjin wrote:
> If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
> then we get the address: 0x97ffffff80000100, is this address ok?

the address is broken TO_UNCAC doesn't work properly for CKSEG0 addresses.
And that's IMHO the real bug... I'm wondering whether this 
set_uncached_handler() stunt is even needed. Is there a machine
where CKSEG0 and CKSEG1 address different memory ? If not, we could
just use the normal set_handler() function and be done with it.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Wu Zhangjin]

On Tue, 2010-04-13 at 18:16 +0100, Ralf Baechle wrote:
> On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote:
> 
> > On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
> > > This patch have broken the support to the MIPS variants whose
> > > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
> > > in these MIPSs.
> > 
> > I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
> > about CPU we are talking ? And wouldn't it make for senso to have
> > an extra define for the exception base then ?
> 
> C0_ebase's design was a short-sigthed only considering 32-bit processors.
> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
> older.  So yes, there is a bug as I've verified by testing but the patch
> is unfortunately incorrect.

Just debugged it via PMON:

loaded the kernel and used "g console=tty root=/dev/hda5 init=/bin/bash"
to start the kernel, there was a bad address exception.

the kernel stopped at:

Exception Cause=address error on store, SR=0x24000002, PC=0x8020526c
...
BADVADDR=0x97ffffff80000100, ENTHI=0xfffffe000
...
...
__copy_user+0x48  ... sd  t0,0(a0)  # addr = 0x80000100 rt=0x401a8000

Seems the a0 argument of __copy_user is _bad_.

And tried to set a break pointer to trap_init() and per_cpu_trap_init(),
and then cpu_cache_init() ... r4k_cache_init() and at last found that
set_uncached_handler(0x100, &except_vec2_generic, 0x80);

/*
 * Install uncached CPU exception handler.
 * This is suitable only for the cache error exception which is the only
 * exception handler that is being run uncached.
 */
void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
        unsigned long size)
{
#ifdef CONFIG_32BIT
        unsigned long uncached_ebase = KSEG1ADDR(ebase);
#endif       
#ifdef CONFIG_64BIT
        unsigned long uncached_ebase = TO_UNCAC(ebase);
#endif       

        if (!addr)
                panic(panic_null_cerr);

        memcpy((void *)(uncached_ebase + offset), addr, size);
}

memcpy() called __copy_user... and the a0 is uncached_ebase + offset,
and uncached_ebase is defined by TO_UNCAC:

#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
#define UNCAC_BASE _AC(0x9000000000000000, UL)

If using CKSEG0 as the ebase, CKSEG0 is defined as 0xffffffff80000000,
then we get the address: 0x97ffffff80000100, is this address ok?

And before, we have used the CAC_BASE as the ebase, the CAC_BASE is
defined as following:

#ifndef CAC_BASE
#ifdef CONFIG_DMA_NONCOHERENT
#define CAC_BASE                _AC(0x9800000000000000, UL)
#else
#define CAC_BASE                _AC(0xa800000000000000, UL)
#endif
#endif

So, before, the uncached_base is 0x9000000000000000.

Regards,
	Wu Zhangjin

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Thomas Bogendoerfer]

On Tue, Apr 13, 2010 at 06:16:10PM +0100, Ralf Baechle wrote:
> C0_ebase's design was a short-sigthed only considering 32-bit processors.
> So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
> older.  So yes, there is a bug as I've verified by testing but the patch
> is unfortunately incorrect.

well not quite every 64bit CPU, R8k is as always special. R8k has
a trap vector register. But since support for R8k is still lacking
no problem for now.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Ralf Baechle]

On Tue, Apr 13, 2010 at 09:34:38AM +0200, Thomas Bogendoerfer wrote:

> On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
> > This patch have broken the support to the MIPS variants whose
> > cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
> > in these MIPSs.
> 
> I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
> about CPU we are talking ? And wouldn't it make for senso to have
> an extra define for the exception base then ?

C0_ebase's design was a short-sigthed only considering 32-bit processors.
So the exception base is in CKSEG0 on every 64-bit processor, be it R2 or
older.  So yes, there is a bug as I've verified by testing but the patch
is unfortunately incorrect.

  Ralf

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Thomas Bogendoerfer]

On Tue, Apr 13, 2010 at 01:03:54PM +0800, Wu Zhangjin wrote:
> This patch have broken the support to the MIPS variants whose
> cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
> in these MIPSs.

I've checked R4k and R10k manulas and the exception base is at CKSEG0, so
about CPU we are talking ? And wouldn't it make for senso to have
an extra define for the exception base then ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Wu Zhangjin]

Hi, David and Ralf

This patch have broken the support to the MIPS variants whose
cpu_has_mips_r2 is 0 for the CAC_BASE and CKSEG0 is completely different
in these MIPSs.

With the patch, the kernel will exit when booting(later after
trap_init()).

A potential patch to fix the above problem is:

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 1a4dd65..d8cb554 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1599,7 +1599,7 @@ void __init trap_init(void)
 		ebase = (unsigned long)
 			__alloc_bootmem(size, 1 << fls(size), 0);
 	} else {
-		ebase = CKSEG0;
+		ebase = (cpu_has_mips_r2) ? CKSEG0 : CAC_BASE;
 		if (cpu_has_mips_r2)
 			ebase += (read_c0_ebase() & 0x3ffff000);
 	}

Regards,
	Wu Zhangjin

On Tue, 2010-04-06 at 13:29 -0700, David Daney wrote:
> The ebase is relative to CKSEG0 not CAC_BASE.  On a 32-bit kernel they
> are the same thing, for a 64-bit kernel they are not.
> 
> It happens to kind of work on a 64-bit kernel as they both reference
> the same physical memory.  However since the CPU uses the CKSEG0 base,
> determining if a J instruction will reach always gives the wrong
> result unless we use the same number the CPU uses.
> 
> Signed-off-by: David Daney <ddaney@caviumnetworks.com>
> ---
>  arch/mips/kernel/traps.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 7ce84bb..b122f76 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1706,7 +1706,7 @@ void __init trap_init(void)
>  		ebase = (unsigned long)
>  			__alloc_bootmem(size, 1 << fls(size), 0);
>  	} else {
> -		ebase = CAC_BASE;
> +		ebase = CKSEG0;
>  		if (cpu_has_mips_r2)
>  			ebase += (read_c0_ebase() & 0x3ffff000);
>  	}

Re: [PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[Ralf Baechle]

On Tue, Apr 06, 2010 at 01:29:50PM -0700, David Daney wrote:

> The ebase is relative to CKSEG0 not CAC_BASE.  On a 32-bit kernel they
> are the same thing, for a 64-bit kernel they are not.
> 
> It happens to kind of work on a 64-bit kernel as they both reference
> the same physical memory.  However since the CPU uses the CKSEG0 base,
> determining if a J instruction will reach always gives the wrong
> result unless we use the same number the CPU uses.

Applied, thanks!

  Ralf

[PATCH] MIPS: Calculate proper ebase value for 64-bit kernels

[David Daney]

The ebase is relative to CKSEG0 not CAC_BASE.  On a 32-bit kernel they
are the same thing, for a 64-bit kernel they are not.

It happens to kind of work on a 64-bit kernel as they both reference
the same physical memory.  However since the CPU uses the CKSEG0 base,
determining if a J instruction will reach always gives the wrong
result unless we use the same number the CPU uses.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
 arch/mips/kernel/traps.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 7ce84bb..b122f76 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1706,7 +1706,7 @@ void __init trap_init(void)
 		ebase = (unsigned long)
 			__alloc_bootmem(size, 1 << fls(size), 0);
 	} else {
-		ebase = CAC_BASE;
+		ebase = CKSEG0;
 		if (cpu_has_mips_r2)
 			ebase += (read_c0_ebase() & 0x3ffff000);
 	}
-- 
1.6.6.1