[U-Boot] PPC440GX TLB setting problem.

[U-Boot] PPC440GX TLB setting problem.

[Wouter Eckhardt]

Hi all,

I'm working on trying to get VxWorks to boot on a PPC440GX processor
using U-Boot, using an ALPR board. In order to boot VxWorks properly (it
expects caching on the SDRAM to be disabled), I created a new board
directory and such (based on the ALPR board), and then changed the TLB
settings in init.S.

My problem is that when my new U-Boot has booted, the TLBs are not
configured as I have programmed them. I verified this using a BDI
debugger. The TLB settings are still the same as the settings the
original ALPR U-Boot used. I'm really at a loss here. It seems that no
matter what I try (I tried quite a few variantions of the TLB settings),
the TLB settings won't change.

So now I several, related, questions:
- What could be the cause of this? Have I done something wrong? 
- Is U-Boot reconfiguring the TLBs after init.S has executed? 
- If so, how can I control those TLBs?

Here's a code snippet from my init.S:
/***********************************************************************
***
 * TLB TABLE
 *
 * This table is used by the cpu boot code to setup the initial tlb
 * entries. Rather than make broad assumptions in the cpu source tree,
 * this table lets each board set things up however they like.
 *
 *  Pointer to the table is returned in r1
 *
 
************************************************************************
*/
/* Updated to reflect TLB entries in VxWorks. */
        .section .bootpg,"ax"
        .globl tlbtab

tlbtab:
        tlbtab_start
        tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
        tlbentry( 0x80000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_I )
        tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1,
AC_R|AC_W|SA_G|SA_I )
        tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )
        tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X
)

#ifdef CFG_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!)
*/
        tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
AC_R|AC_W|AC_X|SA_G )
#endif
        tlbtab_end

And here's the BDI's listing of the TLBs after U-Boot has booted (no
auto boot):
- TARGET: processing target startup ....
- TARGET: processing target startup passed
ALPR>go
ALPR>halt
    Core number       : 0
    Core state        : debug mode
    Debug entry cause : JTAG stop request
    Current PC        : 0x0ffe372c
    Current CR        : 0x28dcff82
    Current MSR       : 0x00029000
    Current LR        : 0x0ffe378c
ALPR>tlb 0 15
IDX TID      EPN  SIZE VTS          RPN   USER WIMGE USRSVC
 0 : 00 ff000000  16MB V0 -> 1_ff000000 U:0000 -I-G- XWRXWR
 1 : 00 e0000000 256MB V0 -> 1_40000000 U:0000 -I-G- -WR-WR
 2 : 00 c0000000   4KB V0 -> 0_80000000 U:0000 ----- XWRXWR
 3 : 00 c0001000   4KB V0 -> 0_80001000 U:0000 ----- XWRXWR
 4 : 00 00000000 256MB V0 -> 0_00000000 U:0000 ---G- XWRXWR
 5 : 00 d0000000 256MB V0 -> 2_00000000 U:0000 -I-G- -WR-WR
 6 : 00 80000000 256MB V0 -> 3_80000000 U:0000 -I-G- -WR-WR
 7 : 00 90000000 256MB V0 -> 3_90000000 U:0000 -I-G- -WR-WR
 8 : 00 a0000000 256MB V0 -> 3_a0000000 U:0000 -I-G- -WR-WR
 9 : 00 f0000000   4KB V0 -> 1_f0000000 U:0000 -I-G- XWRXWR
10 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
11 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
12 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
13 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
14 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
15 : 00 00000000   1KB -0 -> 0_00000000 U:0000 ----- ------
ALPR>

Thanks in advance!

Met vriendelijke groet,
With kind regards,

Wouter Eckhardt
Engineer
wouter.eckhardt at prodrive.nl
tel. +31 40 2676187
Prodrive B.V.
Postbus 28030
5602 JA Eindhoven
Ekkersrijt 5025
5692 EB Son
The Netherlands
tel. +31 40 2676200
fax: +31 40 2676201
www.prodrive.nl


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[U-Boot] PPC440GX TLB setting problem.

[Stefan Roese]

Hi Wouter,

On Thursday 23 July 2009 20:39:44 Wouter Eckhardt wrote:
> I'm working on trying to get VxWorks to boot on a PPC440GX processor
> using U-Boot, using an ALPR board. In order to boot VxWorks properly (it
> expects caching on the SDRAM to be disabled), I created a new board
> directory and such (based on the ALPR board), and then changed the TLB
> settings in init.S.

Are you sure that the cache needs to be disabled? Perhaps it just needs to get 
properly flushed before booting VxWorks? Just checking.

> My problem is that when my new U-Boot has booted, the TLBs are not
> configured as I have programmed them. I verified this using a BDI
> debugger. The TLB settings are still the same as the settings the
> original ALPR U-Boot used. I'm really at a loss here. It seems that no
> matter what I try (I tried quite a few variantions of the TLB settings),
> the TLB settings won't change.
>
> So now I several, related, questions:
> - What could be the cause of this? Have I done something wrong?

This could have multiple reasons. Are you sure that you are running the 
freshly compiled image on the board? Did you check the build time?

> - Is U-Boot reconfiguring the TLBs after init.S has executed?

Yes. But only one (IIRC). The first TLB for bootrom access. Caching will be 
disabled before relocating to SDRAM.

> - If so, how can I control those TLBs?

All other TLB's should be the same.

Not sure what's going wrong here.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] PPC440GX TLB setting problem.

[Wouter Eckhardt]

Hi Stefan,

Thanks for the quick reply.

> On Thursday 23 July 2009 20:39:44 Wouter Eckhardt wrote:
> > I'm working on trying to get VxWorks to boot on a PPC440GX processor
> > using U-Boot, using an ALPR board. In order to boot VxWorks properly
(it
> > expects caching on the SDRAM to be disabled), I created a new board
> > directory and such (based on the ALPR board), and then changed the
TLB
> > settings in init.S.
> 
> Are you sure that the cache needs to be disabled? Perhaps it just
needs to
> get
> properly flushed before booting VxWorks? Just checking.
> 

Yes, I've checked the VxWorks kernel code. The comments mention that if
caching is enabled, the cache should be flushed before the call to MMU
TLB initialization is done. However, the calling code never actually
flushes the cache. So they're not even following their own advice. In
the calling code, they just assume that caching is disabled.

> > My problem is that when my new U-Boot has booted, the TLBs are not
> > configured as I have programmed them. I verified this using a BDI
> > debugger. The TLB settings are still the same as the settings the
> > original ALPR U-Boot used. I'm really at a loss here. It seems that
no
> > matter what I try (I tried quite a few variantions of the TLB
settings),
> > the TLB settings won't change.
> >
> > So now I several, related, questions:
> > - What could be the cause of this? Have I done something wrong?
> 
> This could have multiple reasons. Are you sure that you are running
the
> freshly compiled image on the board? Did you check the build time?
> 

The build date and time of the U-Boot image I'm running is correct. I've
also verified this because #undef-ing the 4XX_DCACHE config causes
U-Boot to not function properly (Ethernet problem). So I'm confident
that I really am running my own build. I've also verified that I'm
compiling the right source, by forcing syntax errors.

> > - Is U-Boot reconfiguring the TLBs after init.S has executed?
> 
> Yes. But only one (IIRC). The first TLB for bootrom access. Caching
will
> be
> disabled before relocating to SDRAM.
> 

Hmmm. This should be a problem since I changed the TLB settings to have
SDRAM at the first TLB. However, the SDRAM gets remapped in a different
TLB as well. Where in the code can I find this? I tried looking for
something like that, but couldn't find it. Perhaps that piece of code is
actually replacing all TLBs, not just the bootrom access one.

> > - If so, how can I control those TLBs?
> 
> All other TLB's should be the same.
> 
> Not sure what's going wrong here.
> 
> Best regards,
> Stefan
> 
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
> =====================================================================

Kind regards,
Wouter Eckhardt.

Disclaimer: The information contained in this email, including any attachments is 
confidential and is for the sole use of the intended recipient(s). Any unauthorized 
review, use, disclosure or distribution is prohibited. If you are not the intended 
recipient, please notify the sender immediately by replying to this message and 
destroy all copies of this message and any attachments.

[U-Boot] PPC440GX TLB setting problem.

[Stefan Roese]

Hi Wouter,

On Friday 24 July 2009 09:48:17 Wouter Eckhardt wrote:
> Yes, I've checked the VxWorks kernel code. The comments mention that if
> caching is enabled, the cache should be flushed before the call to MMU
> TLB initialization is done. However, the calling code never actually
> flushes the cache. So they're not even following their own advice. In
> the calling code, they just assume that caching is disabled.

OK.

> > > - Is U-Boot reconfiguring the TLBs after init.S has executed?
> >
> > Yes. But only one (IIRC). The first TLB for bootrom access. Caching
> > will be disabled before relocating to SDRAM.
> Hmmm. This should be a problem since I changed the TLB settings to have
> SDRAM at the first TLB. However, the SDRAM gets remapped in a different
> TLB as well. Where in the code can I find this? I tried looking for
> something like that, but couldn't find it. Perhaps that piece of code is
> actually replacing all TLBs, not just the bootrom access one.

Take a look at Sequoia. It has support for VxWorks booting. You need to switch 
the sequence of the TLB entries. init.S:

	/* vxWorks needs this as first entry for the Machine Check interrupt */
	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )

And you need to set CONFIG_SYS_TLB_FOR_BOOT_FLASH in your board config header 
to the number of the boot TLB entry.

Let me know if this helps.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================