Re: [PATCH][RFC] FPU LWP 2/5: add mask option to xsave/xrstor

Re: [PATCH][RFC] FPU LWP 2/5: add mask option to xsave/xrstor

[Jan Beulich]

>>> On 14.04.11 at 22:38, Wei Huang <wei.huang2@amd.com> wrote:
> This patch adds a mask option to xsave/xrstor. This mask is used by 
> xsave and xrstor instructions to selectively save/restore memory area.
> 
> Signed-off-by: Wei Huang <wei.huang2@amd.com>

This

>-static void xsave(struct vcpu *v)
>+static void xsave(struct vcpu *v, uint64_t mask)
> {
>     struct xsave_struct *ptr = v->arch.xsave_area;
>+    uint32_t hmask = mask >> 32;
>+    uint32_t lmask = mask;
> 
>     asm volatile (
>         ".byte " REX_PREFIX "0x0f,0xae,0x27"
>         :
>-        : "a" (-1), "d" (-1), "D"(ptr)
>+        : "a" (lmask), "d" (hmask), "D"(ptr)
>         : "memory" );
> }
>... 
>@@ -185,7 +191,7 @@
>      * we set all supported feature mask before doing save/restore.
>      */
>     set_xcr0(v->arch.xcr0_accum);
>-    xrstor(v);
>+    xrstor(v, XCNTXT_MASK);
>     set_xcr0(v->arch.xcr0);
> }
> 

(and similarly in other functions) isn't forward compatible anymore.
The mask had all bits set previously, but now only is

>+#define XCNTXT_MASK         (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | XSTATE_LWP)

My understanding of xsave and its cpuid leaf is that it is meant to be
possible to have new hardware features added without OSes
constantly needing modification to make them available to user
mode software.

LWP not fitting into the lazy restore picture is rather unfortunate
here, and I wonder whether it was a good decision to have its
save/restore done via xsave... Does native Linux already have
LWP support (can't seem to spot it in 3.6.39-rc3)? If so, how is
this being addressed there?

Jan

[PATCH][RFC] FPU LWP 2/5: add mask option to xsave/xrstor

[Wei Huang]

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This patch adds a mask option to xsave/xrstor. This mask is used by 
xsave and xrstor instructions to selectively save/restore memory area.

Signed-off-by: Wei Huang <wei.huang2@amd.com>


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# HG changeset patch
# User Wei Huang <wei.huang2@amd.com>
# Date 1302811998 18000
# Branch lwp3
# Node ID f5c4d99cde695bd0342a96d3ea6d5b34bd6047af
# Parent  4ed4e3d9106e691dddf3bbf54afd935ef0a9000f
FPU: Add mask option to xsave/xrstor

This patch adds a mask option to xsave/xrstor. This mask is used by xsave and xrstor instructions to selectively save/restore memory area.

Signed-off-by: Wei Huang <wei.huang2@amd.com>

diff -r 4ed4e3d9106e -r f5c4d99cde69 xen/arch/x86/i387.c
--- a/xen/arch/x86/i387.c	Thu Apr 14 15:12:07 2011 -0500
+++ b/xen/arch/x86/i387.c	Thu Apr 14 15:13:18 2011 -0500
@@ -127,36 +127,42 @@
     return cpu_has_xsave;	
 }
 
-static void xsave(struct vcpu *v)
+static void xsave(struct vcpu *v, uint64_t mask)
 {
     struct xsave_struct *ptr = v->arch.xsave_area;
+    uint32_t hmask = mask >> 32;
+    uint32_t lmask = mask;
 
     asm volatile (
         ".byte " REX_PREFIX "0x0f,0xae,0x27"
         :
-        : "a" (-1), "d" (-1), "D"(ptr)
+        : "a" (lmask), "d" (hmask), "D"(ptr)
         : "memory" );
 }
 
-static void xsaveopt(struct vcpu *v)
+static void xsaveopt(struct vcpu *v, uint64_t mask)
 {
     struct xsave_struct *ptr = v->arch.xsave_area;
+    uint32_t hmask = mask >> 32;
+    uint32_t lmask = mask;
 
     asm volatile (
         ".byte " REX_PREFIX "0x0f,0xae,0x37"
         :
-        : "a" (-1), "d" (-1), "D"(ptr)
+        : "a" (lmask), "d" (hmask), "D"(ptr)
         : "memory" );
 }
 
-static void xrstor(struct vcpu *v)
+static void xrstor(struct vcpu *v, uint64_t mask)
 {
     struct xsave_struct *ptr = v->arch.xsave_area;
+    uint32_t hmask = mask >> 32;
+    uint32_t lmask = mask;
 
     asm volatile (
         ".byte " REX_PREFIX "0x0f,0xae,0x2f"
         :
-        : "m" (*ptr), "a" (-1), "d" (-1), "D"(ptr) );
+        : "m" (*ptr), "a" (lmask), "d" (hmask), "D"(ptr) );
 }
 
 /******************************/
@@ -185,7 +191,7 @@
      * we set all supported feature mask before doing save/restore.
      */
     set_xcr0(v->arch.xcr0_accum);
-    xrstor(v);
+    xrstor(v, XCNTXT_MASK);
     set_xcr0(v->arch.xcr0);
 }
 
@@ -270,10 +276,10 @@
      */
     set_xcr0(v->arch.xcr0_accum);
     if ( cpu_has_xsaveopt )
-        xsaveopt(v);
+        xsaveopt(v, XCNTXT_MASK);
     else
-        xsave(v);
-    set_xcr0(v->arch.xcr0);    
+        xsave(v, XCNTXT_MASK);
+    set_xcr0(v->arch.xcr0);
 }
 
 /* Save x87 FPU, MMX, SSE and SSE2 state */
diff -r 4ed4e3d9106e -r f5c4d99cde69 xen/include/asm-x86/i387.h
--- a/xen/include/asm-x86/i387.h	Thu Apr 14 15:12:07 2011 -0500
+++ b/xen/include/asm-x86/i387.h	Thu Apr 14 15:13:18 2011 -0500
@@ -23,15 +23,17 @@
 extern u64 xfeature_mask;
 
 #define XSAVE_AREA_MIN_SIZE (512 + 64) /* FP/SSE + XSAVE.HEADER */
-#define XSTATE_FP       (1ULL << 0)
-#define XSTATE_SSE      (1ULL << 1)
-#define XSTATE_YMM      (1ULL << 2)
-#define XSTATE_LWP      (1ULL << 62) /* AMD lightweight profiling */
-#define XSTATE_FP_SSE   (XSTATE_FP | XSTATE_SSE)
-#define XCNTXT_MASK     (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | XSTATE_LWP)
-#define XSTATE_YMM_OFFSET  XSAVE_AREA_MIN_SIZE
-#define XSTATE_YMM_SIZE    256
-#define XSAVEOPT        (1 << 0)
+#define XSTATE_YMM_OFFSET   XSAVE_AREA_MIN_SIZE
+#define XSTATE_YMM_SIZE     256
+
+#define XSTATE_FP           (1ULL << 0)
+#define XSTATE_SSE          (1ULL << 1)
+#define XSTATE_YMM          (1ULL << 2)
+#define XSTATE_LWP          (1ULL << 62) /* AMD lightweight profiling */
+#define XSTATE_FP_SSE       (XSTATE_FP | XSTATE_SSE)
+#define XCNTXT_MASK         (XSTATE_FP | XSTATE_SSE | XSTATE_YMM | XSTATE_LWP)
+
+#define XSAVEOPT            (1 << 0)
 
 #define XCR_XFEATURE_ENABLED_MASK   0
 

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