[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Marc Zyngier]

The current GIC per-cpu interrupt (aka PPIs) suffers from a number of
problems:

- It uses a completely separate scheme to handle the interrupts,
  mostly because the PPI concept doesn't really match the kernel view
  of an interrupt.
- Some low-level code gets duplicated, as usual...
- At least one platform (msm) has started implementing its own
  alternative scheme.

The proposed solution is to let the GIC code expose the PPIs as
something that the kernel can manage. Instead of having a single
interrupt number shared on all cores, make the interrupt number be
different on each CPU.

This enables the use of the normal kernel API (request_irq() and
friends) and the elimination of some low level code.

This patch set is based on 2.6.39-rc6, and depends on Will Deacon's
GIC fasteoi patches. Tested on VExpress, PB-11MP, Pandaboard and
SMDK-S5PV310.

[RFC PATCH v2 01/12] ARM: gic: add per-cpu interrupt multiplexer

[Marc Zyngier]

The kernel doesn't handle very well the concept of per-cpu interrupt
as implemented by the ARM architecture (the same interrupt level is
exposed on each core).

To work around the problem, add another irq_chip to handle PPIs and
remap them so that a single interrupt number is only used on a given
CPU (for example, IRQ 29 and 30 get exposed as IRQ 128 and 129 on
core 0, 130 and 131 on core 1...).

A helper function gic_ppi_to_vppi() is used to convert the PPI number
to the per-processor IRQ.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/common/Kconfig                         |    5 +
 arch/arm/common/gic.c                           |  133 ++++++++++++++++++++++-
 arch/arm/include/asm/entry-macro-multi.S        |    2 +-
 arch/arm/include/asm/hardware/entry-macro-gic.S |   19 ++--
 arch/arm/include/asm/hardware/gic.h             |   11 ++
 arch/arm/kernel/irq.c                           |    8 ++-
 6 files changed, 165 insertions(+), 13 deletions(-)

diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index ea5ee4d..020a531 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,6 +1,11 @@
 config ARM_GIC
 	bool
 
+config ARM_GIC_VPPI
+	depends on ARM_GIC
+	select SPARSE_IRQ
+        bool
+
 config ARM_VIC
 	bool
 
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index e9c2ff8..529a8ed 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -42,6 +42,12 @@ struct gic_chip_data {
 	unsigned int irq_offset;
 	void __iomem *dist_base;
 	void __iomem *cpu_base;
+#ifdef CONFIG_ARM_GIC_VPPI
+	/* These fields must be 0 on secondary GICs */
+	int	     ppi_base;
+	int	     vppi_base;
+	u16	     nrppis;
+#endif
 };
 
 /*
@@ -262,12 +268,88 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 	irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
+#ifdef CONFIG_ARM_GIC_VPPI
+unsigned int gic_ppi_to_vppi(unsigned int irq)
+{
+	struct gic_chip_data *chip_data = irq_get_chip_data(irq);
+	unsigned int vppi_irq;
+	unsigned int ppi;
+
+	WARN_ON(!chip_data->vppi_base);
+
+	ppi = irq - chip_data->ppi_base;
+	vppi_irq = ppi + chip_data->nrppis * smp_processor_id();
+	vppi_irq += chip_data->vppi_base;
+
+	return vppi_irq;
+}
+
+static void gic_handle_ppi(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned int vppi_irq;
+
+	vppi_irq = gic_ppi_to_vppi(irq);
+	generic_handle_irq(vppi_irq);
+}
+
+static struct irq_data *gic_vppi_to_ppi(struct irq_data *d)
+{
+	struct gic_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	unsigned int ppi_irq;
+
+	ppi_irq = d->irq - chip_data->vppi_base - chip_data->nrppis * smp_processor_id();
+	ppi_irq += chip_data->ppi_base;
+
+	return irq_get_irq_data(ppi_irq);
+}
+
+static void gic_ppi_eoi_irq(struct irq_data *d)
+{
+	gic_eoi_irq(gic_vppi_to_ppi(d));
+}
+
+static void gic_ppi_mask_irq(struct irq_data *d)
+{
+	gic_mask_irq(gic_vppi_to_ppi(d));
+}
+
+static void gic_ppi_unmask_irq(struct irq_data *d)
+{
+	gic_unmask_irq(gic_vppi_to_ppi(d));
+}
+
+static int gic_ppi_set_type(struct irq_data *d, unsigned int type)
+{
+	return gic_set_type(gic_vppi_to_ppi(d), type);
+}
+
+static int gic_ppi_set_wake(struct irq_data *d, unsigned int on)
+{
+	return gic_set_wake(gic_vppi_to_ppi(d), on);
+}
+
+static int __init gic_irq_is_ppi(struct gic_chip_data *gic, unsigned int irq)
+{
+	return (irq >= (gic->irq_offset + 16) && irq <= (gic->irq_offset + 31));
+}
+
+static struct irq_chip gic_ppi_chip = {
+	.name			= "GIC-PPI",
+	.irq_eoi		= gic_ppi_eoi_irq,
+	.irq_mask		= gic_ppi_mask_irq,
+	.irq_unmask		= gic_ppi_unmask_irq,
+	.irq_set_type		= gic_ppi_set_type,
+	.irq_set_wake		= gic_ppi_set_wake,
+};
+#endif
+
 static void __init gic_dist_init(struct gic_chip_data *gic,
 	unsigned int irq_start)
 {
-	unsigned int gic_irqs, irq_limit, i;
+	unsigned int gic_irqs, irq_limit, i, nrvppis = 0;
 	void __iomem *base = gic->dist_base;
 	u32 cpumask = 1 << smp_processor_id();
+	u32 dist_ctr, nrcpus;
 
 	cpumask |= cpumask << 8;
 	cpumask |= cpumask << 16;
@@ -278,11 +360,32 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
 	 * Find out how many interrupts are supported.
 	 * The GIC only supports up to 1020 interrupt sources.
 	 */
-	gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
-	gic_irqs = (gic_irqs + 1) * 32;
+	dist_ctr = readl(base + GIC_DIST_CTR);
+	gic_irqs = ((dist_ctr & 0x1f) + 1) * 32;
 	if (gic_irqs > 1020)
 		gic_irqs = 1020;
 
+	/* Find out how many CPUs are supported (8 max). */
+	nrcpus = ((dist_ctr >> 5) & 7) + 1;
+
+#ifdef CONFIG_ARM_GIC_VPPI
+	/*
+	 * Nobody would be insane enough to use PPIs on a secondary
+	 * GIC, right?
+	 */
+	if (gic == &gic_data[0]) {
+		gic->nrppis = 16 - (irq_start % 16);
+		gic->ppi_base = gic->irq_offset + 32 - gic->nrppis;
+		nrvppis = gic->nrppis * nrcpus;
+	} else {
+		gic->ppi_base = 0;
+		gic->vppi_base = 0;
+	}
+#endif
+
+	pr_info("Configuring GIC with %d sources (%d additional PPIs)\n",
+		gic_irqs, nrvppis);
+
 	/*
 	 * Set all global interrupts to be level triggered, active low.
 	 */
@@ -319,10 +422,32 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
 	 * Setup the Linux IRQ subsystem.
 	 */
 	for (i = irq_start; i < irq_limit; i++) {
-		irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
+#ifdef CONFIG_ARM_GIC_VPPI
+		if (nrvppis && gic_irq_is_ppi(gic, i))
+			irq_set_chip_and_handler(i, &gic_chip, gic_handle_ppi);
+		else
+#endif
+		{
+			irq_set_chip_and_handler(i, &gic_chip,
+						 handle_fasteoi_irq);
+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+		}
+		irq_set_chip_data(i, gic);
+	}
+
+#ifdef CONFIG_ARM_GIC_VPPI
+	if (!nrvppis)
+		goto out;
+	gic->vppi_base = irq_alloc_descs(-1, 0, nrvppis, 0);
+	if (WARN_ON(gic->vppi_base < 0))
+		goto out;
+	for (i = gic->vppi_base; i < (gic->vppi_base + nrvppis); i++) {
+		irq_set_chip_and_handler(i, &gic_ppi_chip, handle_percpu_irq);
 		irq_set_chip_data(i, gic);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 	}
+out:
+#endif
 
 	writel(1, base + GIC_DIST_CTRL);
 }
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index ec0bbf7..c599795 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -24,7 +24,7 @@
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
 
-#ifdef CONFIG_LOCAL_TIMERS
+#if defined(CONFIG_LOCAL_TIMERS) && !defined(CONFIG_ARM_GIC_VPPI)
 	test_for_ltirq r0, r6, r5, lr
 	movne	r0, sp
 	adrne	lr, BSYM(1b)
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index c115b82..14a3363 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -17,23 +17,26 @@
 	.endm
 #endif
 
+#ifdef CONFIG_ARM_GIC_VPPI
+#define DO_IRQ_BASE	16
+#else
+#define DO_IRQ_BASE	30
+#endif
+
 /*
  * The interrupt numbering scheme is defined in the
  * interrupt controller spec.  To wit:
  *
  * Interrupts 0-15 are IPI
- * 16-28 are reserved
- * 29-31 are local.  We allow 30 to be used for the watchdog.
+ * 16-31 are local.  We allow 30 to be used for the watchdog.
  * 32-1020 are global
  * 1021-1022 are reserved
  * 1023 is "spurious" (no interrupt)
  *
- * For now, we ignore all local interrupts so only return an interrupt if it's
- * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
- *
  * A simple read from the controller will tell us the number of the highest
  * priority enabled interrupt.  We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
+ * valid range for an IRQ (30-1020 inclusive). If CONFIG_ARM_GIC_VPPI is
+ * enabled, local interrupts are handled the same way as global ones.
  */
 
 	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
@@ -43,7 +46,7 @@
 
 	ldr	\tmp, =1021
 	bic     \irqnr, \irqstat, #0x1c00
-	cmp     \irqnr, #29
+	cmp     \irqnr, #(DO_IRQ_BASE - 1)
 	cmpcc	\irqnr, \irqnr
 	cmpne	\irqnr, \tmp
 	cmpcs	\irqnr, \irqnr
@@ -63,6 +66,7 @@
 	cmpcs	\irqnr, \irqnr
 	.endm
 
+#ifndef CONFIG_ARM_GIC_VPPI
 /* As above, this assumes that irqstat and base are preserved.. */
 
 	.macro test_for_ltirq, irqnr, irqstat, base, tmp
@@ -73,3 +77,4 @@
 	streq	\irqstat, [\base, #GIC_CPU_EOI]
 	cmp	\tmp, #0
 	.endm
+#endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0691f9d..9dbffed 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,6 +33,8 @@
 #define GIC_DIST_SOFTINT		0xf00
 
 #ifndef __ASSEMBLY__
+#include <linux/cpumask.h>
+
 extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
@@ -41,6 +43,15 @@ void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 void gic_enable_ppi(unsigned int);
+#ifdef CONFIG_ARM_GIC_VPPI
+unsigned int gic_ppi_to_vppi(unsigned int irq);
+#else
+static inline unsigned int gic_ppi_to_vppi(unsigned int irq)
+{
+	return irq;
+}
+#endif
+
 #endif
 
 #endif
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 83bbad0..237959f 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -124,8 +124,14 @@ void __init init_IRQ(void)
 #ifdef CONFIG_SPARSE_IRQ
 int __init arch_probe_nr_irqs(void)
 {
+	int initcnt;
+
 	nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
-	return nr_irqs;
+	initcnt = nr_irqs;
+#ifdef CONFIG_ARM_GIC_VPPI
+	nr_irqs += 16 * 8;	/* 16 PPIs, 8 CPUs */
+#endif
+	return initcnt;
 }
 #endif
 
-- 
1.7.0.4

[RFC PATCH v2 02/12] ARM: smp_twd: add support for remapped PPI interrupts

[Marc Zyngier]

When CONFIG_ARM_GIC_VPPI is enabled, let smp_twd request interrupts
the normal way (ie using request_irq()).

This involves letting PPIs go via the same code path as SPIs and
having normal interrupt handler for the local timer code.

The previous ad-hoc code is still supported when CONFIG_ARM_GIC_VPPI
is not defined.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/localtimer.h |    6 ++++++
 arch/arm/kernel/smp.c             |   12 ++++++++++++
 arch/arm/kernel/smp_twd.c         |   20 +++++++++++++++++++-
 3 files changed, 37 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 080d74f..bef44b3 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_LOCALTIMER_H
 #define __ASM_ARM_LOCALTIMER_H
 
+#include <linux/interrupt.h>
+
 struct clock_event_device;
 
 /*
@@ -22,6 +24,10 @@ void percpu_timer_setup(void);
  */
 asmlinkage void do_local_timer(struct pt_regs *);
 
+/*
+ * Per-cpu timer IRQ handler
+ */
+irqreturn_t percpu_timer_handler(int irq, void *dev_id);
 
 #ifdef CONFIG_LOCAL_TIMERS
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index f29b8a2..30201a0 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -452,6 +452,18 @@ asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
 	set_irq_regs(old_regs);
 }
 
+irqreturn_t percpu_timer_handler(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	if (local_timer_ack()) {
+		evt->event_handler(evt);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
 void show_local_irqs(struct seq_file *p, int prec)
 {
 	unsigned int cpu;
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 60636f4..2256360 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -15,10 +15,11 @@
 #include <linux/smp.h>
 #include <linux/jiffies.h>
 #include <linux/clockchips.h>
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
 
 #include <asm/smp_twd.h>
+#include <asm/localtimer.h>
 #include <asm/hardware/gic.h>
 
 /* set up by the platform code */
@@ -43,6 +44,10 @@ static void twd_set_mode(enum clock_event_mode mode,
 		ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
+#ifdef CONFIG_ARM_GIC_VPPI
+		free_irq(clk->irq, clk);
+		/* fall through */
+#endif
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	default:
 		ctrl = 0;
@@ -124,6 +129,8 @@ static void __cpuinit twd_calibrate_rate(void)
  */
 void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
+	int err;
+
 	twd_calibrate_rate();
 
 	clk->name = "local_timer";
@@ -137,8 +144,19 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
 	clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
 
+#ifdef CONFIG_ARM_GIC_VPPI
+	err = request_irq(clk->irq, percpu_timer_handler,
+			  IRQF_PERCPU | IRQF_NOBALANCING | IRQF_TIMER,
+			  clk->name, clk);
+	if (err) {
+		pr_err("%s: can't register interrupt %d on cpu %d (%d)\n",
+		       clk->name, clk->irq, smp_processor_id(), err);
+		return;
+	}
+#else
 	/* Make sure our local interrupt controller has this enabled */
 	gic_enable_ppi(clk->irq);
+#endif
 
 	clockevents_register_device(clk);
 }
-- 
1.7.0.4

[RFC PATCH v2 02/12] ARM: smp_twd: add support for remapped PPI interrupts

[Stephen Boyd]

On 5/6/2011 3:33 AM, Marc Zyngier wrote:
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index f29b8a2..30201a0 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -452,6 +452,18 @@ asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
>  	set_irq_regs(old_regs);
>  }
>  
> +irqreturn_t percpu_timer_handler(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = dev_id;
> +
> +	if (local_timer_ack()) {
> +		evt->event_handler(evt);
> +		return IRQ_HANDLED;
> +	}
> +
> +	return IRQ_NONE;
> +}
> +

MSM needs this second patch again. I suppose it's not titled correctly?
I'd rather not have MSM use this function at all though. Perhaps its
better to just hide this in smp_twd.c along with local_timer_ack()?

What is going on with mach-exynos4/mct.c? Their local_timer_ack() is a
return 0 and they do a setup_irq() in their local_timer_setup() path.
That all seems very broken and I would be surprised if hotplug and local
timer stats worked on that system.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH v2 02/12] ARM: smp_twd: add support for remapped PPI interrupts

[Marc Zyngier]

On Thu, 2011-05-12 at 10:59 -0700, Stephen Boyd wrote:
> On 5/6/2011 3:33 AM, Marc Zyngier wrote:
> > diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> > index f29b8a2..30201a0 100644
> > --- a/arch/arm/kernel/smp.c
> > +++ b/arch/arm/kernel/smp.c
> > @@ -452,6 +452,18 @@ asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
> >  	set_irq_regs(old_regs);
> >  }
> >  
> > +irqreturn_t percpu_timer_handler(int irq, void *dev_id)
> > +{
> > +	struct clock_event_device *evt = dev_id;
> > +
> > +	if (local_timer_ack()) {
> > +		evt->event_handler(evt);
> > +		return IRQ_HANDLED;
> > +	}
> > +
> > +	return IRQ_NONE;
> > +}
> > +
> 
> MSM needs this second patch again. I suppose it's not titled correctly?
> I'd rather not have MSM use this function at all though. Perhaps its
> better to just hide this in smp_twd.c along with local_timer_ack()?

I'd like to keep the handler in a separate file, as I have an additional
patch set for the A15 timers that are using the same handler.

> What is going on with mach-exynos4/mct.c? Their local_timer_ack() is a
> return 0 and they do a setup_irq() in their local_timer_setup() path.
> That all seems very broken and I would be surprised if hotplug and local
> timer stats worked on that system.

MCT is an odd case. They're using SPI, not PPI, and local_timer_ack() is
only present to please the linker (never called).

Could probably have them to converge as well.

	M.
-- 
Reality is an implementation detail.
-- 
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[RFC PATCH v2 03/12] ARM: omap4: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Tested on a Pandaboard.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-omap2/Kconfig                    |    1 +
 arch/arm/mach-omap2/include/mach/entry-macro.S |   14 +-------------
 arch/arm/mach-omap2/timer-mpu.c                |    3 ++-
 3 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b997a35..8282921 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select LOCAL_TIMERS if SMP
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index a48690b..22d86ef 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -78,7 +78,7 @@
 4401:		ldr     \irqstat, [\base, #GIC_CPU_INTACK]
 		ldr     \tmp, =1021
 		bic     \irqnr, \irqstat, #0x1c00
-		cmp     \irqnr, #29
+		cmp     \irqnr, #15
 		cmpcc   \irqnr, \irqnr
 		cmpne   \irqnr, \tmp
 		cmpcs   \irqnr, \irqnr
@@ -101,18 +101,6 @@
 		it	cs
 		cmpcs	\irqnr, \irqnr
 		.endm
-
-		/* As above, this assumes that irqstat and base are preserved */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov 	\tmp, #0
-		cmp	\irqnr, #29
-		itt	eq
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
 #endif	/* CONFIG_SMP */
 
 #else	/* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index 31c0ac4..1fd5ca5 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -22,6 +22,7 @@
 #include <asm/irq.h>
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 
 /*
  * Setup the local clock events for a CPU.
@@ -32,7 +33,7 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 	if (omap_rev() == OMAP4430_REV_ES1_0)
 		return -ENXIO;
 
-	evt->irq = OMAP44XX_IRQ_LOCALTIMER;
+	evt->irq = gic_ppi_to_vppi(OMAP44XX_IRQ_LOCALTIMER);
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.0.4

[RFC PATCH v2 04/12] ARM: versatile: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Tested on VExpress and PB-11MP.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-realview/Kconfig       |    2 ++
 arch/arm/mach-vexpress/Kconfig       |    1 +
 arch/arm/plat-versatile/localtimer.c |    3 ++-
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index b9a9805..12c7c56 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -38,6 +38,7 @@ config MACH_REALVIEW_PB11MP
 	bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
 	select CPU_V6K
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select HAVE_PATA_PLATFORM
 	select ARCH_HAS_BARRIERS if SMP
 	help
@@ -76,6 +77,7 @@ config MACH_REALVIEW_PBA8
 config MACH_REALVIEW_PBX
 	bool "Support RealView(R) Platform Baseboard Explore"
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 9311484..07a53aa 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,6 +5,7 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970
diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
index 0fb3961..a76daf4 100644
--- a/arch/arm/plat-versatile/localtimer.c
+++ b/arch/arm/plat-versatile/localtimer.c
@@ -14,6 +14,7 @@
 
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 #include <mach/irqs.h>
 
 /*
@@ -21,7 +22,7 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = IRQ_LOCALTIMER;
+	evt->irq = gic_ppi_to_vppi(IRQ_LOCALTIMER);
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.0.4

[RFC PATCH v2 05/12] ARM: shmobile: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-shmobile/Kconfig                    |    1 +
 arch/arm/mach-shmobile/entry-intc.S               |    3 ---
 arch/arm/mach-shmobile/include/mach/entry-macro.S |    3 ---
 arch/arm/mach-shmobile/localtimer.c               |    3 ++-
 4 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0c8f6cf..ddcf28c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -26,6 +26,7 @@ config ARCH_SH73A0
 	select SH_CLK_CPG
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
+	select ARM_GIC_VPPI
 
 comment "SH-Mobile Board Type"
 
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
index cac0a7a..1a1c00c 100644
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ b/arch/arm/mach-shmobile/entry-intc.S
@@ -51,7 +51,4 @@
 	.macro  test_for_ipi, irqnr, irqstat, base, tmp
 	.endm
 
-	.macro  test_for_ltirq, irqnr, irqstat, base, tmp
-	.endm
-
 	arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index d791f10..8d4a416 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -27,8 +27,5 @@
 	.macro  test_for_ipi, irqnr, irqstat, base, tmp
 	.endm
 
-	.macro  test_for_ltirq, irqnr, irqstat, base, tmp
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
index ad9ccc9..8a67b1c 100644
--- a/arch/arm/mach-shmobile/localtimer.c
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -14,13 +14,14 @@
 #include <linux/clockchips.h>
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 
 /*
  * Setup the local clock events for a CPU.
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = 29;
+	evt->irq = gic_ppi_to_vppi(29);
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.0.4

[RFC PATCH v2 06/12] ARM: ux500: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-ux500/Kconfig      |    1 +
 arch/arm/mach-ux500/localtimer.c |    3 ++-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5862601..6f3eb99 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -4,6 +4,7 @@ config UX500_SOC_COMMON
 	bool
 	default y
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select HAS_MTU
 	select NOMADIK_GPIO
 	select ARM_ERRATA_753970
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
index 5ba1133..f027cef 100644
--- a/arch/arm/mach-ux500/localtimer.c
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -17,13 +17,14 @@
 #include <asm/irq.h>
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 
 /*
  * Setup the local clock events for a CPU.
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = IRQ_LOCALTIMER;
+	evt->irq = gic_ppi_to_vppi(IRQ_LOCALTIMER);
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.0.4

[RFC PATCH v2 07/12] ARM: tegra: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Cc: Colin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-tegra/Kconfig      |    1 +
 arch/arm/mach-tegra/localtimer.c |    3 ++-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 3cdeffc..67f478b 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -9,6 +9,7 @@ config ARCH_TEGRA_2x_SOC
 	bool "Tegra 2 family"
 	select CPU_V7
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select ARCH_REQUIRE_GPIOLIB
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
index e91d681..97cd0a9 100644
--- a/arch/arm/mach-tegra/localtimer.c
+++ b/arch/arm/mach-tegra/localtimer.c
@@ -14,13 +14,14 @@
 #include <asm/irq.h>
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 
 /*
  * Setup the local clock events for a CPU.
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = IRQ_LOCALTIMER;
+	evt->irq = gic_ppi_to_vppi(IRQ_LOCALTIMER);
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.0.4

[RFC PATCH v2 08/12] ARM: msm: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

MSM already had a very similar scheme, though still mixing both
GIC-specific and generic APIs.

Fixes and ideas courtesy of Stephen Boyd.

Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-msm/Kconfig                         |    2 +
 arch/arm/mach-msm/board-msm8x60.c                 |   11 ---
 arch/arm/mach-msm/include/mach/entry-macro-qgic.S |   73 +--------------------
 arch/arm/mach-msm/timer.c                         |   62 ++++++++----------
 4 files changed, 30 insertions(+), 118 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1516896..1ea7d6f 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -42,6 +42,7 @@ config ARCH_MSM8X60
 				  && !MACH_MSM8X60_FFA)
 	select ARCH_MSM_SCORPIONMP
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select CPU_V7
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
@@ -52,6 +53,7 @@ config ARCH_MSM8960
 	select ARCH_MSM_SCORPIONMP
 	select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
 	select ARM_GIC
+	select ARM_GIC_VPPI
 	select CPU_V7
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 1163b6f..d70a2f6 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -36,8 +36,6 @@ static void __init msm8x60_map_io(void)
 
 static void __init msm8x60_init_irq(void)
 {
-	unsigned int i;
-
 	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
 		 (void *)MSM_QGIC_CPU_BASE);
 
@@ -49,15 +47,6 @@ static void __init msm8x60_init_irq(void)
 	 */
 	if (!machine_is_msm8x60_sim())
 		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-	 * as they are configured as level, which does not play nice with
-	 * handle_percpu_irq.
-	 */
-	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-			irq_set_handler(i, handle_percpu_irq);
-	}
 }
 
 static void __init msm8x60_init(void)
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
index 1246715..717076f 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -8,81 +8,10 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
 	.macro	disable_fiq
 	.endm
 
-	.macro  get_irqnr_preamble, base, tmp
-	ldr	\base, =gic_cpu_base_addr
-	ldr	\base, [\base]
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
-
-	/*
-	 * The interrupt numbering scheme is defined in the
-	 * interrupt controller spec.  To wit:
-	 *
-	 * Migrated the code from ARM MP port to be more consistent
-	 * with interrupt processing , the following still holds true
-	 * however, all interrupts are treated the same regardless of
-	 * if they are local IPI or PPI
-	 *
-	 * Interrupts 0-15 are IPI
-	 * 16-31 are PPI
-	 *   (16-18 are the timers)
-	 * 32-1020 are global
-	 * 1021-1022 are reserved
-	 * 1023 is "spurious" (no interrupt)
-	 *
-	 * A simple read from the controller will tell us the number of the
-	 * highest priority enabled interrupt.  We then just need to check
-	 * whether it is in the valid range for an IRQ (0-1020 inclusive).
-	 *
-	 * Base ARM code assumes that the local (private) peripheral interrupts
-	 * are not valid, we treat them differently, in that the privates are
-	 * handled like normal shared interrupts with the exception that only
-	 * one processor can register the interrupt and the handler must be
-	 * the same for all processors.
-	 */
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-	ldr  \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
-						   9-0 =int # */
-
-	bic     \irqnr, \irqstat, #0x1c00	@mask src
-	cmp     \irqnr, #15
-	ldr		\tmp, =1021
-	cmpcc	\irqnr, \irqnr
-	cmpne	\irqnr, \tmp
-	cmpcs	\irqnr, \irqnr
-
-	.endm
-
-	/* We assume that irqstat (the raw value of the IRQ acknowledge
-	 * register) is preserved from the macro above.
-	 * If there is an IPI, we immediately signal end of interrupt on the
-	 * controller, since this requires the original irqstat value which
-	 * we won't easily be able to recreate later.
-	 */
-	.macro test_for_ipi, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    cmp \irqnr, #16
-    strcc   \irqstat, [\base, #GIC_CPU_EOI]
-    cmpcs   \irqnr, \irqnr
-	.endm
-
-	/* As above, this assumes that irqstat and base are preserved.. */
-
-	.macro test_for_ltirq, irqnr, irqstat, base, tmp
-    bic \irqnr, \irqstat, #0x1c00
-    mov     \tmp, #0
-    cmp \irqnr, #16
-    moveq   \tmp, #1
-    streq   \irqstat, [\base, #GIC_CPU_EOI]
-    cmp \tmp, #0
-	.endm
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 38b95e9..f063860 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -22,7 +22,9 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
+#include <asm/localtimer.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <mach/msm_iomap.h>
 #include <mach/cpu.h>
 
@@ -67,7 +69,7 @@ enum timer_location {
 struct msm_clock {
 	struct clock_event_device   clockevent;
 	struct clocksource          clocksource;
-	struct irqaction            irq;
+	unsigned int		    irq;
 	void __iomem                *regbase;
 	uint32_t                    freq;
 	uint32_t                    shift;
@@ -83,18 +85,7 @@ enum {
 
 
 static struct msm_clock msm_clocks[];
-static struct clock_event_device *local_clock_event;
-
-static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *evt = dev_id;
-	if (smp_processor_id() != 0)
-		evt = local_clock_event;
-	if (evt->event_handler == NULL)
-		return IRQ_HANDLED;
-	evt->event_handler(evt);
-	return IRQ_HANDLED;
-}
+static int local_timer_inited;
 
 static cycle_t msm_read_timer_count(struct clocksource *cs)
 {
@@ -140,6 +131,8 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
 		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
+		free_irq(evt->irq, evt);
+		/* fall through */
 	case CLOCK_EVT_MODE_SHUTDOWN:
 		writel(0, clock->regbase + TIMER_ENABLE);
 		break;
@@ -163,13 +156,7 @@ static struct msm_clock msm_clocks[] = {
 			.mask           = CLOCKSOURCE_MASK(32),
 			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 		},
-		.irq = {
-			.name    = "gp_timer",
-			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-			.handler = msm_timer_interrupt,
-			.dev_id  = &msm_clocks[0].clockevent,
-			.irq     = INT_GP_TIMER_EXP
-		},
+		.irq = INT_GP_TIMER_EXP,
 		.freq = GPT_HZ,
 	},
 	[MSM_CLOCK_DGT] = {
@@ -188,13 +175,7 @@ static struct msm_clock msm_clocks[] = {
 			.mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
 			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 		},
-		.irq = {
-			.name    = "dg_timer",
-			.flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
-			.handler = msm_timer_interrupt,
-			.dev_id  = &msm_clocks[1].clockevent,
-			.irq     = INT_DEBUG_TIMER_EXP
-		},
+		.irq = INT_DEBUG_TIMER_EXP,
 		.freq = DGT_HZ >> MSM_DGT_SHIFT,
 		.shift = MSM_DGT_SHIFT,
 	}
@@ -232,6 +213,7 @@ static void __init msm_timer_init(void)
 		struct msm_clock *clock = &msm_clocks[i];
 		struct clock_event_device *ce = &clock->clockevent;
 		struct clocksource *cs = &clock->clocksource;
+		int irq;
 
 		clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
 		clock->global_counter = clock->local_counter + global_offset;
@@ -253,10 +235,13 @@ static void __init msm_timer_init(void)
 			printk(KERN_ERR "msm_timer_init: clocksource_register "
 			       "failed for %s\n", cs->name);
 
-		res = setup_irq(clock->irq.irq, &clock->irq);
+		irq = gic_ppi_to_vppi(clock->irq);
+		res = request_irq(irq, percpu_timer_handler,
+				  IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
+				  ce->name, ce);
 		if (res)
-			printk(KERN_ERR "msm_timer_init: setup_irq "
-			       "failed for %s\n", cs->name);
+			pr_err("msm_timer_init: request_irq failed for %s\n",
+			       ce->name);
 
 		clockevents_register_device(ce);
 	}
@@ -266,6 +251,7 @@ static void __init msm_timer_init(void)
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
 	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+	int res;
 
 	/* Use existing clock_event for cpu 0 */
 	if (!smp_processor_id())
@@ -273,12 +259,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 
 	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 
-	if (!local_clock_event) {
+	if (!local_timer_inited) {
 		writel(0, clock->regbase  + TIMER_ENABLE);
 		writel(0, clock->regbase + TIMER_CLEAR);
 		writel(~0, clock->regbase + TIMER_MATCH_VAL);
+		local_timer_inited = 1;
 	}
-	evt->irq = clock->irq.irq;
+	evt->irq = gic_ppi_to_vppi(clock->irq);
 	evt->name = "local_timer";
 	evt->features = CLOCK_EVT_FEAT_ONESHOT;
 	evt->rating = clock->clockevent.rating;
@@ -290,9 +277,14 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
 		clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
 	evt->min_delta_ns = clockevent_delta2ns(4, evt);
 
-	local_clock_event = evt;
-
-	gic_enable_ppi(clock->irq.irq);
+	res = request_irq(evt->irq, percpu_timer_handler,
+			  IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
+			  clock->clockevent.name, evt);
+	if (res) {
+		pr_err("local_timer_setup: request_irq failed for %s\n",
+		       clock->clockevent.name);
+		return res;
+	}
 
 	clockevents_register_device(evt);
 	return 0;
-- 
1.7.0.4

[RFC PATCH v2 08/12] ARM: msm: use remapped PPI interrupts for local timer

[Stephen Boyd]

On 5/6/2011 3:33 AM, Marc Zyngier wrote:
> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> index 38b95e9..f063860 100644
> --- a/arch/arm/mach-msm/timer.c
> +++ b/arch/arm/mach-msm/timer.c
> @@ -83,18 +85,7 @@ enum {
>  
>  
>  static struct msm_clock msm_clocks[];
> -static struct clock_event_device *local_clock_event;
> -
> -static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
> -{
> -	struct clock_event_device *evt = dev_id;
> -	if (smp_processor_id() != 0)
> -		evt = local_clock_event;
> -	if (evt->event_handler == NULL)
> -		return IRQ_HANDLED;

We just lost this important line. This prevents spurious interrupts from
crashing the system.

> -	evt->event_handler(evt);
> -	return IRQ_HANDLED;
> -}

I would prefer to keep the whole interrupt function because 1) MSM
doesn't have a local_timer_ack() to implement and 2) I want to put code
in here to stop the timer so that the timer doesn't wrap and cause
another interrupt (yes the patches haven't been sent yet).

> +static int local_timer_inited;
>  
>  static cycle_t msm_read_timer_count(struct clocksource *cs)
>  {
> @@ -140,6 +131,8 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
>  		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
>  		break;
>  	case CLOCK_EVT_MODE_UNUSED:
> +		free_irq(evt->irq, evt);

This is crashing because evt->irq is never assigned in the case of
CPU0's timer.

> @@ -253,10 +235,13 @@ static void __init msm_timer_init(void)
>  			printk(KERN_ERR "msm_timer_init: clocksource_register "
>  			       "failed for %s\n", cs->name);
>  
> -		res = setup_irq(clock->irq.irq, &clock->irq);
> +		irq = gic_ppi_to_vppi(clock->irq);
> +		res = request_irq(irq, percpu_timer_handler,
> +				  IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
> +				  ce->name, ce);

How about assigning evt->irq to gic_ppi_to_vppi() and then use that
instead of a local variable? That would fix the free_irq() bug up above.

Also, percpu_timer_handler() is only defined in arm/kernel/smp.c which
isn't going to be compiled in on non-SMP targets. This timer driver is
common to all MSMs so it needs to work with SMP and non-SMP.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH v2 08/12] ARM: msm: use remapped PPI interrupts for local timer

[Marc Zyngier]

On Thu, 2011-05-12 at 13:23 -0700, Stephen Boyd wrote:
> On 5/6/2011 3:33 AM, Marc Zyngier wrote:
> > diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> > index 38b95e9..f063860 100644
> > --- a/arch/arm/mach-msm/timer.c
> > +++ b/arch/arm/mach-msm/timer.c
> > @@ -83,18 +85,7 @@ enum {
> >  
> >  
> >  static struct msm_clock msm_clocks[];
> > -static struct clock_event_device *local_clock_event;
> > -
> > -static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
> > -{
> > -	struct clock_event_device *evt = dev_id;
> > -	if (smp_processor_id() != 0)
> > -		evt = local_clock_event;
> > -	if (evt->event_handler == NULL)
> > -		return IRQ_HANDLED;
> 
> We just lost this important line. This prevents spurious interrupts from
> crashing the system.

Is this something you actually see on a real system, or just a guard in
case something goes horribly wrong?

> > -	evt->event_handler(evt);
> > -	return IRQ_HANDLED;
> > -}
> 
> I would prefer to keep the whole interrupt function because 1) MSM
> doesn't have a local_timer_ack() to implement and 2) I want to put code
> in here to stop the timer so that the timer doesn't wrap and cause
> another interrupt (yes the patches haven't been sent yet).

I was thinking of reusing the local_timer_ack() for that, possibly
passing some useful parameters (evt, cpu...). I'd really like the
event_handler() call to become common code, and move everything else to
the local_timer_ack() method (with a possible empty default implemented
as a weak symbol).

> > +static int local_timer_inited;
> >  
> >  static cycle_t msm_read_timer_count(struct clocksource *cs)
> >  {
> > @@ -140,6 +131,8 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
> >  		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
> >  		break;
> >  	case CLOCK_EVT_MODE_UNUSED:
> > +		free_irq(evt->irq, evt);
> 
> This is crashing because evt->irq is never assigned in the case of
> CPU0's timer.
> 
> > @@ -253,10 +235,13 @@ static void __init msm_timer_init(void)
> >  			printk(KERN_ERR "msm_timer_init: clocksource_register "
> >  			       "failed for %s\n", cs->name);
> >  
> > -		res = setup_irq(clock->irq.irq, &clock->irq);
> > +		irq = gic_ppi_to_vppi(clock->irq);
> > +		res = request_irq(irq, percpu_timer_handler,
> > +				  IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
> > +				  ce->name, ce);
> 
> How about assigning evt->irq to gic_ppi_to_vppi() and then use that
> instead of a local variable? That would fix the free_irq() bug up above.

Indeed. Fixed.

> Also, percpu_timer_handler() is only defined in arm/kernel/smp.c which
> isn't going to be compiled in on non-SMP targets. This timer driver is
> common to all MSMs so it needs to work with SMP and non-SMP.

My plan is to move most (if not all) of the timer stuff out of smp.c, as
A15 has the same requirements as MSM (local timers are used even on
non-smp configurations). I'll introduce that earlier than expected,
then.

Expect a v3 shortly...

Thanks for reviewing,

	M.
-- 
Reality is an implementation detail.

[RFC PATCH v2 08/12] ARM: msm: use remapped PPI interrupts for local timer

[Stephen Boyd]

On 05/19/2011 03:15 AM, Marc Zyngier wrote:
> On Thu, 2011-05-12 at 13:23 -0700, Stephen Boyd wrote:
>> On 5/6/2011 3:33 AM, Marc Zyngier wrote:
>>> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
>>> index 38b95e9..f063860 100644
>>> --- a/arch/arm/mach-msm/timer.c
>>> +++ b/arch/arm/mach-msm/timer.c
>>> @@ -83,18 +85,7 @@ enum {
>>>  
>>>  
>>>  static struct msm_clock msm_clocks[];
>>> -static struct clock_event_device *local_clock_event;
>>> -
>>> -static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
>>> -{
>>> -	struct clock_event_device *evt = dev_id;
>>> -	if (smp_processor_id() != 0)
>>> -		evt = local_clock_event;
>>> -	if (evt->event_handler == NULL)
>>> -		return IRQ_HANDLED;
>> We just lost this important line. This prevents spurious interrupts from
>> crashing the system.
> Is this something you actually see on a real system, or just a guard in
> case something goes horribly wrong?
>

I believe a bootloader left a pending interrupt at some point and thus
when we request the interrupt before registering the clockevent the
interrupt handler will be called and evt->event_handler == NULL. Perhaps
we could register the clockevent before registering the interrupt
handler? I'm not sure that works. Otherwise we need to clear the
interrupt in the GIC or something. Any suggestions?

If it's any consolation, x86 seems to do the same thing presumably for
the same reason.

>>> -	evt->event_handler(evt);
>>> -	return IRQ_HANDLED;
>>> -}
>> I would prefer to keep the whole interrupt function because 1) MSM
>> doesn't have a local_timer_ack() to implement and 2) I want to put code
>> in here to stop the timer so that the timer doesn't wrap and cause
>> another interrupt (yes the patches haven't been sent yet).
> I was thinking of reusing the local_timer_ack() for that, possibly
> passing some useful parameters (evt, cpu...). I'd really like the
> event_handler() call to become common code, and move everything else to
> the local_timer_ack() method (with a possible empty default implemented
> as a weak symbol).
>

Ok. So you're saying there is one interrupt handler that will call down
to the hardware specific handler via local_timer_ack()? That sounds like
one step backwards when you consider we want to compile many machines
into one kernel.

A generic interrupt handler for simple timers where there is nothing to
do besides call the event handler is probably good consolidation. But if
the hardware requires something else, it doesn't seem so bad to write
your own.

What's the use of local_timer_ack() in the scheme of this patch series
again? I was really hoping that function would go away.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[RFC PATCH v2 08/12] ARM: msm: use remapped PPI interrupts for local timer

[Marc Zyngier]

On Tue, 2011-05-24 at 12:31 -0700, Stephen Boyd wrote:
> On 05/19/2011 03:15 AM, Marc Zyngier wrote:
> > On Thu, 2011-05-12 at 13:23 -0700, Stephen Boyd wrote:
> >> On 5/6/2011 3:33 AM, Marc Zyngier wrote:
> >>> diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
> >>> index 38b95e9..f063860 100644
> >>> --- a/arch/arm/mach-msm/timer.c
> >>> +++ b/arch/arm/mach-msm/timer.c
> >>> @@ -83,18 +85,7 @@ enum {
> >>>  
> >>>  
> >>>  static struct msm_clock msm_clocks[];
> >>> -static struct clock_event_device *local_clock_event;
> >>> -
> >>> -static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
> >>> -{
> >>> -	struct clock_event_device *evt = dev_id;
> >>> -	if (smp_processor_id() != 0)
> >>> -		evt = local_clock_event;
> >>> -	if (evt->event_handler == NULL)
> >>> -		return IRQ_HANDLED;
> >> We just lost this important line. This prevents spurious interrupts from
> >> crashing the system.
> > Is this something you actually see on a real system, or just a guard in
> > case something goes horribly wrong?
> >
> 
> I believe a bootloader left a pending interrupt at some point and thus
> when we request the interrupt before registering the clockevent the
> interrupt handler will be called and evt->event_handler == NULL. Perhaps
> we could register the clockevent before registering the interrupt
> handler? I'm not sure that works. Otherwise we need to clear the
> interrupt in the GIC or something. Any suggestions?

The generic code could install a dummy event_handler before calling into
the platform code. That way, no need to test for this on the hot path.

> If it's any consolation, x86 seems to do the same thing presumably for
> the same reason.

Oh well... ;-)

> >>> -	evt->event_handler(evt);
> >>> -	return IRQ_HANDLED;
> >>> -}
> >> I would prefer to keep the whole interrupt function because 1) MSM
> >> doesn't have a local_timer_ack() to implement and 2) I want to put code
> >> in here to stop the timer so that the timer doesn't wrap and cause
> >> another interrupt (yes the patches haven't been sent yet).
> > I was thinking of reusing the local_timer_ack() for that, possibly
> > passing some useful parameters (evt, cpu...). I'd really like the
> > event_handler() call to become common code, and move everything else to
> > the local_timer_ack() method (with a possible empty default implemented
> > as a weak symbol).
> >
> 
> Ok. So you're saying there is one interrupt handler that will call down
> to the hardware specific handler via local_timer_ack()? That sounds like
> one step backwards when you consider we want to compile many machines
> into one kernel.

That would only be an interim hack. I proposed a solution for that a
while ago, as part of my A15 timer series:
http://www.spinics.net/lists/arm-kernel/msg118579.html

Basically, you register a set of function pointers with the core timer
code, local_timer_ack() being one of them. If you do not provide one,
even better.

That gives you a way to register your timer at runtime (I have the same
binary kernel running on A5 using TWD and A15 using the architected
timers).

> A generic interrupt handler for simple timers where there is nothing to
> do besides call the event handler is probably good consolidation. But if
> the hardware requires something else, it doesn't seem so bad to write
> your own.
> 
> What's the use of local_timer_ack() in the scheme of this patch series
> again? I was really hoping that function would go away.

Maybe this is a bit out of the scope of this patch series, actually.
I'll drop this change, and will create another series only impacting
local_ack()/interrupt handler.

Cheers,

	M.
-- 
Reality is an implementation detail.

[RFC PATCH v2 09/12] ARM: exynos4: use remapped PPI interrupts for local timer

[Marc Zyngier]

Use the normal interrupt scheme for the local timers by using
a remapped PPI interrupt.

Tested on a SMDK-S5PV310 board.

Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |   12 +-----------
 arch/arm/mach-exynos4/localtimer.c               |    3 ++-
 arch/arm/plat-s5p/Kconfig                        |    1 +
 3 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2..f007168 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -50,7 +50,7 @@
 
 		bic     \irqnr, \irqstat, #0x1c00
 
-		cmp     \irqnr, #29
+		cmp     \irqnr, #15
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
@@ -72,13 +72,3 @@
 		cmpcs	\irqnr, \irqnr
 		.endm
 
-		/* As above, this assumes that irqstat and base are preserved.. */
-
-		.macro test_for_ltirq, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		mov	\tmp, #0
-		cmp	\irqnr, #29
-		moveq	\tmp, #1
-		streq	\irqstat, [\base, #GIC_CPU_EOI]
-		cmp	\tmp, #0
-		.endm
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
index 6bf3d0a..315de6f 100644
--- a/arch/arm/mach-exynos4/localtimer.c
+++ b/arch/arm/mach-exynos4/localtimer.c
@@ -14,13 +14,14 @@
 
 #include <asm/irq.h>
 #include <asm/localtimer.h>
+#include <asm/hardware/gic.h>
 
 /*
  * Setup the local clock events for a CPU.
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = IRQ_LOCALTIMER;
+	evt->irq = gic_ppi_to_vppi(IRQ_LOCALTIMER);
 	twd_timer_setup(evt);
 	return 0;
 }
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8492297..1ee4a1a 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -11,6 +11,7 @@ config PLAT_S5P
 	default y
 	select ARM_VIC if !ARCH_EXYNOS4
 	select ARM_GIC if ARCH_EXYNOS4
+	select ARM_GIC_VPPI if ARCH_EXYNOS4
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select S3C_GPIO_TRACK
-- 
1.7.0.4

[RFC PATCH v2 10/12] ARM: gic: remove previous local timer interrupt handling

[Marc Zyngier]

Now that all users of local timers are using CONFIG_ARM_GIC_VPPI,
the now unused local timer infrastructure can be safely removed.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/common/gic.c                           |   10 --------
 arch/arm/include/asm/entry-macro-multi.S        |    7 -----
 arch/arm/include/asm/hardirq.h                  |    3 --
 arch/arm/include/asm/hardware/entry-macro-gic.S |   13 ----------
 arch/arm/include/asm/hardware/gic.h             |    1 -
 arch/arm/include/asm/localtimer.h               |    5 ----
 arch/arm/include/asm/smp.h                      |    5 ----
 arch/arm/kernel/irq.c                           |    3 --
 arch/arm/kernel/smp.c                           |   29 -----------------------
 arch/arm/kernel/smp_twd.c                       |    7 -----
 10 files changed, 0 insertions(+), 83 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 529a8ed..d39a164 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -501,16 +501,6 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)
 	gic_cpu_init(&gic_data[gic_nr]);
 }
 
-void __cpuinit gic_enable_ppi(unsigned int irq)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	irq_set_status_flags(irq, IRQ_NOPROBE);
-	gic_unmask_irq(irq_get_irq_data(irq));
-	local_irq_restore(flags);
-}
-
 #ifdef CONFIG_SMP
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index c599795..4ef27af 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -23,13 +23,6 @@
 	movne	r1, sp
 	adrne	lr, BSYM(1b)
 	bne	do_IPI
-
-#if defined(CONFIG_LOCAL_TIMERS) && !defined(CONFIG_ARM_GIC_VPPI)
-	test_for_ltirq r0, r6, r5, lr
-	movne	r0, sp
-	adrne	lr, BSYM(1b)
-	bne	do_local_timer
-#endif
 #endif
 9997:
 	.endm
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad180..ddf07a9 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -9,9 +9,6 @@
 
 typedef struct {
 	unsigned int __softirq_pending;
-#ifdef CONFIG_LOCAL_TIMERS
-	unsigned int local_timer_irqs;
-#endif
 #ifdef CONFIG_SMP
 	unsigned int ipi_irqs[NR_IPI];
 #endif
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index 14a3363..db83287 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -65,16 +65,3 @@
 	strcc	\irqstat, [\base, #GIC_CPU_EOI]
 	cmpcs	\irqnr, \irqnr
 	.endm
-
-#ifndef CONFIG_ARM_GIC_VPPI
-/* As above, this assumes that irqstat and base are preserved.. */
-
-	.macro test_for_ltirq, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	mov 	\tmp, #0
-	cmp	\irqnr, #29
-	moveq	\tmp, #1
-	streq	\irqstat, [\base, #GIC_CPU_EOI]
-	cmp	\tmp, #0
-	.endm
-#endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 9dbffed..069d4c0 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -42,7 +42,6 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-void gic_enable_ppi(unsigned int);
 #ifdef CONFIG_ARM_GIC_VPPI
 unsigned int gic_ppi_to_vppi(unsigned int irq);
 #else
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index bef44b3..5c8acb4 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -20,11 +20,6 @@ struct clock_event_device;
 void percpu_timer_setup(void);
 
 /*
- * Called from assembly, this is the local timer IRQ handler
- */
-asmlinkage void do_local_timer(struct pt_regs *);
-
-/*
  * Per-cpu timer IRQ handler
  */
 irqreturn_t percpu_timer_handler(int irq, void *dev_id);
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 96ed521..6cf609c 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -95,9 +95,4 @@ extern void platform_cpu_enable(unsigned int cpu);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
-/*
- * show local interrupt info
- */
-extern void show_local_irqs(struct seq_file *, int);
-
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 237959f..9f3e427 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -59,9 +59,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 #ifdef CONFIG_SMP
 	show_ipi_list(p, prec);
 #endif
-#ifdef CONFIG_LOCAL_TIMERS
-	show_local_irqs(p, prec);
-#endif
 	seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
 	return 0;
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 30201a0..84bc221 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -418,10 +418,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
 	for (i = 0; i < NR_IPI; i++)
 		sum += __get_irq_stat(cpu, ipi_irqs[i]);
 
-#ifdef CONFIG_LOCAL_TIMERS
-	sum += __get_irq_stat(cpu, local_timer_irqs);
-#endif
-
 	return sum;
 }
 
@@ -439,19 +435,6 @@ static void ipi_timer(void)
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
-asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
-{
-	struct pt_regs *old_regs = set_irq_regs(regs);
-	int cpu = smp_processor_id();
-
-	if (local_timer_ack()) {
-		__inc_irq_stat(cpu, local_timer_irqs);
-		ipi_timer();
-	}
-
-	set_irq_regs(old_regs);
-}
-
 irqreturn_t percpu_timer_handler(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = dev_id;
@@ -463,18 +446,6 @@ irqreturn_t percpu_timer_handler(int irq, void *dev_id)
 
 	return IRQ_NONE;
 }
-
-void show_local_irqs(struct seq_file *p, int prec)
-{
-	unsigned int cpu;
-
-	seq_printf(p, "%*s: ", prec, "LOC");
-
-	for_each_present_cpu(cpu)
-		seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
-
-	seq_printf(p, " Local timer interrupts\n");
-}
 #endif
 
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 2256360..72ae9e3 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -44,10 +44,8 @@ static void twd_set_mode(enum clock_event_mode mode,
 		ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
-#ifdef CONFIG_ARM_GIC_VPPI
 		free_irq(clk->irq, clk);
 		/* fall through */
-#endif
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	default:
 		ctrl = 0;
@@ -144,7 +142,6 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 	clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
 	clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
 
-#ifdef CONFIG_ARM_GIC_VPPI
 	err = request_irq(clk->irq, percpu_timer_handler,
 			  IRQF_PERCPU | IRQF_NOBALANCING | IRQF_TIMER,
 			  clk->name, clk);
@@ -153,10 +150,6 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 		       clk->name, clk->irq, smp_processor_id(), err);
 		return;
 	}
-#else
-	/* Make sure our local interrupt controller has this enabled */
-	gic_enable_ppi(clk->irq);
-#endif
 
 	clockevents_register_device(clk);
 }
-- 
1.7.0.4

[RFC PATCH v2 11/12] ARM: gic: add compute_irqnr macro for exynos4

[Marc Zyngier]

exynos4 has a full copy of entry-macro-gic.S, just for the sake
of an offset added to the IRQ number read from the GIC.

Add a compute_irqnr macro to entry-macro-gic.S so that any platform
can add it's own hook without having to copy the whole file again.

Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/include/asm/hardware/entry-macro-gic.S  |    3 +
 arch/arm/mach-exynos4/include/mach/entry-macro.S |   60 ++--------------------
 2 files changed, 8 insertions(+), 55 deletions(-)

diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index db83287..a01dc80 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -50,6 +50,9 @@
 	cmpcc	\irqnr, \irqnr
 	cmpne	\irqnr, \tmp
 	cmpcs	\irqnr, \irqnr
+#ifdef HAVE_GIC_BASE_OFFSET
+	compute_irqnr	\irqnr, \tmp
+#endif
 	.endm
 
 /* We assume that irqstat (the raw value of the IRQ acknowledge
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index f007168..7d87d4e 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -9,66 +9,16 @@
  * warranty of any kind, whether express or implied.
 */
 
-#include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#define HAVE_GIC_BASE_OFFSET	1
+#include <asm/hardware/entry-macro-gic.S>
 
-		.macro	disable_fiq
+		.macro	compute_irqnr, irqnr, tmp
+		addne	\irqnr, #32
 		.endm
 
-		.macro  get_irqnr_preamble, base, tmp
-		ldr	\base, =gic_cpu_base_addr
-		ldr	\base, [\base]
+		.macro	disable_fiq
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
 
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an interrupt if it's
-		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-		 *
-		 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-		 * valid range for an IRQ (30-1020 inclusive).
-		 */
-
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-		ldr	\tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #15
-		cmpcc	\irqnr, \irqnr
-		cmpne	\irqnr, \tmp
-		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
-
-		.endm
-
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt on the
-		 * controller, since this requires the original irqstat value which
-		 * we won't easily be able to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		cmpcs	\irqnr, \irqnr
-		.endm
-
-- 
1.7.0.4

[RFC PATCH v2 12/12] ARM: SMP: automatically select ARM_GIC_VPPI

[Marc Zyngier]

All SMP platforms are selecting ARM_GIC_VPPI.
Instead, make SMP select ARM_GIC_VPPI and remove select statements
from the platform code.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig               |    1 +
 arch/arm/mach-msm/Kconfig      |    2 --
 arch/arm/mach-omap2/Kconfig    |    1 -
 arch/arm/mach-realview/Kconfig |    2 --
 arch/arm/mach-shmobile/Kconfig |    1 -
 arch/arm/mach-tegra/Kconfig    |    1 -
 arch/arm/mach-ux500/Kconfig    |    1 -
 arch/arm/mach-vexpress/Kconfig |    1 -
 arch/arm/plat-s5p/Kconfig      |    1 -
 9 files changed, 1 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a5..f58303f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1327,6 +1327,7 @@ config SMP
 		 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
 		 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
 	select USE_GENERIC_SMP_HELPERS
+	select ARM_GIC_VPPI
 	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
 	help
 	  This enables support for systems with more than one CPU. If you have
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1ea7d6f..1516896 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -42,7 +42,6 @@ config ARCH_MSM8X60
 				  && !MACH_MSM8X60_FFA)
 	select ARCH_MSM_SCORPIONMP
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select CPU_V7
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
@@ -53,7 +52,6 @@ config ARCH_MSM8960
 	select ARCH_MSM_SCORPIONMP
 	select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select CPU_V7
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8282921..b997a35 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,7 +44,6 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select LOCAL_TIMERS if SMP
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 12c7c56..b9a9805 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -38,7 +38,6 @@ config MACH_REALVIEW_PB11MP
 	bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
 	select CPU_V6K
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select HAVE_PATA_PLATFORM
 	select ARCH_HAS_BARRIERS if SMP
 	help
@@ -77,7 +76,6 @@ config MACH_REALVIEW_PBA8
 config MACH_REALVIEW_PBX
 	bool "Support RealView(R) Platform Baseboard Explore"
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index ddcf28c..0c8f6cf 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -26,7 +26,6 @@ config ARCH_SH73A0
 	select SH_CLK_CPG
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_GIC
-	select ARM_GIC_VPPI
 
 comment "SH-Mobile Board Type"
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 67f478b..3cdeffc 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -9,7 +9,6 @@ config ARCH_TEGRA_2x_SOC
 	bool "Tegra 2 family"
 	select CPU_V7
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select ARCH_REQUIRE_GPIOLIB
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6f3eb99..5862601 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -4,7 +4,6 @@ config UX500_SOC_COMMON
 	bool
 	default y
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select HAS_MTU
 	select NOMADIK_GPIO
 	select ARM_ERRATA_753970
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 07a53aa..9311484 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,7 +5,6 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
-	select ARM_GIC_VPPI
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 1ee4a1a..8492297 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -11,7 +11,6 @@ config PLAT_S5P
 	default y
 	select ARM_VIC if !ARCH_EXYNOS4
 	select ARM_GIC if ARCH_EXYNOS4
-	select ARM_GIC_VPPI if ARCH_EXYNOS4
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select S3C_GPIO_TRACK
-- 
1.7.0.4

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Santosh Shilimkar]

Marc,

On 5/6/2011 4:03 PM, Marc Zyngier wrote:
> The current GIC per-cpu interrupt (aka PPIs) suffers from a number of
> problems:
>
> - It uses a completely separate scheme to handle the interrupts,
>    mostly because the PPI concept doesn't really match the kernel view
>    of an interrupt.
> - Some low-level code gets duplicated, as usual...
> - At least one platform (msm) has started implementing its own
>    alternative scheme.
>
> The proposed solution is to let the GIC code expose the PPIs as
> something that the kernel can manage. Instead of having a single
> interrupt number shared on all cores, make the interrupt number be
> different on each CPU.
>
> This enables the use of the normal kernel API (request_irq() and
> friends) and the elimination of some low level code.
>
> This patch set is based on 2.6.39-rc6, and depends on Will Deacon's
> GIC fasteoi patches. Tested on VExpress, PB-11MP, Pandaboard and
> SMDK-S5PV310.
>

Looks like, this series breaks system wide supsend. Please
check.

Regards
Santosh

-------
# echo mem > /sys/power/state
[   37.503112] PM: Syncing filesystems ... done.
[   37.552032] Freezing user space processes ... (elapsed 0.01 seconds) 
done.
[   37.577545] Freezing remaining freezable tasks ... (elapsed 0.02 
seconds) done.
[   37.616210] PM: suspend of devices complete after 5.187 msecs
[   37.623657] PM: late suspend of devices complete after 1.403 msecs
[   37.630187] Disabling non-boot CPUs ...
[   37.731964] CPU1: shutdown
[   38.285888] Enabling non-boot CPUs ...
[   38.291137] CPU1: Booted secondary processor
[   38.291168] CPU1: Unknown IPI message 0x1
[   38.291168] local_timer: can't register interrupt 413 on cpu 1 (-16)
[   38.365112] Unable to handle kernel NULL pointer dereference at 
virtual address 0000004c
[   38.388946] pgd = c0004000
[   38.391784] [0000004c] *pgd=00000000
[   38.395538] Internal error: Oops: 805 [#1] SMP
[   38.400207] last sysfs file: /sys/devices/virtual/vc/vcsa63/dev
[   38.406433] Modules linked in:
[   38.409637] CPU: 1    Not tainted  (2.6.39-rc5-00099-g9e06a0a #6)
[   38.416046] PC is at clockevents_program_event+0x60/0xd4
[   38.421630] LR is at tick_dev_program_event+0x38/0x140
[   38.427032] pc : [<c00bc270>]    lr : [<c00bd730>]    psr: 60000193
[   38.427032] sp : ef885f78  ip : 00000008  fp : 00000000
[   38.439086] r10: 00000000  r9 : 00000008  r8 : cebb6148
[   38.444580] r7 : 00000000  r6 : 0076bbcd  r5 : 00000000  r4 : 00000000
[   38.451446] r3 : 00000008  r2 : cebb6148  r1 : 00000000  r0 : cebb6148
[   38.458282] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM 
Segment kernel
[   38.466064] Control: 10c53c7d  Table: 8000404a  DAC: 00000017
[   38.472076] Process swapper (pid: 0, stack limit = 0xef8842f8)
[   38.478210] Stack: (0xef885f78 to 0xef886000)
[   38.482788] 5f60: 
    00000000 00000000
[   38.491394] 5f80: 00000001 c00bd730 ce44a57b 00000008 ce44a57b 
00000008 cebb6148 00000008
[   38.499969] 5fa0: ce442e45 00000000 411fc092 c00bd8ac 00000000 
00000008 00000000 c1164ef0
[   38.508575] 5fc0: 00000008 c00be464 00773594 00000000 ce442e45 
00000008 ef884000 0000001f
[   38.517150] 5fe0: 10c03c7d c05f8630 00000000 c005b9a4 00000001 
c006bd8c 5e3adbb2 b8403c00
[   38.525756] [<c00bc270>] (clockevents_program_event+0x60/0xd4) from 
[<c00bd730>] (tick_dev_program_event+0x38/0x140)
[   38.536804] [<c00bd730>] (tick_dev_program_event+0x38/0x140) from 
[<c00bd8ac>] (tick_program_event+0x3c/0x48)
[   38.547241] [<c00bd8ac>] (tick_program_event+0x3c/0x48) from 
[<c00be464>] (tick_nohz_restart_sched_tick+0x170/0x1b8)
[   38.558319] [<c00be464>] (tick_nohz_restart_sched_tick+0x170/0x1b8) 
from [<c005b9a4>] (cpu_idle+0xdc/0xf8)
[   38.568481] [<c005b9a4>] (cpu_idle+0xdc/0xf8) from [<c006bd8c>] 
(platform_cpu_die+0x3c/0x50)
[   38.577331] Code: e0c17007 e3560001 e2d71000 ba000018 (e584304c)
[   38.583740] ---[ end trace fd37aa01e7ce7dcd ]---
[   38.588592] Kernel panic - not syncing: Attempted to kill the idle task!
[   38.595642] CPU0: stopping
[   38.598510] [<c0060cdc>] (unwind_backtrace+0x0/0xe4) from 
[<c00502a4>] (do_IPI+0xb4/0x12c)
[   38.607208] [<c00502a4>] (do_IPI+0xb4/0x12c) from [<c03f6c9c>] 
(__irq_svc+0x3c/0x100)
[   38.615447] Exception stack(0xc058bf88 to 0xc058bfd0)
[   38.620727] bf80:                   c005b948 00000000 c058bfc0 
00000000 c058a000 c0034c0c
[   38.629333] bfa0: c0034c08 c0590ddc 80000000 411fc092 00000000 
00000000 00000000 c058bfd0
[   38.637908] bfc0: c005b948 c005b94c 60000013 ffffffff
[   38.643218] [<c03f6c9c>] (__irq_svc+0x3c/0x100) from [<c005b94c>] 
(cpu_idle+0x84/0xf8)
[   38.651550] [<c005b94c>] (cpu_idle+0x84/0xf8) from [<c000893c>] 
(start_kernel+0x298/0x2f0)
[   38.660247] [<c000893c>] (start_kernel+0x298/0x2f0) from [<8000803c>] 
(0x8000803c)

Regards
Santosh

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Marc Zyngier]

On Fri, 13 May 2011 22:36:04 +0530
Santosh Shilimkar <santosh.shilimkar@ti.com> wrote:

Hi Santosh,

> Looks like, this series breaks system wide supsend. Please
> check.
> 
> Regards
> Santosh
> 
> -------
> # echo mem > /sys/power/state
> [   37.503112] PM: Syncing filesystems ... done.
> [   37.552032] Freezing user space processes ... (elapsed 0.01 seconds) 
> done.
> [   37.577545] Freezing remaining freezable tasks ... (elapsed 0.02 
> seconds) done.
> [   37.616210] PM: suspend of devices complete after 5.187 msecs
> [   37.623657] PM: late suspend of devices complete after 1.403 msecs
> [   37.630187] Disabling non-boot CPUs ...
> [   37.731964] CPU1: shutdown
> [   38.285888] Enabling non-boot CPUs ...
> [   38.291137] CPU1: Booted secondary processor
> [   38.291168] CPU1: Unknown IPI message 0x1
> [   38.291168] local_timer: can't register interrupt 413 on cpu 1 (-16)

Blah... We obviously don't stop the timer on secondary CPUs, and then
try to request the interrupt again. I'll have a look on Monday.

Thanks for pointing this out.

	M.
-- 
I'm the slime oozin' out from your TV set...

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Marc Zyngier]

Hi Santosh,

On Fri, 2011-05-13 at 22:36 +0530, Santosh Shilimkar wrote:
> Marc,
> 
> On 5/6/2011 4:03 PM, Marc Zyngier wrote:
> > The current GIC per-cpu interrupt (aka PPIs) suffers from a number of
> > problems:
> >
> > - It uses a completely separate scheme to handle the interrupts,
> >    mostly because the PPI concept doesn't really match the kernel view
> >    of an interrupt.
> > - Some low-level code gets duplicated, as usual...
> > - At least one platform (msm) has started implementing its own
> >    alternative scheme.
> >
> > The proposed solution is to let the GIC code expose the PPIs as
> > something that the kernel can manage. Instead of having a single
> > interrupt number shared on all cores, make the interrupt number be
> > different on each CPU.
> >
> > This enables the use of the normal kernel API (request_irq() and
> > friends) and the elimination of some low level code.
> >
> > This patch set is based on 2.6.39-rc6, and depends on Will Deacon's
> > GIC fasteoi patches. Tested on VExpress, PB-11MP, Pandaboard and
> > SMDK-S5PV310.
> >
> 
> Looks like, this series breaks system wide supsend. Please
> check.

Are you sure you're testing with v2? v1 is known to be broken with
CPU_HOTPLUG, but v2 should deal with it. Here is a suspend/resume cycle
on my Panda:

root at florentine-pogen:~# echo mem>/sys/power/state 
[  136.215667] PM: Syncing filesystems ... done.
[  136.220977] PM: Preparing system for mem sleep
[  136.226989] Freezing user space processes ... (elapsed 0.02 seconds) done.
[  136.257232] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
[  136.280670] PM: Entering mem sleep
[  136.332916] usb 1-1.1: unlink qh8-0001/dfb97460 start 2 [1/0 us]
[  136.339447] usb 1-1.1: usb suspend
[  136.363861] hub 1-1:1.0: hub_suspend
[  136.367614] usb 1-1: unlink qh256-0001/dfa846e0 start 1 [1/0 us]
[  136.373992] usb 1-1: usb suspend
[  136.395111] hub 1-0:1.0: hub_suspend
[  136.398864] usb usb1: bus suspend
[  136.402343] ehci-omap ehci-omap.0: suspend root hub
[  136.408477] PM: suspend of devices complete after 123.748 msecs
[  136.414703] PM: suspend devices took 0.132 seconds
[  136.420135] PM: late suspend of devices complete after 0.427 msecs
[  136.426605] Disabling non-boot CPUs ...
[  136.528137] CPU1: shutdown
[  138.320465] Enabling non-boot CPUs ...
[  138.324737] CPU1: Booted secondary processor
[  138.324737] CPU1: Unknown IPI message 0x1
[  138.332183] Switched to NOHz mode on CPU #1
[  138.527862] CPU1 is up
[  138.543518] PM: early resume of devices complete after 0.152 msecs

[  138.793670] usb usb1: usb resume
[  138.797058] ehci-omap ehci-omap.0: resume root hub
[  138.848022] hub 1-0:1.0: hub_resume
[  138.851684] hub 1-0:1.0: port 1: status 0507 change 0000
[  138.857299] usb 1-1: usb resume
[  138.894897] ehci-omap ehci-omap.0: GetStatus port:1 status 001005 0  ACK POWER sig=se0 PE CONNECT
[  138.926147] usb 1-1: finish resume
[  138.933868] hub 1-1:1.0: hub_resume
[  138.937591] hub 1-1:1.0: port 1: status 0507 change 0000
[  138.957489] ehci-omap ehci-omap.0: reused qh dfa846e0 schedule
[  138.963592] usb 1-1: link qh256-0001/dfa846e0 start 1 [1/0 us]
[  138.972991] usb 1-1.1: usb resume
[  139.037353] usb 1-1.1: finish resume
[  139.041259] ehci-omap ehci-omap.0: reused qh dfb97460 schedule
[  139.047363] usb 1-1.1: link qh8-0001/dfb97460 start 2 [1/0 us]
[  139.053649] PM: resume of devices complete after 503.509 msecs
[  139.059936] PM: resume devices took 0.515 seconds
[  139.064880] PM: Finishing wakeup.
[  139.068359] Restarting tasks ... 
[  139.071685] hub 1-0:1.0: state 7 ports 3 chg 0000 evt 0000
[  139.072631] done.
[  139.079681] hub 1-1:1.0: state 7 ports 5 chg 0000 evt 0002
root at florentine-pogen:~# 

Seems to be just fine here...

Cheers,

	M.
-- 
Reality is an implementation detail.
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[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Santosh Shilimkar]

On 5/17/2011 7:51 PM, Marc Zyngier wrote:
> Hi Santosh,
>
> On Fri, 2011-05-13 at 22:36 +0530, Santosh Shilimkar wrote:
>> Marc,
>>
>> On 5/6/2011 4:03 PM, Marc Zyngier wrote:
>>> The current GIC per-cpu interrupt (aka PPIs) suffers from a number of
>>> problems:
>>>
>>> - It uses a completely separate scheme to handle the interrupts,
>>>     mostly because the PPI concept doesn't really match the kernel view
>>>     of an interrupt.
>>> - Some low-level code gets duplicated, as usual...
>>> - At least one platform (msm) has started implementing its own
>>>     alternative scheme.
>>>
>>> The proposed solution is to let the GIC code expose the PPIs as
>>> something that the kernel can manage. Instead of having a single
>>> interrupt number shared on all cores, make the interrupt number be
>>> different on each CPU.
>>>
>>> This enables the use of the normal kernel API (request_irq() and
>>> friends) and the elimination of some low level code.
>>>
>>> This patch set is based on 2.6.39-rc6, and depends on Will Deacon's
>>> GIC fasteoi patches. Tested on VExpress, PB-11MP, Pandaboard and
>>> SMDK-S5PV310.
>>>
>>
>> Looks like, this series breaks system wide supsend. Please
>> check.
>
> Are you sure you're testing with v2? v1 is known to be broken with
> CPU_HOTPLUG, but v2 should deal with it. Here is a suspend/resume cycle
> on my Panda:
>
May be I tried V1 then. Will try your v2 tomorrow and let you know

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Santosh Shilimkar]

Marc,

On 5/17/2011 8:02 PM, Santosh Shilimkar wrote:
> On 5/17/2011 7:51 PM, Marc Zyngier wrote:
>> Hi Santosh,
>>

[...]

>>> Looks like, this series breaks system wide supsend. Please
>>> check.
>>
>> Are you sure you're testing with v2? v1 is known to be broken with
>> CPU_HOTPLUG, but v2 should deal with it. Here is a suspend/resume cycle
>> on my Panda:
>>
> May be I tried V1 then. Will try your v2 tomorrow and let you know

V2 seems to work with suspend.

Regards
Santosh

[RFC PATCH v2 00/12] Consolidating GIC per-cpu interrupts

[Marc Zyngier]

On Wed, 2011-05-18 at 19:34 +0530, Santosh Shilimkar wrote:
> Marc,
> 
> On 5/17/2011 8:02 PM, Santosh Shilimkar wrote:
> > On 5/17/2011 7:51 PM, Marc Zyngier wrote:
> >> Hi Santosh,
> >>
> 
> [...]
> 
> >>> Looks like, this series breaks system wide supsend. Please
> >>> check.
> >>
> >> Are you sure you're testing with v2? v1 is known to be broken with
> >> CPU_HOTPLUG, but v2 should deal with it. Here is a suspend/resume cycle
> >> on my Panda:
> >>
> > May be I tried V1 then. Will try your v2 tomorrow and let you know
> 
> V2 seems to work with suspend.

Thanks a lot for testing!

	M.
-- 
Reality is an implementation detail.