[U-Boot] [PATCH v3 3/4] MX5: Introduce a function for setting the chip select size

[Stefano Babic <sbabic@denx.de>]

On 05/18/2011 10:47 PM, Fabio Estevam wrote:
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---

Hi Fabio,

> +void set_chipselect_size(int const cs_size)
> +{
> +	unsigned int reg;
> +	struct iomuxc *iomuxc_regs = (struct weim *)IOMUXC_BASE_ADDR;
> +	reg = readl(&iomuxc_regs->gpr1);
> +
> +	switch (cs_size) {
> +	case CS0_128:
> +		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
> +		reg |= 0x5;
> +		break;
> +	case CS0_64M_CS1_64M:
> +		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
> +		reg |= 0x1B;
> +		break;
> +	case CS0_64M_CS1_32M_CS2_32M:
> +		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
> +		reg |= 0x4B;
> +		break;
> +	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
> +		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
> +		reg |= 0x249;
> +		break;
> +	default:
> +		printf("Unknown chip select size\n");
> +		break;
> +	}
> +
> +	writel(reg, &iomuxc_regs->gpr1);
> +}

mmmhhh...it seems to me not complete, because not all combinations are
covered. And setting fixed values in the switch constraints us to have
very long defines, as CS0_32M_CS1_32M_CS2_32M_CS3_32M.

What about to do in another way ? In the register, there are four bits
for each chip select, and the value to be set can then easy shifted to
the right place. You could define an enum with

CS_SIZE_32M = 0,
CS_SIZE_64M,
CS_SIZE_128

and use it as size. The function could take the chipselect as parameter,
and you could set the register with something like (size | ACT_CS) <<
(CS_SHIFT * chipselect), with CS_SHIFT=3. Then all cases are covered.

Best regards,
Stefano Babic

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