[PATCH 0/8] OMAP: DSS2: misc improvements

[PATCH 0/8] OMAP: DSS2: misc improvements

[Tomi Valkeinen]

Some small DSS improvements, mostly HDMI related.

 Tomi

Tomi Valkeinen (8):
  OMAP: DSS2: DISPC: Fix minimum PCD value
  OMAP: DSS2: HDMI: use default dividers
  OMAP: DSS2: HDMI: change regn definition
  OMAP: DSS2: DSI: Add comment about regn
  OMAP: DSS2: DISPC: Add missing IRQ  definitions
  OMAP: DSS2: add dss_get_hdmi_venc_clk_source()
  OMAP: DSS2: DISPC: improve dispc_mgr_enable_digit_out()
  OMAP: DSS2: HDMI: fix hdmi output enable

 arch/arm/mach-omap2/board-4430sdp.c    |    9 -----
 drivers/video/omap2/dss/dispc.c        |   63 ++++++++++++++++++++------------
 drivers/video/omap2/dss/dss.c          |   11 ++++++
 drivers/video/omap2/dss/dss.h          |    1 +
 drivers/video/omap2/dss/dss_features.c |    3 ++
 drivers/video/omap2/dss/dss_features.h |    1 +
 drivers/video/omap2/dss/hdmi.c         |   25 +++++++++----
 include/video/omapdss.h                |    5 +++
 8 files changed, 78 insertions(+), 40 deletions(-)

-- 
1.7.4.1

[PATCH 0/8] OMAP: DSS2: misc improvements

[Tomi Valkeinen]

Some small DSS improvements, mostly HDMI related.

 Tomi

Tomi Valkeinen (8):
  OMAP: DSS2: DISPC: Fix minimum PCD value
  OMAP: DSS2: HDMI: use default dividers
  OMAP: DSS2: HDMI: change regn definition
  OMAP: DSS2: DSI: Add comment about regn
  OMAP: DSS2: DISPC: Add missing IRQ  definitions
  OMAP: DSS2: add dss_get_hdmi_venc_clk_source()
  OMAP: DSS2: DISPC: improve dispc_mgr_enable_digit_out()
  OMAP: DSS2: HDMI: fix hdmi output enable

 arch/arm/mach-omap2/board-4430sdp.c    |    9 -----
 drivers/video/omap2/dss/dispc.c        |   63 ++++++++++++++++++++------------
 drivers/video/omap2/dss/dss.c          |   11 ++++++
 drivers/video/omap2/dss/dss.h          |    1 +
 drivers/video/omap2/dss/dss_features.c |    3 ++
 drivers/video/omap2/dss/dss_features.h |    1 +
 drivers/video/omap2/dss/hdmi.c         |   25 +++++++++----
 include/video/omapdss.h                |    5 +++
 8 files changed, 78 insertions(+), 40 deletions(-)

-- 
1.7.4.1

[PATCH 1/8] OMAP: DSS2: DISPC: Fix minimum PCD value

[Tomi Valkeinen]

The current driver had a hardcoded minimum value of 2 for pixel clock
divisor (PCD). This doesn't seem to be right.

OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted
pixel clock (IPC) is off.

OMAP3 TRM says the same, but also in the register descriptions that PCD
value 1 is invalid.

OMAP2 TRM says PCD 2 is the minimum.

OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to
work fine.

This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to
find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and
1 for OMAP3/4.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dispc.c        |   14 ++++++++++----
 drivers/video/omap2/dss/dss_features.c |    3 +++
 drivers/video/omap2/dss/dss_features.h |    1 +
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index de20936..7f3d847 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2339,7 +2339,7 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
 		u16 pck_div)
 {
 	BUG_ON(lck_div < 1);
-	BUG_ON(pck_div < 2);
+	BUG_ON(pck_div < 1);
 
 	dispc_write_reg(DISPC_DIVISORo(channel),
 			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
@@ -2726,11 +2726,17 @@ void dispc_mgr_set_pol_freq(enum omap_channel channel,
 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 		struct dispc_clock_info *cinfo)
 {
-	u16 pcd_min = is_tft ? 2 : 3;
+	u16 pcd_min, pcd_max;
 	unsigned long best_pck;
 	u16 best_ld, cur_ld;
 	u16 best_pd, cur_pd;
 
+	pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
+	pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
+
+	if (!is_tft)
+		pcd_min = 3;
+
 	best_pck = 0;
 	best_ld = 0;
 	best_pd = 0;
@@ -2738,7 +2744,7 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 	for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
 		unsigned long lck = fck / cur_ld;
 
-		for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
+		for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
 			unsigned long pck = lck / cur_pd;
 			long old_delta = abs(best_pck - req_pck);
 			long new_delta = abs(pck - req_pck);
@@ -2773,7 +2779,7 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 {
 	if (cinfo->lck_div > 255 || cinfo->lck_div = 0)
 		return -EINVAL;
-	if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
+	if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
 		return -EINVAL;
 
 	cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index b63c5f8..85b07ca 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -281,6 +281,7 @@ static const char * const omap4_dss_clk_source_names[] = {
 
 static const struct dss_param_range omap2_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 2, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, 0 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, 0 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, 0 },
@@ -291,6 +292,7 @@ static const struct dss_param_range omap2_dss_param_range[] = {
 
 static const struct dss_param_range omap3_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1 << 7) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1 << 11) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1 << 4) - 1 },
@@ -301,6 +303,7 @@ static const struct dss_param_range omap3_dss_param_range[] = {
 
 static const struct dss_param_range omap4_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 186000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1 << 8) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1 << 12) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1 << 5) - 1 },
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 4271e96..158d922 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -73,6 +73,7 @@ enum dss_feat_reg_field {
 
 enum dss_range_param {
 	FEAT_PARAM_DSS_FCK,
+	FEAT_PARAM_DSS_PCD,
 	FEAT_PARAM_DSIPLL_REGN,
 	FEAT_PARAM_DSIPLL_REGM,
 	FEAT_PARAM_DSIPLL_REGM_DISPC,
-- 
1.7.4.1

[PATCH 1/8] OMAP: DSS2: DISPC: Fix minimum PCD value

[Tomi Valkeinen]

The current driver had a hardcoded minimum value of 2 for pixel clock
divisor (PCD). This doesn't seem to be right.

OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted
pixel clock (IPC) is off.

OMAP3 TRM says the same, but also in the register descriptions that PCD
value 1 is invalid.

OMAP2 TRM says PCD 2 is the minimum.

OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to
work fine.

This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to
find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and
1 for OMAP3/4.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dispc.c        |   14 ++++++++++----
 drivers/video/omap2/dss/dss_features.c |    3 +++
 drivers/video/omap2/dss/dss_features.h |    1 +
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index de20936..7f3d847 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2339,7 +2339,7 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
 		u16 pck_div)
 {
 	BUG_ON(lck_div < 1);
-	BUG_ON(pck_div < 2);
+	BUG_ON(pck_div < 1);
 
 	dispc_write_reg(DISPC_DIVISORo(channel),
 			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
@@ -2726,11 +2726,17 @@ void dispc_mgr_set_pol_freq(enum omap_channel channel,
 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 		struct dispc_clock_info *cinfo)
 {
-	u16 pcd_min = is_tft ? 2 : 3;
+	u16 pcd_min, pcd_max;
 	unsigned long best_pck;
 	u16 best_ld, cur_ld;
 	u16 best_pd, cur_pd;
 
+	pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
+	pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
+
+	if (!is_tft)
+		pcd_min = 3;
+
 	best_pck = 0;
 	best_ld = 0;
 	best_pd = 0;
@@ -2738,7 +2744,7 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 	for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
 		unsigned long lck = fck / cur_ld;
 
-		for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
+		for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
 			unsigned long pck = lck / cur_pd;
 			long old_delta = abs(best_pck - req_pck);
 			long new_delta = abs(pck - req_pck);
@@ -2773,7 +2779,7 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 {
 	if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
 		return -EINVAL;
-	if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
+	if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
 		return -EINVAL;
 
 	cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index b63c5f8..85b07ca 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -281,6 +281,7 @@ static const char * const omap4_dss_clk_source_names[] = {
 
 static const struct dss_param_range omap2_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 2, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, 0 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, 0 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, 0 },
@@ -291,6 +292,7 @@ static const struct dss_param_range omap2_dss_param_range[] = {
 
 static const struct dss_param_range omap3_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1 << 7) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1 << 11) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1 << 4) - 1 },
@@ -301,6 +303,7 @@ static const struct dss_param_range omap3_dss_param_range[] = {
 
 static const struct dss_param_range omap4_dss_param_range[] = {
 	[FEAT_PARAM_DSS_FCK]			= { 0, 186000000 },
+	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
 	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1 << 8) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1 << 12) - 1 },
 	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1 << 5) - 1 },
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 4271e96..158d922 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -73,6 +73,7 @@ enum dss_feat_reg_field {
 
 enum dss_range_param {
 	FEAT_PARAM_DSS_FCK,
+	FEAT_PARAM_DSS_PCD,
 	FEAT_PARAM_DSIPLL_REGN,
 	FEAT_PARAM_DSIPLL_REGM,
 	FEAT_PARAM_DSIPLL_REGM_DISPC,
-- 
1.7.4.1

[PATCH 2/8] OMAP: DSS2: HDMI: use default dividers

[Tomi Valkeinen]

Use default regn and regm2 dividers in the hdmi driver if the board file
does not define them.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c |    9 ---------
 drivers/video/omap2/dss/hdmi.c      |   15 +++++++++++++--
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 6713d6e..3fd7e8f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -818,15 +818,6 @@ static struct omap_dss_device sdp4430_hdmi_device = {
 	.name = "hdmi",
 	.driver_name = "hdmi_panel",
 	.type = OMAP_DISPLAY_TYPE_HDMI,
-	.clocks	= {
-		.dispc	= {
-			.dispc_fclk_src	= OMAP_DSS_CLK_SRC_FCK,
-		},
-		.hdmi	= {
-			.regn	= 15,
-			.regm2	= 1,
-		},
-	},
 	.platform_enable = sdp4430_panel_enable_hdmi,
 	.platform_disable = sdp4430_panel_disable_hdmi,
 	.channel = OMAP_DSS_CHANNEL_DIGIT,
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index b8e02e4..a3b3899 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -43,6 +43,9 @@
 #include "hdmi.h"
 #include "dss_features.h"
 
+#define HDMI_DEFAULT_REGN 15
+#define HDMI_DEFAULT_REGM2 1
+
 static struct {
 	struct mutex lock;
 	struct omap_display_platform_data *pdata;
@@ -1076,7 +1079,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * Input clock is predivided by N + 1
 	 * out put of which is reference clk
 	 */
-	pi->regn = dssdev->clocks.hdmi.regn;
+	if (dssdev->clocks.hdmi.regn = 0)
+		pi->regn = HDMI_DEFAULT_REGN;
+	else
+		pi->regn = dssdev->clocks.hdmi.regn;
+
 	refclk = clkin / (pi->regn + 1);
 
 	/*
@@ -1084,7 +1091,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * Multiplying by 100 to avoid fractional part removal
 	 */
 	pi->regm = (phy * 100 / (refclk)) / 100;
-	pi->regm2 = dssdev->clocks.hdmi.regm2;
+
+	if (dssdev->clocks.hdmi.regm2 = 0)
+		pi->regm2 = HDMI_DEFAULT_REGM2;
+	else
+		pi->regm2 = dssdev->clocks.hdmi.regm2;
 
 	/*
 	 * fractional multiplier is remainder of the difference between
-- 
1.7.4.1

[PATCH 2/8] OMAP: DSS2: HDMI: use default dividers

[Tomi Valkeinen]

Use default regn and regm2 dividers in the hdmi driver if the board file
does not define them.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c |    9 ---------
 drivers/video/omap2/dss/hdmi.c      |   15 +++++++++++++--
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 6713d6e..3fd7e8f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -818,15 +818,6 @@ static struct omap_dss_device sdp4430_hdmi_device = {
 	.name = "hdmi",
 	.driver_name = "hdmi_panel",
 	.type = OMAP_DISPLAY_TYPE_HDMI,
-	.clocks	= {
-		.dispc	= {
-			.dispc_fclk_src	= OMAP_DSS_CLK_SRC_FCK,
-		},
-		.hdmi	= {
-			.regn	= 15,
-			.regm2	= 1,
-		},
-	},
 	.platform_enable = sdp4430_panel_enable_hdmi,
 	.platform_disable = sdp4430_panel_disable_hdmi,
 	.channel = OMAP_DSS_CHANNEL_DIGIT,
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index b8e02e4..a3b3899 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -43,6 +43,9 @@
 #include "hdmi.h"
 #include "dss_features.h"
 
+#define HDMI_DEFAULT_REGN 15
+#define HDMI_DEFAULT_REGM2 1
+
 static struct {
 	struct mutex lock;
 	struct omap_display_platform_data *pdata;
@@ -1076,7 +1079,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * Input clock is predivided by N + 1
 	 * out put of which is reference clk
 	 */
-	pi->regn = dssdev->clocks.hdmi.regn;
+	if (dssdev->clocks.hdmi.regn == 0)
+		pi->regn = HDMI_DEFAULT_REGN;
+	else
+		pi->regn = dssdev->clocks.hdmi.regn;
+
 	refclk = clkin / (pi->regn + 1);
 
 	/*
@@ -1084,7 +1091,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * Multiplying by 100 to avoid fractional part removal
 	 */
 	pi->regm = (phy * 100 / (refclk)) / 100;
-	pi->regm2 = dssdev->clocks.hdmi.regm2;
+
+	if (dssdev->clocks.hdmi.regm2 == 0)
+		pi->regm2 = HDMI_DEFAULT_REGM2;
+	else
+		pi->regm2 = dssdev->clocks.hdmi.regm2;
 
 	/*
 	 * fractional multiplier is remainder of the difference between
-- 
1.7.4.1

[PATCH 3/8] OMAP: DSS2: HDMI: change regn definition

[Tomi Valkeinen]

regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.

To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.

This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/hdmi.c |    8 ++++----
 include/video/omapdss.h        |    1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index a3b3899..504c507 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -43,7 +43,7 @@
 #include "hdmi.h"
 #include "dss_features.h"
 
-#define HDMI_DEFAULT_REGN 15
+#define HDMI_DEFAULT_REGN 16
 #define HDMI_DEFAULT_REGM2 1
 
 static struct {
@@ -208,7 +208,7 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
 
 	r = hdmi_read_reg(PLLCTRL_CFG1);
 	r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
-	r = FLD_MOD(r, fmt->regn, 8, 1);  /* CFG1_PLL_REGN */
+	r = FLD_MOD(r, fmt->regn - 1, 8, 1);  /* CFG1_PLL_REGN */
 
 	hdmi_write_reg(PLLCTRL_CFG1, r);
 
@@ -1084,7 +1084,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	else
 		pi->regn = dssdev->clocks.hdmi.regn;
 
-	refclk = clkin / (pi->regn + 1);
+	refclk = clkin / pi->regn;
 
 	/*
 	 * multiplier is pixel_clk/ref_clk
@@ -1110,7 +1110,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * is greater than 1000MHz
 	 */
 	pi->dcofreq = phy > 1000 * 100;
-	pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
+	pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
 
 	DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
 	DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 9398dd3..534e3d1 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -460,6 +460,7 @@ struct omap_dss_device {
 		} dsi;
 
 		struct {
+			/* regn is one greater than TRM's REGN value */
 			u16 regn;
 			u16 regm2;
 		} hdmi;
-- 
1.7.4.1

[PATCH 3/8] OMAP: DSS2: HDMI: change regn definition

[Tomi Valkeinen]

regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.

To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.

This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/hdmi.c |    8 ++++----
 include/video/omapdss.h        |    1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index a3b3899..504c507 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -43,7 +43,7 @@
 #include "hdmi.h"
 #include "dss_features.h"
 
-#define HDMI_DEFAULT_REGN 15
+#define HDMI_DEFAULT_REGN 16
 #define HDMI_DEFAULT_REGM2 1
 
 static struct {
@@ -208,7 +208,7 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
 
 	r = hdmi_read_reg(PLLCTRL_CFG1);
 	r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
-	r = FLD_MOD(r, fmt->regn, 8, 1);  /* CFG1_PLL_REGN */
+	r = FLD_MOD(r, fmt->regn - 1, 8, 1);  /* CFG1_PLL_REGN */
 
 	hdmi_write_reg(PLLCTRL_CFG1, r);
 
@@ -1084,7 +1084,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	else
 		pi->regn = dssdev->clocks.hdmi.regn;
 
-	refclk = clkin / (pi->regn + 1);
+	refclk = clkin / pi->regn;
 
 	/*
 	 * multiplier is pixel_clk/ref_clk
@@ -1110,7 +1110,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 	 * is greater than 1000MHz
 	 */
 	pi->dcofreq = phy > 1000 * 100;
-	pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
+	pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
 
 	DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
 	DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 9398dd3..534e3d1 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -460,6 +460,7 @@ struct omap_dss_device {
 		} dsi;
 
 		struct {
+			/* regn is one greater than TRM's REGN value */
 			u16 regn;
 			u16 regm2;
 		} hdmi;
-- 
1.7.4.1

[PATCH 4/8] OMAP: DSS2: DSI: Add comment about regn

[Tomi Valkeinen]

regn divider is one greater than the REGN divider in TRM. Add a comment
to point this out.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 include/video/omapdss.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 534e3d1..d4c85f2 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -450,6 +450,7 @@ struct omap_dss_device {
 		} dispc;
 
 		struct {
+			/* regn is one greater than TRM's REGN value */
 			u16 regn;
 			u16 regm;
 			u16 regm_dispc;
-- 
1.7.4.1

[PATCH 4/8] OMAP: DSS2: DSI: Add comment about regn

[Tomi Valkeinen]

regn divider is one greater than the REGN divider in TRM. Add a comment
to point this out.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 include/video/omapdss.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 534e3d1..d4c85f2 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -450,6 +450,7 @@ struct omap_dss_device {
 		} dispc;
 
 		struct {
+			/* regn is one greater than TRM's REGN value */
 			u16 regn;
 			u16 regm;
 			u16 regm_dispc;
-- 
1.7.4.1

[PATCH 5/8] OMAP: DSS2: DISPC: Add missing IRQ definitions

[Tomi Valkeinen]

Add IRQ definitions for missing OMAP4 IRQs: FRAMEDONEWB, FRAMEDONETV,
WBBUFFEROVERFLOW.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 include/video/omapdss.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index d4c85f2..f8385ae 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -43,6 +43,9 @@
 #define DISPC_IRQ_VSYNC2		(1 << 18)
 #define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
 #define DISPC_IRQ_FRAMEDONE2		(1 << 22)
+#define DISPC_IRQ_FRAMEDONEWB		(1 << 23)
+#define DISPC_IRQ_FRAMEDONETV		(1 << 24)
+#define DISPC_IRQ_WBBUFFEROVERFLOW	(1 << 25)
 
 struct omap_dss_device;
 struct omap_overlay_manager;
-- 
1.7.4.1

[PATCH 5/8] OMAP: DSS2: DISPC: Add missing IRQ definitions

[Tomi Valkeinen]

Add IRQ definitions for missing OMAP4 IRQs: FRAMEDONEWB, FRAMEDONETV,
WBBUFFEROVERFLOW.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 include/video/omapdss.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index d4c85f2..f8385ae 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -43,6 +43,9 @@
 #define DISPC_IRQ_VSYNC2		(1 << 18)
 #define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
 #define DISPC_IRQ_FRAMEDONE2		(1 << 22)
+#define DISPC_IRQ_FRAMEDONEWB		(1 << 23)
+#define DISPC_IRQ_FRAMEDONETV		(1 << 24)
+#define DISPC_IRQ_WBBUFFEROVERFLOW	(1 << 25)
 
 struct omap_dss_device;
 struct omap_overlay_manager;
-- 
1.7.4.1

[PATCH 6/8] OMAP: DSS2: add dss_get_hdmi_venc_clk_source()

[Tomi Valkeinen]

Add dss_get_hdmi_venc_clk_source(), which can be used to get the value
programmed with dss_select_hdmi_venc_clk_source(). This can be used to
find out if the digit output is going to VENC or HDMI.

For OMAP2/3 dss_get_hdmi_venc_clk_source() always returns
DSS_VENC_TV_CLK.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dss.c |   11 +++++++++++
 drivers/video/omap2/dss/dss.h |    1 +
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 356d3c1..3e09726 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -639,6 +639,17 @@ void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 	REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15);	/* VENC_HDMI_SWITCH */
 }
 
+enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
+{
+	enum omap_display_type displays;
+
+	displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
+	if ((displays & OMAP_DISPLAY_TYPE_HDMI) = 0)
+		return DSS_VENC_TV_CLK;
+
+	return REG_GET(DSS_CONTROL, 15, 15);
+}
+
 static int dss_get_clocks(void)
 {
 	struct clk *clk;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index a095a62..57b1a01 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -210,6 +210,7 @@ int dss_runtime_get(void);
 void dss_runtime_put(void);
 
 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
+enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 void dss_dump_clocks(struct seq_file *s);
 
-- 
1.7.4.1

[PATCH 6/8] OMAP: DSS2: add dss_get_hdmi_venc_clk_source()

[Tomi Valkeinen]

Add dss_get_hdmi_venc_clk_source(), which can be used to get the value
programmed with dss_select_hdmi_venc_clk_source(). This can be used to
find out if the digit output is going to VENC or HDMI.

For OMAP2/3 dss_get_hdmi_venc_clk_source() always returns
DSS_VENC_TV_CLK.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dss.c |   11 +++++++++++
 drivers/video/omap2/dss/dss.h |    1 +
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 356d3c1..3e09726 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -639,6 +639,17 @@ void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 	REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15);	/* VENC_HDMI_SWITCH */
 }
 
+enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
+{
+	enum omap_display_type displays;
+
+	displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
+	if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
+		return DSS_VENC_TV_CLK;
+
+	return REG_GET(DSS_CONTROL, 15, 15);
+}
+
 static int dss_get_clocks(void)
 {
 	struct clk *clk;
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index a095a62..57b1a01 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -210,6 +210,7 @@ int dss_runtime_get(void);
 void dss_runtime_put(void);
 
 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
+enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 void dss_dump_clocks(struct seq_file *s);
 
-- 
1.7.4.1

[PATCH 7/8] OMAP: DSS2: DISPC: improve dispc_mgr_enable_digit_out()

[Tomi Valkeinen]

dispc_mgr_enable_digit_out() didn't handle HDMI case very well.

Improve the function to use FRAMEDONETV interrupt to see when HDMI has
been disabled.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dispc.c |   49 +++++++++++++++++++++++----------------
 1 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7f3d847..4af4bd4 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1924,11 +1924,16 @@ static void _enable_digit_out(bool enable)
 static void dispc_mgr_enable_digit_out(bool enable)
 {
 	struct completion frame_done_completion;
-	int r;
+	enum dss_hdmi_venc_clk_source_select src;
+	int r, i;
+	u32 irq_mask;
+	int num_irqs;
 
 	if (REG_GET(DISPC_CONTROL, 1, 1) = enable)
 		return;
 
+	src = dss_get_hdmi_venc_clk_source();
+
 	if (enable) {
 		unsigned long flags;
 		/* When we enable digit output, we'll get an extra digit
@@ -1945,36 +1950,40 @@ static void dispc_mgr_enable_digit_out(bool enable)
 	 * wait for the extra sync losts */
 	init_completion(&frame_done_completion);
 
+	if (src = DSS_HDMI_M_PCLK && enable = false) {
+		irq_mask = DISPC_IRQ_FRAMEDONETV;
+		num_irqs = 1;
+	} else {
+		irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
+		/* XXX I understand from TRM that we should only wait for the
+		 * current field to complete. But it seems we have to wait for
+		 * both fields */
+		num_irqs = 2;
+	}
+
 	r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
-			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
+			irq_mask);
 	if (r)
-		DSSERR("failed to register EVSYNC isr\n");
+		DSSERR("failed to register %x isr\n", irq_mask);
 
 	_enable_digit_out(enable);
 
-	/* XXX I understand from TRM that we should only wait for the
-	 * current field to complete. But it seems we have to wait
-	 * for both fields */
-	if (!wait_for_completion_timeout(&frame_done_completion,
-				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
-
-	if (!wait_for_completion_timeout(&frame_done_completion,
-				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
+	for (i = 0; i < num_irqs; ++i) {
+		if (!wait_for_completion_timeout(&frame_done_completion,
+					msecs_to_jiffies(100)))
+			DSSERR("timeout waiting for digit out to %s\n",
+					enable ? "start" : "stop");
+	}
 
-	r = omap_dispc_unregister_isr(dispc_disable_isr,
-			&frame_done_completion,
-			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
+	r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
+			irq_mask);
 	if (r)
-		DSSERR("failed to unregister EVSYNC isr\n");
+		DSSERR("failed to unregister %x isr\n", irq_mask);
 
 	if (enable) {
 		unsigned long flags;
 		spin_lock_irqsave(&dispc.irq_lock, flags);
-		dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
-		if (dss_has_feature(FEAT_MGR_LCD2))
-			dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
+		dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
 		dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 		_omap_dispc_set_irqs();
 		spin_unlock_irqrestore(&dispc.irq_lock, flags);
-- 
1.7.4.1

[PATCH 7/8] OMAP: DSS2: DISPC: improve dispc_mgr_enable_digit_out()

[Tomi Valkeinen]

dispc_mgr_enable_digit_out() didn't handle HDMI case very well.

Improve the function to use FRAMEDONETV interrupt to see when HDMI has
been disabled.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/dispc.c |   49 +++++++++++++++++++++++----------------
 1 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7f3d847..4af4bd4 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1924,11 +1924,16 @@ static void _enable_digit_out(bool enable)
 static void dispc_mgr_enable_digit_out(bool enable)
 {
 	struct completion frame_done_completion;
-	int r;
+	enum dss_hdmi_venc_clk_source_select src;
+	int r, i;
+	u32 irq_mask;
+	int num_irqs;
 
 	if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
 		return;
 
+	src = dss_get_hdmi_venc_clk_source();
+
 	if (enable) {
 		unsigned long flags;
 		/* When we enable digit output, we'll get an extra digit
@@ -1945,36 +1950,40 @@ static void dispc_mgr_enable_digit_out(bool enable)
 	 * wait for the extra sync losts */
 	init_completion(&frame_done_completion);
 
+	if (src == DSS_HDMI_M_PCLK && enable == false) {
+		irq_mask = DISPC_IRQ_FRAMEDONETV;
+		num_irqs = 1;
+	} else {
+		irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
+		/* XXX I understand from TRM that we should only wait for the
+		 * current field to complete. But it seems we have to wait for
+		 * both fields */
+		num_irqs = 2;
+	}
+
 	r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
-			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
+			irq_mask);
 	if (r)
-		DSSERR("failed to register EVSYNC isr\n");
+		DSSERR("failed to register %x isr\n", irq_mask);
 
 	_enable_digit_out(enable);
 
-	/* XXX I understand from TRM that we should only wait for the
-	 * current field to complete. But it seems we have to wait
-	 * for both fields */
-	if (!wait_for_completion_timeout(&frame_done_completion,
-				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
-
-	if (!wait_for_completion_timeout(&frame_done_completion,
-				msecs_to_jiffies(100)))
-		DSSERR("timeout waiting for EVSYNC\n");
+	for (i = 0; i < num_irqs; ++i) {
+		if (!wait_for_completion_timeout(&frame_done_completion,
+					msecs_to_jiffies(100)))
+			DSSERR("timeout waiting for digit out to %s\n",
+					enable ? "start" : "stop");
+	}
 
-	r = omap_dispc_unregister_isr(dispc_disable_isr,
-			&frame_done_completion,
-			DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
+	r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
+			irq_mask);
 	if (r)
-		DSSERR("failed to unregister EVSYNC isr\n");
+		DSSERR("failed to unregister %x isr\n", irq_mask);
 
 	if (enable) {
 		unsigned long flags;
 		spin_lock_irqsave(&dispc.irq_lock, flags);
-		dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
-		if (dss_has_feature(FEAT_MGR_LCD2))
-			dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
+		dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
 		dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 		_omap_dispc_set_irqs();
 		spin_unlock_irqrestore(&dispc.irq_lock, flags);
-- 
1.7.4.1

[PATCH 8/8] OMAP: DSS2: HDMI: fix hdmi output enable

[Tomi Valkeinen]

Enabling HDMI output often causes sync lost errors. The problem seems to
go away if we first enable the HDMI output, and only then enable the
DISPC output.

This will also fix the dispc's dispc_mgr_enable_digit_out(), as the code
waits for two VSYNCs after enabling the output. If the HDMI output is
disabled (as it was previously), there are no VSYNCs and
dispc_mgr_enable_digit_out() will print timeout errors.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/hdmi.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 504c507..d08096b 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -1184,10 +1184,10 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
 	dispc_set_digit_size(dssdev->panel.timings.x_res,
 			dssdev->panel.timings.y_res);
 
-	dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
-
 	hdmi_wp_video_start(1);
 
+	dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
+
 	return 0;
 err:
 	hdmi_runtime_put();
-- 
1.7.4.1

[PATCH 8/8] OMAP: DSS2: HDMI: fix hdmi output enable

[Tomi Valkeinen]

Enabling HDMI output often causes sync lost errors. The problem seems to
go away if we first enable the HDMI output, and only then enable the
DISPC output.

This will also fix the dispc's dispc_mgr_enable_digit_out(), as the code
waits for two VSYNCs after enabling the output. If the HDMI output is
disabled (as it was previously), there are no VSYNCs and
dispc_mgr_enable_digit_out() will print timeout errors.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
 drivers/video/omap2/dss/hdmi.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 504c507..d08096b 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -1184,10 +1184,10 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
 	dispc_set_digit_size(dssdev->panel.timings.x_res,
 			dssdev->panel.timings.y_res);
 
-	dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
-
 	hdmi_wp_video_start(1);
 
+	dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
+
 	return 0;
 err:
 	hdmi_runtime_put();
-- 
1.7.4.1

Re: [PATCH 1/8] OMAP: DSS2: DISPC: Fix minimum PCD value

[Archit Taneja]

On Wednesday 31 August 2011 06:51 PM, Valkeinen, Tomi wrote:
> The current driver had a hardcoded minimum value of 2 for pixel clock
> divisor (PCD). This doesn't seem to be right.
>
> OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted
> pixel clock (IPC) is off.
>
> OMAP3 TRM says the same, but also in the register descriptions that PCD
> value 1 is invalid.
>
> OMAP2 TRM says PCD 2 is the minimum.
>
> OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to
> work fine.
>
> This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to
> find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and
> 1 for OMAP3/4.

This looks good to me.

Archit

>
> Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>
> ---
>   drivers/video/omap2/dss/dispc.c        |   14 ++++++++++----
>   drivers/video/omap2/dss/dss_features.c |    3 +++
>   drivers/video/omap2/dss/dss_features.h |    1 +
>   3 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index de20936..7f3d847 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -2339,7 +2339,7 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
>   		u16 pck_div)
>   {
>   	BUG_ON(lck_div<  1);
> -	BUG_ON(pck_div<  2);
> +	BUG_ON(pck_div<  1);
>
>   	dispc_write_reg(DISPC_DIVISORo(channel),
>   			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
> @@ -2726,11 +2726,17 @@ void dispc_mgr_set_pol_freq(enum omap_channel channel,
>   void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
>   		struct dispc_clock_info *cinfo)
>   {
> -	u16 pcd_min = is_tft ? 2 : 3;
> +	u16 pcd_min, pcd_max;
>   	unsigned long best_pck;
>   	u16 best_ld, cur_ld;
>   	u16 best_pd, cur_pd;
>
> +	pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
> +	pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
> +
> +	if (!is_tft)
> +		pcd_min = 3;
> +
>   	best_pck = 0;
>   	best_ld = 0;
>   	best_pd = 0;
> @@ -2738,7 +2744,7 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
>   	for (cur_ld = 1; cur_ld<= 255; ++cur_ld) {
>   		unsigned long lck = fck / cur_ld;
>
> -		for (cur_pd = pcd_min; cur_pd<= 255; ++cur_pd) {
> +		for (cur_pd = pcd_min; cur_pd<= pcd_max; ++cur_pd) {
>   			unsigned long pck = lck / cur_pd;
>   			long old_delta = abs(best_pck - req_pck);
>   			long new_delta = abs(pck - req_pck);
> @@ -2773,7 +2779,7 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
>   {
>   	if (cinfo->lck_div>  255 || cinfo->lck_div == 0)
>   		return -EINVAL;
> -	if (cinfo->pck_div<  2 || cinfo->pck_div>  255)
> +	if (cinfo->pck_div<  1 || cinfo->pck_div>  255)
>   		return -EINVAL;
>
>   	cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
> diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
> index b63c5f8..85b07ca 100644
> --- a/drivers/video/omap2/dss/dss_features.c
> +++ b/drivers/video/omap2/dss/dss_features.c
> @@ -281,6 +281,7 @@ static const char * const omap4_dss_clk_source_names[] = {
>
>   static const struct dss_param_range omap2_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 2, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, 0 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, 0 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, 0 },
> @@ -291,6 +292,7 @@ static const struct dss_param_range omap2_dss_param_range[] = {
>
>   static const struct dss_param_range omap3_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1<<  7) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1<<  11) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1<<  4) - 1 },
> @@ -301,6 +303,7 @@ static const struct dss_param_range omap3_dss_param_range[] = {
>
>   static const struct dss_param_range omap4_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 186000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1<<  8) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1<<  12) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1<<  5) - 1 },
> diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
> index 4271e96..158d922 100644
> --- a/drivers/video/omap2/dss/dss_features.h
> +++ b/drivers/video/omap2/dss/dss_features.h
> @@ -73,6 +73,7 @@ enum dss_feat_reg_field {
>
>   enum dss_range_param {
>   	FEAT_PARAM_DSS_FCK,
> +	FEAT_PARAM_DSS_PCD,
>   	FEAT_PARAM_DSIPLL_REGN,
>   	FEAT_PARAM_DSIPLL_REGM,
>   	FEAT_PARAM_DSIPLL_REGM_DISPC,

Re: [PATCH 1/8] OMAP: DSS2: DISPC: Fix minimum PCD value

[Archit Taneja]

On Wednesday 31 August 2011 06:51 PM, Valkeinen, Tomi wrote:
> The current driver had a hardcoded minimum value of 2 for pixel clock
> divisor (PCD). This doesn't seem to be right.
>
> OMAP4 TRM says that PCD can be 1 when not downscaling, and inverted
> pixel clock (IPC) is off.
>
> OMAP3 TRM says the same, but also in the register descriptions that PCD
> value 1 is invalid.
>
> OMAP2 TRM says PCD 2 is the minimum.
>
> OMAP2 is still untested, but for both OMAP3 and OMAP4 PCD of 1 seems to
> work fine.
>
> This patch adds a new DSS feature, FEAT_PARAM_DSS_PCD, which is used to
> find the minimum and maximum PCD. The minimum is set to 2 for OMAP2, and
> 1 for OMAP3/4.

This looks good to me.

Archit

>
> Signed-off-by: Tomi Valkeinen<tomi.valkeinen@ti.com>
> ---
>   drivers/video/omap2/dss/dispc.c        |   14 ++++++++++----
>   drivers/video/omap2/dss/dss_features.c |    3 +++
>   drivers/video/omap2/dss/dss_features.h |    1 +
>   3 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
> index de20936..7f3d847 100644
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -2339,7 +2339,7 @@ static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
>   		u16 pck_div)
>   {
>   	BUG_ON(lck_div<  1);
> -	BUG_ON(pck_div<  2);
> +	BUG_ON(pck_div<  1);
>
>   	dispc_write_reg(DISPC_DIVISORo(channel),
>   			FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
> @@ -2726,11 +2726,17 @@ void dispc_mgr_set_pol_freq(enum omap_channel channel,
>   void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
>   		struct dispc_clock_info *cinfo)
>   {
> -	u16 pcd_min = is_tft ? 2 : 3;
> +	u16 pcd_min, pcd_max;
>   	unsigned long best_pck;
>   	u16 best_ld, cur_ld;
>   	u16 best_pd, cur_pd;
>
> +	pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
> +	pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
> +
> +	if (!is_tft)
> +		pcd_min = 3;
> +
>   	best_pck = 0;
>   	best_ld = 0;
>   	best_pd = 0;
> @@ -2738,7 +2744,7 @@ void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
>   	for (cur_ld = 1; cur_ld<= 255; ++cur_ld) {
>   		unsigned long lck = fck / cur_ld;
>
> -		for (cur_pd = pcd_min; cur_pd<= 255; ++cur_pd) {
> +		for (cur_pd = pcd_min; cur_pd<= pcd_max; ++cur_pd) {
>   			unsigned long pck = lck / cur_pd;
>   			long old_delta = abs(best_pck - req_pck);
>   			long new_delta = abs(pck - req_pck);
> @@ -2773,7 +2779,7 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
>   {
>   	if (cinfo->lck_div>  255 || cinfo->lck_div = 0)
>   		return -EINVAL;
> -	if (cinfo->pck_div<  2 || cinfo->pck_div>  255)
> +	if (cinfo->pck_div<  1 || cinfo->pck_div>  255)
>   		return -EINVAL;
>
>   	cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
> diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
> index b63c5f8..85b07ca 100644
> --- a/drivers/video/omap2/dss/dss_features.c
> +++ b/drivers/video/omap2/dss/dss_features.c
> @@ -281,6 +281,7 @@ static const char * const omap4_dss_clk_source_names[] = {
>
>   static const struct dss_param_range omap2_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 2, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, 0 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, 0 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, 0 },
> @@ -291,6 +292,7 @@ static const struct dss_param_range omap2_dss_param_range[] = {
>
>   static const struct dss_param_range omap3_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 173000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1<<  7) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1<<  11) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1<<  4) - 1 },
> @@ -301,6 +303,7 @@ static const struct dss_param_range omap3_dss_param_range[] = {
>
>   static const struct dss_param_range omap4_dss_param_range[] = {
>   	[FEAT_PARAM_DSS_FCK]			= { 0, 186000000 },
> +	[FEAT_PARAM_DSS_PCD]			= { 1, 255 },
>   	[FEAT_PARAM_DSIPLL_REGN]		= { 0, (1<<  8) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM]		= { 0, (1<<  12) - 1 },
>   	[FEAT_PARAM_DSIPLL_REGM_DISPC]		= { 0, (1<<  5) - 1 },
> diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
> index 4271e96..158d922 100644
> --- a/drivers/video/omap2/dss/dss_features.h
> +++ b/drivers/video/omap2/dss/dss_features.h
> @@ -73,6 +73,7 @@ enum dss_feat_reg_field {
>
>   enum dss_range_param {
>   	FEAT_PARAM_DSS_FCK,
> +	FEAT_PARAM_DSS_PCD,
>   	FEAT_PARAM_DSIPLL_REGN,
>   	FEAT_PARAM_DSIPLL_REGM,
>   	FEAT_PARAM_DSIPLL_REGM_DISPC,