[PATCH] powerpc: Fix xmon for systems without MSR[RI]

[PATCH] powerpc: Fix xmon for systems without MSR[RI]

[Jimi Xenidis]

From: David Gibson <dwg@au1.ibm.com>

Based on patch by David Gibson <dwg@au1.ibm.com>

xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output.  This patch fixes it, by ignoring
the RI bit if the processor does not support it.

There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point.  For now this adds
BookE processors to the mix.

Signed-off-by: Jimi Xenidis <jimix@pobox.com>
---
 arch/powerpc/xmon/xmon.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..fdb2f7e 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
 
 static inline int unrecoverable_excp(struct pt_regs *regs)
 {
-#ifdef CONFIG_4xx
-	/* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
 	return 0;
 #else
 	return ((regs->msr & MSR_RI) == 0);
-- 
1.7.0.4

Re: [PATCH] powerpc: Fix xmon for systems without MSR[RI]

[Benjamin Herrenschmidt]

On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote:
> From: David Gibson <dwg@au1.ibm.com>
> 
> Based on patch by David Gibson <dwg@au1.ibm.com>
> 
> xmon has a longstanding bug on systems which are SMP-capable but lack
> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
> CPUs will not properly keep quiet, but will print stuff, thereby
> garbling the primary xmon's output.  This patch fixes it, by ignoring
> the RI bit if the processor does not support it.
> 
> There's already a version of this for 4xx upstream, which we'll need
> to extend to other RI-lacking CPUs at some point.  For now this adds
> BookE processors to the mix.

Don't freescale one have RI ?

Cheers,
Ben.

> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
> ---
>  arch/powerpc/xmon/xmon.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 42541bb..fdb2f7e 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
>  
>  static inline int unrecoverable_excp(struct pt_regs *regs)
>  {
> -#ifdef CONFIG_4xx
> -	/* We have no MSR_RI bit on 4xx, so we simply return false */
> +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
> +	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
>  	return 0;
>  #else
>  	return ((regs->msr & MSR_RI) == 0);

Re: [PATCH] powerpc: Fix xmon for systems without MSR[RI]

[Scott Wood]

On 08/30/2011 01:11 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote:
>> From: David Gibson <dwg@au1.ibm.com>
>>
>> Based on patch by David Gibson <dwg@au1.ibm.com>
>>
>> xmon has a longstanding bug on systems which are SMP-capable but lack
>> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
>> CPUs will not properly keep quiet, but will print stuff, thereby
>> garbling the primary xmon's output.  This patch fixes it, by ignoring
>> the RI bit if the processor does not support it.
>>
>> There's already a version of this for 4xx upstream, which we'll need
>> to extend to other RI-lacking CPUs at some point.  For now this adds
>> BookE processors to the mix.
> 
> Don't freescale one have RI ?

e500mc does.

e500v2 doesn't -- if a machine check happens while MSR[ME]=0, it causes
a checkstop.

-Scott

Re: [PATCH] powerpc: Fix xmon for systems without MSR[RI]

[Jimi Xenidis]

On Aug 30, 2011, at 1:08 PM, Scott Wood wrote:

> On 08/30/2011 01:11 AM, Benjamin Herrenschmidt wrote:
>> On Mon, 2011-08-08 at 16:25 -0500, Jimi Xenidis wrote:
>>> From: David Gibson <dwg@au1.ibm.com>
>>>=20
>>> Based on patch by David Gibson <dwg@au1.ibm.com>
>>>=20
>>> xmon has a longstanding bug on systems which are SMP-capable but =
lack
>>> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
>>> CPUs will not properly keep quiet, but will print stuff, thereby
>>> garbling the primary xmon's output.  This patch fixes it, by =
ignoring
>>> the RI bit if the processor does not support it.
>>>=20
>>> There's already a version of this for 4xx upstream, which we'll need
>>> to extend to other RI-lacking CPUs at some point.  For now this adds
>>> BookE processors to the mix.
>>=20
>> Don't freescale one have RI ?
>=20
> e500mc does.

hmm, according to the ISA, MSR[RI] is only defined for Book3s and is not =
defined for Book3e
Should we scope it to just book3e?
-jx

>=20
> e500v2 doesn't -- if a machine check happens while MSR[ME]=3D0, it =
causes
> a checkstop.
>=20
> -Scott
>=20

[PATCH v2] powerpc: Fix xmon for systems without MSR[RI]

[Jimi Xenidis]

From: David Gibson <dwg@au1.ibm.com>

Based on patch by David Gibson <dwg@au1.ibm.com>

xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output.  This patch fixes it, by ignoring
the RI bit if the processor does not support it.

There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point.  For now this adds
Book3e processors to the mix.

Signed-off-by: Jimi Xenidis <jimix@pobox.com>

---
Restricted it to Book3e
---
 arch/powerpc/xmon/xmon.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..13f82f8 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
 
 static inline int unrecoverable_excp(struct pt_regs *regs)
 {
-#ifdef CONFIG_4xx
-	/* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
+	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
 	return 0;
 #else
 	return ((regs->msr & MSR_RI) == 0);
-- 
1.7.0.4

Re: [PATCH v2] powerpc: Fix xmon for systems without MSR[RI]

[Scott Wood]

On 09/23/2011 10:01 AM, Jimi Xenidis wrote:
> From: David Gibson <dwg@au1.ibm.com>
> 
> Based on patch by David Gibson <dwg@au1.ibm.com>
> 
> xmon has a longstanding bug on systems which are SMP-capable but lack
> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
> CPUs will not properly keep quiet, but will print stuff, thereby
> garbling the primary xmon's output.  This patch fixes it, by ignoring
> the RI bit if the processor does not support it.
> 
> There's already a version of this for 4xx upstream, which we'll need
> to extend to other RI-lacking CPUs at some point.  For now this adds
> Book3e processors to the mix.
> 
> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
> 
> ---
> Restricted it to Book3e
> ---
>  arch/powerpc/xmon/xmon.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 42541bb..13f82f8 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
>  
>  static inline int unrecoverable_excp(struct pt_regs *regs)
>  {
> -#ifdef CONFIG_4xx
> -	/* We have no MSR_RI bit on 4xx, so we simply return false */
> +#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
> +	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
>  	return 0;
>  #else
>  	return ((regs->msr & MSR_RI) == 0);

How is CONFIG_BOOK3E better than CONFIG_BOOKE?  Both e500mc (has RI) and
e500v2 (doesn't have RI) will select both symbols.  Sounds like it
should be a cputable flag.

-Scott

Re: [PATCH v2] powerpc: Fix xmon for systems without MSR[RI]

[Jimi Xenidis]

On Sep 23, 2011, at 11:32 AM, Scott Wood wrote:

> On 09/23/2011 10:01 AM, Jimi Xenidis wrote:
>> From: David Gibson <dwg@au1.ibm.com>
>>=20
>> Based on patch by David Gibson <dwg@au1.ibm.com>
>>=20
>> xmon has a longstanding bug on systems which are SMP-capable but lack
>> the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
>> CPUs will not properly keep quiet, but will print stuff, thereby
>> garbling the primary xmon's output.  This patch fixes it, by ignoring
>> the RI bit if the processor does not support it.
>>=20
>> There's already a version of this for 4xx upstream, which we'll need
>> to extend to other RI-lacking CPUs at some point.  For now this adds
>> Book3e processors to the mix.
>>=20
>> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
>>=20
>> ---
>> Restricted it to Book3e
>> ---
>> arch/powerpc/xmon/xmon.c |    4 ++--
>> 1 files changed, 2 insertions(+), 2 deletions(-)
>>=20
>> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>> index 42541bb..13f82f8 100644
>> --- a/arch/powerpc/xmon/xmon.c
>> +++ b/arch/powerpc/xmon/xmon.c
>> @@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
>>=20
>> static inline int unrecoverable_excp(struct pt_regs *regs)
>> {
>> -#ifdef CONFIG_4xx
>> -	/* We have no MSR_RI bit on 4xx, so we simply return false */
>> +#if defined(CONFIG_4xx) || defined(CONFIG_BOOK3E)
>> +	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return =
false */
>> 	return 0;
>> #else
>> 	return ((regs->msr & MSR_RI) =3D=3D 0);
>=20
> How is CONFIG_BOOK3E better than CONFIG_BOOKE?  Both e500mc (has RI) =
and
> e500v2 (doesn't have RI) will select both symbols.  Sounds like it
> should be a cputable flag.

Ben was not in favor of wasting a cpu feature bit on this.
I figured that since Book3e ISA does not support an RI bit than I would =
leave that too the those who extend it. :)
Any other ideas are welcome.

-JX


>=20
> -Scott
>=20

Re: [PATCH v2] powerpc: Fix xmon for systems without MSR[RI]

[Scott Wood]

On 09/23/2011 12:54 PM, Jimi Xenidis wrote:
> On Sep 23, 2011, at 11:32 AM, Scott Wood wrote:
>> How is CONFIG_BOOK3E better than CONFIG_BOOKE?  Both e500mc (has RI) and
>> e500v2 (doesn't have RI) will select both symbols.  Sounds like it
>> should be a cputable flag.
> 
> Ben was not in favor of wasting a cpu feature bit on this.

That we're discussing the wastage of a single *bit* suggests the CPU
feature mechanism could use an overhaul. :-P

-Scott

[PATCH] [PATCH v3] powerpc: Fix xmon for systems without MSR[RI]

[Jimi Xenidis]

From: David Gibson <dwg@au1.ibm.com>

Based on patch by David Gibson <dwg@au1.ibm.com>

xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output.  This patch fixes it, by ignoring
the RI bit if the processor does not support it.

There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point.  For now this adds
Book3e processors to the mix.

Signed-off-by: Jimi Xenidis <jimix@pobox.com>

---
Restricted it to Book3e
Fix typo, its supposed to be CONFIG_PPC_BOOK3E
---
 arch/powerpc/xmon/xmon.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 42541bb..e88e7f5 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -340,8 +340,8 @@ int cpus_are_in_xmon(void)
 
 static inline int unrecoverable_excp(struct pt_regs *regs)
 {
-#ifdef CONFIG_4xx
-	/* We have no MSR_RI bit on 4xx, so we simply return false */
+#if defined(CONFIG_4xx) || defined(CONFIG_PPC_BOOK3E)
+	/* We have no MSR_RI bit on 4xx or Book3e, so we simply return false */
 	return 0;
 #else
 	return ((regs->msr & MSR_RI) == 0);
-- 
1.7.0.4