[U-Boot] [PATCH 0/4] Add code to read in the coreboot tables and fill in memory info.

[U-Boot] [PATCH 0/4] Add code to read in the coreboot tables and fill in memory info.

[Gabe Black]

These changes add code which reads in the coreboot tables exported by
coreboot and puts the info into a single structure for easy access. It also
adds some code which uses that info to fill in an e820 table.


Gabe Black (4):
  x86: Import code from coreboot's libpayload to parse the coreboot
    table
  x86: Determine the ram size using the coreboot tables
  x86: Force the lib_sysinfo structure to be in the .data section
  x86: Add infrastructure to extract an e820 table from the coreboot
    tables

 arch/x86/cpu/coreboot/Makefile                |    3 +
 arch/x86/cpu/coreboot/ipchecksum.c            |   54 ++++++
 arch/x86/cpu/coreboot/sdram.c                 |   38 ++++-
 arch/x86/cpu/coreboot/sysinfo.c               |   39 ++++
 arch/x86/cpu/coreboot/tables.c                |  183 +++++++++++++++++++
 arch/x86/include/asm/ic/coreboot/ipchecksum.h |   37 ++++
 arch/x86/include/asm/ic/coreboot/sysinfo.h    |   64 +++++++
 arch/x86/include/asm/ic/coreboot/tables.h     |  241 +++++++++++++++++++++++++
 arch/x86/include/asm/zimage.h                 |    5 +
 arch/x86/lib/zimage.c                         |   10 +
 board/chromebook-x86/coreboot/coreboot.c      |   10 +
 11 files changed, 683 insertions(+), 1 deletions(-)
 create mode 100644 arch/x86/cpu/coreboot/ipchecksum.c
 create mode 100644 arch/x86/cpu/coreboot/sysinfo.c
 create mode 100644 arch/x86/cpu/coreboot/tables.c
 create mode 100644 arch/x86/include/asm/ic/coreboot/ipchecksum.h
 create mode 100644 arch/x86/include/asm/ic/coreboot/sysinfo.h
 create mode 100644 arch/x86/include/asm/ic/coreboot/tables.h

-- 
1.7.3.1

[U-Boot] [PATCH 1/4] x86: Import code from coreboot's libpayload to parse the coreboot table

[Gabe Black]

Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
 arch/x86/cpu/coreboot/Makefile                |    3 +
 arch/x86/cpu/coreboot/ipchecksum.c            |   54 ++++++
 arch/x86/cpu/coreboot/sysinfo.c               |   33 ++++
 arch/x86/cpu/coreboot/tables.c                |  183 +++++++++++++++++++
 arch/x86/include/asm/ic/coreboot/ipchecksum.h |   37 ++++
 arch/x86/include/asm/ic/coreboot/sysinfo.h    |   64 +++++++
 arch/x86/include/asm/ic/coreboot/tables.h     |  241 +++++++++++++++++++++++++
 board/chromebook-x86/coreboot/coreboot.c      |   10 +
 8 files changed, 625 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/cpu/coreboot/ipchecksum.c
 create mode 100644 arch/x86/cpu/coreboot/sysinfo.c
 create mode 100644 arch/x86/cpu/coreboot/tables.c
 create mode 100644 arch/x86/include/asm/ic/coreboot/ipchecksum.h
 create mode 100644 arch/x86/include/asm/ic/coreboot/sysinfo.h
 create mode 100644 arch/x86/include/asm/ic/coreboot/tables.h

diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 0444399..13f5f8a 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -33,7 +33,10 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(SOC).o
 
+COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
+COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
 COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
+COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o
 
 SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
 
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c b/arch/x86/cpu/coreboot/ipchecksum.c
new file mode 100644
index 0000000..63a3aab
--- /dev/null
+++ b/arch/x86/cpu/coreboot/ipchecksum.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * It has originally been taken from the FreeBSD project.
+ *
+ * Copyright (c) 2001 Charles Mott <cm@linktel.net>
+ * Copyright (c) 2008 coresystems GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <compiler.h>
+#include <asm/ic/coreboot/ipchecksum.h>
+
+unsigned short ipchksum(const void *vptr, unsigned long nbytes)
+{
+	int sum, oddbyte;
+	const unsigned short *ptr = vptr;
+
+	sum = 0;
+	while (nbytes > 1) {
+		sum += *ptr++;
+		nbytes -= 2;
+	}
+	if (nbytes == 1) {
+		oddbyte = 0;
+		((u8 *)&oddbyte)[0] = *(u8 *) ptr;
+		((u8 *)&oddbyte)[1] = 0;
+		sum += oddbyte;
+	}
+	sum = (sum >> 16) + (sum & 0xffff);
+	sum += (sum >> 16);
+	return ~sum;
+}
diff --git a/arch/x86/cpu/coreboot/sysinfo.c b/arch/x86/cpu/coreboot/sysinfo.c
new file mode 100644
index 0000000..464f8a1
--- /dev/null
+++ b/arch/x86/cpu/coreboot/sysinfo.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <asm/ic/coreboot/sysinfo.h>
+
+struct sysinfo_t lib_sysinfo;
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
new file mode 100644
index 0000000..6c8b103
--- /dev/null
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <asm/ic/coreboot/ipchecksum.h>
+#include <asm/ic/coreboot/sysinfo.h>
+#include <asm/ic/coreboot/tables.h>
+
+/*
+ * Some of this is x86 specific, and the rest of it is generic. Right now,
+ * since we only support x86, we'll avoid trying to make lots of infrastructure
+ * we don't need. If in the future, we want to use coreboot on some other
+ * architecture, then take out the generic parsing code and move it elsewhere.
+ */
+
+/* === Parsing code === */
+/* This is the generic parsing code. */
+
+static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
+{
+	struct cb_memory *mem = (struct cb_memory *)ptr;
+	int count = MEM_RANGE_COUNT(mem);
+	int i;
+
+	if (count > SYSINFO_MAX_MEM_RANGES)
+		count = SYSINFO_MAX_MEM_RANGES;
+
+	info->n_memranges = 0;
+
+	for (i = 0; i < count; i++) {
+		struct cb_memory_range *range =
+		    (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
+
+		info->memrange[info->n_memranges].base =
+		    UNPACK_CB64(range->start);
+
+		info->memrange[info->n_memranges].size =
+		    UNPACK_CB64(range->size);
+
+		info->memrange[info->n_memranges].type = range->type;
+
+		info->n_memranges++;
+	}
+}
+
+static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
+{
+	struct cb_serial *ser = (struct cb_serial *)ptr;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
+}
+
+static void cb_parse_optiontable(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->option_table = (struct cb_cmos_option_table *)ptr;
+}
+
+static void cb_parse_checksum(unsigned char *ptr, struct sysinfo_t *info)
+{
+	struct cb_cmos_checksum *cmos_cksum = (struct cb_cmos_checksum *)ptr;
+	info->cmos_range_start = cmos_cksum->range_start;
+	info->cmos_range_end = cmos_cksum->range_end;
+	info->cmos_checksum_location = cmos_cksum->location;
+}
+
+static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
+{
+	info->framebuffer = (struct cb_framebuffer *)ptr;
+}
+
+static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+{
+	struct cb_header *header;
+	unsigned char *ptr = (unsigned char *)addr;
+	int i;
+
+	for (i = 0; i < len; i += 16, ptr += 16) {
+		header = (struct cb_header *)ptr;
+		if (!strncmp((const char *)header->signature, "LBIO", 4))
+			break;
+	}
+
+	/* We walked the entire space and didn't find anything. */
+	if (i >= len)
+		return -1;
+
+	if (!header->table_bytes)
+		return 0;
+
+	/* Make sure the checksums match. */
+	if (ipchksum((u16 *) header, sizeof(*header)) != 0)
+		return -1;
+
+	if (ipchksum((u16 *) (ptr + sizeof(*header)),
+		     header->table_bytes) != header->table_checksum)
+		return -1;
+
+	/* Now, walk the tables. */
+	ptr += header->header_bytes;
+
+	for (i = 0; i < header->table_entries; i++) {
+		struct cb_record *rec = (struct cb_record *)ptr;
+
+		/* We only care about a few tags here (maybe more later). */
+		switch (rec->tag) {
+		case CB_TAG_FORWARD:
+			return cb_parse_header(
+				(void *)(unsigned long)
+				((struct cb_forward *)rec)->forward,
+				len, info);
+			continue;
+		case CB_TAG_MEMORY:
+			cb_parse_memory(ptr, info);
+			break;
+		case CB_TAG_SERIAL:
+			cb_parse_serial(ptr, info);
+			break;
+		case CB_TAG_CMOS_OPTION_TABLE:
+			cb_parse_optiontable(ptr, info);
+			break;
+		case CB_TAG_OPTION_CHECKSUM:
+			cb_parse_checksum(ptr, info);
+			break;
+		/*
+		 * FIXME we should warn on serial if coreboot set up a
+		 * framebuffer buf the payload does not know about it.
+		 */
+		case CB_TAG_FRAMEBUFFER:
+			cb_parse_framebuffer(ptr, info);
+			break;
+		}
+
+		ptr += rec->size;
+	}
+
+	return 1;
+}
+
+/* == Architecture specific == */
+/* This is the x86 specific stuff. */
+
+/* Assume no translation or that memory is identity mapped. */
+static void *phys_to_virt(unsigned long virt)
+{
+	return (void *)(uintptr_t)virt;
+}
+
+int get_coreboot_info(struct sysinfo_t *info)
+{
+	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+
+	if (ret != 1)
+		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+
+	return (ret == 1) ? 0 : -1;
+}
diff --git a/arch/x86/include/asm/ic/coreboot/ipchecksum.h b/arch/x86/include/asm/ic/coreboot/ipchecksum.h
new file mode 100644
index 0000000..1d73b4d
--- /dev/null
+++ b/arch/x86/include/asm/ic/coreboot/ipchecksum.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * It has originally been taken from the FreeBSD project.
+ *
+ * Copyright (c) 2001 Charles Mott <cm@linktel.net>
+ * Copyright (c) 2008 coresystems GmbH
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _COREBOOT_IPCHECKSUM_H
+#define _COREBOOT_IPCHECKSUM_H
+
+unsigned short ipchksum(const void *vptr, unsigned long nbytes);
+
+#endif
diff --git a/arch/x86/include/asm/ic/coreboot/sysinfo.h b/arch/x86/include/asm/ic/coreboot/sysinfo.h
new file mode 100644
index 0000000..612342b
--- /dev/null
+++ b/arch/x86/include/asm/ic/coreboot/sysinfo.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _COREBOOT_SYSINFO_H
+#define _COREBOOT_SYSINFO_H
+
+#include <compiler.h>
+
+/* Allow a maximum of 16 memory range definitions. */
+#define SYSINFO_MAX_MEM_RANGES 16
+
+struct sysinfo_t {
+	unsigned int cpu_khz;
+	unsigned short ser_ioport;
+	unsigned long ser_base; /* for mmapped serial */
+
+	int n_memranges;
+
+	struct memrange {
+		unsigned long long base;
+		unsigned long long size;
+		unsigned int type;
+	} memrange[SYSINFO_MAX_MEM_RANGES];
+
+	struct cb_cmos_option_table *option_table;
+	u32 cmos_range_start;
+	u32 cmos_range_end;
+	u32 cmos_checksum_location;
+
+	struct cb_framebuffer *framebuffer;
+
+	unsigned long *mbtable; /** Pointer to the multiboot table */
+};
+
+extern struct sysinfo_t lib_sysinfo;
+
+#endif
+
diff --git a/arch/x86/include/asm/ic/coreboot/tables.h b/arch/x86/include/asm/ic/coreboot/tables.h
new file mode 100644
index 0000000..c286973
--- /dev/null
+++ b/arch/x86/include/asm/ic/coreboot/tables.h
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _COREBOOT_TABLES_H
+#define _COREBOOT_TABLES_H
+
+#include <compiler.h>
+
+struct cbuint64 {
+	u32 lo;
+	u32 hi;
+};
+
+struct cb_header {
+	u8 signature[4];
+	u32 header_bytes;
+	u32 header_checksum;
+	u32 table_bytes;
+	u32 table_checksum;
+	u32 table_entries;
+};
+
+struct cb_record {
+	u32 tag;
+	u32 size;
+};
+
+#define CB_TAG_UNUSED     0x0000
+#define CB_TAG_MEMORY     0x0001
+
+struct cb_memory_range {
+	struct cbuint64 start;
+	struct cbuint64 size;
+	u32 type;
+};
+
+#define CB_MEM_RAM          1
+#define CB_MEM_RESERVED     2
+#define CB_MEM_ACPI         3
+#define CB_MEM_NVS          4
+#define CB_MEM_UNUSABLE     5
+#define CB_MEM_VENDOR_RSVD  6
+#define CB_MEM_TABLE       16
+
+struct cb_memory {
+	u32 tag;
+	u32 size;
+	struct cb_memory_range map[0];
+};
+
+#define CB_TAG_HWRPB      0x0002
+
+struct cb_hwrpb {
+	u32 tag;
+	u32 size;
+	u64 hwrpb;
+};
+
+#define CB_TAG_MAINBOARD  0x0003
+
+struct cb_mainboard {
+	u32 tag;
+	u32 size;
+	u8 vendor_idx;
+	u8 part_number_idx;
+	u8 strings[0];
+};
+
+#define CB_TAG_VERSION        0x0004
+#define CB_TAG_EXTRA_VERSION  0x0005
+#define CB_TAG_BUILD          0x0006
+#define CB_TAG_COMPILE_TIME   0x0007
+#define CB_TAG_COMPILE_BY     0x0008
+#define CB_TAG_COMPILE_HOST   0x0009
+#define CB_TAG_COMPILE_DOMAIN 0x000a
+#define CB_TAG_COMPILER       0x000b
+#define CB_TAG_LINKER         0x000c
+#define CB_TAG_ASSEMBLER      0x000d
+
+struct cb_string {
+	u32 tag;
+	u32 size;
+	u8 string[0];
+};
+
+#define CB_TAG_SERIAL         0x000f
+
+struct cb_serial {
+	u32 tag;
+	u32 size;
+#define CB_SERIAL_TYPE_IO_MAPPED     1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
+};
+
+#define CB_TAG_CONSOLE       0x00010
+
+struct cb_console {
+	u32 tag;
+	u32 size;
+	u16 type;
+};
+
+#define CB_TAG_CONSOLE_SERIAL8250 0
+#define CB_TAG_CONSOLE_VGA        1 /* OBSOLETE */
+#define CB_TAG_CONSOLE_BTEXT      2 /* OBSOLETE */
+#define CB_TAG_CONSOLE_LOGBUF     3
+#define CB_TAG_CONSOLE_SROM       4 /* OBSOLETE */
+#define CB_TAG_CONSOLE_EHCI       5
+
+#define CB_TAG_FORWARD       0x00011
+
+struct cb_forward {
+	u32 tag;
+	u32 size;
+	u64 forward;
+};
+
+#define CB_TAG_FRAMEBUFFER      0x0012
+struct cb_framebuffer {
+	u32 tag;
+	u32 size;
+
+	u64 physical_address;
+	u32 x_resolution;
+	u32 y_resolution;
+	u32 bytes_per_line;
+	u8 bits_per_pixel;
+	u8 red_mask_pos;
+	u8 red_mask_size;
+	u8 green_mask_pos;
+	u8 green_mask_size;
+	u8 blue_mask_pos;
+	u8 blue_mask_size;
+	u8 reserved_mask_pos;
+	u8 reserved_mask_size;
+};
+
+#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
+struct cb_cmos_option_table {
+	u32 tag;
+	u32 size;
+	u32 header_length;
+};
+
+#define CB_TAG_OPTION         0x00c9
+#define CMOS_MAX_NAME_LENGTH    32
+struct cb_cmos_entries {
+	u32 tag;
+	u32 size;
+	u32 bit;
+	u32 length;
+	u32 config;
+	u32 config_id;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+};
+
+
+#define CB_TAG_OPTION_ENUM    0x00ca
+#define CMOS_MAX_TEXT_LENGTH 32
+struct cb_cmos_enums {
+	u32 tag;
+	u32 size;
+	u32 config_id;
+	u32 value;
+	u8 text[CMOS_MAX_TEXT_LENGTH];
+};
+
+#define CB_TAG_OPTION_DEFAULTS 0x00cb
+#define CMOS_IMAGE_BUFFER_SIZE 128
+struct cb_cmos_defaults {
+	u32 tag;
+	u32 size;
+	u32 name_length;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+	u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
+};
+
+#define CB_TAG_OPTION_CHECKSUM 0x00cc
+#define CHECKSUM_NONE	0
+#define CHECKSUM_PCBIOS	1
+struct	cb_cmos_checksum {
+	u32 tag;
+	u32 size;
+	u32 range_start;
+	u32 range_end;
+	u32 location;
+	u32 type;
+};
+
+/* Helpful macros */
+
+#define MEM_RANGE_COUNT(_rec) \
+	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
+
+#define MEM_RANGE_PTR(_rec, _idx) \
+	(((u8 *) (_rec)) + sizeof(*(_rec)) \
+	+ (sizeof((_rec)->map[0]) * (_idx)))
+
+#define MB_VENDOR_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
+
+#define MB_PART_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
+
+#define UNPACK_CB64(_in) \
+	((((u64) _in.hi) << 32) | _in.lo)
+
+struct sysinfo_t;
+
+int get_coreboot_info(struct sysinfo_t *info);
+
+#endif
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c
index 44c6f15..a2d6ef5 100644
--- a/board/chromebook-x86/coreboot/coreboot.c
+++ b/board/chromebook-x86/coreboot/coreboot.c
@@ -26,6 +26,8 @@
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <asm/ic/coreboot/tables.h>
+#include <asm/ic/coreboot/sysinfo.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,6 +36,14 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 /*
  * Miscellaneous platform dependent initializations
  */
+int cpu_init_f(void)
+{
+	int ret = get_coreboot_info(&lib_sysinfo);
+	if (ret != 0)
+		printf("Failed to parse coreboot tables.\n");
+	return ret;
+}
+
 int board_early_init_f(void)
 {
 	return 0;
-- 
1.7.3.1

[U-Boot] [PATCH 1/4] x86: Import code from coreboot's libpayload to parse the coreboot table

[Graeme Russ]

Hi Gabe,

On 30/11/11 17:07, Gabe Black wrote:
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> ---
>  arch/x86/cpu/coreboot/Makefile                |    3 +
>  arch/x86/cpu/coreboot/ipchecksum.c            |   54 ++++++
>  arch/x86/cpu/coreboot/sysinfo.c               |   33 ++++
>  arch/x86/cpu/coreboot/tables.c                |  183 +++++++++++++++++++
>  arch/x86/include/asm/ic/coreboot/ipchecksum.h |   37 ++++
>  arch/x86/include/asm/ic/coreboot/sysinfo.h    |   64 +++++++
>  arch/x86/include/asm/ic/coreboot/tables.h     |  241 +++++++++++++++++++++++++

Please move these to arch/x86/include/asm/arch-coreboot/

>  board/chromebook-x86/coreboot/coreboot.c      |   10 +
>  8 files changed, 625 insertions(+), 0 deletions(-)
>  create mode 100644 arch/x86/cpu/coreboot/ipchecksum.c
>  create mode 100644 arch/x86/cpu/coreboot/sysinfo.c
>  create mode 100644 arch/x86/cpu/coreboot/tables.c
>  create mode 100644 arch/x86/include/asm/ic/coreboot/ipchecksum.h
>  create mode 100644 arch/x86/include/asm/ic/coreboot/sysinfo.h
>  create mode 100644 arch/x86/include/asm/ic/coreboot/tables.h
> 

Regards,

Graeme

[U-Boot] [PATCH 2/4] x86: Determine the ram size using the coreboot tables

[Gabe Black]

This is really only an approximation using the largest RAM address available
in the tables. There may be areas which are marked as reserved which are
actually at the end of RAM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
 arch/x86/cpu/coreboot/sdram.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index b56085a..b5b086b 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -24,12 +24,28 @@
 
 #include <common.h>
 #include <asm/u-boot-x86.h>
+#include <asm/global_data.h>
+#include <asm/ic/coreboot/sysinfo.h>
+#include <asm/ic/coreboot/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init_f(void)
 {
-	gd->ram_size = 64*1024*1024;
+	int i;
+	phys_size_t ram_size = 0;
+	for (i = 0; i < lib_sysinfo.n_memranges; i++) {
+		unsigned long long end = \
+			lib_sysinfo.memrange[i].base +
+			lib_sysinfo.memrange[i].size;
+		if (lib_sysinfo.memrange[i].type == CB_MEM_RAM &&
+			end > ram_size) {
+			ram_size = end;
+		}
+	}
+	gd->ram_size = ram_size;
+	if (ram_size == 0)
+		return -1;
 	return 0;
 }
 
-- 
1.7.3.1

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Gabe Black]

Otherwise it ends up in the .bss section. U-boot assumes that it doesn't
need to copy it over during relocation, and instead fills that whole
section with zeroes. If we really were booting from ROM that would be
appropriate, but we need some information from the coreboot tables (memory
size) before then and have to fill that structure before relocation. We
skirt u-boot's assumption by putting this in .data where it assumes there
is still read only but non-zero data.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
 arch/x86/cpu/coreboot/sysinfo.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/x86/cpu/coreboot/sysinfo.c b/arch/x86/cpu/coreboot/sysinfo.c
index 464f8a1..e74fe0a 100644
--- a/arch/x86/cpu/coreboot/sysinfo.c
+++ b/arch/x86/cpu/coreboot/sysinfo.c
@@ -30,4 +30,10 @@
 
 #include <asm/ic/coreboot/sysinfo.h>
 
-struct sysinfo_t lib_sysinfo;
+/*
+ * This needs to be in the .data section so that it's copied over during
+ * relocation. By default it's put in the .bss section which is simply filled
+ * with zeroes when transitioning from "ROM", which is really RAM, to other
+ * RAM.
+ */
+struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
-- 
1.7.3.1

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Graeme Russ]

Hi Gabe,

On 30/11/11 17:07, Gabe Black wrote:
> Otherwise it ends up in the .bss section. U-boot assumes that it doesn't
> need to copy it over during relocation, and instead fills that whole
> section with zeroes. If we really were booting from ROM that would be
> appropriate, but we need some information from the coreboot tables (memory
> size) before then and have to fill that structure before relocation. We
> skirt u-boot's assumption by putting this in .data where it assumes there
> is still read only but non-zero data.
> 
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> ---
>  arch/x86/cpu/coreboot/sysinfo.c |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/x86/cpu/coreboot/sysinfo.c b/arch/x86/cpu/coreboot/sysinfo.c
> index 464f8a1..e74fe0a 100644
> --- a/arch/x86/cpu/coreboot/sysinfo.c
> +++ b/arch/x86/cpu/coreboot/sysinfo.c
> @@ -30,4 +30,10 @@
>  
>  #include <asm/ic/coreboot/sysinfo.h>
>  
> -struct sysinfo_t lib_sysinfo;
> +/*
> + * This needs to be in the .data section so that it's copied over during
> + * relocation. By default it's put in the .bss section which is simply filled
> + * with zeroes when transitioning from "ROM", which is really RAM, to other
> + * RAM.
> + */
> +struct sysinfo_t lib_sysinfo __attribute__((section(".data")));

I think this can be logically folded into the first patch

Regards,

Graeme

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Gabe Black]

On Fri, Dec 2, 2011 at 1:10 PM, Graeme Russ <graeme.russ@gmail.com> wrote:

> Hi Gabe,
>
> On 30/11/11 17:07, Gabe Black wrote:
> > Otherwise it ends up in the .bss section. U-boot assumes that it doesn't
> > need to copy it over during relocation, and instead fills that whole
> > section with zeroes. If we really were booting from ROM that would be
> > appropriate, but we need some information from the coreboot tables
> (memory
> > size) before then and have to fill that structure before relocation. We
> > skirt u-boot's assumption by putting this in .data where it assumes there
> > is still read only but non-zero data.
> >
> > Signed-off-by: Gabe Black <gabeblack@chromium.org>
> > ---
> >  arch/x86/cpu/coreboot/sysinfo.c |    8 +++++++-
> >  1 files changed, 7 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/x86/cpu/coreboot/sysinfo.c
> b/arch/x86/cpu/coreboot/sysinfo.c
> > index 464f8a1..e74fe0a 100644
> > --- a/arch/x86/cpu/coreboot/sysinfo.c
> > +++ b/arch/x86/cpu/coreboot/sysinfo.c
> > @@ -30,4 +30,10 @@
> >
> >  #include <asm/ic/coreboot/sysinfo.h>
> >
> > -struct sysinfo_t lib_sysinfo;
> > +/*
> > + * This needs to be in the .data section so that it's copied over during
> > + * relocation. By default it's put in the .bss section which is simply
> filled
> > + * with zeroes when transitioning from "ROM", which is really RAM, to
> other
> > + * RAM.
> > + */
> > +struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
>
> I think this can be logically folded into the first patch
>
> Regards,
>
> Graeme
>

I would rather not do that since the first patch is, modulo checkpatch and
build fixes, just importing that code from coreboot's libpayload. This
change is making an important, non-obvious change which makes it work
properly within u-boot. These are two different things, and one way or the
other this one is important enough to be singled out as its own change and
not lost in the midst of the other.

Gabe

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Graeme Russ]

Hi Gabe,

On 03/12/11 08:16, Gabe Black wrote:
> 
> 
> On Fri, Dec 2, 2011 at 1:10 PM, Graeme Russ <graeme.russ@gmail.com
> <mailto:graeme.russ@gmail.com>> wrote:
> 
>     Hi Gabe,
> 
>     On 30/11/11 17:07, Gabe Black wrote:
>     > Otherwise it ends up in the .bss section. U-boot assumes that it doesn't
>     > need to copy it over during relocation, and instead fills that whole
>     > section with zeroes. If we really were booting from ROM that would be
>     > appropriate, but we need some information from the coreboot tables
>     (memory
>     > size) before then and have to fill that structure before relocation. We
>     > skirt u-boot's assumption by putting this in .data where it assumes there
>     > is still read only but non-zero data.
>     >
>     > Signed-off-by: Gabe Black <gabeblack@chromium.org
>     <mailto:gabeblack@chromium.org>>
>     > ---
>     >  arch/x86/cpu/coreboot/sysinfo.c |    8 +++++++-
>     >  1 files changed, 7 insertions(+), 1 deletions(-)
>     >
>     > diff --git a/arch/x86/cpu/coreboot/sysinfo.c
>     b/arch/x86/cpu/coreboot/sysinfo.c
>     > index 464f8a1..e74fe0a 100644
>     > --- a/arch/x86/cpu/coreboot/sysinfo.c
>     > +++ b/arch/x86/cpu/coreboot/sysinfo.c
>     > @@ -30,4 +30,10 @@
>     >
>     >  #include <asm/ic/coreboot/sysinfo.h>
>     >
>     > -struct sysinfo_t lib_sysinfo;
>     > +/*
>     > + * This needs to be in the .data section so that it's copied over during
>     > + * relocation. By default it's put in the .bss section which is
>     simply filled
>     > + * with zeroes when transitioning from "ROM", which is really RAM,
>     to other
>     > + * RAM.
>     > + */
>     > +struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
> 
>     I think this can be logically folded into the first patch
> 
>     Regards,
> 
>     Graeme
> 
> 
> I would rather not do that since the first patch is, modulo checkpatch and
> build fixes, just importing that code from coreboot's libpayload. This
> change is making an important, non-obvious change which makes it work
> properly within u-boot. These are two different things, and one way or the
> other this one is important enough to be singled out as its own change and
> not lost in the midst of the other.

I agree that is a logical position to take, however I think that the fact
that you introduce a commit which is known to be 'broken' is the overriding
factor - Include to fact that the modification is made in the commit
message and the comment like:

/*
 * Note: U-Boot needs this to be in the .data section so....
 * ...
 */

Also, can you supply any specific commit id(s) for the originating source -
We typically try to include as much canonical information to identify the
source to a particular commit

Regards,

Graeme

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Gabe Black]

On Fri, Dec 2, 2011 at 1:22 PM, Graeme Russ <graeme.russ@gmail.com> wrote:

> Hi Gabe,
>
> On 03/12/11 08:16, Gabe Black wrote:
> >
> >
> > On Fri, Dec 2, 2011 at 1:10 PM, Graeme Russ <graeme.russ@gmail.com
> > <mailto:graeme.russ@gmail.com>> wrote:
> >
> >     Hi Gabe,
> >
> >     On 30/11/11 17:07, Gabe Black wrote:
> >     > Otherwise it ends up in the .bss section. U-boot assumes that it
> doesn't
> >     > need to copy it over during relocation, and instead fills that
> whole
> >     > section with zeroes. If we really were booting from ROM that would
> be
> >     > appropriate, but we need some information from the coreboot tables
> >     (memory
> >     > size) before then and have to fill that structure before
> relocation. We
> >     > skirt u-boot's assumption by putting this in .data where it
> assumes there
> >     > is still read only but non-zero data.
> >     >
> >     > Signed-off-by: Gabe Black <gabeblack@chromium.org
> >     <mailto:gabeblack@chromium.org>>
> >     > ---
> >     >  arch/x86/cpu/coreboot/sysinfo.c |    8 +++++++-
> >     >  1 files changed, 7 insertions(+), 1 deletions(-)
> >     >
> >     > diff --git a/arch/x86/cpu/coreboot/sysinfo.c
> >     b/arch/x86/cpu/coreboot/sysinfo.c
> >     > index 464f8a1..e74fe0a 100644
> >     > --- a/arch/x86/cpu/coreboot/sysinfo.c
> >     > +++ b/arch/x86/cpu/coreboot/sysinfo.c
> >     > @@ -30,4 +30,10 @@
> >     >
> >     >  #include <asm/ic/coreboot/sysinfo.h>
> >     >
> >     > -struct sysinfo_t lib_sysinfo;
> >     > +/*
> >     > + * This needs to be in the .data section so that it's copied over
> during
> >     > + * relocation. By default it's put in the .bss section which is
> >     simply filled
> >     > + * with zeroes when transitioning from "ROM", which is really RAM,
> >     to other
> >     > + * RAM.
> >     > + */
> >     > +struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
> >
> >     I think this can be logically folded into the first patch
> >
> >     Regards,
> >
> >     Graeme
> >
> >
> > I would rather not do that since the first patch is, modulo checkpatch
> and
> > build fixes, just importing that code from coreboot's libpayload. This
> > change is making an important, non-obvious change which makes it work
> > properly within u-boot. These are two different things, and one way or
> the
> > other this one is important enough to be singled out as its own change
> and
> > not lost in the midst of the other.
>
> I agree that is a logical position to take, however I think that the fact
> that you introduce a commit which is known to be 'broken' is the overriding
> factor - Include to fact that the modification is made in the commit
> message and the comment like:
>
> /*
>  * Note: U-Boot needs this to be in the .data section so....
>  * ...
>  */
>
> Also, can you supply any specific commit id(s) for the originating source -
> We typically try to include as much canonical information to identify the
> source to a particular commit
>
> Regards,
>
> Graeme
>


These commits were originally put together many months ago, so the exact
version of the original source is lost.

[U-Boot] [PATCH 3/4] x86: Force the lib_sysinfo structure to be in the .data section

[Mike Frysinger]

On Wednesday 30 November 2011 01:07:54 Gabe Black wrote:
> +struct sysinfo_t lib_sysinfo __attribute__((section(".data")));

seems like it should be .data.lib_sysinfo

or maybe pick a field you always init and set it to something non-zero.
struct sysinfo_t lib_sysinfo = {
	/* force into .data */
	.cpu_khz = 1,
};
-mike
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[U-Boot] [PATCH 4/4] x86: Add infrastructure to extract an e820 table from the coreboot tables

[Gabe Black]

Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
 arch/x86/cpu/coreboot/sdram.c |   32 ++++++++++++++++++++++++++------
 arch/x86/include/asm/zimage.h |    5 +++++
 arch/x86/lib/zimage.c         |   10 ++++++++++
 3 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index b5b086b..ce73467 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -23,6 +23,8 @@
  */
 
 #include <common.h>
+#include <malloc.h>
+#include <asm/e820.h>
 #include <asm/u-boot-x86.h>
 #include <asm/global_data.h>
 #include <asm/ic/coreboot/sysinfo.h>
@@ -30,18 +32,36 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	int i;
+
+	unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
+	if (num_entries < lib_sysinfo.n_memranges) {
+		printf("Warning: Limiting e820 map to %d entries.\n",
+			num_entries);
+	}
+	for (i = 0; i < num_entries; i++) {
+		struct memrange *memrange = &lib_sysinfo.memrange[i];
+
+		entries[i].addr = memrange->base;
+		entries[i].size = memrange->size;
+		entries[i].type = memrange->type;
+	}
+	return num_entries;
+}
+
 int dram_init_f(void)
 {
 	int i;
 	phys_size_t ram_size = 0;
+
 	for (i = 0; i < lib_sysinfo.n_memranges; i++) {
-		unsigned long long end = \
-			lib_sysinfo.memrange[i].base +
-			lib_sysinfo.memrange[i].size;
-		if (lib_sysinfo.memrange[i].type == CB_MEM_RAM &&
-			end > ram_size) {
+		struct memrange *memrange = &lib_sysinfo.memrange[i];
+		unsigned long long end = memrange->base + memrange->size;
+
+		if (memrange->type == CB_MEM_RAM && end > ram_size)
 			ram_size = end;
-		}
 	}
 	gd->ram_size = ram_size;
 	if (ram_size == 0)
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index a02637f..b172048 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -24,6 +24,8 @@
 #ifndef _ASM_ZIMAGE_H_
 #define _ASM_ZIMAGE_H_
 
+#include <asm/e820.h>
+
 /* linux i386 zImage/bzImage header. Offsets relative to
  * the start of the image */
 
@@ -65,6 +67,9 @@
 #define BZIMAGE_LOAD_ADDR  0x100000
 #define ZIMAGE_LOAD_ADDR   0x10000
 
+/* Implementation defined function to install an e820 map. */
+unsigned install_e820_map(unsigned max_entries, struct e820entry *);
+
 void *load_zimage(char *image, unsigned long kernel_size,
 		  unsigned long initrd_addr, unsigned long initrd_size,
 		  int auto_boot);
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 6843ff6..1fde13f 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -51,6 +51,16 @@
 
 #define COMMAND_LINE_SIZE	2048
 
+unsigned generic_install_e820_map(unsigned max_entries,
+				  struct e820entry *entries)
+{
+	return 0;
+}
+
+unsigned install_e820_map(unsigned max_entries,
+			  struct e820entry *entries)
+	__attribute__((weak, alias("generic_install_e820_map")));
+
 static void build_command_line(char *command_line, int auto_boot)
 {
 	char *env_command_line;
-- 
1.7.3.1

[U-Boot] [PATCH 4/4] x86: Add infrastructure to extract an e820 table from the coreboot tables

[Graeme Russ]

Hi Gabe,

On 30/11/11 17:07, Gabe Black wrote:
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> ---
>  arch/x86/cpu/coreboot/sdram.c |   32 ++++++++++++++++++++++++++------
>  arch/x86/include/asm/zimage.h |    5 +++++
>  arch/x86/lib/zimage.c         |   10 ++++++++++
>  3 files changed, 41 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
> index b5b086b..ce73467 100644
> --- a/arch/x86/cpu/coreboot/sdram.c
> +++ b/arch/x86/cpu/coreboot/sdram.c
> @@ -23,6 +23,8 @@
>   */
>  
>  #include <common.h>
> +#include <malloc.h>
> +#include <asm/e820.h>
>  #include <asm/u-boot-x86.h>
>  #include <asm/global_data.h>
>  #include <asm/ic/coreboot/sysinfo.h>
> @@ -30,18 +32,36 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
> +{
> +	int i;
> +
> +	unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
> +	if (num_entries < lib_sysinfo.n_memranges) {
> +		printf("Warning: Limiting e820 map to %d entries.\n",
> +			num_entries);
> +	}
> +	for (i = 0; i < num_entries; i++) {
> +		struct memrange *memrange = &lib_sysinfo.memrange[i];
> +
> +		entries[i].addr = memrange->base;
> +		entries[i].size = memrange->size;
> +		entries[i].type = memrange->type;
> +	}
> +	return num_entries;
> +}
> +
>  int dram_init_f(void)
>  {
>  	int i;
>  	phys_size_t ram_size = 0;
> +
>  	for (i = 0; i < lib_sysinfo.n_memranges; i++) {
> -		unsigned long long end = \
> -			lib_sysinfo.memrange[i].base +
> -			lib_sysinfo.memrange[i].size;
> -		if (lib_sysinfo.memrange[i].type == CB_MEM_RAM &&
> -			end > ram_size) {
> +		struct memrange *memrange = &lib_sysinfo.memrange[i];
> +		unsigned long long end = memrange->base + memrange->size;
> +
> +		if (memrange->type == CB_MEM_RAM && end > ram_size)
>  			ram_size = end;
> -		}
>  	}
>  	gd->ram_size = ram_size;
>  	if (ram_size == 0)

Please fold these changes to dram_init_f() into the second patch

> diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
> index a02637f..b172048 100644
> --- a/arch/x86/include/asm/zimage.h
> +++ b/arch/x86/include/asm/zimage.h
> @@ -24,6 +24,8 @@
>  #ifndef _ASM_ZIMAGE_H_
>  #define _ASM_ZIMAGE_H_
>  
> +#include <asm/e820.h>
> +
>  /* linux i386 zImage/bzImage header. Offsets relative to
>   * the start of the image */
>  
> @@ -65,6 +67,9 @@
>  #define BZIMAGE_LOAD_ADDR  0x100000
>  #define ZIMAGE_LOAD_ADDR   0x10000
>  
> +/* Implementation defined function to install an e820 map. */
> +unsigned install_e820_map(unsigned max_entries, struct e820entry *);
> +
>  void *load_zimage(char *image, unsigned long kernel_size,
>  		  unsigned long initrd_addr, unsigned long initrd_size,
>  		  int auto_boot);
> diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
> index 6843ff6..1fde13f 100644
> --- a/arch/x86/lib/zimage.c
> +++ b/arch/x86/lib/zimage.c
> @@ -51,6 +51,16 @@
>  
>  #define COMMAND_LINE_SIZE	2048
>  
> +unsigned generic_install_e820_map(unsigned max_entries,
> +				  struct e820entry *entries)
> +{
> +	return 0;
> +}
> +
> +unsigned install_e820_map(unsigned max_entries,
> +			  struct e820entry *entries)
> +	__attribute__((weak, alias("generic_install_e820_map")));
> +
>  static void build_command_line(char *command_line, int auto_boot)
>  {
>  	char *env_command_line;

I think all of the e820 code can be moved into your 32-bit boot protocol
patch series

Regards,

Graeme

[U-Boot] [PATCH 4/4] x86: Add infrastructure to extract an e820 table from the coreboot tables

[Gabe Black]

On Fri, Dec 2, 2011 at 1:14 PM, Graeme Russ <graeme.russ@gmail.com> wrote:

> Hi Gabe,
>
> On 30/11/11 17:07, Gabe Black wrote:
> > Signed-off-by: Gabe Black <gabeblack@chromium.org>
> > ---
> >  arch/x86/cpu/coreboot/sdram.c |   32 ++++++++++++++++++++++++++------
> >  arch/x86/include/asm/zimage.h |    5 +++++
> >  arch/x86/lib/zimage.c         |   10 ++++++++++
> >  3 files changed, 41 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/x86/cpu/coreboot/sdram.c
> b/arch/x86/cpu/coreboot/sdram.c
> > index b5b086b..ce73467 100644
> > --- a/arch/x86/cpu/coreboot/sdram.c
> > +++ b/arch/x86/cpu/coreboot/sdram.c
> > @@ -23,6 +23,8 @@
> >   */
> >
> >  #include <common.h>
> > +#include <malloc.h>
> > +#include <asm/e820.h>
> >  #include <asm/u-boot-x86.h>
> >  #include <asm/global_data.h>
> >  #include <asm/ic/coreboot/sysinfo.h>
> > @@ -30,18 +32,36 @@
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > +unsigned install_e820_map(unsigned max_entries, struct e820entry
> *entries)
> > +{
> > +     int i;
> > +
> > +     unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
> > +     if (num_entries < lib_sysinfo.n_memranges) {
> > +             printf("Warning: Limiting e820 map to %d entries.\n",
> > +                     num_entries);
> > +     }
> > +     for (i = 0; i < num_entries; i++) {
> > +             struct memrange *memrange = &lib_sysinfo.memrange[i];
> > +
> > +             entries[i].addr = memrange->base;
> > +             entries[i].size = memrange->size;
> > +             entries[i].type = memrange->type;
> > +     }
> > +     return num_entries;
> > +}
> > +
> >  int dram_init_f(void)
> >  {
> >       int i;
> >       phys_size_t ram_size = 0;
> > +
> >       for (i = 0; i < lib_sysinfo.n_memranges; i++) {
> > -             unsigned long long end = \
> > -                     lib_sysinfo.memrange[i].base +
> > -                     lib_sysinfo.memrange[i].size;
> > -             if (lib_sysinfo.memrange[i].type == CB_MEM_RAM &&
> > -                     end > ram_size) {
> > +             struct memrange *memrange = &lib_sysinfo.memrange[i];
> > +             unsigned long long end = memrange->base + memrange->size;
> > +
> > +             if (memrange->type == CB_MEM_RAM && end > ram_size)
> >                       ram_size = end;
> > -             }
> >       }
> >       gd->ram_size = ram_size;
> >       if (ram_size == 0)
>
> Please fold these changes to dram_init_f() into the second patch
>
> > diff --git a/arch/x86/include/asm/zimage.h
> b/arch/x86/include/asm/zimage.h
> > index a02637f..b172048 100644
> > --- a/arch/x86/include/asm/zimage.h
> > +++ b/arch/x86/include/asm/zimage.h
> > @@ -24,6 +24,8 @@
> >  #ifndef _ASM_ZIMAGE_H_
> >  #define _ASM_ZIMAGE_H_
> >
> > +#include <asm/e820.h>
> > +
> >  /* linux i386 zImage/bzImage header. Offsets relative to
> >   * the start of the image */
> >
> > @@ -65,6 +67,9 @@
> >  #define BZIMAGE_LOAD_ADDR  0x100000
> >  #define ZIMAGE_LOAD_ADDR   0x10000
> >
> > +/* Implementation defined function to install an e820 map. */
> > +unsigned install_e820_map(unsigned max_entries, struct e820entry *);
> > +
> >  void *load_zimage(char *image, unsigned long kernel_size,
> >                 unsigned long initrd_addr, unsigned long initrd_size,
> >                 int auto_boot);
> > diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
> > index 6843ff6..1fde13f 100644
> > --- a/arch/x86/lib/zimage.c
> > +++ b/arch/x86/lib/zimage.c
> > @@ -51,6 +51,16 @@
> >
> >  #define COMMAND_LINE_SIZE    2048
> >
> > +unsigned generic_install_e820_map(unsigned max_entries,
> > +                               struct e820entry *entries)
> > +{
> > +     return 0;
> > +}
> > +
> > +unsigned install_e820_map(unsigned max_entries,
> > +                       struct e820entry *entries)
> > +     __attribute__((weak, alias("generic_install_e820_map")));
> > +
> >  static void build_command_line(char *command_line, int auto_boot)
> >  {
> >       char *env_command_line;
>
> I think all of the e820 code can be moved into your 32-bit boot protocol
> patch series
>
> Regards,
>
> Graeme
>


The changes which gather e820 information from the coreboot tables don't
really have anything specifically to do with the zboot command. The e820
information could be gathered another way (or generated on the spot like
you're doing) and the e820 info could be consumed by something else like
the bootm command. They are not a single logical change and should not be
merged.

Gabe

[U-Boot] [PATCH 4/4] x86: Add infrastructure to extract an e820 table from the coreboot tables

[Graeme Russ]

Hi Gabe,

On 03/12/11 08:24, Gabe Black wrote:
> 
> 
> On Fri, Dec 2, 2011 at 1:14 PM, Graeme Russ <graeme.russ@gmail.com
> <mailto:graeme.russ@gmail.com>> wrote:
> 
>     Hi Gabe,
> 
>     On 30/11/11 17:07, Gabe Black wrote:
>     > Signed-off-by: Gabe Black <gabeblack@chromium.org
>     <mailto:gabeblack@chromium.org>>
>     > ---
>     >  arch/x86/cpu/coreboot/sdram.c |   32 ++++++++++++++++++++++++++------
>     >  arch/x86/include/asm/zimage.h |    5 +++++
>     >  arch/x86/lib/zimage.c         |   10 ++++++++++
>     >  3 files changed, 41 insertions(+), 6 deletions(-)
>     >
>     > diff --git a/arch/x86/cpu/coreboot/sdram.c
>     b/arch/x86/cpu/coreboot/sdram.c
>     > index b5b086b..ce73467 100644
>     > --- a/arch/x86/cpu/coreboot/sdram.c
>     > +++ b/arch/x86/cpu/coreboot/sdram.c
>     > @@ -23,6 +23,8 @@
>     >   */
>     >
>     >  #include <common.h>
>     > +#include <malloc.h>
>     > +#include <asm/e820.h>
>     >  #include <asm/u-boot-x86.h>
>     >  #include <asm/global_data.h>
>     >  #include <asm/ic/coreboot/sysinfo.h>
>     > @@ -30,18 +32,36 @@
>     >
>     >  DECLARE_GLOBAL_DATA_PTR;
>     >
>     > +unsigned install_e820_map(unsigned max_entries, struct e820entry
>     *entries)
>     > +{
>     > +     int i;
>     > +
>     > +     unsigned num_entries = min(lib_sysinfo.n_memranges, max_entries);
>     > +     if (num_entries < lib_sysinfo.n_memranges) {
>     > +             printf("Warning: Limiting e820 map to %d entries.\n",
>     > +                     num_entries);
>     > +     }
>     > +     for (i = 0; i < num_entries; i++) {
>     > +             struct memrange *memrange = &lib_sysinfo.memrange[i];
>     > +
>     > +             entries[i].addr = memrange->base;
>     > +             entries[i].size = memrange->size;
>     > +             entries[i].type = memrange->type;
>     > +     }
>     > +     return num_entries;
>     > +}
>     > +
>     >  int dram_init_f(void)
>     >  {
>     >       int i;
>     >       phys_size_t ram_size = 0;
>     > +
>     >       for (i = 0; i < lib_sysinfo.n_memranges; i++) {
>     > -             unsigned long long end = \
>     > -                     lib_sysinfo.memrange[i].base +
>     > -                     lib_sysinfo.memrange[i].size;
>     > -             if (lib_sysinfo.memrange[i].type == CB_MEM_RAM &&
>     > -                     end > ram_size) {
>     > +             struct memrange *memrange = &lib_sysinfo.memrange[i];
>     > +             unsigned long long end = memrange->base + memrange->size;
>     > +
>     > +             if (memrange->type == CB_MEM_RAM && end > ram_size)
>     >                       ram_size = end;
>     > -             }
>     >       }
>     >       gd->ram_size = ram_size;
>     >       if (ram_size == 0)
> 
>     Please fold these changes to dram_init_f() into the second patch
> 
>     > diff --git a/arch/x86/include/asm/zimage.h
>     b/arch/x86/include/asm/zimage.h
>     > index a02637f..b172048 100644
>     > --- a/arch/x86/include/asm/zimage.h
>     > +++ b/arch/x86/include/asm/zimage.h
>     > @@ -24,6 +24,8 @@
>     >  #ifndef _ASM_ZIMAGE_H_
>     >  #define _ASM_ZIMAGE_H_
>     >
>     > +#include <asm/e820.h>
>     > +
>     >  /* linux i386 zImage/bzImage header. Offsets relative to
>     >   * the start of the image */
>     >
>     > @@ -65,6 +67,9 @@
>     >  #define BZIMAGE_LOAD_ADDR  0x100000
>     >  #define ZIMAGE_LOAD_ADDR   0x10000
>     >
>     > +/* Implementation defined function to install an e820 map. */
>     > +unsigned install_e820_map(unsigned max_entries, struct e820entry *);
>     > +
>     >  void *load_zimage(char *image, unsigned long kernel_size,
>     >                 unsigned long initrd_addr, unsigned long initrd_size,
>     >                 int auto_boot);
>     > diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
>     > index 6843ff6..1fde13f 100644
>     > --- a/arch/x86/lib/zimage.c
>     > +++ b/arch/x86/lib/zimage.c
>     > @@ -51,6 +51,16 @@
>     >
>     >  #define COMMAND_LINE_SIZE    2048
>     >
>     > +unsigned generic_install_e820_map(unsigned max_entries,
>     > +                               struct e820entry *entries)
>     > +{
>     > +     return 0;
>     > +}
>     > +
>     > +unsigned install_e820_map(unsigned max_entries,
>     > +                       struct e820entry *entries)
>     > +     __attribute__((weak, alias("generic_install_e820_map")));
>     > +
>     >  static void build_command_line(char *command_line, int auto_boot)
>     >  {
>     >       char *env_command_line;
> 
>     I think all of the e820 code can be moved into your 32-bit boot protocol
>     patch series
> 
>     Regards,
> 
>     Graeme
> 
> 
> 
> The changes which gather e820 information from the coreboot tables don't
> really have anything specifically to do with the zboot command. The e820
> information could be gathered another way (or generated on the spot like
> you're doing) and the e820 info could be consumed by something else like
> the bootm command. They are not a single logical change and should not be
> merged.

Well to 32-bit boot protocol requires a function that fills out the e820
map which is what install_e820_map() does so, IMHO, they really belong
together. Maybe we fold the two patch series together (git does not care
for series of patches) as:

1) x86, coreboot: Import code from coreboot's libpayload to parse the
coreboot table
2) x86, coreboot: Determine the ram size using the coreboot tables
3) x86: Clean up the x86 zimage code in preparation to extend it
4) x86: Add support for booting Linux using the 32 bit boot protocol
5) x86, coreboot: Populate e820 tables from coreboot tables
6) x86: Refactor the zboot innards so they can be reused with a vboot image
7) x86: Add support for specifying an initrd with the zboot command

4) would include adding the generic_install_e820_map() function
5) would add the coreboot specific implementation

Regards,

Graeme