* [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules
@ 2011-12-14 22:47 Peter Barada
2011-12-15 0:15 ` Tom Rini
` (2 more replies)
0 siblings, 3 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-14 22:47 UTC (permalink / raw)
To: u-boot
From: Peter Barada <peterb@logicpd.com>
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
---
board/logicpd/omap3som/Makefile | 48 +++
board/logicpd/omap3som/config.mk | 33 ++
board/logicpd/omap3som/omap3logic.c | 566 +++++++++++++++++++++++++++++++++++
board/logicpd/omap3som/omap3logic.h | 35 +++
boards.cfg | 1 +
include/configs/omap3_logic.h | 356 ++++++++++++++++++++++
6 files changed, 1039 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/omap3som/Makefile
create mode 100644 board/logicpd/omap3som/config.mk
create mode 100644 board/logicpd/omap3som/omap3logic.c
create mode 100644 board/logicpd/omap3som/omap3logic.h
create mode 100644 include/configs/omap3_logic.h
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..ef0409f
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := omap3logic.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/config.mk b/board/logicpd/omap3som/config.mk
new file mode 100644
index 0000000..897b252
--- /dev/null
+++ b/board/logicpd/omap3som/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006 - 2008
+# Texas Instruments, <www.ti.com>
+#
+# EVM uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80400000
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..5c6e896
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,566 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Mux hsusb0_data5 as gpio_189 */
+#define MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX() \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4))
+
+/* Mux hsusb0_data5 as hasusb0_data5 */
+#define MUX_LOGIC_HSUSB0_DATA5_DATA5() \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0))
+
+/*
+ * Routine: logic_identify
+ * Description: Detect if we are running on a Logic or Torpedo.
+ * This can be done by GPIO_189. If its low after driving it high,
+ * then its a SOM LV, else Torpedo.
+ */
+unsigned int logic_identify(void)
+{
+ unsigned int val = 0;
+ u32 cpu_family = get_cpu_family();
+ int i;
+
+ MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX();
+
+ if (!gpio_request(189, "")) {
+
+ gpio_direction_output(189, 0);
+ gpio_set_value(189, 1);
+
+ /* Let it soak for a bit */
+ for (i = 0; i < 0x100; ++i)
+ asm("nop");
+
+ gpio_direction_input(189);
+ val = gpio_get_value(189);
+ gpio_free(189);
+
+ printf("Board:");
+ if (cpu_family == CPU_OMAP36XX) {
+ printf(" DM37xx");
+ if (val) {
+ printf(" Torpedo\n");
+ val = MACH_TYPE_DM3730_TORPEDO;
+ } else {
+ printf(" SOM LV\n");
+ val = MACH_TYPE_DM3730_SOM_LV;
+ }
+ } else {
+ printf(" OMAP35xx");
+ if (val) {
+ printf(" Torpedo\n");
+ val = MACH_TYPE_OMAP3_TORPEDO;
+ } else {
+ printf(" SOM LV\n");
+ val = MACH_TYPE_OMAP3530_LV_SOM;
+ }
+ }
+ }
+
+ MUX_LOGIC_HSUSB0_DATA5_DATA5();
+
+ return val;
+}
+
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+#define LOGIC_NET_GPMC_CONFIG1 0x00001000
+#define LOGIC_NET_GPMC_CONFIG2 0x00080801
+#define LOGIC_NET_GPMC_CONFIG3 0x00000000
+#define LOGIC_NET_GPMC_CONFIG4 0x08010801
+#define LOGIC_NET_GPMC_CONFIG5 0x00080a0a
+#define LOGIC_NET_GPMC_CONFIG6 0x03000280
+#define LOGIC_NET_GPMC_CONFIG7 0x00000848
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
+ writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
+ writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
+ writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
+ writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
+ writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
+ writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+}
+
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* board id for Linux */
+ gd->bd->bi_arch_number = logic_identify();
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ unsigned char enetaddr[6];
+
+#ifdef CONFIG_CMD_CACHE
+ dcache_enable();
+ printf("Data (writethrough) Cache is %s\n",
+ dcache_status() ? "ON" : "OFF");
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ return 0;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*SDRC*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
+ /*DSS*/
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
+ /*CAMERA*/
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
+ /*Audio Interface */
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Wireless LAN */
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Bluetooth*/
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Modem Interface */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
+
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Serial Interface*/
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+ /*Die to Die */
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..5b2ca66
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee
am3517_evm arm armv7 am3517evm logicpd omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_logic arm armv7 omap3som logicpd omap3
omap3_mvblx arm armv7 mvblx matrix_vision omap3
am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..3c7c821
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 35x/37x */
+#define CONFIG_OMAP3_LOGIC 1 /* working with Logic OMAP boards */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R /* misc_init_r sets up SMSC911x and
+ * dumps the die id */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+#define CONFIG_CMDLINE_EDITING 1 /* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK 1 /* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+
+#define CONFIG_L2_OFF 1 /* Keep L2 Cache Disabled */
+
+#define BOARD_LATE_INIT
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 2
+
+#define CONFIG_PREBOOT \
+ "echo ======================NOTICE============================;"\
+ "echo The u-boot environment is not set. - You are;" \
+ "echo required to set a valid display for your LCD panel.;" \
+ "echo Valid display options are:;" \
+ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
+ "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
+ "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
+ "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
+ "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
+ "echo \" vga[-16 OR -24] LCD VGA 640x480\";" \
+ "echo \" svga[-16 OR -24] LCD SVGA 800x600\";" \
+ "echo \" xga[-16 OR -24] LCD XGA 1024x768\";" \
+ "echo \" 720p[-16 OR -24] LCD 720P 1280x720\";" \
+ "echo \" sxga[-16 OR -24] LCD SXGA 1280x1024\";" \
+ "echo \" uxga[-16 OR -24] LCD UXGA 1600x1200\";" \
+ "echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;" \
+ "setenv display 15;" \
+ "setenv preboot;" \
+ "saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mmcdev=0\0" \
+ "autoboot=if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "run defaultboot;" \
+ "fi; " \
+ "else run defaultboot; fi\0" \
+ "defaultboot=run mmcramboot\0" \
+ "consoledevice=ttyO0\0" \
+ "display=15\0" \
+ "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+ "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+ "rotation=0\0" \
+ "vrfb_arg=if itest ${rotation} -ne 0; then " \
+ "setenv bootargs ${bootargs} omapfb.vrfb=y " \
+ "omapfb.rotate=${rotation}; " \
+ "fi\0" \
+ "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "${otherbootargs};" \
+ "run addmtdparts; " \
+ "run vrfb_arg\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo 'Running bootscript from mmc ...'; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=mmc rescan ${mmcdev}; " \
+ "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "ramdisksize=64000\0" \
+ "ramdiskaddr=0x82000000\0" \
+ "ramdiskimage=rootfs.ext2.gz.uboot\0" \
+ "ramargs=run setconsole; setenv bootargs console=${console} " \
+ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+ "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "run loaduimage; " \
+ "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP Logic # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-14 22:47 [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules Peter Barada
@ 2011-12-15 0:15 ` Tom Rini
2011-12-15 4:59 ` Peter Barada
2011-12-15 8:47 ` Igor Grinberg
2011-12-15 17:15 ` [U-Boot] [PATCH v2] " Peter Barada
2 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2011-12-15 0:15 UTC (permalink / raw)
To: u-boot
On Wed, Dec 14, 2011 at 3:47 PM, Peter Barada <peter.barada@logicpd.com> wrote:
> From: Peter Barada <peterb@logicpd.com>
>
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
We can't merge this with the existing am3517evm support? Also, have
you tried out SPL for this board yet? It'd probably be good to switch
from x-loader.
[snip]
> +++ b/board/logicpd/omap3som/config.mk
> +CONFIG_SYS_TEXT_BASE = 0x80400000
This should be in the config file.
> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
[snip]
> +unsigned int logic_identify(void)
Should be 'static'
> +{
> + ? ? ? unsigned int val = 0;
> + ? ? ? u32 cpu_family = get_cpu_family();
> + ? ? ? int i;
> +
> + ? ? ? MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX();
> +
> + ? ? ? if (!gpio_request(189, "")) {
> +
> + ? ? ? ? ? ? ? gpio_direction_output(189, 0);
> + ? ? ? ? ? ? ? gpio_set_value(189, 1);
> +
> + ? ? ? ? ? ? ? /* Let it soak for a bit */
> + ? ? ? ? ? ? ? for (i = 0; i < 0x100; ++i)
> + ? ? ? ? ? ? ? ? ? ? ? asm("nop");
Just use one of the existing delay functions?
> + ? ? ? ? ? ? ? printf("Board:");
> + ? ? ? ? ? ? ? if (cpu_family == CPU_OMAP36XX) {
> + ? ? ? ? ? ? ? ? ? ? ? printf(" DM37xx");
> + ? ? ? ? ? ? ? ? ? ? ? if (val) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf(" Torpedo\n");
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? val = MACH_TYPE_DM3730_TORPEDO;
> + ? ? ? ? ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf(" SOM LV\n");
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? val = MACH_TYPE_DM3730_SOM_LV;
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? printf(" OMAP35xx");
> + ? ? ? ? ? ? ? ? ? ? ? if (val) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf(" Torpedo\n");
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? val = MACH_TYPE_OMAP3_TORPEDO;
> + ? ? ? ? ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf(" SOM LV\n");
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? val = MACH_TYPE_OMAP3530_LV_SOM;
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? }
> + ? ? ? }
This could be condensed into just two checks, cpu_family and then val.
> +static void setup_net_chip(void)
> +{
> + ? ? ? struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> +
> + ? ? ? /* Configure GPMC registers */
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
> +
> + ? ? ? /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> + ? ? ? /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> + ? ? ? /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> + ? ? ? ? ? ? ? &ctrl_base->gpmc_nadv_ale);
Please switch this to enable_gpmc_cs_config(..) and note that config7
is computed so shouldn't be #defined.
[snip]
> +int board_late_init(void)
> +{
> + ? ? ? unsigned char enetaddr[6];
> +
> +#ifdef CONFIG_CMD_CACHE
> + ? ? ? dcache_enable();
> + ? ? ? printf("Data (writethrough) Cache is %s\n",
> + ? ? ? ? ? ? ? dcache_status() ? "ON" : "OFF");
> +#endif
> + ? ? ? return 0;
> +}
Cache should be defaulting to enabled already and enetaddr is unused,
so you could drop board_late_init.
> +
> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
> +int board_mmc_init(bd_t *bis)
> +{
> + ? ? ? omap_mmc_init(0);
> + ? ? ? return 0;
> +}
> +#endif
Just a one line return omap_mmc_init(0);
> +/*
> + * Routine: misc_init_r
> + * Description: Init ethernet (done here so udelay works)
> + */
> +int misc_init_r(void)
> +{
> +#if defined(CONFIG_CMD_NET)
> + ? ? ? setup_net_chip();
> +#endif
> +
> + ? ? ? dieid_num_r();
> +
> + ? ? ? return 0;
> +}
> +
> +
> +
> +int board_eth_init(bd_t *bis)
> +{
> + ? ? ? int rc = 0;
> +#ifdef CONFIG_SMC911X
> + ? ? ? rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + ? ? ? return rc;
> +}
Just return smc911x_..(...); and iirc you only need to provide
board_eth_init when CONFIG_CMD_NET or perhaps CONFIG_SMC911X is set.
[snip]
> +++ b/include/configs/omap3_logic.h
[snip]
> +#define CONFIG_ARMV7 ? ? ? ? ? 1 ? ? ? /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP ? ? ? ? ? ?1 ? ? ? /* in a TI OMAP core */
In this file at large, two problems. One, you've got 'dead' #defines
like CONFIG_ARMV7 and CONFIG_NET_MULTI (and probably others, there's
been a number of recent threads and patches removing stuff I think I
see you bringing back) and two the preferred syntax is just '#define
CONFIG_FOO' for on/off stuff.
Thanks!
--
Tom
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-15 0:15 ` Tom Rini
@ 2011-12-15 4:59 ` Peter Barada
0 siblings, 0 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-15 4:59 UTC (permalink / raw)
To: u-boot
On 12/14/2011 07:15 PM, Tom Rini wrote:
> On Wed, Dec 14, 2011 at 3:47 PM, Peter Barada <peter.barada@logicpd.com> wrote:
>> From: Peter Barada <peterb@logicpd.com>
>>
>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>> reference boards. It assumes U-boot is loaded to SDRAM with the
>> help of another small bootloader (x-load) running from SRAM.
> We can't merge this with the existing am3517evm support? Also, have
> you tried out SPL for this board yet? It'd probably be good to switch
> from x-loader.
>
>
At first glance this board file and the am3517evm board files look
close, but I think they will diverge shortly when I submit more patches
to deal with specific peripherals on these boards (such as dynamic
LCD/HDMI screen configuration based on environment variables).
I want to switch from x-loader to SPL, and will (when I can find time) -
and submit patches for SPL support then.
I'll incorporate your suggestions into a new version and resubmit the patch.
--
Peter Barada
peter.barada at logicpd.com
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-14 22:47 [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules Peter Barada
2011-12-15 0:15 ` Tom Rini
@ 2011-12-15 8:47 ` Igor Grinberg
2011-12-15 17:15 ` [U-Boot] [PATCH v2] " Peter Barada
2 siblings, 0 replies; 21+ messages in thread
From: Igor Grinberg @ 2011-12-15 8:47 UTC (permalink / raw)
To: u-boot
Hi Peter,
In addition to Tom's comments, several comments below:
On 12/15/11 00:47, Peter Barada wrote:
> From: Peter Barada <peterb@logicpd.com>
>
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> ---
> board/logicpd/omap3som/Makefile | 48 +++
> board/logicpd/omap3som/config.mk | 33 ++
> board/logicpd/omap3som/omap3logic.c | 566 +++++++++++++++++++++++++++++++++++
> board/logicpd/omap3som/omap3logic.h | 35 +++
> boards.cfg | 1 +
> include/configs/omap3_logic.h | 356 ++++++++++++++++++++++
> 6 files changed, 1039 insertions(+), 0 deletions(-)
> create mode 100644 board/logicpd/omap3som/Makefile
> create mode 100644 board/logicpd/omap3som/config.mk
> create mode 100644 board/logicpd/omap3som/omap3logic.c
> create mode 100644 board/logicpd/omap3som/omap3logic.h
> create mode 100644 include/configs/omap3_logic.h
>
> diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
> new file mode 100644
> index 0000000..ef0409f
> --- /dev/null
> +++ b/board/logicpd/omap3som/Makefile
> @@ -0,0 +1,48 @@
> +#
> +# (C) Copyright 2000, 2001, 2002
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS-y := omap3logic.o
> +
> +COBJS := $(sort $(COBJS-y))
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +clean:
> + rm -f $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
clean and distclean are obsolete in this directory level, please remove.
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> diff --git a/board/logicpd/omap3som/config.mk b/board/logicpd/omap3som/config.mk
> new file mode 100644
> index 0000000..897b252
> --- /dev/null
> +++ b/board/logicpd/omap3som/config.mk
> @@ -0,0 +1,33 @@
> +#
> +# (C) Copyright 2006 - 2008
> +# Texas Instruments, <www.ti.com>
> +#
> +# EVM uses OMAP3 (ARM-CortexA8) cpu
> +# see http://www.ti.com/ for more information on Texas Instruments
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +# Physical Address:
> +# 8000'0000 (bank0)
> +# A000/0000 (bank1)
> +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> +# (mem base + reserved)
> +
> +# For use with external or internal boots.
> +CONFIG_SYS_TEXT_BASE = 0x80400000
As Tom already said, this should be in the board config file
and this file should be removed completely.
> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
> new file mode 100644
> index 0000000..5c6e896
> --- /dev/null
> +++ b/board/logicpd/omap3som/omap3logic.c
> @@ -0,0 +1,566 @@
> +/*
> + * (C) Copyright 2011
> + * Logic Product Development <www.logicpd.com>
> + *
> + * Author :
> + * Peter Barada <peter.barada@logicpd.com>
> + *
> + * Derived from Beagle Board and 3430 SDP code by
> + * Richard Woodruff <r-woodruff2@ti.com>
> + * Syed Mohammed Khasim <khasim@ti.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
I vote for removing the postal address,
because it is subject to change and you will not follow it,
but it is not a blocker.
[...]
> +/*
> + * Routine: logic_identify
> + * Description: Detect if we are running on a Logic or Torpedo.
> + * This can be done by GPIO_189. If its low after driving it high,
> + * then its a SOM LV, else Torpedo.
> + */
> +unsigned int logic_identify(void)
> +{
> + unsigned int val = 0;
> + u32 cpu_family = get_cpu_family();
You only use this once, so IMO can be inlined.
> + int i;
> +
> + MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX();
> +
> + if (!gpio_request(189, "")) {
This does not look good... can it be:
if (gpio_request(...) == 0)
and also please provide a label with a description
instead of an empty one.
> +
> + gpio_direction_output(189, 0);
> + gpio_set_value(189, 1);
> +
> + /* Let it soak for a bit */
> + for (i = 0; i < 0x100; ++i)
> + asm("nop");
> +
> + gpio_direction_input(189);
> + val = gpio_get_value(189);
> + gpio_free(189);
> +
> + printf("Board:");
> + if (cpu_family == CPU_OMAP36XX) {
> + printf(" DM37xx");
> + if (val) {
> + printf(" Torpedo\n");
> + val = MACH_TYPE_DM3730_TORPEDO;
> + } else {
> + printf(" SOM LV\n");
> + val = MACH_TYPE_DM3730_SOM_LV;
> + }
> + } else {
> + printf(" OMAP35xx");
> + if (val) {
> + printf(" Torpedo\n");
> + val = MACH_TYPE_OMAP3_TORPEDO;
> + } else {
> + printf(" SOM LV\n");
> + val = MACH_TYPE_OMAP3530_LV_SOM;
> + }
> + }
> + }
> +
> + MUX_LOGIC_HSUSB0_DATA5_DATA5();
> +
> + return val;
> +}
The whole function looks like checkboard(), isn't it?
I think it should be then.
[...]
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> +
> + /* board id for Linux */
> + gd->bd->bi_arch_number = logic_identify();
This also can be moved to checkboard().
> +
> + /* boot param addr */
> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> +
> + return 0;
> +}
[...]
> +/*
> + * Routine: misc_init_r
> + * Description: Init ethernet (done here so udelay works)
> + */
> +int misc_init_r(void)
> +{
> +#if defined(CONFIG_CMD_NET)
> + setup_net_chip();
> +#endif
Can this be done in board_eth_init()?
So the net init code will be close to each other?
> +
> + dieid_num_r();
> +
> + return 0;
> +}
> +
> +
> +
Three empty lines?
There should be only one line between functions.
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_SMC911X
> + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return rc;
> +}
board_eth_init() has a weak implementation, so
I think it would be much nicer:
#ifdef CONFIG_SMC911X
int board_eth_init(bd_t *bis)
{
setup_net_chip();
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
> +
> +
> +
Again three empty lines?
> +/*
> + * IEN - Input Enable
> + * IDIS - Input Disable
> + * PTD - Pull type Down
> + * PTU - Pull type Up
> + * DIS - Pull type selection is inactive
> + * EN - Pull type selection is active
> + * M0 - Mode 0
> + * The commented string gives the final mux configuration for that pin
> + */
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
> + /*SDRC*/
Alignment...
[...]
> + /*GPMC*/
same here, comments must be aligned to code.
[...]
> + /*DSS*/
ditto
[...]
> + /*CAMERA*/
ditto
[...]
> + /*Audio Interface */
ditto
> + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
> +
> + /*Expansion card */
ditto
> + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
> + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Wireless LAN */
ditto
> + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Bluetooth*/
ditto
> + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Modem Interface */
ditto
> + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
> + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
> + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
> + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
> + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
> +
> + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Serial Interface*/
ditto
[...]
> + /*Control and debug */
ditto
[...]
> + /*Die to Die */
ditto
[...]
> +}
I think this function is *much better* than the mux config done .h file.
Good job!
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-14 22:47 [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules Peter Barada
2011-12-15 0:15 ` Tom Rini
2011-12-15 8:47 ` Igor Grinberg
@ 2011-12-15 17:15 ` Peter Barada
2011-12-15 18:30 ` Tom Rini
2 siblings, 1 reply; 21+ messages in thread
From: Peter Barada @ 2011-12-15 17:15 UTC (permalink / raw)
To: u-boot
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
Changes for V2:
Rework logic_identify() into identify_board() - can't use checkboard()
since its enabled by CONFIG_DISPLAY_BOARDINFO
Properly indent comments in set_muxconf_regs()
Move setup_net_chip() call from misc_init_r to board_eth_init()
Remove triple empty line spacing
Pass gpio_request(189) non-empty description
Remove board/logicpd/omap3som/config.mk
Remove clean/distclean from board/logicpd/omap3som/Makefile
Modify board_mmc_init() to be one line function
Modify include/configs/omap3_logic.h to use on/off #defines
board/logicpd/omap3som/Makefile | 42 +++
board/logicpd/omap3som/omap3logic.c | 582 +++++++++++++++++++++++++++++++++++
board/logicpd/omap3som/omap3logic.h | 35 ++
boards.cfg | 1 +
include/configs/omap3_logic.h | 359 +++++++++++++++++++++
5 files changed, 1019 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/omap3som/Makefile
create mode 100644 board/logicpd/omap3som/omap3logic.c
create mode 100644 board/logicpd/omap3som/omap3logic.h
create mode 100644 include/configs/omap3_logic.h
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..75e237b
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := omap3logic.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..0411adb
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,582 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Mux hsusb0_data5 as gpio_189 */
+#define MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX() \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4))
+
+/* Mux hsusb0_data5 as hasusb0_data5 */
+#define MUX_LOGIC_HSUSB0_DATA5_DATA5() \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0))
+
+/* two dimensional array of Linux machine IDs; row it selected based on CPU,
+ * column is slected based on hsusb0_data5 having pulldown resistor */
+static struct board_id {
+ char *name;
+ int machine_id;
+} boards[2][2] = {
+ {
+ {
+ .name = "OMAP35xx SOM LV",
+ .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ },
+ {
+ .name = "OMAP35xx Torpedo",
+ .machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ },
+ },
+ {
+ {
+ .name = "DM37xx SOM LV",
+ .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ },
+ {
+ .name = "DM37xx Torpedo",
+ .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ },
+ },
+};
+
+/*
+ * Routine: identify_board
+ * Description: Detect if we are running on a Logic or Torpedo and which
+ * variant (omap35x/dm37x). Check gpio_189 - if its low after
+ * driving it high, then its a SOM LV, else a Torpedo.
+ */
+static int identify_board(void)
+{
+ unsigned int val = 0;
+ u32 cpu_family = get_cpu_family();
+ int i;
+ struct board_id *board;
+
+ MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX();
+
+ if (gpio_request(189, "husb0_data5.gpio_189") == 0) {
+
+ gpio_direction_output(189, 0);
+ gpio_set_value(189, 1);
+
+ /* Let it soak for a bit */
+ for (i = 0; i < 0x100; ++i)
+ asm("nop");
+
+ gpio_direction_input(189);
+ val = gpio_get_value(189);
+ gpio_free(189);
+
+
+ board = &boards[!!(cpu_family == CPU_OMAP36XX)][!!val];
+
+ printf("Board: %s\n", board->name);
+ gd->bd->bi_arch_number = board->machine_id;
+
+#if 0
+ if (cpu_family == CPU_OMAP36XX) {
+ printf(" DM37xx");
+ if (val) {
+ printf(" Torpedo\n");
+ val = MACH_TYPE_DM3730_TORPEDO;
+ } else {
+ printf(" SOM LV\n");
+ val = MACH_TYPE_DM3730_SOM_LV;
+ }
+ } else {
+ printf(" OMAP35xx");
+ if (val) {
+ printf(" Torpedo\n");
+ val = MACH_TYPE_OMAP3_TORPEDO;
+ } else {
+ printf(" SOM LV\n");
+ val = MACH_TYPE_OMAP3530_LV_SOM;
+ }
+ }
+#endif
+ }
+
+ MUX_LOGIC_HSUSB0_DATA5_DATA5();
+
+
+ return 0;
+}
+
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+#define LOGIC_NET_GPMC_CONFIG1 0x00001000
+#define LOGIC_NET_GPMC_CONFIG2 0x00080801
+#define LOGIC_NET_GPMC_CONFIG3 0x00000000
+#define LOGIC_NET_GPMC_CONFIG4 0x08010801
+#define LOGIC_NET_GPMC_CONFIG5 0x00080a0a
+#define LOGIC_NET_GPMC_CONFIG6 0x03000280
+#define LOGIC_NET_GPMC_CONFIG7 0x00000848
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
+ writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
+ writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
+ writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
+ writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
+ writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
+ writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /* Identify the board/cpu combination and set arch_number */
+ identify_board();
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+ dieid_num_r();
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*SDRC*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
+ /*DSS*/
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
+ /*CAMERA*/
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
+ /*Audio Interface */
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Wireless LAN */
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Bluetooth*/
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Modem Interface */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
+
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Serial Interface*/
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+ /*Die to Die */
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..5b2ca66
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee
am3517_evm arm armv7 am3517evm logicpd omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_logic arm armv7 omap3som logicpd omap3
omap3_mvblx arm armv7 mvblx matrix_vision omap3
am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..3ab4edb
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#if 0
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#endif
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#if 0
+#define CONFIG_OMAP3430 1 /* which is in a 35x/37x */
+#endif
+#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+#define CONFIG_SYS_TEXT_BASE 0x80400000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+
+#define CONFIG_L2_OFF /* Keep L2 Cache Disabled */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 2
+
+#define CONFIG_PREBOOT \
+ "echo ======================NOTICE============================;"\
+ "echo The u-boot environment is not set. - You are;" \
+ "echo required to set a valid display for your LCD panel.;" \
+ "echo Valid display options are:;" \
+ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
+ "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
+ "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
+ "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
+ "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
+ "echo \" vga[-16 OR -24] LCD VGA 640x480\";" \
+ "echo \" svga[-16 OR -24] LCD SVGA 800x600\";" \
+ "echo \" xga[-16 OR -24] LCD XGA 1024x768\";" \
+ "echo \" 720p[-16 OR -24] LCD 720P 1280x720\";" \
+ "echo \" sxga[-16 OR -24] LCD SXGA 1280x1024\";" \
+ "echo \" uxga[-16 OR -24] LCD UXGA 1600x1200\";" \
+ "echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;" \
+ "setenv display 15;" \
+ "setenv preboot;" \
+ "saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mmcdev=0\0" \
+ "autoboot=if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "run defaultboot;" \
+ "fi; " \
+ "else run defaultboot; fi\0" \
+ "defaultboot=run mmcramboot\0" \
+ "consoledevice=ttyO0\0" \
+ "display=15\0" \
+ "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+ "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+ "rotation=0\0" \
+ "vrfb_arg=if itest ${rotation} -ne 0; then " \
+ "setenv bootargs ${bootargs} omapfb.vrfb=y " \
+ "omapfb.rotate=${rotation}; " \
+ "fi\0" \
+ "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "${otherbootargs};" \
+ "run addmtdparts; " \
+ "run vrfb_arg\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo 'Running bootscript from mmc ...'; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=mmc rescan ${mmcdev}; " \
+ "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "ramdisksize=64000\0" \
+ "ramdiskaddr=0x82000000\0" \
+ "ramdiskimage=rootfs.ext2.gz.uboot\0" \
+ "ramargs=run setconsole; setenv bootargs console=${console} " \
+ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+ "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "run loaduimage; " \
+ "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP Logic # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-15 17:15 ` [U-Boot] [PATCH v2] " Peter Barada
@ 2011-12-15 18:30 ` Tom Rini
2011-12-16 6:09 ` Peter Barada
0 siblings, 1 reply; 21+ messages in thread
From: Tom Rini @ 2011-12-15 18:30 UTC (permalink / raw)
To: u-boot
On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
#if 0'd code isn't allowed for merging so I assume this is an RFC :)
> + ? ? ? ? ? ? ? /* Let it soak for a bit */
> + ? ? ? ? ? ? ? for (i = 0; i < 0x100; ++i)
> + ? ? ? ? ? ? ? ? ? ? ? asm("nop");
Can we just use a sdelay(...) here? And in the whole function you
haven't addressed Igor's comment (unless it's incoming and I just
haven't gotten the email yet) about this just being checkboard().
> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> +#define LOGIC_NET_GPMC_CONFIG1 ?0x00001000
> +#define LOGIC_NET_GPMC_CONFIG2 ?0x00080801
> +#define LOGIC_NET_GPMC_CONFIG3 ?0x00000000
> +#define LOGIC_NET_GPMC_CONFIG4 ?0x08010801
> +#define LOGIC_NET_GPMC_CONFIG5 ?0x00080a0a
> +#define LOGIC_NET_GPMC_CONFIG6 ?0x03000280
> +#define LOGIC_NET_GPMC_CONFIG7 ?0x00000848
> +
> +/*
> + * Routine: setup_net_chip
> + * Description: Setting up the configuration GPMC registers specific to the
> + * ? ? ? ? ? ? Ethernet hardware.
> + */
> +static void setup_net_chip(void)
> +{
> + ? ? ? struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> +
> + ? ? ? /* Configure GPMC registers */
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
> + ? ? ? writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
> +
> + ? ? ? /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> + ? ? ? /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> + ? ? ? /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> + ? ? ? ? ? ? ? &ctrl_base->gpmc_nadv_ale);
> +
> +}
Or this just being an enable_gpmc_cs_config call.
> +int misc_init_r(void)
> +{
> +
> + ? ? ? dieid_num_r();
> +
> + ? ? ? return 0;
> +}
Extra whitespace. I think checkpatch.pl will catch this so please run
your patch through checkpatch.pl, roughly like this:
$ git format-patch -1
$ ./tools/checkpatch.pl 0001-whatever-its-called.patch
[snip]
> +#define CONFIG_L2_OFF ? ? ? ? ? ? ? ? ?/* Keep L2 Cache Disabled */
Why do we want to do this?
[snip]
> +#define CONFIG_SYS_MAXARGS ? ? ? ? ? ? 64 ? ? ?/* max number of command args */
This is very very large and probably doesn't need to be. This is the
number of arguments to the u-boot commands, not to the linux kernel.
Thanks.
--
Tom
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-15 18:30 ` Tom Rini
@ 2011-12-16 6:09 ` Peter Barada
2011-12-16 16:28 ` Tom Rini
2011-12-18 9:00 ` [U-Boot] [PATCH v2] " Igor Grinberg
0 siblings, 2 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-16 6:09 UTC (permalink / raw)
To: u-boot
On 12/15/2011 01:30 PM, Tom Rini wrote:
> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>> reference boards. It assumes U-boot is loaded to SDRAM with the
>> help of another small bootloader (x-load) running from SRAM.
> #if 0'd code isn't allowed for merging so I assume this is an RFC :)
My bad - sent the wrong patch. I'll update and send again.
>> + /* Let it soak for a bit */
>> + for (i = 0; i < 0x100; ++i)
>> + asm("nop");
> Can we just use a sdelay(...) here? And in the whole function you
> haven't addressed Igor's comment (unless it's incoming and I just
> haven't gotten the email yet) about this just being checkboard().
Done - "sdelay(0x100)" instead of the delay loop.
As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
a checkboard() function that is called early (before relocation) that
prints out the banner. I tried to make that a weak alias and override
it in my board file, but when its called, gd->bd is not setup so that
code aborts when it tries to set gd->bd->bi_arch_number. I then tried
storing the value in a global and then set gd->bd->bi_arch_number in
board_init(), but between the call to checkboard() and board_init() the
BSS section is zeroed. If I stored/load the computed bi_arch_number
into a non-zero static value it works, but I feel that is really fragile.
Remember that identify_board() not only prints a banner but also
determines one of four machine IDs passed to the linux kernel to
identify which of the variants its running on.
>> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
>> +#define LOGIC_NET_GPMC_CONFIG1 0x00001000
>> +#define LOGIC_NET_GPMC_CONFIG2 0x00080801
>> +#define LOGIC_NET_GPMC_CONFIG3 0x00000000
>> +#define LOGIC_NET_GPMC_CONFIG4 0x08010801
>> +#define LOGIC_NET_GPMC_CONFIG5 0x00080a0a
>> +#define LOGIC_NET_GPMC_CONFIG6 0x03000280
>> +#define LOGIC_NET_GPMC_CONFIG7 0x00000848
>> +
>> +/*
>> + * Routine: setup_net_chip
>> + * Description: Setting up the configuration GPMC registers specific to the
>> + * Ethernet hardware.
>> + */
>> +static void setup_net_chip(void)
>> +{
>> + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
>> +
>> + /* Configure GPMC registers */
>> + writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1);
>> + writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2);
>> + writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3);
>> + writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4);
>> + writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5);
>> + writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6);
>> + writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7);
>> +
>> + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
>> + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
>> + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
>> + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
>> + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
>> + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
>> + &ctrl_base->gpmc_nadv_ale);
>> +
>> +}
> Or this just being an enable_gpmc_cs_config call.
Done.
>> +int misc_init_r(void)
>> +{
>> +
>> + dieid_num_r();
>> +
>> + return 0;
>> +}
> Extra whitespace. I think checkpatch.pl will catch this so please run
> your patch through checkpatch.pl, roughly like this:
> $ git format-patch -1
> $ ./tools/checkpatch.pl 0001-whatever-its-called.patch
I rand checkpatch.pl over the result of "git diff --cached" and it
didn't complain about the emty line after the open brace. I've removed it.
> [snip]
>> +#define CONFIG_L2_OFF /* Keep L2 Cache Disabled */
> Why do we want to do this?
This is a holdover from a previous verison ofu-boot (2010.06) where I
added LCD/HDMI support for up to a 720p 32bpp display and when I did
that the kernel wouldn't start w/o disabling L2 in u-boot (possibly
because the reserved memory for the display in u-boot alone is larger
than the L2 cache in a OMAP35x/DM37x), but I never figured out why it
failed. I've removed it and will readdress when I add in the LCD/HDMI
support.
> [snip]
>> +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
> This is very very large and probably doesn't need to be. This is the
> number of arguments to the u-boot commands, not to the linux kernel.
You're right, yet another holdover from an older version of u-boot.
I've reduced it 16 to match up with most of the other boards.
So the big question before I submit V3 of this patch is whether to
include overriding OMAP3's checkboard() function or to use
identify_board() as is to compute bi_arch_number... I can do it either
way, but don't want to waste anyone's time (with the wrong method).
Thanks in advance!
--
Peter Barada
peter.barada at logicpd.com
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 6:09 ` Peter Barada
@ 2011-12-16 16:28 ` Tom Rini
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
2011-12-18 9:00 ` [U-Boot] [PATCH v2] " Igor Grinberg
1 sibling, 1 reply; 21+ messages in thread
From: Tom Rini @ 2011-12-16 16:28 UTC (permalink / raw)
To: u-boot
On Thu, Dec 15, 2011 at 11:09 PM, Peter Barada <peter.barada@logicpd.com> wrote:
> On 12/15/2011 01:30 PM, Tom Rini wrote:
>> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>>> reference boards. It assumes U-boot is loaded to SDRAM with the
>>> help of another small bootloader (x-load) running from SRAM.
>> #if 0'd code isn't allowed for merging so I assume this is an RFC :)
> My bad - sent the wrong patch. ?I'll update and send again.
>>> + ? ? ? ? ? ? ? /* Let it soak for a bit */
>>> + ? ? ? ? ? ? ? for (i = 0; i < 0x100; ++i)
>>> + ? ? ? ? ? ? ? ? ? ? ? asm("nop");
>> Can we just use a sdelay(...) here? ?And in the whole function you
>> haven't addressed Igor's comment (unless it's incoming and I just
>> haven't gotten the email yet) about this just being checkboard().
> Done - "sdelay(0x100)" instead of the delay loop.
Great, thanks.
> As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> a checkboard() function that is called early (before relocation) that
> prints out the banner. ?I tried to make that a weak alias and override
> it in my board file, but when its called, gd->bd is not setup so that
> code aborts when it tries to set gd->bd->bi_arch_number. ?I then tried
> storing the value in a global and then set gd->bd->bi_arch_number in
> board_init(), but between the call to checkboard() and board_init() the
> BSS section is zeroed. ?If I stored/load the computed bi_arch_number
> into a non-zero static value it works, but I feel that is really fragile.
>
> Remember that identify_board() not only prints a banner but also
> determines one of four machine IDs passed to the linux kernel to
> identify which of the variants its running on.
[snip]
> So the big question before I submit V3 of this patch is whether to
> include overriding OMAP3's checkboard() function or to use
> identify_board() as is to compute bi_arch_number... ?I can do it either
> way, but don't want to waste anyone's time (with the wrong method).
OK, after re-reading (and mentally applying the changes you said
you've got) the patches, along with Igor's comments on v1, just inline
your identify logic to board_init()
--
Tom
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 16:28 ` Tom Rini
@ 2011-12-16 20:31 ` Peter Barada
2011-12-16 20:33 ` Peter Barada
` (3 more replies)
0 siblings, 4 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-16 20:31 UTC (permalink / raw)
To: u-boot
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
---
Changes for V3:
Inline identify_board() into board_init()
Remove triple empty lines
Use sdelay() instead of naked delay loop
Use enable_gpmc_cs_config() to setup GPMC CS1 access to LAN92xx
Remove CONFIG_L2_OFF - holdover from previous work in u-boot-2011.06
where adding 270p 32bpp frambuffer support cause failure while
booting linux kernel. Will address when I add video support
Reduce CONFIG_SYS_MAXARGS to 16
Changes for V2:
Rework logic_identify() into identify_board() - can't use checkboard()
since its enabled by CONFIG_DISPLAY_BOARDINFO
Properly indent comments in set_muxconf_regs()
Move setup_net_chip() call from misc_init_r to board_eth_init()
Remove triple empty line spacing
Pass gpio_request(189) non-empty description
Remove board/logicpd/omap3som/config.mk
Remove clean/distclean from board/logicpd/omap3som/Makefile
Modify board_mmc_init() to be one line function
Modify include/configs/omap3_logic.h to use on/off #defines
board/logicpd/omap3som/Makefile | 42 +++
board/logicpd/omap3som/omap3logic.c | 523 +++++++++++++++++++++++++++++++++++
board/logicpd/omap3som/omap3logic.h | 35 +++
boards.cfg | 1 +
include/configs/omap3_logic.h | 351 +++++++++++++++++++++++
5 files changed, 952 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/omap3som/Makefile
create mode 100644 board/logicpd/omap3som/omap3logic.c
create mode 100644 board/logicpd/omap3som/omap3logic.h
create mode 100644 include/configs/omap3_logic.h
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..75e237b
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := omap3logic.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..eb051db
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor */
+static struct board_id {
+ char *name;
+ int machine_id;
+} boards[2][2] = {
+ {
+ {
+ .name = "OMAP35xx SOM LV",
+ .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ },
+ {
+ .name = "OMAP35xx Torpedo",
+ .machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ },
+ },
+ {
+ {
+ .name = "DM37xx SOM LV",
+ .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ },
+ {
+ .name = "DM37xx Torpedo",
+ .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ },
+ },
+};
+
+#define GPIO_189 189 /* hsusb0_data5 pin that has a pullup on the SOM LV */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ struct board_id *board;
+ unsigned int val;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /*
+ * To identify between a SOM LV and Torpedo module,
+ * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
+ * Drive the pin (and let it soak), then read it back.
+ * If the pin is still high its a Torpedo. If low its a SOM LV
+ */
+
+ /* Mux hsusb0_data5 as a GPIO */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
+
+ if (gpio_request(GPIO_189, "husb0_data5.gpio_189") == 0) {
+
+ /* Drive GPIO_189 - the pulldown resistor on the SOM LV
+ * will drain the voltage */
+ gpio_direction_output(GPIO_189, 0);
+ gpio_set_value(GPIO_189, 1);
+
+ /* Let it soak for a bit */
+ sdelay(0x100);
+
+ /* Read state of GPIO_189 as an input and if its set.
+ * If so the board is a Torpedo */
+ gpio_direction_input(GPIO_189);
+ val = gpio_get_value(GPIO_189);
+ gpio_free(GPIO_189);
+
+ board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
+ printf("Board: %s\n", board->name);
+
+ /* Set the machine_id passed to Linux */
+ gd->bd->bi_arch_number = board->machine_id;
+ }
+
+ /* restore hsusb0_data5 pin as hsusb0_data5 */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+ dieid_num_r();
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+static const u32 gpmc_lan92xx_config[] = {
+ 0x00001000,
+ 0x00080801,
+ 0x00000000,
+ 0x08010801,
+ 0x00080a0a,
+ 0x03000280,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*SDRC*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
+ /*DSS*/
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
+ /*CAMERA*/
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
+ /*Audio Interface */
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Wireless LAN */
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Bluetooth*/
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Modem Interface */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
+
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Serial Interface*/
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+ /*Die to Die */
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..5b2ca66
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee
am3517_evm arm armv7 am3517evm logicpd omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_logic arm armv7 omap3som logicpd omap3
omap3_mvblx arm armv7 mvblx matrix_vision omap3
am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..d741c61
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+#define CONFIG_SYS_TEXT_BASE 0x80400000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 2
+
+#define CONFIG_PREBOOT \
+ "echo ======================NOTICE============================;"\
+ "echo The u-boot environment is not set. - You are;" \
+ "echo required to set a valid display for your LCD panel.;" \
+ "echo Valid display options are:;" \
+ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
+ "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
+ "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
+ "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
+ "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
+ "echo \" vga[-16 OR -24] LCD VGA 640x480\";" \
+ "echo \" svga[-16 OR -24] LCD SVGA 800x600\";" \
+ "echo \" xga[-16 OR -24] LCD XGA 1024x768\";" \
+ "echo \" 720p[-16 OR -24] LCD 720P 1280x720\";" \
+ "echo \" sxga[-16 OR -24] LCD SXGA 1280x1024\";" \
+ "echo \" uxga[-16 OR -24] LCD UXGA 1600x1200\";" \
+ "echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;" \
+ "setenv display 15;" \
+ "setenv preboot;" \
+ "saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mmcdev=0\0" \
+ "autoboot=if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "run defaultboot;" \
+ "fi; " \
+ "else run defaultboot; fi\0" \
+ "defaultboot=run mmcramboot\0" \
+ "consoledevice=ttyO0\0" \
+ "display=15\0" \
+ "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+ "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+ "rotation=0\0" \
+ "vrfb_arg=if itest ${rotation} -ne 0; then " \
+ "setenv bootargs ${bootargs} omapfb.vrfb=y " \
+ "omapfb.rotate=${rotation}; " \
+ "fi\0" \
+ "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "${otherbootargs};" \
+ "run addmtdparts; " \
+ "run vrfb_arg\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo 'Running bootscript from mmc ...'; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=mmc rescan ${mmcdev}; " \
+ "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "ramdisksize=64000\0" \
+ "ramdiskaddr=0x82000000\0" \
+ "ramdiskimage=rootfs.ext2.gz.uboot\0" \
+ "ramargs=run setconsole; setenv bootargs console=${console} " \
+ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+ "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "run loaduimage; " \
+ "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP Logic # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* __CONFIG_H */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
@ 2011-12-16 20:33 ` Peter Barada
2011-12-16 22:43 ` Tom Rini
` (2 subsequent siblings)
3 siblings, 0 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-16 20:33 UTC (permalink / raw)
To: u-boot
On 12/16/2011 03:31 PM, Peter Barada wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
[snip]
My apologies, I forgot to change the subject to [PATCH V3], but as the
commentary indicates, it is V3. I'm still getting used to git send-email...
--
Peter Barada
peter.barada at logicpd.com
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
2011-12-16 20:33 ` Peter Barada
@ 2011-12-16 22:43 ` Tom Rini
2011-12-17 20:44 ` Wolfgang Denk
2011-12-18 9:16 ` Igor Grinberg
3 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2011-12-16 22:43 UTC (permalink / raw)
To: u-boot
On Fri, Dec 16, 2011 at 1:31 PM, Peter Barada <peter.barada@logicpd.com> wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
[snip]
> +#ifdef CONFIG_SMC911X
> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> +static const u32 gpmc_lan92xx_config[] = {
> + ? ? ? 0x00001000,
> + ? ? ? 0x00080801,
> + ? ? ? 0x00000000,
> + ? ? ? 0x08010801,
> + ? ? ? 0x00080a0a,
> + ? ? ? 0x03000280,
> +};
The correct form here is #define NET_LAN92XX_GPMC_CONFIGn 0x... in
board.h and then ref them here.
And feel free to wait a little before spinning v4 incase others have
comments. Assuming it's just this (or some other trivial comments)
that change in v4 I'll put that v4 into u-boot-ti/next early next
week. Thanks for turning around on the feedback quickly!
--
Tom
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
2011-12-16 20:33 ` Peter Barada
2011-12-16 22:43 ` Tom Rini
@ 2011-12-17 20:44 ` Wolfgang Denk
2011-12-18 9:16 ` Igor Grinberg
3 siblings, 0 replies; 21+ messages in thread
From: Wolfgang Denk @ 2011-12-17 20:44 UTC (permalink / raw)
To: u-boot
Dear Peter Barada,
In message <1324067511-14142-1-git-send-email-peter.barada@logicpd.com> you wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
...
> board/logicpd/omap3som/Makefile | 42 +++
> board/logicpd/omap3som/omap3logic.c | 523 +++++++++++++++++++++++++++++++++++
> board/logicpd/omap3som/omap3logic.h | 35 +++
> boards.cfg | 1 +
> include/configs/omap3_logic.h | 351 +++++++++++++++++++++++
> 5 files changed, 952 insertions(+), 0 deletions(-)
> create mode 100644 board/logicpd/omap3som/Makefile
> create mode 100644 board/logicpd/omap3som/omap3logic.c
> create mode 100644 board/logicpd/omap3som/omap3logic.h
> create mode 100644 include/configs/omap3_logic.h
Entry to MAINTAINERS missing.
> +/* two dimensional array of strucures containining board name and Linux
> + * machine IDs; row it selected based on CPU column is slected based
> + * on hsusb0_data5 pin having a pulldown resistor */
Incorrect multiline comment style. Please fix globally.
> +#ifdef CONFIG_SMC911X
> +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
> +static const u32 gpmc_lan92xx_config[] = {
> + 0x00001000,
> + 0x00080801,
> + 0x00000000,
> + 0x08010801,
> + 0x00080a0a,
> + 0x03000280,
> +};
And what exactly is the meaning of these magic numbers?
> +#define CONFIG_HARD_I2C 1
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#define CONFIG_SYS_I2C_SLAVE 1
> +#define CONFIG_SYS_I2C_BUS 0
> +#define CONFIG_SYS_I2C_BUS_SELECT 1
> +#define CONFIG_I2C_MULTI_BUS 1
> +#define CONFIG_DRIVER_OMAP34XX_I2C 1
Please do not define values for macros that only switch on a feature.
...
> +#define CONFIG_PREBOOT \
> + "echo ======================NOTICE============================;"\
> + "echo The u-boot environment is not set. - You are;" \
> + "echo required to set a valid display for your LCD panel.;" \
> + "echo Valid display options are:;" \
> + "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
> + "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
> + "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
> + "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
> + "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
> + "echo \" vga[-16 OR -24] LCD VGA 640x480\";" \
> + "echo \" svga[-16 OR -24] LCD SVGA 800x600\";" \
> + "echo \" xga[-16 OR -24] LCD XGA 1024x768\";" \
> + "echo \" 720p[-16 OR -24] LCD 720P 1280x720\";" \
> + "echo \" sxga[-16 OR -24] LCD SXGA 1280x1024\";" \
> + "echo \" uxga[-16 OR -24] LCD UXGA 1600x1200\";" \
> + "echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;" \
> + "setenv display 15;" \
Strange. First you ask the user to set a valid display type, and then
you hard-set it to some predefined value. What's the reationale
behind that?
> + "setenv preboot;" \
> + "saveenv;"
Would it not be better to erase the preboot setting only after some
display type definition was entered and saved _by_the_user_ ?
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
Incorrect multiline comment style. Please fix globally.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If all the Chinese simultaneously jumped into the Pacific off a 10
foot platform erected 10 feet off their coast, it would cause a tidal
wave that would destroy everything in this country west of Nebraska.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 6:09 ` Peter Barada
2011-12-16 16:28 ` Tom Rini
@ 2011-12-18 9:00 ` Igor Grinberg
2011-12-18 12:33 ` Wolfgang Denk
1 sibling, 1 reply; 21+ messages in thread
From: Igor Grinberg @ 2011-12-18 9:00 UTC (permalink / raw)
To: u-boot
Hi Peter,
On 12/16/11 08:09, Peter Barada wrote:
> On 12/15/2011 01:30 PM, Tom Rini wrote:
>> On Thu, Dec 15, 2011 at 10:15 AM, Peter Barada <peter.barada@logicpd.com> wrote:
>>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>>> reference boards. It assumes U-boot is loaded to SDRAM with the
>>> help of another small bootloader (x-load) running from SRAM.
[...]
> As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> a checkboard() function that is called early (before relocation) that
> prints out the banner. I tried to make that a weak alias and override
> it in my board file, but when its called, gd->bd is not setup so that
> code aborts when it tries to set gd->bd->bi_arch_number. I then tried
> storing the value in a global and then set gd->bd->bi_arch_number in
> board_init(), but between the call to checkboard() and board_init() the
> BSS section is zeroed. If I stored/load the computed bi_arch_number
> into a non-zero static value it works, but I feel that is really fragile.
This make me wonder, should we move the checkboard() call further
in the init sequence?
Because, IIRC, it stayed in the same place, where it was, before
the relocation feature was introduced and board_init() was called
before the checkboard() (as board_init_f() does now).
Also, the struct bd_info (bd_t) should have the board data and
ironically it is not available in checkboard() function.
So, Albert, Wolfgang,
the question is, should we move the checkboard() call after
the gd->bd pointer initialization or are there any cases
where it is not appropriate?
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
` (2 preceding siblings ...)
2011-12-17 20:44 ` Wolfgang Denk
@ 2011-12-18 9:16 ` Igor Grinberg
2011-12-18 17:25 ` [U-Boot] [PATCH v4] " Peter Barada
3 siblings, 1 reply; 21+ messages in thread
From: Igor Grinberg @ 2011-12-18 9:16 UTC (permalink / raw)
To: u-boot
Hi Peter,
Some comments (hopefully last ones) in addition to Wolfgang's and Tom's:
On 12/16/11 22:31, Peter Barada wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> ---
>
> Changes for V3:
> Inline identify_board() into board_init()
> Remove triple empty lines
> Use sdelay() instead of naked delay loop
> Use enable_gpmc_cs_config() to setup GPMC CS1 access to LAN92xx
> Remove CONFIG_L2_OFF - holdover from previous work in u-boot-2011.06
> where adding 270p 32bpp frambuffer support cause failure while
> booting linux kernel. Will address when I add video support
> Reduce CONFIG_SYS_MAXARGS to 16
>
> Changes for V2:
> Rework logic_identify() into identify_board() - can't use checkboard()
> since its enabled by CONFIG_DISPLAY_BOARDINFO
> Properly indent comments in set_muxconf_regs()
> Move setup_net_chip() call from misc_init_r to board_eth_init()
> Remove triple empty line spacing
> Pass gpio_request(189) non-empty description
> Remove board/logicpd/omap3som/config.mk
> Remove clean/distclean from board/logicpd/omap3som/Makefile
> Modify board_mmc_init() to be one line function
> Modify include/configs/omap3_logic.h to use on/off #defines
>
> board/logicpd/omap3som/Makefile | 42 +++
> board/logicpd/omap3som/omap3logic.c | 523 +++++++++++++++++++++++++++++++++++
> board/logicpd/omap3som/omap3logic.h | 35 +++
> boards.cfg | 1 +
> include/configs/omap3_logic.h | 351 +++++++++++++++++++++++
> 5 files changed, 952 insertions(+), 0 deletions(-)
> create mode 100644 board/logicpd/omap3som/Makefile
> create mode 100644 board/logicpd/omap3som/omap3logic.c
> create mode 100644 board/logicpd/omap3som/omap3logic.h
> create mode 100644 include/configs/omap3_logic.h
[...]
> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
> new file mode 100644
> index 0000000..eb051db
> --- /dev/null
> +++ b/board/logicpd/omap3som/omap3logic.c
[...]
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + struct board_id *board;
> + unsigned int val;
> +
> + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> +
> + /* boot param addr */
> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> + /*
> + * To identify between a SOM LV and Torpedo module,
> + * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
> + * Drive the pin (and let it soak), then read it back.
> + * If the pin is still high its a Torpedo. If low its a SOM LV
> + */
> +
> + /* Mux hsusb0_data5 as a GPIO */
> + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
> +
> + if (gpio_request(GPIO_189, "husb0_data5.gpio_189") == 0) {
Usually, by the label goes the functionality it is used for
in current request, but af course it is up to you, it is not a
blocker as long as the label is valid.
> +
> + /* Drive GPIO_189 - the pulldown resistor on the SOM LV
> + * will drain the voltage */
incorrect multi-line comment (fix globally) and probably,
the empty line before it can be removed.
> + gpio_direction_output(GPIO_189, 0);
> + gpio_set_value(GPIO_189, 1);
> +
> + /* Let it soak for a bit */
> + sdelay(0x100);
> +
> + /* Read state of GPIO_189 as an input and if its set.
> + * If so the board is a Torpedo */
> + gpio_direction_input(GPIO_189);
> + val = gpio_get_value(GPIO_189);
> + gpio_free(GPIO_189);
> +
> + board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
> + printf("Board: %s\n", board->name);
> +
> + /* Set the machine_id passed to Linux */
> + gd->bd->bi_arch_number = board->machine_id;
> + }
> +
> + /* restore hsusb0_data5 pin as hsusb0_data5 */
> + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
> +
> + return 0;
> +}
[...]
> +/*
> + * Routine: misc_init_r
> + * Description: Init ethernet (done here so udelay works)
Function changed, comment left...
> + */
> +int misc_init_r(void)
> +{
> + dieid_num_r();
> +
> + return 0;
> +}
[...]
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-18 9:00 ` [U-Boot] [PATCH v2] " Igor Grinberg
@ 2011-12-18 12:33 ` Wolfgang Denk
0 siblings, 0 replies; 21+ messages in thread
From: Wolfgang Denk @ 2011-12-18 12:33 UTC (permalink / raw)
To: u-boot
Dear Igor Grinberg,
In message <4EEDABA8.4010409@compulab.co.il> you wrote:
>
> > As for the function, in arch/arm/cpu/armv7/omap3/board.c there's already
> > a checkboard() function that is called early (before relocation) that
And keep in mind: before relocation means that the BSS segment is not
available, and data segment is read-only. [You may be lucky on some
systems that things appear to be different, but this is nothing you
should take granted, and it is definitely nothing that should be used
for common code.]
> > code aborts when it tries to set gd->bd->bi_arch_number. I then tried
> > storing the value in a global and then set gd->bd->bi_arch_number in
> > board_init(), but between the call to checkboard() and board_init() the
> > BSS section is zeroed. If I stored/load the computed bi_arch_number
> > into a non-zero static value it works, but I feel that is really fragile.
It is not only fragile, but broken. See above: the data ssegment must
not be written before relocation.
> This make me wonder, should we move the checkboard() call further
> in the init sequence?
No, it should not. It is part of the very early init code, and should
remain where it is. Just don't add any code that does not belong
there.
> Also, the struct bd_info (bd_t) should have the board data and
> ironically it is not available in checkboard() function.
I don't see what is ironically about thaat. bd_info does not exist at
that point of time. You misinterpret the purpose of the checkboard()
function, it seems.
> So, Albert, Wolfgang,
> the question is, should we move the checkboard() call after
> the gd->bd pointer initialization or are there any cases
> where it is not appropriate?
Please leave as is, it is perfectly intentional. Just don't place any
code in checkboard() which does not fit there.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A stone was placed at a ford in a river with the inscription:
"When this stone is covered it is dangerous to ford here."
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-18 9:16 ` Igor Grinberg
@ 2011-12-18 17:25 ` Peter Barada
2011-12-19 7:37 ` Igor Grinberg
0 siblings, 1 reply; 21+ messages in thread
From: Peter Barada @ 2011-12-18 17:25 UTC (permalink / raw)
To: u-boot
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Wolfgang Denk <wd@denx.de>
---
Changes for V4:
Use #defines for LAN92XX GPMC register settings
Add myself to MAINTAINERS
Fix multiline comments
Remove switch values in on/off macro definitions
Modify CONFIG_PREBOOT to make it clear the 4.3" display is the default
Rework name of GPIO_189 to better describe what its used for
Fix misc_init_r comment
Changes for V3:
Inline identify_board() into board_init()
Remove triple empty lines
Use sdelay() instead of naked delay loop
Use enable_gpmc_cs_config() to setup GPMC CS1 access to LAN92xx
Remove CONFIG_L2_OFF - holdover from previous work in u-boot-2011.06
where adding 270p 32bpp frambuffer support cause failure while
booting linux kernel. Will address when I add video support
Reduce CONFIG_SYS_MAXARGS to 16
Changes for V2:
Rework logic_identify() into identify_board() - can't use checkboard()
since its enabled but CONFIG_DISPLAY_BOARDINFO.
Properly indent comments in set_muxconf_regs()
Move setup_net_chip() call from misc_init_r to board_eth_init()
Remove triple empty line spacing
Pass gpio_request(189) non-empty description
Remove board/logicpd/omap3som/config.mk
Remove clean/distclean from board/logicpd/omap3som/Makefile
Modify board_mmc_init() to be one line function
Modify include/configs/omap3_logic.h to use on/off #defines
MAINTAINERS | 4 +
board/logicpd/omap3som/Makefile | 42 +++
board/logicpd/omap3som/omap3logic.c | 532 +++++++++++++++++++++++++++++++++++
board/logicpd/omap3som/omap3logic.h | 47 +++
boards.cfg | 1 +
include/configs/omap3_logic.h | 358 +++++++++++++++++++++++
6 files changed, 984 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/omap3som/Makefile
create mode 100644 board/logicpd/omap3som/omap3logic.c
create mode 100644 board/logicpd/omap3som/omap3logic.h
create mode 100644 include/configs/omap3_logic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a56ca10..c37bf11 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -41,6 +41,10 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
CPCI750 PPC750FX/GX
+Peter Barada <peter.barada@logicpd.com>
+
+ omap3_logic ARM ARMV7 (Logic OMAP35xx/DM37xx)
+
Yuli Barcohen <yuli@arabellasw.com>
Adder MPC87x/MPC852T
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..75e237b
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := omap3logic.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..3a5d3d5
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor
+ */
+static struct board_id {
+ char *name;
+ int machine_id;
+} boards[2][2] = {
+ {
+ {
+ .name = "OMAP35xx SOM LV",
+ .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ },
+ {
+ .name = "OMAP35xx Torpedo",
+ .machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ },
+ },
+ {
+ {
+ .name = "DM37xx SOM LV",
+ .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ },
+ {
+ .name = "DM37xx Torpedo",
+ .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ },
+ },
+};
+
+/*
+ * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
+ */
+#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ struct board_id *board;
+ unsigned int val;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /*
+ * To identify between a SOM LV and Torpedo module,
+ * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
+ * Drive the pin (and let it soak), then read it back.
+ * If the pin is still high its a Torpedo. If low its a SOM LV
+ */
+
+ /* Mux hsusb0_data5 as a GPIO */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
+
+ if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
+
+ /*
+ * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
+ * will drain the voltage.
+ */
+ gpio_direction_output(BOARD_ID_GPIO, 0);
+ gpio_set_value(BOARD_ID_GPIO, 1);
+
+ /* Let it soak for a bit */
+ sdelay(0x100);
+
+ /*
+ * Read state of BOARD_ID_GPIO as an input and if its set.
+ * If so the board is a Torpedo
+ */
+ gpio_direction_input(BOARD_ID_GPIO);
+ val = gpio_get_value(BOARD_ID_GPIO);
+ gpio_free(BOARD_ID_GPIO);
+
+ board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
+ printf("Board: %s\n", board->name);
+
+ /* Set the machine_id passed to Linux */
+ gd->bd->bi_arch_number = board->machine_id;
+ }
+
+ /* restore hsusb0_data5 pin as hsusb0_data5 */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: display die ID register
+ */
+int misc_init_r(void)
+{
+ dieid_num_r();
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+static const u32 gpmc_lan92xx_config[] = {
+ NET_LAN92XX_GPMC_CONFIG1,
+ NET_LAN92XX_GPMC_CONFIG2,
+ NET_LAN92XX_GPMC_CONFIG3,
+ NET_LAN92XX_GPMC_CONFIG4,
+ NET_LAN92XX_GPMC_CONFIG5,
+ NET_LAN92XX_GPMC_CONFIG6,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*SDRC*/
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
+ /*DSS*/
+ MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
+ /*CAMERA*/
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
+ /*Audio Interface */
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Wireless LAN */
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Bluetooth*/
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Modem Interface */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
+
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Serial Interface*/
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
+ /*Control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
+ /*Die to Die */
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..94f6b2e
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+/*
+ * OMAP3 GPMC register settings for CS1 LAN922x
+ */
+#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
+#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
+#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
+#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
+#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
+#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee
am3517_evm arm armv7 am3517evm logicpd omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_logic arm armv7 omap3som logicpd omap3
omap3_mvblx arm armv7 mvblx matrix_vision omap3
am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..1a30f63
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,358 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+#define CONFIG_SYS_TEXT_BASE 0x80400000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 2
+
+/*
+ * PREBOOT assumes the 4.3" display is attached. User can interrupt
+ * and modify display variable to suit their needs.
+ */
+#define CONFIG_PREBOOT \
+ "echo ======================NOTICE============================;"\
+ "echo \"The u-boot environment is not set.\";" \
+ "echo \"If using a display a valid display varible for your panel\";" \
+ "echo \"needs to be set.\";" \
+ "echo \"Valid display options are:\";" \
+ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
+ "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
+ "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
+ "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
+ "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
+ "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
+ "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
+ "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
+ "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
+ "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
+ "setenv display 15;" \
+ "setenv preboot;" \
+ "saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mmcdev=0\0" \
+ "autoboot=if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "run defaultboot;" \
+ "fi; " \
+ "else run defaultboot; fi\0" \
+ "defaultboot=run mmcramboot\0" \
+ "consoledevice=ttyO0\0" \
+ "display=15\0" \
+ "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+ "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+ "rotation=0\0" \
+ "vrfb_arg=if itest ${rotation} -ne 0; then " \
+ "setenv bootargs ${bootargs} omapfb.vrfb=y " \
+ "omapfb.rotate=${rotation}; " \
+ "fi\0" \
+ "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "${otherbootargs};" \
+ "run addmtdparts; " \
+ "run vrfb_arg\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo 'Running bootscript from mmc ...'; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=mmc rescan ${mmcdev}; " \
+ "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "ramdisksize=64000\0" \
+ "ramdiskaddr=0x82000000\0" \
+ "ramdiskimage=rootfs.ext2.gz.uboot\0" \
+ "ramargs=run setconsole; setenv bootargs console=${console} " \
+ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+ "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "run loaduimage; " \
+ "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP Logic # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SMSC922x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-18 17:25 ` [U-Boot] [PATCH v4] " Peter Barada
@ 2011-12-19 7:37 ` Igor Grinberg
2011-12-19 15:44 ` Peter Barada
2011-12-20 5:54 ` [U-Boot] [PATCH v5] " Peter Barada
0 siblings, 2 replies; 21+ messages in thread
From: Igor Grinberg @ 2011-12-19 7:37 UTC (permalink / raw)
To: u-boot
Hi Peter,
Thanks for fixing all the issues pointed.
I have one last question (sorry for not seeing it earlier) and one neat below.
On 12/18/11 19:25, Peter Barada wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> Cc: Wolfgang Denk <wd@denx.de>
> ---
[...]
> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
> new file mode 100644
> index 0000000..3a5d3d5
> --- /dev/null
> +++ b/board/logicpd/omap3som/omap3logic.c
[...]
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
[...]
> + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */
[...]
> + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
> + /*DSS*/
> + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
> + /*CAMERA*/
> + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
> + /*Audio Interface */
> + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */
[...]
> + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Wireless LAN */
> + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Bluetooth*/
> + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/
[...]
> + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
> +
> + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Serial Interface*/
> + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/
[...]
> + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
[...]
> + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */
[...]
> + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/
The TRM says that the initial state of pins is the safe mode (M7).
Also not every pin has this state by definition.
So the question is, wouldn't it be better to remove those lines
that setup the safe mode, or is there a purpose, which I don't see?
Removing those lines will make the file/patch much shorter.
[...]
> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> new file mode 100644
> index 0000000..1a30f63
> --- /dev/null
> +++ b/include/configs/omap3_logic.h
[...]
> +/* DDR - I use Micron DDR */
> +#define CONFIG_OMAP3_MICRON_DDR
You forgot to remove that one - it is not used anymore...
[...]
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-19 7:37 ` Igor Grinberg
@ 2011-12-19 15:44 ` Peter Barada
2011-12-20 5:54 ` [U-Boot] [PATCH v5] " Peter Barada
1 sibling, 0 replies; 21+ messages in thread
From: Peter Barada @ 2011-12-19 15:44 UTC (permalink / raw)
To: u-boot
On 12/19/2011 02:37 AM, Igor Grinberg wrote:
> Hi Peter,
>
> Thanks for fixing all the issues pointed.
> I have one last question (sorry for not seeing it earlier) and one neat below.
>
> On 12/18/11 19:25, Peter Barada wrote:
>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>> reference boards. It assumes U-boot is loaded to SDRAM with the
>> help of another small bootloader (x-load) running from SRAM.
>>
>> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
>> Cc: Tom Rini <tom.rini@gmail.com>
>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>> Cc: Wolfgang Denk <wd@denx.de>
>> ---
[ ... ]
>
>
> The TRM says that the initial state of pins is the safe mode (M7).
> Also not every pin has this state by definition.
> So the question is, wouldn't it be better to remove those lines
> that setup the safe mode, or is there a purpose, which I don't see?
> Removing those lines will make the file/patch much shorter.
Back when we first started with u-boot on these boards, it was loaded
from another bootloader that did its own pinmux setup and this was how I
put all the pins back to a known state. Moving to SPL/u-boot will
preclude having to tweak all the pins.
I'll trim the pinmux setup back to only those pins that are different
than their reset values (or those that need PTD/EN pulldowns to minimise
power consumption when the kernel goes into suspend).
>> +/* DDR - I use Micron DDR */
>> +#define CONFIG_OMAP3_MICRON_DDR
> You forgot to remove that one - it is not used anymore...
Done...
> [...]
>
> --
> Regards,
> Igor.
--
Peter Barada
peter.barada at logicpd.com
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-19 7:37 ` Igor Grinberg
2011-12-19 15:44 ` Peter Barada
@ 2011-12-20 5:54 ` Peter Barada
2011-12-20 7:18 ` Igor Grinberg
1 sibling, 1 reply; 21+ messages in thread
From: Peter Barada @ 2011-12-20 5:54 UTC (permalink / raw)
To: u-boot
This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
reference boards. It assumes U-boot is loaded to SDRAM with the
help of another small bootloader (x-load) running from SRAM.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Wolfgang Denk <wd@denx.de>
---
Changes for V5:
Remove CONFIG_OMAP3_MICRON_DDR - not used anymore
Trim set_muxconf_regs() to only those different from reset values
Add 'ramboot' environment commands to load kernel/root-ramdisk via tftp
Changes for V4:
Use #defines for LAN92XX GPMC register settings
Add myself to MAINTAINERS
Fix multiline comments
Remove switch values in on/off macro definitions
Modify CONFIG_PREBOOT to make it clear the 4.3" display is the default
Rework name of GPIO_189 to better describe what its used for
Fix misc_init_r comment
Changes for V3:
Inline identify_board() into board_init()
Remove triple empty lines
Use sdelay() instead of naked delay loop
Use enable_gpmc_cs_config() to setup GPMC CS1 access to LAN92xx
Remove CONFIG_L2_OFF - holdover from previous work in u-boot-2011.06
where adding 270p 32bpp frambuffer support cause failure while
booting linux kernel. Will address when I add video support
Reduce CONFIG_SYS_MAXARGS to 16
Changes for V2:
Rework logic_identify() into identify_board() - can't use checkboard()
since its enabled but CONFIG_DISPLAY_BOARDINFO.
Properly indent comments in set_muxconf_regs()
Move setup_net_chip() call from misc_init_r to board_eth_init()
Remove triple empty line spacing
Pass gpio_request(189) non-empty description
Remove board/logicpd/omap3som/config.mk
Remove clean/distclean from board/logicpd/omap3som/Makefile
Modify board_mmc_init() to be one line function
Modify include/configs/omap3_logic.h to use on/off #defines
MAINTAINERS | 4 +
board/logicpd/omap3som/Makefile | 42 ++++
board/logicpd/omap3som/omap3logic.c | 247 ++++++++++++++++++++++++
board/logicpd/omap3som/omap3logic.h | 47 +++++
boards.cfg | 1 +
include/configs/omap3_logic.h | 362 +++++++++++++++++++++++++++++++++++
6 files changed, 703 insertions(+), 0 deletions(-)
create mode 100644 board/logicpd/omap3som/Makefile
create mode 100644 board/logicpd/omap3som/omap3logic.c
create mode 100644 board/logicpd/omap3som/omap3logic.h
create mode 100644 include/configs/omap3_logic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a56ca10..c37bf11 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -41,6 +41,10 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
CPCI750 PPC750FX/GX
+Peter Barada <peter.barada@logicpd.com>
+
+ omap3_logic ARM ARMV7 (Logic OMAP35xx/DM37xx)
+
Yuli Barcohen <yuli@arabellasw.com>
Adder MPC87x/MPC852T
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..75e237b
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := omap3logic.o
+
+COBJS := $(sort $(COBJS-y))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..4f5fa8d
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor
+ */
+static struct board_id {
+ char *name;
+ int machine_id;
+} boards[2][2] = {
+ {
+ {
+ .name = "OMAP35xx SOM LV",
+ .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ },
+ {
+ .name = "OMAP35xx Torpedo",
+ .machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ },
+ },
+ {
+ {
+ .name = "DM37xx SOM LV",
+ .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ },
+ {
+ .name = "DM37xx Torpedo",
+ .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ },
+ },
+};
+
+/*
+ * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
+ */
+#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ struct board_id *board;
+ unsigned int val;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /*
+ * To identify between a SOM LV and Torpedo module,
+ * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
+ * Drive the pin (and let it soak), then read it back.
+ * If the pin is still high its a Torpedo. If low its a SOM LV
+ */
+
+ /* Mux hsusb0_data5 as a GPIO */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
+
+ if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
+
+ /*
+ * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
+ * will drain the voltage.
+ */
+ gpio_direction_output(BOARD_ID_GPIO, 0);
+ gpio_set_value(BOARD_ID_GPIO, 1);
+
+ /* Let it soak for a bit */
+ sdelay(0x100);
+
+ /*
+ * Read state of BOARD_ID_GPIO as an input and if its set.
+ * If so the board is a Torpedo
+ */
+ gpio_direction_input(BOARD_ID_GPIO);
+ val = gpio_get_value(BOARD_ID_GPIO);
+ gpio_free(BOARD_ID_GPIO);
+
+ board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
+ printf("Board: %s\n", board->name);
+
+ /* Set the machine_id passed to Linux */
+ gd->bd->bi_arch_number = board->machine_id;
+ }
+
+ /* restore hsusb0_data5 pin as hsusb0_data5 */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: display die ID register
+ */
+int misc_init_r(void)
+{
+ dieid_num_r();
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+static const u32 gpmc_lan92xx_config[] = {
+ NET_LAN92XX_GPMC_CONFIG1,
+ NET_LAN92XX_GPMC_CONFIG2,
+ NET_LAN92XX_GPMC_CONFIG3,
+ NET_LAN92XX_GPMC_CONFIG4,
+ NET_LAN92XX_GPMC_CONFIG5,
+ NET_LAN92XX_GPMC_CONFIG6,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* Serial Console */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ /*Control and debug */
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..94f6b2e
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+/*
+ * OMAP3 GPMC register settings for CS1 LAN922x
+ */
+#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
+#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
+#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
+#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
+#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
+#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 1e5b3e0..f07ae28 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee
am3517_evm arm armv7 am3517evm logicpd omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_logic arm armv7 omap3som logicpd omap3
omap3_mvblx arm armv7 mvblx matrix_vision omap3
am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..01360f6
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+
+#define CONFIG_SYS_TEXT_BASE 0x80400000
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
+ /* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x680000
+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
+ /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 2
+
+/*
+ * PREBOOT assumes the 4.3" display is attached. User can interrupt
+ * and modify display variable to suit their needs.
+ */
+#define CONFIG_PREBOOT \
+ "echo ======================NOTICE============================;"\
+ "echo \"The u-boot environment is not set.\";" \
+ "echo \"If using a display a valid display varible for your panel\";" \
+ "echo \"needs to be set.\";" \
+ "echo \"Valid display options are:\";" \
+ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \
+ "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \
+ "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \
+ "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \
+ "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \
+ "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \
+ "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \
+ "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \
+ "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \
+ "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
+ "setenv display 15;" \
+ "setenv preboot;" \
+ "saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "mmcdev=0\0" \
+ "autoboot=if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "run defaultboot;" \
+ "fi; " \
+ "else run defaultboot; fi\0" \
+ "defaultboot=run mmcramboot\0" \
+ "consoledevice=ttyO0\0" \
+ "display=15\0" \
+ "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+ "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+ "rotation=0\0" \
+ "vrfb_arg=if itest ${rotation} -ne 0; then " \
+ "setenv bootargs ${bootargs} omapfb.vrfb=y " \
+ "omapfb.rotate=${rotation}; " \
+ "fi\0" \
+ "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+ "${otherbootargs};" \
+ "run addmtdparts; " \
+ "run vrfb_arg\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo 'Running bootscript from mmc ...'; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=mmc rescan ${mmcdev}; " \
+ "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "ramdisksize=64000\0" \
+ "ramdiskaddr=0x82000000\0" \
+ "ramdiskimage=rootfs.ext2.gz.uboot\0" \
+ "ramargs=run setconsole; setenv bootargs console=${console} " \
+ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+ "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "run loaduimage; " \
+ "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0" \
+ "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
+ "run ramargs; " \
+ "run common_bootargs; " \
+ "run dump_bootargs; " \
+ "tftpboot ${loadaddr} ${bootfile}; "\
+ "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
+ "bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "OMAP Logic # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
+ /* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
+#endif
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SMSC922x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE 0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+
+#endif /* __CONFIG_H */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-20 5:54 ` [U-Boot] [PATCH v5] " Peter Barada
@ 2011-12-20 7:18 ` Igor Grinberg
2012-01-03 16:48 ` Tom Rini
0 siblings, 1 reply; 21+ messages in thread
From: Igor Grinberg @ 2011-12-20 7:18 UTC (permalink / raw)
To: u-boot
On 12/20/11 07:54, Peter Barada wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v5] ARMV7: Add support For Logic OMAP35x/DM37x modules
2011-12-20 7:18 ` Igor Grinberg
@ 2012-01-03 16:48 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2012-01-03 16:48 UTC (permalink / raw)
To: u-boot
On Tue, Dec 20, 2011 at 12:18 AM, Igor Grinberg <grinberg@compulab.co.il> wrote:
> On 12/20/11 07:54, Peter Barada wrote:
>> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
>> reference boards. It assumes U-boot is loaded to SDRAM with the
>> help of another small bootloader (x-load) running from SRAM.
>>
>> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
>> Cc: Tom Rini <tom.rini@gmail.com>
>> Cc: Igor Grinberg <grinberg@compulab.co.il>
>> Cc: Wolfgang Denk <wd@denx.de>
>
> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Applied to u-boot-ti/master, thanks!
--
Tom
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2012-01-03 16:48 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-12-14 22:47 [U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules Peter Barada
2011-12-15 0:15 ` Tom Rini
2011-12-15 4:59 ` Peter Barada
2011-12-15 8:47 ` Igor Grinberg
2011-12-15 17:15 ` [U-Boot] [PATCH v2] " Peter Barada
2011-12-15 18:30 ` Tom Rini
2011-12-16 6:09 ` Peter Barada
2011-12-16 16:28 ` Tom Rini
2011-12-16 20:31 ` [U-Boot] [PATCH] " Peter Barada
2011-12-16 20:33 ` Peter Barada
2011-12-16 22:43 ` Tom Rini
2011-12-17 20:44 ` Wolfgang Denk
2011-12-18 9:16 ` Igor Grinberg
2011-12-18 17:25 ` [U-Boot] [PATCH v4] " Peter Barada
2011-12-19 7:37 ` Igor Grinberg
2011-12-19 15:44 ` Peter Barada
2011-12-20 5:54 ` [U-Boot] [PATCH v5] " Peter Barada
2011-12-20 7:18 ` Igor Grinberg
2012-01-03 16:48 ` Tom Rini
2011-12-18 9:00 ` [U-Boot] [PATCH v2] " Igor Grinberg
2011-12-18 12:33 ` Wolfgang Denk
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