* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
@ 2011-12-18 22:09 Michael Walle
2011-12-18 22:19 ` Michael Walle
2011-12-18 23:04 ` Marek Vasut
0 siblings, 2 replies; 14+ messages in thread
From: Michael Walle @ 2011-12-18 22:09 UTC (permalink / raw)
To: u-boot
The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
---
arch/arm/cpu/arm926ejs/cache.c | 15 +++++++++++
arch/arm/cpu/arm926ejs/cpu.c | 2 +
arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 +
arch/arm/cpu/arm926ejs/kirkwood/cache.c | 41 ++++++++++++++++++++++++++++++
4 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 4415642..7a7d0a6 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -73,3 +73,18 @@ void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_enable(void)
+{
+}
+void l2_cache_enable(void)
+ __attribute__((weak, alias("__l2_cache_enable")));
+
+void __l2_cache_disable(void)
+{
+}
+void l2_cache_disable(void)
+ __attribute__((weak, alias("__l2_cache_disable")));
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index 5c902df..626384c 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
/* turn off I/D-cache */
icache_disable();
dcache_disable();
+ l2_cache_disable();
+
/* flush I/D-cache */
cache_flush();
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index 0754297..777006c 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -30,6 +30,7 @@ COBJS-y = cpu.o
COBJS-y += dram.o
COBJS-y += mpp.o
COBJS-y += timer.o
+COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
new file mode 100644
index 0000000..84207f7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+void l2_cache_enable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl |= 1 << 22; /* enable l2 cache */
+ writefr_extra_feature_reg(ctrl);
+}
+
+void l2_cache_disable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl &= ~(1 << 22); /* disable l2 cache */
+ writefr_extra_feature_reg(ctrl);
+}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 22:09 [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot Michael Walle
@ 2011-12-18 22:19 ` Michael Walle
2011-12-18 23:04 ` Marek Vasut
1 sibling, 0 replies; 14+ messages in thread
From: Michael Walle @ 2011-12-18 22:19 UTC (permalink / raw)
To: u-boot
Am Sonntag 18 Dezember 2011, 23:09:51 schrieb Michael Walle:
> The decompressor expects the L2 cache to be disabled. This fixes booting
> some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
You should consider applying this patch to the RC, too.
CONFIG_ARM_PATCH_PHYS_VIRT is enabled by default since 3.2-rc1.
--
michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 22:09 [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot Michael Walle
2011-12-18 22:19 ` Michael Walle
@ 2011-12-18 23:04 ` Marek Vasut
2011-12-18 23:21 ` Michael Walle
` (2 more replies)
1 sibling, 3 replies; 14+ messages in thread
From: Marek Vasut @ 2011-12-18 23:04 UTC (permalink / raw)
To: u-boot
> The decompressor expects the L2 cache to be disabled. This fixes booting
> some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> arch/arm/cpu/arm926ejs/cache.c | 15 +++++++++++
> arch/arm/cpu/arm926ejs/cpu.c | 2 +
> arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 +
> arch/arm/cpu/arm926ejs/kirkwood/cache.c | 41
> ++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 0
> deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/cache.c
> b/arch/arm/cpu/arm926ejs/cache.c index 4415642..7a7d0a6 100644
> --- a/arch/arm/cpu/arm926ejs/cache.c
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -73,3 +73,18 @@ void flush_cache(unsigned long start, unsigned long
> size) {
> }
> #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +
> +/*
> + * Stub implementations for l2 cache operations
> + */
> +void __l2_cache_enable(void)
> +{
> +}
> +void l2_cache_enable(void)
> + __attribute__((weak, alias("__l2_cache_enable")));
> +
> +void __l2_cache_disable(void)
> +{
> +}
> +void l2_cache_disable(void)
> + __attribute__((weak, alias("__l2_cache_disable")));
> diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
> index 5c902df..626384c 100644
> --- a/arch/arm/cpu/arm926ejs/cpu.c
> +++ b/arch/arm/cpu/arm926ejs/cpu.c
> @@ -50,6 +50,8 @@ int cleanup_before_linux (void)
> /* turn off I/D-cache */
> icache_disable();
> dcache_disable();
> + l2_cache_disable();
> +
> /* flush I/D-cache */
> cache_flush();
>
> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644
> --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> @@ -30,6 +30,7 @@ COBJS-y = cpu.o
> COBJS-y += dram.o
> COBJS-y += mpp.o
> COBJS-y += timer.o
> +COBJS-y += cache.o
>
> SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c
> b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644
> index 0000000..84207f7
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
> @@ -0,0 +1,41 @@
> +/*
> + * Copyright (c) 2011 Michael Walle
> + * Michael Walle <michael@walle.cc>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc.
> + */
> +#include <common.h>
> +#include <asm/arch/cpu.h>
> +
> +void l2_cache_enable()
> +{
> + u32 ctrl;
> +
> + ctrl = readfr_extra_feature_reg();
> + ctrl |= 1 << 22; /* enable l2 cache */
> + writefr_extra_feature_reg(ctrl);
> +}
> +
> +void l2_cache_disable()
> +{
> + u32 ctrl;
> +
> + ctrl = readfr_extra_feature_reg();
> + ctrl &= ~(1 << 22); /* disable l2 cache */
> + writefr_extra_feature_reg(ctrl);
> +}
Please use #define <name> to define the magic value above (1 << 22) and then use
it.
M
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 23:04 ` Marek Vasut
@ 2011-12-18 23:21 ` Michael Walle
2011-12-20 7:04 ` Albert ARIBAUD
2011-12-20 23:35 ` Michael Walle
2012-01-13 22:53 ` [U-Boot] [PATCH v2] " Michael Walle
2 siblings, 1 reply; 14+ messages in thread
From: Michael Walle @ 2011-12-18 23:21 UTC (permalink / raw)
To: u-boot
Am Montag 19 Dezember 2011, 00:04:18 schrieb Marek Vasut:
[..snip..]
> Please use #define <name> to define the magic value above (1 << 22) and
> then use it.
>
> M
The bit was taken from arch/arm/cpu/arm926ejs/kirkwood/cpu.c. Unfortunately
there is no documentation publicly available, so i can only guess names.
FEROCEON_EXTRA_FEATURE_L2C_EN ?
Even the linux kernel has no proper macro names :(
--
Michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 23:21 ` Michael Walle
@ 2011-12-20 7:04 ` Albert ARIBAUD
2011-12-20 23:37 ` Michael Walle
0 siblings, 1 reply; 14+ messages in thread
From: Albert ARIBAUD @ 2011-12-20 7:04 UTC (permalink / raw)
To: u-boot
Hi Michael,
Le 19/12/2011 00:21, Michael Walle a ?crit :
> Am Montag 19 Dezember 2011, 00:04:18 schrieb Marek Vasut:
> [..snip..]
>> Please use #define<name> to define the magic value above (1<< 22) and
>> then use it.
>>
>> M
>
> The bit was taken from arch/arm/cpu/arm926ejs/kirkwood/cpu.c. Unfortunately
> there is no documentation publicly available, so i can only guess names.
>
> FEROCEON_EXTRA_FEATURE_L2C_EN ?
Works for me.
> Even the linux kernel has no proper macro names :(
Time we told them to have one, then. :)
I assume the patch was tested against a 3.2-rc1 kernel and also a
pre-3.2-rc1 kernel to avoid regression?
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 23:04 ` Marek Vasut
2011-12-18 23:21 ` Michael Walle
@ 2011-12-20 23:35 ` Michael Walle
2011-12-21 1:05 ` Marek Vasut
2012-01-02 18:37 ` Michael Walle
2012-01-13 22:53 ` [U-Boot] [PATCH v2] " Michael Walle
2 siblings, 2 replies; 14+ messages in thread
From: Michael Walle @ 2011-12-20 23:35 UTC (permalink / raw)
To: u-boot
The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
---
arch/arm/cpu/arm926ejs/cache.c | 15 ++++++++++
arch/arm/cpu/arm926ejs/cpu.c | 2 +
arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 +
arch/arm/cpu/arm926ejs/kirkwood/cache.c | 43 ++++++++++++++++++++++++++++++
4 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 4415642..7a7d0a6 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -73,3 +73,18 @@ void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_enable(void)
+{
+}
+void l2_cache_enable(void)
+ __attribute__((weak, alias("__l2_cache_enable")));
+
+void __l2_cache_disable(void)
+{
+}
+void l2_cache_disable(void)
+ __attribute__((weak, alias("__l2_cache_disable")));
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index 5c902df..626384c 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
/* turn off I/D-cache */
icache_disable();
dcache_disable();
+ l2_cache_disable();
+
/* flush I/D-cache */
cache_flush();
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index 0754297..777006c 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -30,6 +30,7 @@ COBJS-y = cpu.o
COBJS-y += dram.o
COBJS-y += mpp.o
COBJS-y += timer.o
+COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
new file mode 100644
index 0000000..df90cb9
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2011 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_enable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl |= FEROCEON_EXTRA_FEATURE_L2C_EN;
+ writefr_extra_feature_reg(ctrl);
+}
+
+void l2_cache_disable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
+ writefr_extra_feature_reg(ctrl);
+}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-20 7:04 ` Albert ARIBAUD
@ 2011-12-20 23:37 ` Michael Walle
0 siblings, 0 replies; 14+ messages in thread
From: Michael Walle @ 2011-12-20 23:37 UTC (permalink / raw)
To: u-boot
Am Dienstag 20 Dezember 2011, 08:04:23 schrieb Albert ARIBAUD:
> I assume the patch was tested against a 3.2-rc1 kernel and also a
> pre-3.2-rc1 kernel to avoid regression?
Tested with 3.0, 3.1 and 3.2-rc both with CONFIG_ARM_PATCH_PHYS_VIRT enabled
and disabled.
--
Michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-20 23:35 ` Michael Walle
@ 2011-12-21 1:05 ` Marek Vasut
2012-01-02 18:37 ` Michael Walle
1 sibling, 0 replies; 14+ messages in thread
From: Marek Vasut @ 2011-12-21 1:05 UTC (permalink / raw)
To: u-boot
> The decompressor expects the L2 cache to be disabled. This fixes booting
> some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> arch/arm/cpu/arm926ejs/cache.c | 15 ++++++++++
> arch/arm/cpu/arm926ejs/cpu.c | 2 +
> arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 +
> arch/arm/cpu/arm926ejs/kirkwood/cache.c | 43
> ++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+), 0
> deletions(-)
> create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
>
> diff --git a/arch/arm/cpu/arm926ejs/cache.c
> b/arch/arm/cpu/arm926ejs/cache.c index 4415642..7a7d0a6 100644
> --- a/arch/arm/cpu/arm926ejs/cache.c
> +++ b/arch/arm/cpu/arm926ejs/cache.c
> @@ -73,3 +73,18 @@ void flush_cache(unsigned long start, unsigned long
> size) {
> }
> #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
> +
> +/*
> + * Stub implementations for l2 cache operations
> + */
> +void __l2_cache_enable(void)
> +{
> +}
> +void l2_cache_enable(void)
> + __attribute__((weak, alias("__l2_cache_enable")));
> +
> +void __l2_cache_disable(void)
> +{
> +}
> +void l2_cache_disable(void)
> + __attribute__((weak, alias("__l2_cache_disable")));
> diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
> index 5c902df..626384c 100644
> --- a/arch/arm/cpu/arm926ejs/cpu.c
> +++ b/arch/arm/cpu/arm926ejs/cpu.c
> @@ -50,6 +50,8 @@ int cleanup_before_linux (void)
> /* turn off I/D-cache */
> icache_disable();
> dcache_disable();
> + l2_cache_disable();
> +
> /* flush I/D-cache */
> cache_flush();
>
> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644
> --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
> @@ -30,6 +30,7 @@ COBJS-y = cpu.o
> COBJS-y += dram.o
> COBJS-y += mpp.o
> COBJS-y += timer.o
> +COBJS-y += cache.o
>
> SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
> diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c
> b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644
> index 0000000..df90cb9
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (c) 2011 Michael Walle
> + * Michael Walle <michael@walle.cc>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc.
> + */
> +#include <common.h>
> +#include <asm/arch/cpu.h>
> +
> +#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
> +
> +void l2_cache_enable()
> +{
> + u32 ctrl;
> +
> + ctrl = readfr_extra_feature_reg();
> + ctrl |= FEROCEON_EXTRA_FEATURE_L2C_EN;
> + writefr_extra_feature_reg(ctrl);
> +}
> +
> +void l2_cache_disable()
> +{
> + u32 ctrl;
> +
> + ctrl = readfr_extra_feature_reg();
> + ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
> + writefr_extra_feature_reg(ctrl);
> +}
Fine by me ...
Acked-by: Marek Vasut <marek.vasut@gmail.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2011-12-20 23:35 ` Michael Walle
2011-12-21 1:05 ` Marek Vasut
@ 2012-01-02 18:37 ` Michael Walle
2012-01-12 22:44 ` Albert ARIBAUD
1 sibling, 1 reply; 14+ messages in thread
From: Michael Walle @ 2012-01-02 18:37 UTC (permalink / raw)
To: u-boot
Am Mittwoch 21 Dezember 2011, 00:35:46 schrieb Michael Walle:
> The decompressor expects the L2 cache to be disabled. This fixes booting
> some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Ping :)
--
Michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
2012-01-02 18:37 ` Michael Walle
@ 2012-01-12 22:44 ` Albert ARIBAUD
0 siblings, 0 replies; 14+ messages in thread
From: Albert ARIBAUD @ 2012-01-12 22:44 UTC (permalink / raw)
To: u-boot
Hi Michael,
Le 02/01/2012 19:37, Michael Walle a ?crit :
> Am Mittwoch 21 Dezember 2011, 00:35:46 schrieb Michael Walle:
>> The decompressor expects the L2 cache to be disabled. This fixes booting
>> some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
>
> Ping :)
Sorry, start of year was hectic.
That's V2 of the patch, correct? But it has no V2 tag, nor history.
Also, I'm missing something: you introduce two functions, for enabling
and disabling the cache, yet the code uses only the one for disabling.
So what enabled it in the first place?
Regards,
Albert.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2] arm, arm-kirkwood: disable l2c before linux boot
2011-12-18 23:04 ` Marek Vasut
2011-12-18 23:21 ` Michael Walle
2011-12-20 23:35 ` Michael Walle
@ 2012-01-13 22:53 ` Michael Walle
2012-01-13 22:59 ` Michael Walle
2 siblings, 1 reply; 14+ messages in thread
From: Michael Walle @ 2012-01-13 22:53 UTC (permalink / raw)
To: u-boot
The decompressor expects the L2 cache to be disabled. This fixes booting
some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
---
This is a repost, because the former had no version tag nor a history.
v2:
- replace magic number with macro
arch/arm/cpu/arm926ejs/cache.c | 15 ++++++++++
arch/arm/cpu/arm926ejs/cpu.c | 2 +
arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 +
arch/arm/cpu/arm926ejs/kirkwood/cache.c | 43 ++++++++++++++++++++++++++++++
4 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index ee90ab7..ba13154 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -68,3 +68,18 @@ void flush_cache(unsigned long start, unsigned long size)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_enable(void)
+{
+}
+void l2_cache_enable(void)
+ __attribute__((weak, alias("__l2_cache_enable")));
+
+void __l2_cache_disable(void)
+{
+}
+void l2_cache_disable(void)
+ __attribute__((weak, alias("__l2_cache_disable")));
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index 5c902df..626384c 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
/* turn off I/D-cache */
icache_disable();
dcache_disable();
+ l2_cache_disable();
+
/* flush I/D-cache */
cache_flush();
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
index 0754297..777006c 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
@@ -30,6 +30,7 @@ COBJS-y = cpu.o
COBJS-y += dram.o
COBJS-y += mpp.o
COBJS-y += timer.o
+COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
new file mode 100644
index 0000000..df90cb9
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2011 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_enable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl |= FEROCEON_EXTRA_FEATURE_L2C_EN;
+ writefr_extra_feature_reg(ctrl);
+}
+
+void l2_cache_disable()
+{
+ u32 ctrl;
+
+ ctrl = readfr_extra_feature_reg();
+ ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
+ writefr_extra_feature_reg(ctrl);
+}
--
1.7.2.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2] arm, arm-kirkwood: disable l2c before linux boot
2012-01-13 22:53 ` [U-Boot] [PATCH v2] " Michael Walle
@ 2012-01-13 22:59 ` Michael Walle
2012-01-31 22:49 ` Michael Walle
0 siblings, 1 reply; 14+ messages in thread
From: Michael Walle @ 2012-01-13 22:59 UTC (permalink / raw)
To: u-boot
[Sorry can't answer to the original message, because it was blocked by spam
filter]
> Also, I'm missing something: you introduce two functions, for enabling
> and disabling the cache, yet the code uses only the one for disabling.
> So what enabled it in the first place?
The L2C is enabled in arch_misc_init() in
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
My enable function is just for completeness atm.
--
Michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2] arm, arm-kirkwood: disable l2c before linux boot
2012-01-13 22:59 ` Michael Walle
@ 2012-01-31 22:49 ` Michael Walle
2012-01-31 23:04 ` Wolfgang Denk
0 siblings, 1 reply; 14+ messages in thread
From: Michael Walle @ 2012-01-31 22:49 UTC (permalink / raw)
To: u-boot
Am Freitag 13 Januar 2012, 23:59:08 schrieb Michael Walle:
> [Sorry can't answer to the original message, because it was blocked by spam
> filter]
>
> > Also, I'm missing something: you introduce two functions, for enabling
> > and disabling the cache, yet the code uses only the one for disabling.
> > So what enabled it in the first place?
>
> The L2C is enabled in arch_misc_init() in
> arch/arm/cpu/arm926ejs/kirkwood/cpu.c
>
> My enable function is just for completeness atm.
Ping.
Is there something still uncertain?
--
Michael
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2] arm, arm-kirkwood: disable l2c before linux boot
2012-01-31 22:49 ` Michael Walle
@ 2012-01-31 23:04 ` Wolfgang Denk
0 siblings, 0 replies; 14+ messages in thread
From: Wolfgang Denk @ 2012-01-31 23:04 UTC (permalink / raw)
To: u-boot
Dear Michael Walle,
In message <201201312349.37621.michael@walle.cc> you wrote:
>
> > My enable function is just for completeness atm.
>
> Ping.
>
> Is there something still uncertain?
Nothing is uncertain.
But we do not add dead code.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Pray to God, but keep rowing to shore. - Russian Proverb
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2012-01-31 23:04 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-12-18 22:09 [U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot Michael Walle
2011-12-18 22:19 ` Michael Walle
2011-12-18 23:04 ` Marek Vasut
2011-12-18 23:21 ` Michael Walle
2011-12-20 7:04 ` Albert ARIBAUD
2011-12-20 23:37 ` Michael Walle
2011-12-20 23:35 ` Michael Walle
2011-12-21 1:05 ` Marek Vasut
2012-01-02 18:37 ` Michael Walle
2012-01-12 22:44 ` Albert ARIBAUD
2012-01-13 22:53 ` [U-Boot] [PATCH v2] " Michael Walle
2012-01-13 22:59 ` Michael Walle
2012-01-31 22:49 ` Michael Walle
2012-01-31 23:04 ` Wolfgang Denk
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