[Qemu-devel] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2

[Qemu-devel] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2

[Fabien Chouteau]

The size of EPN field in MAS2 depends on page size. This patch adds a
mask to discard invalid bits in EPN field.

Definition of EPN field from e500v2 RM:
EPN Effective page number: Depending on page size, only the bits
associated with a page boundary are valid. Bits that represent offsets
within a page are ignored and should be cleared.

There is a similar (but more complicated) definition in PowerISA V2.06.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 target-ppc/op_helper.c |   17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 4ef2332..481b51c 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -4227,6 +4227,8 @@ void helper_booke206_tlbwe(void)
     uint32_t tlbncfg, tlbn;
     ppcmas_tlb_t *tlb;
     uint32_t size_tlb, size_ps;
+    target_ulong mask;
+
 
     switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) {
     case MAS0_WQ_ALWAYS:
@@ -4289,8 +4291,19 @@ void helper_booke206_tlbwe(void)
         tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
     }
 
-    /* XXX needs to change when supporting 64-bit e500 */
-    tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & 0xffffffff;
+    /* Make a mask from TLB size to discard invalid bits in EPN field */
+    mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
+    /* Add a mask for page attributes */
+    mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
+
+    if (!msr_cm) {
+        /* Executing a tlbwe instruction in 32-bit mode will set
+         * bits 0:31 of the TLB EPN field to zero.
+         */
+        mask &= 0xffffffff;
+    }
+
+    tlb->mas2 = env->spr[SPR_BOOKE_MAS2] & mask;
 
     if (!(tlbncfg & TLBnCFG_IPROT)) {
         /* no IPROT supported by TLB */
-- 
1.7.9.5

Re: [Qemu-devel] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2

[Andreas Färber]

Am 21.05.2012 18:11, schrieb Fabien Chouteau:
> The size of EPN field in MAS2 depends on page size. This patch adds a
> mask to discard invalid bits in EPN field.
> 
> Definition of EPN field from e500v2 RM:
> EPN Effective page number: Depending on page size, only the bits
> associated with a page boundary are valid. Bits that represent offsets
> within a page are ignored and should be cleared.
> 
> There is a similar (but more complicated) definition in PowerISA V2.06.
> 
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> ---
>  target-ppc/op_helper.c |   17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index 4ef2332..481b51c 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -4227,6 +4227,8 @@ void helper_booke206_tlbwe(void)
>      uint32_t tlbncfg, tlbn;
>      ppcmas_tlb_t *tlb;
>      uint32_t size_tlb, size_ps;
> +    target_ulong mask;
> +
>  
>      switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) {
>      case MAS0_WQ_ALWAYS:

Minor nitpick: This adds a second white line.

More severely, this patch is not marked as for 1.1 and I believe
op_helper.c is dropped in Blue's AREG0 conversion, so I would recommend
to rebase on that, since rebasing the large code movements was kind of
nasty. Now that we've fixed ppc and ppc64 TCG it could be applied to
ppc-next, no?

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2

[Alexander Graf]

On 21.05.2012, at 18:31, Andreas Färber <afaerber@suse.de> wrote:

> Am 21.05.2012 18:11, schrieb Fabien Chouteau:
>> The size of EPN field in MAS2 depends on page size. This patch adds a
>> mask to discard invalid bits in EPN field.
>> 
>> Definition of EPN field from e500v2 RM:
>> EPN Effective page number: Depending on page size, only the bits
>> associated with a page boundary are valid. Bits that represent offsets
>> within a page are ignored and should be cleared.
>> 
>> There is a similar (but more complicated) definition in PowerISA V2.06.
>> 
>> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
>> ---
>> target-ppc/op_helper.c |   17 +++++++++++++++--
>> 1 file changed, 15 insertions(+), 2 deletions(-)
>> 
>> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
>> index 4ef2332..481b51c 100644
>> --- a/target-ppc/op_helper.c
>> +++ b/target-ppc/op_helper.c
>> @@ -4227,6 +4227,8 @@ void helper_booke206_tlbwe(void)
>>     uint32_t tlbncfg, tlbn;
>>     ppcmas_tlb_t *tlb;
>>     uint32_t size_tlb, size_ps;
>> +    target_ulong mask;
>> +
>> 
>>     switch (env->spr[SPR_BOOKE_MAS0] & MAS0_WQ_MASK) {
>>     case MAS0_WQ_ALWAYS:
> 
> Minor nitpick: This adds a second white line.
> 
> More severely, this patch is not marked as for 1.1 and I believe
> op_helper.c is dropped in Blue's AREG0 conversion, so I would recommend
> to rebase on that, since rebasing the large code movements was kind of
> nasty. Now that we've fixed ppc and ppc64 TCG it could be applied to
> ppc-next, no?

Good point. Blue, mind to resend? :)

Alex

Re: [Qemu-devel] [Qemu-ppc] [PATCH V2] booke_206_tlbwe: Discard invalid bits in MAS2

[Andreas Färber]

Am 21.05.2012 21:24, schrieb Alexander Graf:
> 
> On 21.05.2012, at 18:31, Andreas Färber <afaerber@suse.de> wrote:
> 
>> [...] I believe
>> op_helper.c is dropped in Blue's AREG0 conversion, so I would recommend
>> to rebase on that, since rebasing the large code movements was kind of
>> nasty. Now that we've fixed ppc and ppc64 TCG it could be applied to
>> ppc-next, no?
> 
> Good point. Blue, mind to resend? :)

I managed to rebase my copy of Blue's ppc series onto qom-next but ran
into bisectability issues. So I've rebased your branch (qemu.areg0)
instead and pushed it for you to reset ppc-next to:

http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/ppc

This is based on current qom-next; the only conflicts were due to
removal of cpu_state_reset() and return type change of cpu_ppc_init().

Rebased version compile-tested on x86 and ppc w/KVM, and lightly
runtime-tested by booting into openSUSE Factory .iso on -M pseries.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg