* [PATCH v2 1/4] target/i386: add missing vmx features for several CPU models
2020-03-28 3:06 [PATCH v2 0/4] modify CPU model info Chenyi Qiang
@ 2020-03-28 3:06 ` Chenyi Qiang
2020-03-28 3:06 ` [PATCH v2 2/4] target/i386: add fast short REP MOV support Chenyi Qiang
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chenyi Qiang @ 2020-03-28 3:06 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Add some missing VMX features in Skylake-Server, Cascadelake-Server and
Icelake-Server CPU models based on the output of Paolo's script.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 34b511f078..4123d5910e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3059,6 +3059,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
.versions = (X86CPUVersionDefinition[]) {
@@ -3187,6 +3188,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Cascadelake)",
.versions = (X86CPUVersionDefinition[]) {
@@ -3534,7 +3536,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
- VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Icelake)",
.versions = (X86CPUVersionDefinition[]) {
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/4] target/i386: add fast short REP MOV support
2020-03-28 3:06 [PATCH v2 0/4] modify CPU model info Chenyi Qiang
2020-03-28 3:06 ` [PATCH v2 1/4] target/i386: add missing vmx features for several CPU models Chenyi Qiang
@ 2020-03-28 3:06 ` Chenyi Qiang
2020-03-28 3:06 ` [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chenyi Qiang @ 2020-03-28 3:06 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4123d5910e..b01421c6bb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1077,7 +1077,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
- NULL, NULL, NULL, NULL,
+ "fsrm", NULL, NULL, NULL,
NULL, NULL, "md-clear", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL /* pconfig */, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 60d797d594..f7ba813cab 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -770,6 +770,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
/* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
+/* Fast Short Rep Mov */
+#define CPUID_7_0_EDX_FSRM (1U << 4)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model
2020-03-28 3:06 [PATCH v2 0/4] modify CPU model info Chenyi Qiang
2020-03-28 3:06 ` [PATCH v2 1/4] target/i386: add missing vmx features for several CPU models Chenyi Qiang
2020-03-28 3:06 ` [PATCH v2 2/4] target/i386: add fast short REP MOV support Chenyi Qiang
@ 2020-03-28 3:06 ` Chenyi Qiang
2020-03-28 5:12 ` Xiaoyao Li
2020-03-31 8:39 ` Robert Hoo
2020-03-28 3:06 ` [PATCH v2 4/4] target/i386: modify Icelake-Client and Icelake-Server CPU model number Chenyi Qiang
2020-04-07 8:59 ` [PATCH v2 0/4] modify CPU model info Chenyi Qiang
4 siblings, 2 replies; 8+ messages in thread
From: Chenyi Qiang @ 2020-03-28 3:06 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID
feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b01421c6bb..babb074abf 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ { "sha-ni", "on" },
+ { "avx512ifma", "on" },
+ { "rdpid", "on" },
+ { "fsrm", "on" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model
2020-03-28 3:06 ` [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
@ 2020-03-28 5:12 ` Xiaoyao Li
2020-03-31 8:39 ` Robert Hoo
1 sibling, 0 replies; 8+ messages in thread
From: Xiaoyao Li @ 2020-03-28 5:12 UTC (permalink / raw)
To: Chenyi Qiang, Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: qemu-devel, Robert Hoo
On 3/28/2020 11:06 AM, Chenyi Qiang wrote:
> Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID
> feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX.
>
> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
> ---
> target/i386/cpu.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index b01421c6bb..babb074abf 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> },
> },
> + {
> + .version = 3,
Maybe you need to make it as version = 4, since 3 is used to add
ARCH_CAPABILITIES bits and the Patch is queued:
https://lore.kernel.org/qemu-devel/20200323183936.GA3784@habkost.net/
> + .props = (PropValue[]) {
> + { "sha-ni", "on" },
> + { "avx512ifma", "on" },
> + { "rdpid", "on" },
> + { "fsrm", "on" },
> + { /* end of list */ }
> + },
> + },
> { /* end of list */ }
> }
> },
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model
2020-03-28 3:06 ` [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
2020-03-28 5:12 ` Xiaoyao Li
@ 2020-03-31 8:39 ` Robert Hoo
1 sibling, 0 replies; 8+ messages in thread
From: Robert Hoo @ 2020-03-31 8:39 UTC (permalink / raw)
To: Chenyi Qiang, Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel
On Sat, 2020-03-28 at 11:06 +0800, Chenyi Qiang wrote:
> Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX, RDPID
> feature bit in FEAT_7_0_ECX and FSRM feature bit in FEAT_7_0_EDX.
>
> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
> ---
> target/i386/cpu.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index b01421c6bb..babb074abf 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3552,6 +3552,16 @@ static X86CPUDefinition builtin_x86_defs[] = {
> { /* end of list */ }
> },
> },
> + {
> + .version = 3,
> + .props = (PropValue[]) {
> + { "sha-ni", "on" },
> + { "avx512ifma", "on" },
> + { "rdpid", "on" },
> + { "fsrm", "on" },
> + { /* end of list */ }
> + },
> + },
> { /* end of list */ }
I think these 4 new CPUIDs addition is to catch up latest
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
on updates.
This is actually fix to previous v1 definitions.
So my 2 cents:
1. add 1 more version: include v2's hle and rtm properties off
2. make the hle-rtm-disable inclusion version or this v3 default
version of icelake.
Anyway, v1 is not suitable for default choice.
Then questions comes to how to make non-v1 default.
Perhaps:
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 34b511f..d4eb3d6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5453,7 +5453,7 @@ static void
x86_register_cpudef_types(X86CPUDefinition *def)
/* Unversioned model: */
m = g_new0(X86CPUModel, 1);
m->cpudef = def;
- m->version = CPU_VERSION_AUTO;
+ m->version = CPU_VERSION_LATEST;
m->is_alias = true;
x86_register_cpu_model_type(def->name, m);
I think for builtin_x86_defs[] definitions, latest version is usually
preferable/suitable.
How would Paolo, Eduardo like it?
> }
> },
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/4] target/i386: modify Icelake-Client and Icelake-Server CPU model number
2020-03-28 3:06 [PATCH v2 0/4] modify CPU model info Chenyi Qiang
` (2 preceding siblings ...)
2020-03-28 3:06 ` [PATCH v2 3/4] target/i386: add the missing features for Icelake-Server CPU model Chenyi Qiang
@ 2020-03-28 3:06 ` Chenyi Qiang
2020-04-07 8:59 ` [PATCH v2 0/4] modify CPU model info Chenyi Qiang
4 siblings, 0 replies; 8+ messages in thread
From: Chenyi Qiang @ 2020-03-28 3:06 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
According to the Intel Icelake family list, Icelake-Client uses model
number 125(0x7D) and Icelake-Server uses model number 106(0x6A).
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index babb074abf..5bd52f2c4b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3328,7 +3328,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
- .model = 126,
+ .model = 125,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -3441,7 +3441,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
- .model = 134,
+ .model = 106,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/4] modify CPU model info
2020-03-28 3:06 [PATCH v2 0/4] modify CPU model info Chenyi Qiang
` (3 preceding siblings ...)
2020-03-28 3:06 ` [PATCH v2 4/4] target/i386: modify Icelake-Client and Icelake-Server CPU model number Chenyi Qiang
@ 2020-04-07 8:59 ` Chenyi Qiang
4 siblings, 0 replies; 8+ messages in thread
From: Chenyi Qiang @ 2020-04-07 8:59 UTC (permalink / raw)
To: Paolo Bonzini, Richard Henderson, Eduardo Habkost
Cc: Xiaoyao Li, qemu-devel, Robert Hoo
Ping for comments.
Hi Paolo and Eduardo,
ARCH_CAPABILITIES has been added into Icelake-Server CPU model.
What your opinion of the missing feature bits in this patch set?
Thanks
Chenyi
On 3/28/2020 11:06 AM, Chenyi Qiang wrote:
> Add the missing VMX features in Skylake-Server, Cascadelake-Server and
> Icelake-Server CPU models. In Icelake-Server CPU model, it also lacks
> sha_ni, avx512ifma, rdpid and fsrm. The model numbers of Icelake-Client
> and Icelake-Server need to be fixed.
>
> Changes in v2:
> - add missing features as a new version of CPU model
> - add the support of FSRM
>
> Chenyi Qiang (4):
> target/i386: add missing vmx features for several CPU models
> target/i386: add fast short REP MOV support
> target/i386: add the missing features for Icelake-Server CPU model
> target/i386: modify Icelake-Client and Icelake-Server CPU model number
>
> target/i386/cpu.c | 22 ++++++++++++++++++----
> target/i386/cpu.h | 2 ++
> 2 files changed, 20 insertions(+), 4 deletions(-)
>
^ permalink raw reply [flat|nested] 8+ messages in thread