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From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"mjc@sifive.com" <mjc@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	"alistair23@gmail.com" <alistair23@gmail.com>,
	"stephen@eideticom.com" <stephen@eideticom.com>,
	"palmer@sifive.com" <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device
Date: Thu, 4 Oct 2018 20:06:59 +0000	[thread overview]
Message-ID: <4ae3539e9e432912819b41aefbfdde237a27057d.1538683492.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1538683492.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv32-softmmu.mak |  1 +
 default-configs/riscv64-softmmu.mak |  1 +
 hw/riscv/virt.c                     | 20 +++++++++++++++++---
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 05fae82f1b..bb3dd34606 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 05fae82f1b..bb3dd34606 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI_GENERIC=y
 CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 62a953aa2b..6d91810bcf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "chardev/char.h"
+#include "net/net.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "exec/address-spaces.h"
@@ -322,6 +323,8 @@ static void riscv_virt_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+    DeviceState *dev;
+    PCIBus *pci_bus;
     char *plic_hart_config;
     size_t plic_hart_config_len;
     int i;
@@ -436,9 +439,20 @@ static void riscv_virt_board_init(MachineState *machine)
             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
-    gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
-                   memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
-                   qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+    dev = gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+                         memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
+                         qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+    pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+    for (i = 0; i < nb_nics; i++) {
+        NICInfo *nd = &nd_table[i];
+
+        if (!nd->model) {
+            nd->model = g_strdup("virtio");
+        }
+
+        pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+    }
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
-- 
2.17.1

  parent reply	other threads:[~2018-10-04 20:07 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-04 20:06 [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-10-25 18:47   ` Peter Maydell
2018-10-30 21:39     ` Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-10-04 20:06 ` Alistair Francis [this message]
2018-10-10 12:26 ` [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V Andrea Bolognani
2018-10-10 13:11   ` Stephen  Bates
2018-10-10 13:43     ` Andrea Bolognani
2018-10-10 17:24       ` Stephen  Bates
2018-10-10 17:32       ` Stephen  Bates
2018-10-10 18:01         ` Alistair
2018-10-10 18:47           ` Stephen  Bates
2018-10-10 19:53             ` Alistair
2018-10-11  5:45               ` Andrea Bolognani
2018-10-10 19:01           ` Stephen  Bates
2018-10-10 19:55             ` Alistair
2018-10-10 17:57   ` Alistair
2018-10-11  5:59     ` Andrea Bolognani
2018-10-11  7:55       ` Richard W.M. Jones
2018-10-11 12:00         ` Peter Maydell
2018-10-11  8:01       ` Richard W.M. Jones
2018-10-11 11:45         ` Richard W.M. Jones
2018-10-11 12:15           ` Andrea Bolognani
2018-10-11 12:25             ` Stephen  Bates
2018-10-11 17:40       ` Alistair Francis
2018-10-12 13:46         ` Andrea Bolognani
2018-10-12 16:12           ` Alistair Francis
2018-10-15 14:39             ` Andrea Bolognani
2018-10-15 16:59               ` Alistair Francis
2018-10-16  7:38                 ` Andrea Bolognani
2018-10-16 14:11                   ` Andrea Bolognani
2018-10-16 14:55                     ` Andrea Bolognani
2018-10-16 17:31                       ` Stephen  Bates

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