From: Alistair <alistair23@gmail.com>
To: Andrea Bolognani <abologna@redhat.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"mjc@sifive.com" <mjc@sifive.com>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
"stephen@eideticom.com" <stephen@eideticom.com>,
"Richard W.M. Jones" <rjones@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V
Date: Wed, 10 Oct 2018 10:57:02 -0700 [thread overview]
Message-ID: <892d54c5-2851-74ec-bdf2-286c1665c44f@gmail.com> (raw)
In-Reply-To: <5dd21056229d12a1af8d65e9208f4de43ba4a2ae.camel@redhat.com>
On 10/10/2018 05:26 AM, Andrea Bolognani wrote:
> On Thu, 2018-10-04 at 20:06 +0000, Alistair Francis wrote:
>> Alistair Francis (5):
>> hw/riscv/virt: Increase the number of interrupts
>> hw/riscv/virt: Connect the gpex PCIe
>> riscv: Enable VGA and PCIE_VGA
>> hw/riscv/sifive_u: Connect the Xilinx PCIe
>> hw/riscv/virt: Connect a VirtIO net PCIe device
>>
>> default-configs/riscv32-softmmu.mak | 10 +++-
>> default-configs/riscv64-softmmu.mak | 10 +++-
>> hw/riscv/sifive_u.c | 64 +++++++++++++++++++++++++
>> hw/riscv/virt.c | 72 +++++++++++++++++++++++++++++
>> include/hw/riscv/sifive_u.h | 4 +-
>> include/hw/riscv/virt.h | 6 ++-
>> 6 files changed, 161 insertions(+), 5 deletions(-)
>
> I gave v4 a try a few weeks ago because I wanted to see what would
> be needed to wire this up on the libvirt side. Turns out, not much
> really :)
Great!
>
> I still have a couple of questions that hopefully you'll be able
> to answer:
>
> * what should libvirt look for to figure out whether or not a RISC-V
> guest will have PCI support? For aarch64 we look for the presence
> of the 'gpex-pcihost' device, but of course that won't work for
> RISC-V so we need something else;
I'm not sure what you mean here. Why can we not do the same thing with
RISC-V?
>
> * I have succesfully started a RISC-V guest with virtio-pci devices
> attached but, while they show up in 'info qtree' and friends, the
> guest OS itself doesn't seem to recognize any of them - not even
> pcie.0! I'm using the guest images listed at [1] and following the
> corresponding instructions, but I think the BBL build (config at
> [2]) is missing some feature... Any ideas what we would need to
> add there?
I use this monolithic config:
https://github.com/alistair23/meta-riscv/blob/7a950aa705b439b5ec19bb6f094930888335ba7b/recipes-kernel/linux/files/freedom-u540/defconfig
It has way too much enabled, but I think if you copy the PCIe part that
should be enough.
My colleague Atish has Fedora booting on real hardware with the
MicroSemi PCIe support. You can also see his config here:
https://github.com/westerndigitalcorporation/RISC-V-Linux/blob/master/riscv-linux-conf/config_fedora_success_4.19_demo_sep11
Obviously on top of that you will need to enable the VirtIO support as
that doesn't exist in the hardware.
Alistair
>
> If you can help with these I'll give the patches another spin and
> gladly provide my Tested-by :)
>
>
> [1] https://fedoraproject.org/wiki/Architectures/RISC-V/Installing
> [2] https://github.com/rwmjones/fedora-riscv-kernel/blob/master/config
>
next prev parent reply other threads:[~2018-10-10 17:57 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 20:06 [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-10-25 18:47 ` Peter Maydell
2018-10-30 21:39 ` Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
2018-10-10 12:26 ` [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V Andrea Bolognani
2018-10-10 13:11 ` Stephen Bates
2018-10-10 13:43 ` Andrea Bolognani
2018-10-10 17:24 ` Stephen Bates
2018-10-10 17:32 ` Stephen Bates
2018-10-10 18:01 ` Alistair
2018-10-10 18:47 ` Stephen Bates
2018-10-10 19:53 ` Alistair
2018-10-11 5:45 ` Andrea Bolognani
2018-10-10 19:01 ` Stephen Bates
2018-10-10 19:55 ` Alistair
2018-10-10 17:57 ` Alistair [this message]
2018-10-11 5:59 ` Andrea Bolognani
2018-10-11 7:55 ` Richard W.M. Jones
2018-10-11 12:00 ` Peter Maydell
2018-10-11 8:01 ` Richard W.M. Jones
2018-10-11 11:45 ` Richard W.M. Jones
2018-10-11 12:15 ` Andrea Bolognani
2018-10-11 12:25 ` Stephen Bates
2018-10-11 17:40 ` Alistair Francis
2018-10-12 13:46 ` Andrea Bolognani
2018-10-12 16:12 ` Alistair Francis
2018-10-15 14:39 ` Andrea Bolognani
2018-10-15 16:59 ` Alistair Francis
2018-10-16 7:38 ` Andrea Bolognani
2018-10-16 14:11 ` Andrea Bolognani
2018-10-16 14:55 ` Andrea Bolognani
2018-10-16 17:31 ` Stephen Bates
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