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From: Paolo Bonzini <pbonzini@redhat.com>
To: Efimov Vasily <real@ispras.ru>, qemu-devel@nongnu.org
Cc: John Snow <jsnow@redhat.com>,
	qemu-block@nongnu.org, Gerd Hoffmann <kraxel@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Kevin Wolf <kwolf@redhat.com>, Max Reitz <mreitz@redhat.com>,
	Richard Henderson <rth@twiddle.net>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Kirill Batuzov <batuzovk@ispras.ru>
Subject: Re: [Qemu-devel] [PATCH 11/13] ICH9 LPC: move call of isa_bus_irqs to 'realize' method
Date: Fri, 17 Jun 2016 16:03:58 +0200	[thread overview]
Message-ID: <4c150d1b-05f5-db66-5a06-dcbe8b8baece@redhat.com> (raw)
In-Reply-To: <1466169069-29375-12-git-send-email-real@ispras.ru>



On 17/06/2016 15:11, Efimov Vasily wrote:
> The isa_bus_irqs function initializes ISA bus IRQ array pointer with specified
> value.
> 
> Previously the ICH9 LPC bridge model did not have its own IRQs but
> only IRQ pointer cache. And same GSI were used for ISA bus and other sources
> behind the bridge (PCI, SCI). Hence, the pc_q35_init was only possible place to
> setup both ISA bus IRQs and the bridge IRQ cache.
> 
> As a result, the call of isa_bus_irqs was made from pc_q35_init.
> 
> Now the ICH9 LPC bridge has its own output IRQs which are connected to GSI. The
> output IRQs are already used to route IRQs from PCI and SCI.
> 
> The patch makes the ICH9 LPC bridge output IRQs to used for ISA bus too.
> 
> Signed-off-by: Efimov Vasily <real@ispras.ru>
> ---
>  hw/i386/pc_q35.c  | 3 ---
>  hw/isa/lpc_ich9.c | 2 ++
>  2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index a1fad2b..4661be2 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -200,9 +200,6 @@ static void pc_q35_init(MachineState *machine)
>      pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
>      isa_bus = ich9_lpc->isa_bus;
>  
> -    /*end early*/
> -    isa_bus_irqs(isa_bus, gsi);
> -
>      if (kvm_pic_in_kernel()) {
>          i8259 = kvm_i8259_init(isa_bus);
>      } else if (xen_enabled()) {
> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
> index 1e8e0e4..798d9e7 100644
> --- a/hw/isa/lpc_ich9.c
> +++ b/hw/isa/lpc_ich9.c
> @@ -639,6 +639,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
>  
>      qdev_init_gpio_out(dev, lpc->pic, ISA_NUM_IRQS);
>      qdev_init_gpio_out(dev, lpc->ioapic, IOAPIC_NUM_PINS);
> +
> +    isa_bus_irqs(isa_bus, lpc->pic);

The modeling here was weird.  ICH9 does not need both ->pic and
->ioapic, it can make do with just a 24-entry GSI array.

If you change that in the previous patch, this one makes much more
sense.  As it is now, it seems like the ISA bus will not deliver
interrupts to the IOAPIC, and that makes no sense.

Thanks,

Paolo

>  }
>  
>  static bool ich9_rst_cnt_needed(void *opaque)
> 

  reply	other threads:[~2016-06-17 14:04 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-17 13:10 [Qemu-devel] [PATCH 00/13] Make Q35 devices closer to Qemu object model Efimov Vasily
2016-06-17 13:10 ` [Qemu-devel] [PATCH 01/13] ide: move headers to include folder Efimov Vasily
2016-06-17 13:18   ` Paolo Bonzini
2016-06-17 13:10 ` [Qemu-devel] [PATCH 02/13] pcspk: convert "pit" property type from ptr to link Efimov Vasily
2016-06-17 13:19   ` Paolo Bonzini
2016-06-17 13:20   ` Paolo Bonzini
2016-06-17 13:10 ` [Qemu-devel] [PATCH 03/13] vmport: identify vmport type by macro TYPE_VMPORT Efimov Vasily
2016-06-17 13:19   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 04/13] pflash: make TYPE_CFI_PFLASH0{1, 2} macros public Efimov Vasily
2016-06-17 13:19   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 05/13] Q35: implement property interfece to several parameters Efimov Vasily
2016-06-17 13:20   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 06/13] pc_q35: configure Q35 instance using properties Efimov Vasily
2016-06-17 13:20   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 07/13] pckbd: handle A20 IRQ as GPIO Efimov Vasily
2016-06-17 13:23   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 08/13] port92: " Efimov Vasily
2016-06-17 13:24   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 09/13] ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro public Efimov Vasily
2016-06-17 13:25   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 10/13] ICH9 LPC: handle PIC and I/O APIC IRQs as qdev GPIO Efimov Vasily
2016-06-17 13:26   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 11/13] ICH9 LPC: move call of isa_bus_irqs to 'realize' method Efimov Vasily
2016-06-17 14:03   ` Paolo Bonzini [this message]
2016-06-20 14:40     ` Paolo Bonzini
2016-06-21 13:46       ` Ефимов Василий
2016-06-21 17:08         ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 12/13] MC146818 RTC: add GPIO access to output IRQ Efimov Vasily
2016-06-17 14:08   ` Paolo Bonzini
2016-06-17 13:11 ` [Qemu-devel] [PATCH 13/13] ICH9 LPC: configure PCI IRQs routing internally Efimov Vasily
2016-06-17 14:11   ` Paolo Bonzini

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