* [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
@ 2016-06-30 15:50 Cédric Le Goater
2016-06-30 15:50 ` [Qemu-devel] [PATCH 2/2] hw/misc: use macros to define hw-strap1 register on Aspeed SOC Cédric Le Goater
2016-06-30 18:24 ` [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Peter Maydell
0 siblings, 2 replies; 7+ messages in thread
From: Cédric Le Goater @ 2016-06-30 15:50 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Andrew Jeffery, Cédric Le Goater
These strap registers are complex enough, let's not mix them.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/aspeed_scu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4f9df581e70a..14b2d75e6049 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -254,7 +254,7 @@ static const VMStateDescription vmstate_aspeed_scu = {
static Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
- DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap1, 0),
+ DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 2/2] hw/misc: use macros to define hw-strap1 register on Aspeed SOC
2016-06-30 15:50 [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Cédric Le Goater
@ 2016-06-30 15:50 ` Cédric Le Goater
2016-06-30 18:24 ` [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Peter Maydell
1 sibling, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2016-06-30 15:50 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm, Andrew Jeffery, Cédric Le Goater
This gives some explanation behind the magic number 0x120CE416.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/palmetto-bmc.c | 16 ++++++++-
include/hw/misc/aspeed_scu.h | 78 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index fcbb4f197162..8fac67617825 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -22,6 +22,19 @@
#include "sysemu/blockdev.h"
#include "hw/block/flash.h"
+#define PALMETTO_BMC_HW_STRAP1 ( \
+ SCU_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
+ SCU_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
+ SCU_HW_STRAP_ACPI_DIS | \
+ SCU_HW_STRAP_SET_CLK_SOURCE(CLK_48M_IN) | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_LPC_RESET_PIN | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
+ SCU_HW_STRAP_SET_CPU_AHB_RATIO(CPU_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
+ SCU_HW_STRAP_BOOT_MODE(SPI_BOOT))
+
static struct arm_boot_info palmetto_bmc_binfo = {
.loader_start = AST2400_SDRAM_BASE,
.board_id = 0,
@@ -77,7 +90,8 @@ static void palmetto_bmc_init(MachineState *machine)
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
- object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ object_property_set_int(OBJECT(&bmc->soc), PALMETTO_BMC_HW_STRAP1,
+ "hw-strap1",
&error_abort);
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 6b8e46f85fad..92b81de309b6 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -31,4 +31,82 @@ typedef struct AspeedSCUState {
uint32_t hw_strap2;
} AspeedSCUState;
+/*
+ * Hardware strapping register definition
+ */
+#define SCU_HW_STRAP_SW_DEFINE(x) (x << 29)
+#define SCU_HW_STRAP_SW_DEFINE_MASK (0x3 << 29)
+
+#define SCU_HW_STRAP_DRAM_SIZE(x) (x << 27)
+#define SCU_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
+#define DRAM_SIZE_64MB 0
+#define DRAM_SIZE_128MB 1
+#define DRAM_SIZE_256MB 2
+#define DRAM_SIZE_512MB 3
+
+#define SCU_HW_STRAP_DRAM_CONFIG(x) (x << 24)
+#define SCU_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
+
+#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
+#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
+#define SCU_HW_STRAP_ACPI_DIS (0x1 << 19)
+
+/* bit 23, 18 [1,0] */
+#define SCU_HW_STRAP_SET_CLK_SOURCE(x) ((((x & 0x3) >> 1) << 23) | \
+ ((x & 0x1) << 18))
+#define SCU_HW_STRAP_GET_CLK_SOURCE(x) (((x >> 23) & 0x1 << 1) | \
+ ((x >> 18) & 0x1))
+#define SCU_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
+#define CLK_25M_IN (0x1 << 23)
+#define CLK_24M_IN 0
+#define CLK_48M_IN 1
+#define CLK_25M_IN_24M_USB_CKI 2
+#define CLK_25M_IN_48M_USB_CKI 3
+
+#define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
+#define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
+#define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
+#define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
+#define SCU_HW_STRAP_SPI_MODE(x) (x << 12)
+#define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
+#define SCU_HW_STRAP_SPI_DIS 0
+#define SCU_HW_STRAP_SPI_MASTER 1
+#define SCU_HW_STRAP_SPI_M_S_EN 2
+#define SCU_HW_STRAP_SPI_PASS_THROUGH 3
+
+#define SCU_HW_STRAP_SET_CPU_AHB_RATIO(x) (x << 10)
+#define SCU_HW_STRAP_GET_CPU_AHB_RATIO(x) ((x >> 10) & 3)
+#define SCU_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
+#define CPU_AHB_RATIO_1_1 0
+#define CPU_AHB_RATIO_2_1 1
+#define CPU_AHB_RATIO_4_1 2
+#define CPU_AHB_RATIO_3_1 3
+
+#define SCU_HW_STRAP_GET_H_PLL_CLK(x) ((x >> 8) & 0x3)
+#define SCU_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
+#define CPU_384MHZ 0
+#define CPU_360MHZ 1
+#define CPU_336MHZ 2
+#define CPU_408MHZ 3
+
+#define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
+#define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
+#define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
+#define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
+
+#define SCU_HW_STRAP_VGA_SIZE_GET(x) ((x >> 2) & 0x3)
+#define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
+#define SCU_HW_STRAP_VGA_SIZE_SET(x) (x << 2)
+#define VGA_8M_DRAM 0
+#define VGA_16M_DRAM 1
+#define VGA_32M_DRAM 2
+#define VGA_64M_DRAM 3
+
+#define SCU_HW_STRAP_BOOT_MODE(x) (x)
+#define NOR_BOOT 0
+#define NAND_BOOT 1
+#define SPI_BOOT 2
+#define DIS_BOOT 3
+
#endif /* ASPEED_SCU_H */
--
2.1.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
2016-06-30 15:50 [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Cédric Le Goater
2016-06-30 15:50 ` [Qemu-devel] [PATCH 2/2] hw/misc: use macros to define hw-strap1 register on Aspeed SOC Cédric Le Goater
@ 2016-06-30 18:24 ` Peter Maydell
2016-07-01 6:11 ` Cédric Le Goater
1 sibling, 1 reply; 7+ messages in thread
From: Peter Maydell @ 2016-06-30 18:24 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: QEMU Developers, qemu-arm, Andrew Jeffery
On 30 June 2016 at 16:50, Cédric Le Goater <clg@kaod.org> wrote:
> These strap registers are complex enough, let's not mix them.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Was there a cover letter for this patchset? I can't find
it in my email...
thanks
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
2016-06-30 18:24 ` [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Peter Maydell
@ 2016-07-01 6:11 ` Cédric Le Goater
2016-07-01 6:41 ` Cédric Le Goater
2016-07-01 8:02 ` Peter Maydell
0 siblings, 2 replies; 7+ messages in thread
From: Cédric Le Goater @ 2016-07-01 6:11 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, qemu-arm, Andrew Jeffery
On 06/30/2016 08:24 PM, Peter Maydell wrote:
> On 30 June 2016 at 16:50, Cédric Le Goater <clg@kaod.org> wrote:
>> These strap registers are complex enough, let's not mix them.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Was there a cover letter for this patchset? I can't find
> it in my email...
Ah :/ No, I didn't send one as the patches were small and self
contained. Should we each time ?
Thanks,
C.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
2016-07-01 6:11 ` Cédric Le Goater
@ 2016-07-01 6:41 ` Cédric Le Goater
2016-07-01 8:02 ` Peter Maydell
1 sibling, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2016-07-01 6:41 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, qemu-arm, Andrew Jeffery
On 07/01/2016 08:11 AM, Cédric Le Goater wrote:
> On 06/30/2016 08:24 PM, Peter Maydell wrote:
>> On 30 June 2016 at 16:50, Cédric Le Goater <clg@kaod.org> wrote:
>>> These strap registers are complex enough, let's not mix them.
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> Was there a cover letter for this patchset? I can't find
>> it in my email...
>
> Ah :/ No, I didn't send one as the patches were small and self
> contained. Should we each time ?
Let me rework that if possible. I need to add a few things.
Thanks,
C.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
2016-07-01 6:11 ` Cédric Le Goater
2016-07-01 6:41 ` Cédric Le Goater
@ 2016-07-01 8:02 ` Peter Maydell
2016-07-01 8:28 ` Cédric Le Goater
1 sibling, 1 reply; 7+ messages in thread
From: Peter Maydell @ 2016-07-01 8:02 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: QEMU Developers, qemu-arm, Andrew Jeffery
On 1 July 2016 at 07:11, Cédric Le Goater <clg@kaod.org> wrote:
> On 06/30/2016 08:24 PM, Peter Maydell wrote:
>> On 30 June 2016 at 16:50, Cédric Le Goater <clg@kaod.org> wrote:
>>> These strap registers are complex enough, let's not mix them.
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> Was there a cover letter for this patchset? I can't find
>> it in my email...
>
> Ah :/ No, I didn't send one as the patches were small and self
> contained. Should we each time ?
The basic rule is that single standalone patches don't
need a cover letter; a series with more than one patch
should have a cover letter. Some of our automated tooling
gets confused otherwise (also I like to be able to have a
single email to mark for attention in my mail client).
These confused me a bit because they had the series
indicators in the subject (1/2, 2/2) but no cover.
thanks
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property
2016-07-01 8:02 ` Peter Maydell
@ 2016-07-01 8:28 ` Cédric Le Goater
0 siblings, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2016-07-01 8:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, qemu-arm, Andrew Jeffery
On 07/01/2016 10:02 AM, Peter Maydell wrote:
> On 1 July 2016 at 07:11, Cédric Le Goater <clg@kaod.org> wrote:
>> On 06/30/2016 08:24 PM, Peter Maydell wrote:
>>> On 30 June 2016 at 16:50, Cédric Le Goater <clg@kaod.org> wrote:
>>>> These strap registers are complex enough, let's not mix them.
>>>>
>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>
>>> Was there a cover letter for this patchset? I can't find
>>> it in my email...
>>
>> Ah :/ No, I didn't send one as the patches were small and self
>> contained. Should we each time ?
>
> The basic rule is that single standalone patches don't
> need a cover letter; a series with more than one patch
> should have a cover letter. Some of our automated tooling
> gets confused otherwise (also I like to be able to have a
> single email to mark for attention in my mail client).
> These confused me a bit because they had the series
> indicators in the subject (1/2, 2/2) but no cover.
Yes, the email threading was a bit confusing in my mail
client also. Sorry about that.
I will resend with a cover letter. I need to add where
the macros are coming from.
Thanks,
C.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-07-01 8:29 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-30 15:50 [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Cédric Le Goater
2016-06-30 15:50 ` [Qemu-devel] [PATCH 2/2] hw/misc: use macros to define hw-strap1 register on Aspeed SOC Cédric Le Goater
2016-06-30 18:24 ` [Qemu-devel] [PATCH 1/2] hw/misc: fix Aspeed SCU hw-strap2 property Peter Maydell
2016-07-01 6:11 ` Cédric Le Goater
2016-07-01 6:41 ` Cédric Le Goater
2016-07-01 8:02 ` Peter Maydell
2016-07-01 8:28 ` Cédric Le Goater
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.