* [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init
@ 2021-05-12 21:00 ` Nikola Cornij
0 siblings, 0 replies; 21+ messages in thread
From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König, Pan,
Xinhui, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Ben Skeggs, Mikita Lipski, Eryk Brol,
Aurabindo Pillai, Rodrigo Siqueira, Nikola Cornij, Wayne Lin,
Chris Park, Meenakshikumar Somasundaram, Ville Syrjälä,
Imre Deak, Lyude Paul, Ramalingam C, Sean Paul, Lee Shawn C,
Lucas De Marchi, Matt Roper, Dave Airlie, James Jones, dri-devel,
linux-kernel, intel-gfx, nouveau
Change log:
v2:
- Added 'Acked-by' to comment
v1:
- Initial
Nikola Cornij (1):
drm/dp_mst: Use kHz as link rate units when settig source max link
caps at init
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++--
drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++--
drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
include/drm/drm_dp_mst_helper.h | 8 ++++----
6 files changed, 16 insertions(+), 15 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, James Jones, Rodrigo Siqueira, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Nikola Cornij, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Change log: v2: - Added 'Acked-by' to comment v1: - Initial Nikola Cornij (1): drm/dp_mst: Use kHz as link rate units when settig source max link caps at init .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Leo Li, Lucas De Marchi, intel-gfx, Maxime Ripard, Nikola Cornij, Sean Paul, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Christian König Change log: v2: - Added 'Acked-by' to comment v1: - Initial Nikola Cornij (1): drm/dp_mst: Use kHz as link rate units when settig source max link caps at init .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Leo Li, Lucas De Marchi, intel-gfx, Nikola Cornij, Sean Paul, Rodrigo Vivi, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Change log: v2: - Added 'Acked-by' to comment v1: - Initial Nikola Cornij (1): drm/dp_mst: Use kHz as link rate units when settig source max link caps at init .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Nouveau] [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, Rodrigo Siqueira, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Nikola Cornij, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Change log: v2: - Added 'Acked-by' to comment v1: - Initial Nikola Cornij (1): drm/dp_mst: Use kHz as link rate units when settig source max link caps at init .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) -- 2.25.1 _______________________________________________ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (2 preceding siblings ...) (?) @ 2021-05-12 21:00 ` Nikola Cornij -1 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König, Pan, Xinhui, David Airlie, Daniel Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Ben Skeggs, Mikita Lipski, Eryk Brol, Aurabindo Pillai, Rodrigo Siqueira, Nikola Cornij, Wayne Lin, Chris Park, Meenakshikumar Somasundaram, Ville Syrjälä, Imre Deak, Lyude Paul, Ramalingam C, Sean Paul, Lee Shawn C, Lucas De Marchi, Matt Roper, Dave Airlie, James Jones, dri-devel, linux-kernel, intel-gfx, nouveau, Jani Nikula [why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4a0c24ce5f7d..f78dd021f591 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, - (u8)max_link_enc_cap.lane_count, - (u8)max_link_enc_cap.link_rate, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 54604633e65c..32b7f8983b94 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms } lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count); - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, - drm_dp_bw_code_to_link_rate(link_rate), + link_rate, lane_count); if (mgr->pbn_div == 0) { ret = -EINVAL; @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit * @max_payloads: maximum number of payloads this GPU can source * @max_lane_count: maximum number of lanes this GPU supports - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD + * @max_link_rate: maximum link rate per lane this GPU supports in kHz * @conn_base_id: the connector object ID the MST device is connected to. * * Return 0 for success, or negative error code on failure @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id) { struct drm_dp_mst_topology_state *mst_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f608c0cb98f4..26f65445bc8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, - (u8)dig_port->max_lanes, - drm_dp_link_rate_to_bw_code(max_source_rate), + dig_port->max_lanes, + max_source_rate, conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index c46d0374b6e6..f949767698fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->mgr.cbs = &nv50_mstm; ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, - (u8)max_payloads, outp->dcb->dpconf.link_nr, - (u8)outp->dcb->dpconf.link_bw, conn_base_id); + max_payloads, outp->dcb->dpconf.link_nr, + drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), + conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 13072c2a6502..ec867fa880a4 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector *radeon_connector) radeon_connector->mst_mgr.cbs = &mst_cbs; return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, &radeon_connector->ddc_bus->aux, 16, 6, - 4, (u8)max_link_rate, + 4, drm_dp_bw_code_to_link_rate(max_link_rate), radeon_connector->base.base.id); } diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index c87a829b6498..ddb9231d0309 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { /** * @max_lane_count: maximum number of lanes the GPU can drive. */ - u8 max_lane_count; + int max_lane_count; /** - * @max_link_rate: maximum link rate per lane GPU can output. + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. */ - u8 max_link_rate; + int max_link_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value. @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id); void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- 2.25.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Nikola Cornij, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König [why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4a0c24ce5f7d..f78dd021f591 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, - (u8)max_link_enc_cap.lane_count, - (u8)max_link_enc_cap.link_rate, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 54604633e65c..32b7f8983b94 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms } lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count); - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, - drm_dp_bw_code_to_link_rate(link_rate), + link_rate, lane_count); if (mgr->pbn_div == 0) { ret = -EINVAL; @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit * @max_payloads: maximum number of payloads this GPU can source * @max_lane_count: maximum number of lanes this GPU supports - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD + * @max_link_rate: maximum link rate per lane this GPU supports in kHz * @conn_base_id: the connector object ID the MST device is connected to. * * Return 0 for success, or negative error code on failure @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id) { struct drm_dp_mst_topology_state *mst_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f608c0cb98f4..26f65445bc8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, - (u8)dig_port->max_lanes, - drm_dp_link_rate_to_bw_code(max_source_rate), + dig_port->max_lanes, + max_source_rate, conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index c46d0374b6e6..f949767698fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->mgr.cbs = &nv50_mstm; ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, - (u8)max_payloads, outp->dcb->dpconf.link_nr, - (u8)outp->dcb->dpconf.link_bw, conn_base_id); + max_payloads, outp->dcb->dpconf.link_nr, + drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), + conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 13072c2a6502..ec867fa880a4 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector *radeon_connector) radeon_connector->mst_mgr.cbs = &mst_cbs; return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, &radeon_connector->ddc_bus->aux, 16, 6, - 4, (u8)max_link_rate, + 4, drm_dp_bw_code_to_link_rate(max_link_rate), radeon_connector->base.base.id); } diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index c87a829b6498..ddb9231d0309 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { /** * @max_lane_count: maximum number of lanes the GPU can drive. */ - u8 max_lane_count; + int max_lane_count; /** - * @max_link_rate: maximum link rate per lane GPU can output. + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. */ - u8 max_link_rate; + int max_link_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value. @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id); void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Intel-gfx] [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Leo Li, Lucas De Marchi, intel-gfx, Maxime Ripard, Nikola Cornij, Sean Paul, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Christian König [why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4a0c24ce5f7d..f78dd021f591 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, - (u8)max_link_enc_cap.lane_count, - (u8)max_link_enc_cap.link_rate, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 54604633e65c..32b7f8983b94 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms } lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count); - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, - drm_dp_bw_code_to_link_rate(link_rate), + link_rate, lane_count); if (mgr->pbn_div == 0) { ret = -EINVAL; @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit * @max_payloads: maximum number of payloads this GPU can source * @max_lane_count: maximum number of lanes this GPU supports - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD + * @max_link_rate: maximum link rate per lane this GPU supports in kHz * @conn_base_id: the connector object ID the MST device is connected to. * * Return 0 for success, or negative error code on failure @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id) { struct drm_dp_mst_topology_state *mst_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f608c0cb98f4..26f65445bc8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, - (u8)dig_port->max_lanes, - drm_dp_link_rate_to_bw_code(max_source_rate), + dig_port->max_lanes, + max_source_rate, conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index c46d0374b6e6..f949767698fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->mgr.cbs = &nv50_mstm; ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, - (u8)max_payloads, outp->dcb->dpconf.link_nr, - (u8)outp->dcb->dpconf.link_bw, conn_base_id); + max_payloads, outp->dcb->dpconf.link_nr, + drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), + conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 13072c2a6502..ec867fa880a4 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector *radeon_connector) radeon_connector->mst_mgr.cbs = &mst_cbs; return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, &radeon_connector->ddc_bus->aux, 16, 6, - 4, (u8)max_link_rate, + 4, drm_dp_bw_code_to_link_rate(max_link_rate), radeon_connector->base.base.id); } diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index c87a829b6498..ddb9231d0309 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { /** * @max_lane_count: maximum number of lanes the GPU can drive. */ - u8 max_lane_count; + int max_lane_count; /** - * @max_link_rate: maximum link rate per lane GPU can output. + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. */ - u8 max_link_rate; + int max_link_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value. @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id); void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- 2.25.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Leo Li, Lucas De Marchi, intel-gfx, Nikola Cornij, Sean Paul, Rodrigo Vivi, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König [why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4a0c24ce5f7d..f78dd021f591 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, - (u8)max_link_enc_cap.lane_count, - (u8)max_link_enc_cap.link_rate, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 54604633e65c..32b7f8983b94 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms } lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count); - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, - drm_dp_bw_code_to_link_rate(link_rate), + link_rate, lane_count); if (mgr->pbn_div == 0) { ret = -EINVAL; @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit * @max_payloads: maximum number of payloads this GPU can source * @max_lane_count: maximum number of lanes this GPU supports - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD + * @max_link_rate: maximum link rate per lane this GPU supports in kHz * @conn_base_id: the connector object ID the MST device is connected to. * * Return 0 for success, or negative error code on failure @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id) { struct drm_dp_mst_topology_state *mst_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f608c0cb98f4..26f65445bc8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, - (u8)dig_port->max_lanes, - drm_dp_link_rate_to_bw_code(max_source_rate), + dig_port->max_lanes, + max_source_rate, conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index c46d0374b6e6..f949767698fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->mgr.cbs = &nv50_mstm; ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, - (u8)max_payloads, outp->dcb->dpconf.link_nr, - (u8)outp->dcb->dpconf.link_bw, conn_base_id); + max_payloads, outp->dcb->dpconf.link_nr, + drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), + conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 13072c2a6502..ec867fa880a4 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector *radeon_connector) radeon_connector->mst_mgr.cbs = &mst_cbs; return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, &radeon_connector->ddc_bus->aux, 16, 6, - 4, (u8)max_link_rate, + 4, drm_dp_bw_code_to_link_rate(max_link_rate), radeon_connector->base.base.id); } diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index c87a829b6498..ddb9231d0309 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { /** * @max_lane_count: maximum number of lanes the GPU can drive. */ - u8 max_lane_count; + int max_lane_count; /** - * @max_link_rate: maximum link rate per lane GPU can output. + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. */ - u8 max_link_rate; + int max_link_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value. @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id); void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- 2.25.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Nouveau] [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-12 21:00 ` Nikola Cornij 0 siblings, 0 replies; 21+ messages in thread From: Nikola Cornij @ 2021-05-12 21:00 UTC (permalink / raw) To: amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Nikola Cornij, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König [why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 8 ++++---- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4a0c24ce5f7d..f78dd021f591 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, &aconnector->dm_dp_aux.aux, 16, 4, - (u8)max_link_enc_cap.lane_count, - (u8)max_link_enc_cap.link_rate, + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 54604633e65c..32b7f8983b94 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms } lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count); - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, - drm_dp_bw_code_to_link_rate(link_rate), + link_rate, lane_count); if (mgr->pbn_div == 0) { ret = -EINVAL; @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit * @max_payloads: maximum number of payloads this GPU can source * @max_lane_count: maximum number of lanes this GPU supports - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD + * @max_link_rate: maximum link rate per lane this GPU supports in kHz * @conn_base_id: the connector object ID the MST device is connected to. * * Return 0 for success, or negative error code on failure @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id) { struct drm_dp_mst_topology_state *mst_state; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index f608c0cb98f4..26f65445bc8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, - (u8)dig_port->max_lanes, - drm_dp_link_rate_to_bw_code(max_source_rate), + dig_port->max_lanes, + max_source_rate, conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index c46d0374b6e6..f949767698fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->mgr.cbs = &nv50_mstm; ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, - (u8)max_payloads, outp->dcb->dpconf.link_nr, - (u8)outp->dcb->dpconf.link_bw, conn_base_id); + max_payloads, outp->dcb->dpconf.link_nr, + drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), + conn_base_id); if (ret) return ret; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 13072c2a6502..ec867fa880a4 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector *radeon_connector) radeon_connector->mst_mgr.cbs = &mst_cbs; return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, &radeon_connector->ddc_bus->aux, 16, 6, - 4, (u8)max_link_rate, + 4, drm_dp_bw_code_to_link_rate(max_link_rate), radeon_connector->base.base.id); } diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index c87a829b6498..ddb9231d0309 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { /** * @max_lane_count: maximum number of lanes the GPU can drive. */ - u8 max_lane_count; + int max_lane_count; /** - * @max_link_rate: maximum link rate per lane GPU can output. + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. */ - u8 max_link_rate; + int max_link_rate; /** * @conn_base_id: DRM connector ID this mgr is connected to. Only used * to build the MST connector path value. @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, struct drm_device *dev, struct drm_dp_aux *aux, int max_dpcd_transaction_bytes, int max_payloads, - u8 max_lane_count, u8 max_link_rate, + int max_lane_count, int max_link_rate, int conn_base_id); void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- 2.25.1 _______________________________________________ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (2 preceding siblings ...) (?) @ 2021-05-13 16:30 ` Lyude Paul -1 siblings, 0 replies; 21+ messages in thread From: Lyude Paul @ 2021-05-13 16:30 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: Harry Wentland, Leo Li, Alex Deucher, Christian König, Pan, Xinhui, David Airlie, Daniel Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Ben Skeggs, Mikita Lipski, Eryk Brol, Aurabindo Pillai, Rodrigo Siqueira, Wayne Lin, Chris Park, Meenakshikumar Somasundaram, Ville Syrjälä, Imre Deak, Ramalingam C, Sean Paul, Lee Shawn C, Lucas De Marchi, Matt Roper, Dave Airlie, James Jones, dri-devel, linux-kernel, intel-gfx, nouveau, Jani Nikula Reviewed-by: Lyude Paul <lyude@redhat.com> Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth, which makes kHz a more generic unit. This should also make > forward-compatibility with new DP standards easier. > > [how] > - Replace 'link rate DPCD code' with 'link rate in kHz' when used with > drm_dp_mst_topology_mgr_init() > - Add/remove related DPCD code conversion from/to kHz where applicable > > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- > drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- > include/drm/drm_dp_mst_helper.h | 8 ++++---- > 6 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > index 4a0c24ce5f7d..f78dd021f591 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct > amdgpu_display_manager *dm, > &aconnector->dm_dp_aux.aux, > 16, > 4, > - (u8)max_link_enc_cap.lane_count, > - (u8)max_link_enc_cap.link_rate, > + max_link_enc_cap.lane_count, > + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), > aconnector->connector_id); > > drm_connector_attach_dp_subconnector_property(&aconnector->base); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 54604633e65c..32b7f8983b94 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct > drm_dp_mst_topology_mgr *mgr, bool ms > } > > lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, > mgr->max_lane_count); > - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); > + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr- > >dpcd[1]), mgr->max_link_rate); > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, > - > drm_dp_bw_code_to_link_r > ate(link_rate), > + link_rate, > lane_count); > if (mgr->pbn_div == 0) { > ret = -EINVAL; > @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit > * @max_payloads: maximum number of payloads this GPU can source > * @max_lane_count: maximum number of lanes this GPU supports > - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD > + * @max_link_rate: maximum link rate per lane this GPU supports in kHz > * @conn_base_id: the connector object ID the MST device is connected to. > * > * Return 0 for success, or negative error code on failure > @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, int > max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id) > { > struct drm_dp_mst_topology_state *mst_state; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index f608c0cb98f4..26f65445bc8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > - (u8)dig_port->max_lanes, > - > drm_dp_link_rate_to_bw_code(max_source_rate), > + dig_port->max_lanes, > + max_source_rate, > conn_base_id); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index c46d0374b6e6..f949767698fc 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c > @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct > drm_dp_aux *aux, int aux_max, > mstm->mgr.cbs = &nv50_mstm; > > ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, > - (u8)max_payloads, outp->dcb- > >dpconf.link_nr, > - (u8)outp->dcb->dpconf.link_bw, > conn_base_id); > + max_payloads, outp->dcb- > >dpconf.link_nr, > + drm_dp_bw_code_to_link_rate(outp- > >dcb->dpconf.link_bw), > + conn_base_id); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c > b/drivers/gpu/drm/radeon/radeon_dp_mst.c > index 13072c2a6502..ec867fa880a4 100644 > --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c > +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c > @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector > *radeon_connector) > radeon_connector->mst_mgr.cbs = &mst_cbs; > return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, > &radeon_connector->ddc_bus->aux, > 16, 6, > - 4, (u8)max_link_rate, > + 4, > drm_dp_bw_code_to_link_rate(max_link_rate), > radeon_connector->base.base.id); > } > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index c87a829b6498..ddb9231d0309 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { > /** > * @max_lane_count: maximum number of lanes the GPU can drive. > */ > - u8 max_lane_count; > + int max_lane_count; > /** > - * @max_link_rate: maximum link rate per lane GPU can output. > + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. > */ > - u8 max_link_rate; > + int max_link_rate; > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value. > @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, > int max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id); > > void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-13 16:30 ` Lyude Paul 0 siblings, 0 replies; 21+ messages in thread From: Lyude Paul @ 2021-05-13 16:30 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Reviewed-by: Lyude Paul <lyude@redhat.com> Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth, which makes kHz a more generic unit. This should also make > forward-compatibility with new DP standards easier. > > [how] > - Replace 'link rate DPCD code' with 'link rate in kHz' when used with > drm_dp_mst_topology_mgr_init() > - Add/remove related DPCD code conversion from/to kHz where applicable > > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- > drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- > include/drm/drm_dp_mst_helper.h | 8 ++++---- > 6 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > index 4a0c24ce5f7d..f78dd021f591 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct > amdgpu_display_manager *dm, > &aconnector->dm_dp_aux.aux, > 16, > 4, > - (u8)max_link_enc_cap.lane_count, > - (u8)max_link_enc_cap.link_rate, > + max_link_enc_cap.lane_count, > + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), > aconnector->connector_id); > > drm_connector_attach_dp_subconnector_property(&aconnector->base); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 54604633e65c..32b7f8983b94 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct > drm_dp_mst_topology_mgr *mgr, bool ms > } > > lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, > mgr->max_lane_count); > - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); > + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr- > >dpcd[1]), mgr->max_link_rate); > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, > - > drm_dp_bw_code_to_link_r > ate(link_rate), > + link_rate, > lane_count); > if (mgr->pbn_div == 0) { > ret = -EINVAL; > @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit > * @max_payloads: maximum number of payloads this GPU can source > * @max_lane_count: maximum number of lanes this GPU supports > - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD > + * @max_link_rate: maximum link rate per lane this GPU supports in kHz > * @conn_base_id: the connector object ID the MST device is connected to. > * > * Return 0 for success, or negative error code on failure > @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, int > max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id) > { > struct drm_dp_mst_topology_state *mst_state; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index f608c0cb98f4..26f65445bc8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > - (u8)dig_port->max_lanes, > - > drm_dp_link_rate_to_bw_code(max_source_rate), > + dig_port->max_lanes, > + max_source_rate, > conn_base_id); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index c46d0374b6e6..f949767698fc 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c > @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct > drm_dp_aux *aux, int aux_max, > mstm->mgr.cbs = &nv50_mstm; > > ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, > - (u8)max_payloads, outp->dcb- > >dpconf.link_nr, > - (u8)outp->dcb->dpconf.link_bw, > conn_base_id); > + max_payloads, outp->dcb- > >dpconf.link_nr, > + drm_dp_bw_code_to_link_rate(outp- > >dcb->dpconf.link_bw), > + conn_base_id); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c > b/drivers/gpu/drm/radeon/radeon_dp_mst.c > index 13072c2a6502..ec867fa880a4 100644 > --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c > +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c > @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector > *radeon_connector) > radeon_connector->mst_mgr.cbs = &mst_cbs; > return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, > &radeon_connector->ddc_bus->aux, > 16, 6, > - 4, (u8)max_link_rate, > + 4, > drm_dp_bw_code_to_link_rate(max_link_rate), > radeon_connector->base.base.id); > } > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index c87a829b6498..ddb9231d0309 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { > /** > * @max_lane_count: maximum number of lanes the GPU can drive. > */ > - u8 max_lane_count; > + int max_lane_count; > /** > - * @max_link_rate: maximum link rate per lane GPU can output. > + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. > */ > - u8 max_link_rate; > + int max_link_rate; > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value. > @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, > int max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id); > > void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-13 16:30 ` Lyude Paul 0 siblings, 0 replies; 21+ messages in thread From: Lyude Paul @ 2021-05-13 16:30 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Leo Li, Lucas De Marchi, intel-gfx, Maxime Ripard, Sean Paul, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Christian König Reviewed-by: Lyude Paul <lyude@redhat.com> Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth, which makes kHz a more generic unit. This should also make > forward-compatibility with new DP standards easier. > > [how] > - Replace 'link rate DPCD code' with 'link rate in kHz' when used with > drm_dp_mst_topology_mgr_init() > - Add/remove related DPCD code conversion from/to kHz where applicable > > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- > drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- > include/drm/drm_dp_mst_helper.h | 8 ++++---- > 6 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > index 4a0c24ce5f7d..f78dd021f591 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct > amdgpu_display_manager *dm, > &aconnector->dm_dp_aux.aux, > 16, > 4, > - (u8)max_link_enc_cap.lane_count, > - (u8)max_link_enc_cap.link_rate, > + max_link_enc_cap.lane_count, > + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), > aconnector->connector_id); > > drm_connector_attach_dp_subconnector_property(&aconnector->base); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 54604633e65c..32b7f8983b94 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct > drm_dp_mst_topology_mgr *mgr, bool ms > } > > lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, > mgr->max_lane_count); > - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); > + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr- > >dpcd[1]), mgr->max_link_rate); > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, > - > drm_dp_bw_code_to_link_r > ate(link_rate), > + link_rate, > lane_count); > if (mgr->pbn_div == 0) { > ret = -EINVAL; > @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit > * @max_payloads: maximum number of payloads this GPU can source > * @max_lane_count: maximum number of lanes this GPU supports > - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD > + * @max_link_rate: maximum link rate per lane this GPU supports in kHz > * @conn_base_id: the connector object ID the MST device is connected to. > * > * Return 0 for success, or negative error code on failure > @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, int > max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id) > { > struct drm_dp_mst_topology_state *mst_state; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index f608c0cb98f4..26f65445bc8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > - (u8)dig_port->max_lanes, > - > drm_dp_link_rate_to_bw_code(max_source_rate), > + dig_port->max_lanes, > + max_source_rate, > conn_base_id); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index c46d0374b6e6..f949767698fc 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c > @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct > drm_dp_aux *aux, int aux_max, > mstm->mgr.cbs = &nv50_mstm; > > ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, > - (u8)max_payloads, outp->dcb- > >dpconf.link_nr, > - (u8)outp->dcb->dpconf.link_bw, > conn_base_id); > + max_payloads, outp->dcb- > >dpconf.link_nr, > + drm_dp_bw_code_to_link_rate(outp- > >dcb->dpconf.link_bw), > + conn_base_id); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c > b/drivers/gpu/drm/radeon/radeon_dp_mst.c > index 13072c2a6502..ec867fa880a4 100644 > --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c > +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c > @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector > *radeon_connector) > radeon_connector->mst_mgr.cbs = &mst_cbs; > return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, > &radeon_connector->ddc_bus->aux, > 16, 6, > - 4, (u8)max_link_rate, > + 4, > drm_dp_bw_code_to_link_rate(max_link_rate), > radeon_connector->base.base.id); > } > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index c87a829b6498..ddb9231d0309 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { > /** > * @max_lane_count: maximum number of lanes the GPU can drive. > */ > - u8 max_lane_count; > + int max_lane_count; > /** > - * @max_link_rate: maximum link rate per lane GPU can output. > + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. > */ > - u8 max_link_rate; > + int max_link_rate; > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value. > @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, > int max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id); > > void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-13 16:30 ` Lyude Paul 0 siblings, 0 replies; 21+ messages in thread From: Lyude Paul @ 2021-05-13 16:30 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: David Airlie, dri-devel, Meenakshikumar Somasundaram, James Jones, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Leo Li, Lucas De Marchi, intel-gfx, Sean Paul, Rodrigo Vivi, Mikita Lipski, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Thomas Zimmermann, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Reviewed-by: Lyude Paul <lyude@redhat.com> Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth, which makes kHz a more generic unit. This should also make > forward-compatibility with new DP standards easier. > > [how] > - Replace 'link rate DPCD code' with 'link rate in kHz' when used with > drm_dp_mst_topology_mgr_init() > - Add/remove related DPCD code conversion from/to kHz where applicable > > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- > drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- > include/drm/drm_dp_mst_helper.h | 8 ++++---- > 6 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > index 4a0c24ce5f7d..f78dd021f591 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct > amdgpu_display_manager *dm, > &aconnector->dm_dp_aux.aux, > 16, > 4, > - (u8)max_link_enc_cap.lane_count, > - (u8)max_link_enc_cap.link_rate, > + max_link_enc_cap.lane_count, > + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), > aconnector->connector_id); > > drm_connector_attach_dp_subconnector_property(&aconnector->base); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 54604633e65c..32b7f8983b94 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct > drm_dp_mst_topology_mgr *mgr, bool ms > } > > lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, > mgr->max_lane_count); > - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); > + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr- > >dpcd[1]), mgr->max_link_rate); > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, > - > drm_dp_bw_code_to_link_r > ate(link_rate), > + link_rate, > lane_count); > if (mgr->pbn_div == 0) { > ret = -EINVAL; > @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit > * @max_payloads: maximum number of payloads this GPU can source > * @max_lane_count: maximum number of lanes this GPU supports > - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD > + * @max_link_rate: maximum link rate per lane this GPU supports in kHz > * @conn_base_id: the connector object ID the MST device is connected to. > * > * Return 0 for success, or negative error code on failure > @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, int > max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id) > { > struct drm_dp_mst_topology_state *mst_state; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index f608c0cb98f4..26f65445bc8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > - (u8)dig_port->max_lanes, > - > drm_dp_link_rate_to_bw_code(max_source_rate), > + dig_port->max_lanes, > + max_source_rate, > conn_base_id); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index c46d0374b6e6..f949767698fc 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c > @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct > drm_dp_aux *aux, int aux_max, > mstm->mgr.cbs = &nv50_mstm; > > ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, > - (u8)max_payloads, outp->dcb- > >dpconf.link_nr, > - (u8)outp->dcb->dpconf.link_bw, > conn_base_id); > + max_payloads, outp->dcb- > >dpconf.link_nr, > + drm_dp_bw_code_to_link_rate(outp- > >dcb->dpconf.link_bw), > + conn_base_id); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c > b/drivers/gpu/drm/radeon/radeon_dp_mst.c > index 13072c2a6502..ec867fa880a4 100644 > --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c > +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c > @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector > *radeon_connector) > radeon_connector->mst_mgr.cbs = &mst_cbs; > return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, > &radeon_connector->ddc_bus->aux, > 16, 6, > - 4, (u8)max_link_rate, > + 4, > drm_dp_bw_code_to_link_rate(max_link_rate), > radeon_connector->base.base.id); > } > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index c87a829b6498..ddb9231d0309 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { > /** > * @max_lane_count: maximum number of lanes the GPU can drive. > */ > - u8 max_lane_count; > + int max_lane_count; > /** > - * @max_link_rate: maximum link rate per lane GPU can output. > + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. > */ > - u8 max_link_rate; > + int max_link_rate; > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value. > @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, > int max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id); > > void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Nouveau] [PATCH v2 1/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init @ 2021-05-13 16:30 ` Lyude Paul 0 siblings, 0 replies; 21+ messages in thread From: Lyude Paul @ 2021-05-13 16:30 UTC (permalink / raw) To: Nikola Cornij, amd-gfx Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen, dri-devel, Meenakshikumar Somasundaram, Ville Syrjälä, Rodrigo Siqueira, Jani Nikula, Aurabindo Pillai, Ben Skeggs, nouveau, Dave Airlie, Harry Wentland, Daniel Vetter, Leo Li, Lucas De Marchi, intel-gfx, Maarten Lankhorst, Maxime Ripard, Sean Paul, Jani Nikula, Rodrigo Vivi, Mikita Lipski, Matt Roper, Chris Park, Eryk Brol, Pan, Xinhui, linux-kernel, Wayne Lin, Alex Deucher, Lee Shawn C, Christian König Reviewed-by: Lyude Paul <lyude@redhat.com> Will let this sit on the list for a few days to see if anyone's got any objections and then I'll go ahead and push it On Wed, 2021-05-12 at 17:00 -0400, Nikola Cornij wrote: > [why] > Link rate in kHz is what is eventually required to calculate the link > bandwidth, which makes kHz a more generic unit. This should also make > forward-compatibility with new DP standards easier. > > [how] > - Replace 'link rate DPCD code' with 'link rate in kHz' when used with > drm_dp_mst_topology_mgr_init() > - Add/remove related DPCD code conversion from/to kHz where applicable > > Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> > Acked-by: Jani Nikula <jani.nikula@intel.com> > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- > drivers/gpu/drm/drm_dp_mst_topology.c | 8 ++++---- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +++-- > drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- > include/drm/drm_dp_mst_helper.h | 8 ++++---- > 6 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > index 4a0c24ce5f7d..f78dd021f591 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c > @@ -458,8 +458,8 @@ void amdgpu_dm_initialize_dp_connector(struct > amdgpu_display_manager *dm, > &aconnector->dm_dp_aux.aux, > 16, > 4, > - (u8)max_link_enc_cap.lane_count, > - (u8)max_link_enc_cap.link_rate, > + max_link_enc_cap.lane_count, > + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), > aconnector->connector_id); > > drm_connector_attach_dp_subconnector_property(&aconnector->base); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index 54604633e65c..32b7f8983b94 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -3722,9 +3722,9 @@ int drm_dp_mst_topology_mgr_set_mst(struct > drm_dp_mst_topology_mgr *mgr, bool ms > } > > lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, > mgr->max_lane_count); > - link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate); > + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr- > >dpcd[1]), mgr->max_link_rate); > mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr, > - > drm_dp_bw_code_to_link_r > ate(link_rate), > + link_rate, > lane_count); > if (mgr->pbn_div == 0) { > ret = -EINVAL; > @@ -5454,7 +5454,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit > * @max_payloads: maximum number of payloads this GPU can source > * @max_lane_count: maximum number of lanes this GPU supports > - * @max_link_rate: maximum link rate this GPU supports, units as in DPCD > + * @max_link_rate: maximum link rate per lane this GPU supports in kHz > * @conn_base_id: the connector object ID the MST device is connected to. > * > * Return 0 for success, or negative error code on failure > @@ -5462,7 +5462,7 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state); > int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, int > max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id) > { > struct drm_dp_mst_topology_state *mst_state; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index f608c0cb98f4..26f65445bc8a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -960,8 +960,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port > *dig_port, int conn_base_id) > intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, > - (u8)dig_port->max_lanes, > - > drm_dp_link_rate_to_bw_code(max_source_rate), > + dig_port->max_lanes, > + max_source_rate, > conn_base_id); > if (ret) > return ret; > diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c > b/drivers/gpu/drm/nouveau/dispnv50/disp.c > index c46d0374b6e6..f949767698fc 100644 > --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c > +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c > @@ -1617,8 +1617,9 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct > drm_dp_aux *aux, int aux_max, > mstm->mgr.cbs = &nv50_mstm; > > ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, > - (u8)max_payloads, outp->dcb- > >dpconf.link_nr, > - (u8)outp->dcb->dpconf.link_bw, > conn_base_id); > + max_payloads, outp->dcb- > >dpconf.link_nr, > + drm_dp_bw_code_to_link_rate(outp- > >dcb->dpconf.link_bw), > + conn_base_id); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c > b/drivers/gpu/drm/radeon/radeon_dp_mst.c > index 13072c2a6502..ec867fa880a4 100644 > --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c > +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c > @@ -642,7 +642,7 @@ radeon_dp_mst_init(struct radeon_connector > *radeon_connector) > radeon_connector->mst_mgr.cbs = &mst_cbs; > return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev, > &radeon_connector->ddc_bus->aux, > 16, 6, > - 4, (u8)max_link_rate, > + 4, > drm_dp_bw_code_to_link_rate(max_link_rate), > radeon_connector->base.base.id); > } > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index c87a829b6498..ddb9231d0309 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -596,11 +596,11 @@ struct drm_dp_mst_topology_mgr { > /** > * @max_lane_count: maximum number of lanes the GPU can drive. > */ > - u8 max_lane_count; > + int max_lane_count; > /** > - * @max_link_rate: maximum link rate per lane GPU can output. > + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. > */ > - u8 max_link_rate; > + int max_link_rate; > /** > * @conn_base_id: DRM connector ID this mgr is connected to. Only used > * to build the MST connector path value. > @@ -774,7 +774,7 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > struct drm_device *dev, struct drm_dp_aux > *aux, > int max_dpcd_transaction_bytes, > int max_payloads, > - u8 max_lane_count, u8 max_link_rate, > + int max_lane_count, int max_link_rate, > int conn_base_id); > > void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); -- Sincerely, Lyude Paul (she/her) Software Engineer at Red Hat Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've asked me a question, are waiting for a review/merge on a patch, etc. and I haven't responded in a while, please feel free to send me another email to check on my status. I don't bite! _______________________________________________ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (4 preceding siblings ...) (?) @ 2021-05-12 21:12 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-12 21:12 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init URL : https://patchwork.freedesktop.org/series/90099/ State : warning == Summary == $ dim checkpatch origin/drm-tip c9bc0648dd46 drm/dp_mst: Use kHz as link rate units when settig source max link caps at init -:44: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #44: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:3725: + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); total: 0 errors, 1 warnings, 0 checks, 88 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (5 preceding siblings ...) (?) @ 2021-05-12 21:43 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-12 21:43 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 13109 bytes --] == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init URL : https://patchwork.freedesktop.org/series/90099/ State : success == Summary == CI Bug Log - changes from CI_DRM_10074 -> Patchwork_20114 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/index.html Known issues ------------ Here are the changes found in Patchwork_20114 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html * igt@gem_exec_fence@basic-await@rcs0: - fi-bsw-nick: [PASS][2] -> [FAIL][3] ([i915#3457]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-nick/igt@gem_exec_fence@basic-await@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-nick/igt@gem_exec_fence@basic-await@rcs0.html * igt@gem_exec_fence@basic-await@vecs0: - fi-glk-dsi: [PASS][4] -> [FAIL][5] ([i915#3457]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@gem_exec_fence@basic-await@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-glk-dsi/igt@gem_exec_fence@basic-await@vecs0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271]) +6 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_exec_fence@nb-await@vcs0: - fi-bsw-kefka: [PASS][7] -> [FAIL][8] ([i915#3457]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html * igt@gem_exec_fence@nb-await@vecs0: - fi-bsw-n3050: [PASS][9] -> [FAIL][10] ([i915#3457]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@gem_wait@wait@all: - fi-bwr-2160: [PASS][12] -> [FAIL][13] ([i915#3457]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bwr-2160/igt@gem_wait@wait@all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bwr-2160/igt@gem_wait@wait@all.html * igt@i915_module_load@reload: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][14] ([i915#1982] / [i915#3457]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@i915_module_load@reload.html * igt@i915_selftest@live@execlists: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][15] ([i915#2782] / [i915#3462] / [i915#794]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][16] ([i915#1886] / [i915#2291]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@mman: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][17] ([i915#3457]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@i915_selftest@live@mman.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-elk-e7500: [PASS][20] -> [FAIL][21] ([i915#53]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-bsw-kefka: [PASS][22] -> [FAIL][23] ([i915#53]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@runner@aborted: - fi-kbl-soraka: NOTRUN -> [FAIL][24] ([i915#1436] / [i915#3363]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-soraka/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_fence@basic-await@vcs0: - fi-bsw-kefka: [FAIL][25] ([i915#3457]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html * igt@gem_exec_fence@nb-await@rcs0: - fi-glk-dsi: [FAIL][27] ([i915#3457]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html * igt@gem_exec_fence@nb-await@vcs0: - fi-bsw-nick: [FAIL][29] ([i915#3457]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html * igt@gem_exec_suspend@basic-s3: - {fi-tgl-1115g4}: [FAIL][31] ([i915#1888]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html * igt@gem_wait@wait@all: - fi-pnv-d510: [FAIL][33] ([i915#3457]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-pnv-d510/igt@gem_wait@wait@all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-pnv-d510/igt@gem_wait@wait@all.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [INCOMPLETE][35] ([i915#2782]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-snb-2600/igt@i915_selftest@live@hangcheck.html #### Warnings #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [FAIL][37] ([i915#3457]) -> [FAIL][38] ([i915#3457] / [i915#3472]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-pnv-d510/igt@gem_exec_gttfill@basic.html - fi-ilk-650: [FAIL][39] ([i915#3457]) -> [FAIL][40] ([i915#3472]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-ilk-650/igt@gem_exec_gttfill@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-ilk-650/igt@gem_exec_gttfill@basic.html * igt@i915_module_load@reload: - fi-elk-e7500: [DMESG-WARN][41] ([i915#3457]) -> [DMESG-FAIL][42] ([i915#3457]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-elk-e7500/igt@i915_module_load@reload.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-elk-e7500/igt@i915_module_load@reload.html - fi-bsw-kefka: [DMESG-WARN][43] ([i915#1982] / [i915#3457]) -> [DMESG-FAIL][44] ([i915#1982] / [i915#3457]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-bsw-kefka/igt@i915_module_load@reload.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-bsw-kefka/igt@i915_module_load@reload.html * igt@runner@aborted: - fi-kbl-x1275: [FAIL][45] ([i915#1436] / [i915#3363]) -> [FAIL][46] ([i915#1436] / [i915#2426] / [i915#3363]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-kbl-x1275/igt@runner@aborted.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-kbl-x1275/igt@runner@aborted.html - fi-cfl-8700k: [FAIL][47] ([i915#3363]) -> [FAIL][48] ([i915#2426] / [i915#3363]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-cfl-8700k/igt@runner@aborted.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-cfl-8700k/igt@runner@aborted.html - fi-skl-6600u: [FAIL][49] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][50] ([i915#1436] / [i915#3363]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-skl-6600u/igt@runner@aborted.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-skl-6600u/igt@runner@aborted.html - fi-glk-dsi: [FAIL][51] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][52] ([i915#3363] / [k.org#202321]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-glk-dsi/igt@runner@aborted.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-glk-dsi/igt@runner@aborted.html - fi-cml-u2: [FAIL][53] ([i915#2082] / [i915#2426] / [i915#3363]) -> [FAIL][54] ([i915#3363]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-cml-u2/igt@runner@aborted.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-cml-u2/igt@runner@aborted.html - fi-cfl-guc: [FAIL][55] ([i915#3363]) -> [FAIL][56] ([i915#2426] / [i915#3363]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/fi-cfl-guc/igt@runner@aborted.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/fi-cfl-guc/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932 [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (43 -> 32) ------------------------------ Additional (1): fi-kbl-soraka Missing (12): fi-ilk-m540 fi-bxt-dsi fi-ehl-1 fi-tgl-u2 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-kbl-7500u fi-dg1-1 fi-cfl-8109u fi-bdw-samus fi-skl-6700k2 Build changes ------------- * Linux: CI_DRM_10074 -> Patchwork_20114 CI-20190529: 20190529 CI_DRM_10074: 5aefdc1f23734b6a3d545c8497b098ba4d704a0c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6083: d28aee5c5f528aa6c352c3339f20aaed4d698ffa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20114: c9bc0648dd46f86fe2e194537ce6111106e0a291 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c9bc0648dd46 drm/dp_mst: Use kHz as link rate units when settig source max link caps at init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/index.html [-- Attachment #1.2: Type: text/html, Size: 17501 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (6 preceding siblings ...) (?) @ 2021-05-13 5:07 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-13 5:07 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30302 bytes --] == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init URL : https://patchwork.freedesktop.org/series/90099/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10074_full -> Patchwork_20114_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_20114_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20114_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_20114_full: ### IGT changes ### #### Possible regressions #### * igt@api_intel_bb@render@render-none-reloc-1024: - shard-glk: [PASS][1] -> [WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk2/igt@api_intel_bb@render@render-none-reloc-1024.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk3/igt@api_intel_bb@render@render-none-reloc-1024.html * igt@gem_exec_gttfill@all: - shard-apl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@gem_exec_gttfill@all.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: - shard-snb: NOTRUN -> [INCOMPLETE][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html * igt@i915_pm_rpm@gem-mmap-type@uc: - shard-glk: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@i915_pm_rpm@gem-mmap-type@uc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk5/igt@i915_pm_rpm@gem-mmap-type@uc.html - shard-apl: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl7/igt@i915_pm_rpm@gem-mmap-type@uc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl8/igt@i915_pm_rpm@gem-mmap-type@uc.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled: - shard-skl: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html * igt@kms_plane_cursor@pipe-b-primary-size-256: - shard-snb: NOTRUN -> [FAIL][10] +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@kms_plane_cursor@pipe-b-primary-size-256.html #### Warnings #### * igt@gem_ctx_engines@invalid-engines: - shard-glk: [INCOMPLETE][11] ([i915#3457] / [i915#3468]) -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk3/igt@gem_ctx_engines@invalid-engines.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk7/igt@gem_ctx_engines@invalid-engines.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: - shard-skl: [INCOMPLETE][13] ([i915#3468]) -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-skl7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html * igt@gem_render_copy@yf-tiled-ccs-to-linear: - shard-glk: [INCOMPLETE][15] ([i915#3468]) -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk3/igt@gem_render_copy@yf-tiled-ccs-to-linear.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk5/igt@gem_render_copy@yf-tiled-ccs-to-linear.html * igt@kms_plane_cursor@pipe-c-viewport-size-64: - shard-tglb: [FAIL][17] ([i915#3457]) -> [FAIL][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-tglb8/igt@kms_plane_cursor@pipe-c-viewport-size-64.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb6/igt@kms_plane_cursor@pipe-c-viewport-size-64.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_plane@plane-position-hole@pipe-b-planes}: - shard-glk: [FAIL][19] ([i915#3457]) -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk9/igt@kms_plane@plane-position-hole@pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk8/igt@kms_plane@plane-position-hole@pipe-b-planes.html Known issues ------------ Here are the changes found in Patchwork_20114_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@offset-control: - shard-snb: NOTRUN -> [DMESG-WARN][21] ([i915#3457]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@api_intel_bb@offset-control.html - shard-skl: NOTRUN -> [DMESG-WARN][22] ([i915#3457]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@api_intel_bb@offset-control.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][23] ([i915#180] / [i915#3457]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1099]) +4 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@gem_ctx_persistence@idempotent.html * igt@gem_ctx_ringsize@idle@vcs0: - shard-apl: [PASS][25] -> [FAIL][26] ([i915#3457]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl1/igt@gem_ctx_ringsize@idle@vcs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl2/igt@gem_ctx_ringsize@idle@vcs0.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][27] ([i915#3354] / [i915#3457]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][28] -> [FAIL][29] ([i915#2842] / [i915#3457]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@bcs0: - shard-glk: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3457]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk2/igt@gem_exec_fair@basic-none@bcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][31] -> [FAIL][32] ([i915#2842] / [i915#3457]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [PASS][33] -> [FAIL][34] ([i915#2842] / [i915#3457]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk3/igt@gem_exec_fair@basic-pace@vcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-skl: NOTRUN -> [FAIL][35] ([i915#2389] / [i915#3457]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][36] ([i915#2389] / [i915#3457]) +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_exec_schedule@u-fairslice@vecs0: - shard-glk: NOTRUN -> [FAIL][37] ([i915#3457]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk4/igt@gem_exec_schedule@u-fairslice@vecs0.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl1/igt@gem_exec_suspend@basic-s3.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl4/igt@gem_exec_suspend@basic-s3.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-glk: [PASS][40] -> [INCOMPLETE][41] ([i915#3468]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-snb: NOTRUN -> [INCOMPLETE][42] ([i915#3468]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][43] -> [FAIL][44] ([i915#307]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-iclb: [PASS][45] -> [INCOMPLETE][46] ([i915#3468]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb6/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-iclb3/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html * igt@gem_mmap_gtt@fault-concurrent-y: - shard-skl: NOTRUN -> [INCOMPLETE][47] ([i915#3468]) +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl4/igt@gem_mmap_gtt@fault-concurrent-y.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: - shard-apl: NOTRUN -> [INCOMPLETE][48] ([i915#3468]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html * igt@gem_render_copy@yf-tiled-ccs-to-linear: - shard-skl: NOTRUN -> [INCOMPLETE][49] ([i915#198] / [i915#3468]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl8/igt@gem_render_copy@yf-tiled-ccs-to-linear.html * igt@gem_spin_batch@legacy@default: - shard-apl: NOTRUN -> [FAIL][50] ([i915#2898] / [i915#3457]) +4 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@gem_spin_batch@legacy@default.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3323]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl7/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_wait@await@rcs0: - shard-apl: NOTRUN -> [FAIL][52] ([i915#3457]) +11 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@gem_wait@await@rcs0.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109289]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb5/igt@gen7_exec_parse@oacontrol-tracking.html * igt@gen9_exec_parse@bb-large: - shard-kbl: NOTRUN -> [FAIL][54] ([i915#3296]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@gen9_exec_parse@bb-large.html * igt@i915_module_load@reload: - shard-kbl: NOTRUN -> [DMESG-WARN][55] ([i915#3457]) +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@i915_module_load@reload.html * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: [PASS][56] -> [DMESG-WARN][57] ([i915#3457]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-iclb3/igt@i915_pm_rpm@cursor-dpms.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-iclb5/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@gem-mmap-type@wc: - shard-apl: [PASS][58] -> [DMESG-WARN][59] ([i915#3457]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl7/igt@i915_pm_rpm@gem-mmap-type@wc.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl8/igt@i915_pm_rpm@gem-mmap-type@wc.html * igt@i915_pm_rps@reset: - shard-apl: NOTRUN -> [DMESG-FAIL][60] ([i915#3457]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@i915_pm_rps@reset.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][61] ([i915#2782]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@i915_selftest@live@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][62] -> [FAIL][63] ([i915#2521]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl8/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_big_fb@y-tiled-64bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][64] ([fdo#111614]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb5/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-snb: NOTRUN -> [SKIP][65] ([fdo#109271] / [fdo#111827]) +26 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html * igt@kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +9 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +10 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +6 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> [TIMEOUT][69] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@kms_content_protection@atomic.html * igt@kms_content_protection@lic: - shard-apl: NOTRUN -> [TIMEOUT][70] ([i915#1319]) +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@kms_content_protection@lic.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-skl: NOTRUN -> [FAIL][71] ([i915#3444] / [i915#3457]) +5 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen: - shard-tglb: [PASS][72] -> [FAIL][73] ([i915#2124] / [i915#3457]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-snb: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3457]) +55 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt@kms_cursor_crc@pipe-a-cursor-max-size-random: - shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3457]) +8 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-max-size-random.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen: - shard-snb: NOTRUN -> [FAIL][76] ([i915#3457]) +7 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-random: - shard-kbl: NOTRUN -> [FAIL][77] ([i915#3444] / [i915#3457]) +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-256x256-random.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-kbl: [PASS][78] -> [FAIL][79] ([i915#3444] / [i915#3457]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-random: - shard-apl: NOTRUN -> [FAIL][80] ([i915#3444] / [i915#3457]) +2 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html * igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen: - shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3457]) +13 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x64-random: - shard-glk: [PASS][82] -> [FAIL][83] ([i915#3444] / [i915#3457]) +5 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk9/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk2/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html * igt@kms_cursor_crc@pipe-d-cursor-128x128-rapid-movement: - shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#3457]) +13 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_cursor_crc@pipe-d-cursor-128x128-rapid-movement.html * igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge: - shard-glk: [PASS][85] -> [FAIL][86] ([i915#70]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk5/igt@kms_cursor_edge_walk@pipe-c-128x128-left-edge.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-snb: NOTRUN -> [SKIP][87] ([fdo#109271]) +402 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +78 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-skl: [PASS][89] -> [DMESG-FAIL][90] ([i915#1982] / [i915#3457]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: NOTRUN -> [INCOMPLETE][91] ([i915#155] / [i915#180] / [i915#636]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [PASS][92] -> [DMESG-WARN][93] ([i915#180]) +1 similar issue [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-apl: NOTRUN -> [DMESG-WARN][94] ([i915#180]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-tglb: NOTRUN -> [SKIP][95] ([i915#2587]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_hdr@bpc-switch: - shard-skl: NOTRUN -> [FAIL][96] ([i915#1188]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl4/igt@kms_hdr@bpc-switch.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - shard-glk: [PASS][97] -> [FAIL][98] ([i915#53]) +1 similar issue [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533]) +2 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> [FAIL][100] ([fdo#108145] / [i915#265]) +1 similar issue [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html - shard-apl: NOTRUN -> [FAIL][101] ([fdo#108145] / [i915#265]) +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-kbl: NOTRUN -> [FAIL][102] ([fdo#108145] / [i915#265]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_cursor@pipe-a-primary-size-64: - shard-skl: NOTRUN -> [FAIL][103] ([i915#2657] / [i915#3457] / [i915#3461]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl4/igt@kms_plane_cursor@pipe-a-primary-size-64.html * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-skl: NOTRUN -> [FAIL][104] ([i915#2657] / [i915#3457]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_plane_cursor@pipe-a-viewport-size-128.html * igt@kms_plane_cursor@pipe-a-viewport-size-256: - shard-apl: [PASS][105] -> [FAIL][106] ([i915#2657]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl3/igt@kms_plane_cursor@pipe-a-viewport-size-256.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@kms_plane_cursor@pipe-a-viewport-size-256.html * igt@kms_plane_cursor@pipe-b-overlay-size-128: - shard-kbl: NOTRUN -> [FAIL][107] ([i915#2657]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl4/igt@kms_plane_cursor@pipe-b-overlay-size-128.html * igt@kms_plane_cursor@pipe-b-overlay-size-64: - shard-kbl: NOTRUN -> [FAIL][108] ([i915#2657] / [i915#3457]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@kms_plane_cursor@pipe-b-overlay-size-64.html * igt@kms_plane_cursor@pipe-b-viewport-size-256: - shard-snb: NOTRUN -> [FAIL][109] ([i915#3461]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-snb5/igt@kms_plane_cursor@pipe-b-viewport-size-256.html * igt@kms_plane_cursor@pipe-b-viewport-size-64: - shard-glk: [PASS][110] -> [FAIL][111] ([i915#2657] / [i915#3457]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk3/igt@kms_plane_cursor@pipe-b-viewport-size-64.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk9/igt@kms_plane_cursor@pipe-b-viewport-size-64.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3: - shard-apl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#658]) +2 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html - shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658]) +1 similar issue [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1: - shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658]) +1 similar issue [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html * igt@kms_setmode@clone-exclusive-crtc: - shard-skl: NOTRUN -> [WARN][115] ([i915#2100]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl9/igt@kms_setmode@clone-exclusive-crtc.html * igt@kms_vblank@pipe-d-wait-forked-hang: - shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271]) +92 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@kms_vblank@pipe-d-wait-forked-hang.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#2437]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@kms_writeback@writeback-check-output.html * igt@kms_writeback@writeback-pixel-formats: - shard-kbl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2437]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@kms_writeback@writeback-pixel-formats.html * igt@perf_pmu@busy-check-all@vcs0: - shard-glk: [PASS][119] -> [FAIL][120] ([i915#3457]) +23 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-glk5/igt@perf_pmu@busy-check-all@vcs0.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-glk4/igt@perf_pmu@busy-check-all@vcs0.html * igt@prime_mmap_coherency@read: - shard-kbl: NOTRUN -> [INCOMPLETE][121] ([i915#3468]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl3/igt@prime_mmap_coherency@read.html * igt@prime_nv_pcopy@test2: - shard-kbl: NOTRUN -> [SKIP][122] ([fdo#109271]) +88 similar issues [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl1/igt@prime_nv_pcopy@test2.html * igt@sysfs_clients@pidname: - shard-apl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2994]) +1 similar issue [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl7/igt@sysfs_clients@pidname.html * igt@sysfs_clients@recycle-many: - shard-skl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#2994]) +1 similar issue [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-skl9/igt@sysfs_clients@recycle-many.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-apl: [DMESG-WARN][125] ([i915#180] / [i915#3457]) -> [PASS][126] +2 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_eio@in-flight-suspend: - shard-kbl: [DMESG-WARN][127] ([i915#180] / [i915#3457]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl7/igt@gem_eio@in-flight-suspend.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl3/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][129] ([i915#2842] / [i915#3457]) -> [PASS][130] +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [FAIL][131] ([i915#2842] / [i915#3457]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_schedule@u-independent@vecs0: - shard-apl: [FAIL][133] ([i915#3457]) -> [PASS][134] +6 similar issues [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-apl3/igt@gem_exec_schedule@u-independent@vecs0.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/shard-apl1/igt@gem_exec_schedule@u-independent@vecs0.html * igt@gem_mmap_gtt@big-copy: - shard-skl: [FAIL][135] ([i915#307]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10074/shard-skl9/igt@gem_mmap_gtt@big == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20114/index.html [-- Attachment #1.2: Type: text/html, Size: 33691 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (7 preceding siblings ...) (?) @ 2021-05-20 18:10 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-20 18:10 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) URL : https://patchwork.freedesktop.org/series/90099/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2bc1c0fbd55e drm/dp_mst: Use kHz as link rate units when settig source max link caps at init -:45: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #45: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:3725: + link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate); total: 0 errors, 1 warnings, 0 checks, 88 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (8 preceding siblings ...) (?) @ 2021-05-20 18:42 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-20 18:42 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6810 bytes --] == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) URL : https://patchwork.freedesktop.org/series/90099/ State : success == Summary == CI Bug Log - changes from CI_DRM_10113 -> Patchwork_20163 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/index.html Known issues ------------ Here are the changes found in Patchwork_20163 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][1] ([i915#2283]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html * igt@i915_selftest@live@execlists: - fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][2] ([i915#3462]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-bdw-5557u/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [PASS][3] -> [INCOMPLETE][4] ([i915#2782]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-snb-2600/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1372]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html - fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html * igt@kms_psr@cursor_plane_move: - fi-bdw-5557u: NOTRUN -> [SKIP][8] ([fdo#109271]) +9 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html #### Possible fixes #### * igt@i915_selftest@live@hangcheck: - {fi-hsw-gt1}: [DMESG-WARN][9] ([i915#3303]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [DMESG-WARN][11] ([i915#2868]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html #### Warnings #### * igt@i915_selftest@live@execlists: - fi-icl-u2: [DMESG-FAIL][13] ([i915#3462]) -> [INCOMPLETE][14] ([i915#2782] / [i915#3462]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-icl-u2/igt@i915_selftest@live@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-icl-u2/igt@i915_selftest@live@execlists.html * igt@runner@aborted: - fi-skl-6600u: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#3363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-skl-6600u/igt@runner@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-skl-6600u/igt@runner@aborted.html - fi-icl-u2: [FAIL][17] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][18] ([i915#2782] / [i915#3363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-icl-u2/igt@runner@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-icl-u2/igt@runner@aborted.html - fi-bdw-5557u: [FAIL][19] ([i915#1602] / [i915#2029]) -> [FAIL][20] ([i915#3462]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-bdw-5557u/igt@runner@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-bdw-5557u/igt@runner@aborted.html - fi-kbl-soraka: [FAIL][21] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][22] ([i915#1436] / [i915#3363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-kbl-soraka/igt@runner@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-kbl-soraka/igt@runner@aborted.html - fi-kbl-7567u: [FAIL][23] ([i915#1436] / [i915#3363]) -> [FAIL][24] ([i915#1436] / [i915#2426] / [i915#3363]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/fi-kbl-7567u/igt@runner@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/fi-kbl-7567u/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932 [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 Participating hosts (42 -> 38) ------------------------------ Missing (4): fi-bdw-samus fi-bsw-cyan fi-apl-guc fi-hsw-4200u Build changes ------------- * Linux: CI_DRM_10113 -> Patchwork_20163 CI-20190529: 20190529 CI_DRM_10113: 7a90018e59889ff846d0b9ec9fa4cad75ef978d7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6089: 698613116728db5000759e69c074ce6ab2131765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20163: 2bc1c0fbd55eadd0814263948d63810f6deacdbb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2bc1c0fbd55e drm/dp_mst: Use kHz as link rate units when settig source max link caps at init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/index.html [-- Attachment #1.2: Type: text/html, Size: 9013 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij ` (9 preceding siblings ...) (?) @ 2021-05-22 2:55 ` Patchwork -1 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2021-05-22 2:55 UTC (permalink / raw) To: Nikola Cornij; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30309 bytes --] == Series Details == Series: drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) URL : https://patchwork.freedesktop.org/series/90099/ State : success == Summary == CI Bug Log - changes from CI_DRM_10113_full -> Patchwork_20163_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_20163_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@legacy-engines-persistence: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb2/igt@gem_ctx_persistence@legacy-engines-persistence.html * igt@gem_ctx_ringsize@idle@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][2] ([i915#3316]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@gem_ctx_ringsize@idle@bcs0.html * igt@gem_ctx_sseu@engines: - shard-tglb: NOTRUN -> [SKIP][3] ([i915#280]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@gem_ctx_sseu@engines.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][4] ([i915#2389]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#2055] / [i915#3468]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-glk8/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk4/igt@gem_mmap_gtt@cpuset-basic-small-copy.html - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#3468]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl7/igt@gem_mmap_gtt@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: - shard-snb: NOTRUN -> [INCOMPLETE][9] ([i915#2055]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html - shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([i915#3468]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-tglb1/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2428]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb6/igt@gem_mmap_gtt@cpuset-big-copy-xy.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-xy.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-tglb: [PASS][14] -> [INCOMPLETE][15] ([i915#3468] / [i915#750]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-tglb8/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb7/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html * igt@gem_mmap_gtt@fault-concurrent: - shard-glk: NOTRUN -> [INCOMPLETE][16] ([i915#3468]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk4/igt@gem_mmap_gtt@fault-concurrent.html * igt@gem_mmap_gtt@fault-concurrent-x: - shard-snb: NOTRUN -> [INCOMPLETE][17] ([i915#3468] / [i915#3485]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb5/igt@gem_mmap_gtt@fault-concurrent-x.html * igt@gem_mmap_gtt@fault-concurrent-y: - shard-snb: NOTRUN -> [INCOMPLETE][18] ([i915#3468]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb7/igt@gem_mmap_gtt@fault-concurrent-y.html - shard-apl: NOTRUN -> [INCOMPLETE][19] ([i915#3468]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gem_mmap_gtt@fault-concurrent-y.html * igt@gem_mmap_gtt@medium-copy-xy: - shard-snb: NOTRUN -> [INCOMPLETE][20] ([i915#2055] / [i915#2502]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb2/igt@gem_mmap_gtt@medium-copy-xy.html * igt@gem_mmap_offset@clear: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#3160]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb3/igt@gem_mmap_offset@clear.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb8/igt@gem_mmap_offset@clear.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][23] ([i915#2658]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gem_pread@exhaustion.html * igt@gem_render_copy@linear-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#768]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gem_render_copy@linear-to-vebox-yf-tiled.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271]) +54 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109312]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gem_softpin@evict-snoop.html - shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109312]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@gem_softpin@evict-snoop.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][28] ([i915#3002]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@set-cache-level: - shard-apl: NOTRUN -> [FAIL][29] ([i915#3324]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gem_userptr_blits@set-cache-level.html * igt@gem_workarounds@suspend-resume-context: - shard-kbl: NOTRUN -> [DMESG-WARN][30] ([i915#180]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl2/igt@gem_workarounds@suspend-resume-context.html * igt@gen7_exec_parse@basic-allowed: - shard-tglb: NOTRUN -> [SKIP][31] ([fdo#109289]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@gen7_exec_parse@basic-allowed.html - shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109289]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gen7_exec_parse@basic-allowed.html * igt@gen7_exec_parse@basic-offset: - shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271]) +168 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#112306]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@gen9_exec_parse@bb-start-cmd.html - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#112306]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gen9_exec_parse@bb-start-cmd.html * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][36] -> [INCOMPLETE][37] ([i915#2880]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111615]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#110723]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html * igt@kms_big_joiner@basic: - shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#2705]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl2/igt@kms_big_joiner@basic.html - shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#2705]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@kms_big_joiner@basic.html * igt@kms_ccs@pipe-a-ccs-on-another-bo: - shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271]) +240 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb7/igt@kms_ccs@pipe-a-ccs-on-another-bo.html * igt@kms_ccs@pipe-c-bad-aux-stride: - shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111304]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@kms_ccs@pipe-c-bad-aux-stride.html * igt@kms_chamelium@hdmi-hpd-after-suspend: - shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827]) +3 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_chamelium@hdmi-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-storm: - shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +5 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl2/igt@kms_chamelium@hdmi-hpd-storm.html * igt@kms_chamelium@vga-hpd: - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +19 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl7/igt@kms_chamelium@vga-hpd.html * igt@kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +8 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb2/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue: - shard-glk: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk4/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html * igt@kms_color_chamelium@pipe-d-degamma: - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_color_chamelium@pipe-d-degamma.html - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_color_chamelium@pipe-d-degamma.html * igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes: - shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html * igt@kms_content_protection@legacy: - shard-apl: NOTRUN -> [TIMEOUT][52] ([i915#1319]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@kms_content_protection@legacy.html * igt@kms_content_protection@lic: - shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109300] / [fdo#111066]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_content_protection@lic.html - shard-tglb: NOTRUN -> [SKIP][54] ([fdo#111828]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_content_protection@lic.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-sliding: - shard-tglb: NOTRUN -> [SKIP][55] ([i915#3359]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-32x10-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][56] -> [INCOMPLETE][57] ([i915#300]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_crc@pipe-d-cursor-256x85-random: - shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109278]) +5 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html * igt@kms_cursor_legacy@cursora-vs-flipb-atomic: - shard-tglb: NOTRUN -> [SKIP][59] ([fdo#111825]) +8 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109274] / [fdo#109278]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html * igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium: - shard-tglb: NOTRUN -> [SKIP][61] ([i915#2065]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html - shard-iclb: NOTRUN -> [SKIP][62] ([i915#2065]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_flip@2x-flip-vs-panning-vs-hang: - shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271]) +29 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@kms_flip@2x-flip-vs-panning-vs-hang.html * igt@kms_flip@2x-flip-vs-rmfb-interruptible: - shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109274]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html * igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][65] -> [FAIL][66] ([i915#2122]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@plain-flip-fb-recreate@a-edp1: - shard-skl: [PASS][67] -> [FAIL][68] ([i915#2122]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html * igt@kms_force_connector_basic@force-load-detect: - shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109285]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_force_connector_basic@force-load-detect.html - shard-tglb: NOTRUN -> [SKIP][70] ([fdo#109285]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280]) +5 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][72] -> [DMESG-WARN][73] ([i915#180]) +1 similar issue [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu: - shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271]) +14 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][75] -> [FAIL][76] ([i915#1188]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-skl: NOTRUN -> [FAIL][78] ([i915#265]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html - shard-apl: NOTRUN -> [FAIL][79] ([i915#265]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658]) +2 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1: - shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4: - shard-iclb: NOTRUN -> [SKIP][83] ([i915#658]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html - shard-tglb: NOTRUN -> [SKIP][84] ([i915#2920]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][85] -> [SKIP][86] ([fdo#109441]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb6/igt@kms_psr@psr2_sprite_render.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][87] -> [DMESG-WARN][88] ([i915#180] / [i915#295]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@nouveau_crc@pipe-a-source-rg: - shard-iclb: NOTRUN -> [SKIP][89] ([i915#2530]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@nouveau_crc@pipe-a-source-rg.html - shard-tglb: NOTRUN -> [SKIP][90] ([i915#2530]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@nouveau_crc@pipe-a-source-rg.html * igt@perf@polling-parameterized: - shard-iclb: [PASS][91] -> [FAIL][92] ([i915#1542]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb6/igt@perf@polling-parameterized.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb5/igt@perf@polling-parameterized.html * igt@prime_nv_pcopy@test3_5: - shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109291]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@prime_nv_pcopy@test3_5.html - shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109291]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@prime_nv_pcopy@test3_5.html * igt@sysfs_clients@fair-0: - shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl6/igt@sysfs_clients@fair-0.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +3 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][98] ([i915#2369] / [i915#3063]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-tglb2/igt@gem_eio@unwedge-stress.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb3/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [FAIL][100] ([i915#2842]) -> [PASS][101] +1 similar issue [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][102] ([i915#2842]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [FAIL][104] ([i915#2842]) -> [PASS][105] +1 similar issue [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_reloc@basic-wc-gtt-active: - shard-skl: [FAIL][106] -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl1/igt@gem_exec_reloc@basic-wc-gtt-active.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl9/igt@gem_exec_reloc@basic-wc-gtt-active.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-iclb: [INCOMPLETE][108] ([i915#3468]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@gem_mmap_gtt@cpuset-basic-small-copy.html - shard-tglb: [INCOMPLETE][110] ([i915#3468]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-tglb6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-tglb6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-glk: [INCOMPLETE][112] ([i915#3468]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-glk4/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk2/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html * igt@gem_pwrite@basic-random: - shard-glk: [DMESG-WARN][114] ([i915#118] / [i915#95]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-glk4/igt@gem_pwrite@basic-random.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-glk2/igt@gem_pwrite@basic-random.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [INCOMPLETE][116] ([i915#198]) -> [PASS][117] +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_selftest@live@hangcheck: - shard-snb: [INCOMPLETE][118] ([i915#2782]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-snb2/igt@i915_selftest@live@hangcheck.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-snb7/igt@i915_selftest@live@hangcheck.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [FAIL][120] ([i915#2346]) -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [INCOMPLETE][122] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@plain-flip-ts-check@a-edp1: - shard-skl: [FAIL][124] ([i915#2122]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl2/igt@kms_flip@plain-flip-ts-check@a-edp1.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl2/igt@kms_flip@plain-flip-ts-check@a-edp1.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][126] ([fdo#108145] / [i915#265]) -> [PASS][127] +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@perf@polling-parameterized: - shard-skl: [FAIL][128] ([i915#1542]) -> [PASS][129] [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-skl1/igt@perf@polling-parameterized.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-skl9/igt@perf@polling-parameterized.html * igt@perf_pmu@rc6-suspend: - shard-apl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-apl6/igt@perf_pmu@rc6-suspend.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-apl7/igt@perf_pmu@rc6-suspend.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][132] ([i915#1804] / [i915#2684]) -> [WARN][133] ([i915#2684]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-iclb: [SKIP][134] ([i915#2920]) -> [SKIP][135] ([i915#658]) +2 similar issues [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@runner@aborted: - shard-kbl: ([FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) -> ([FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl2/igt@runner@aborted.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl1/igt@runner@aborted.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl7/igt@runner@aborted.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl4/igt@runner@aborted.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl3/igt@runner@aborted.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl3/igt@runner@aborted.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl7/igt@runner@aborted.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10113/shard-kbl4/igt@runner@aborted.h == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20163/index.html [-- Attachment #1.2: Type: text/html, Size: 34187 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-05-22 2:55 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-12 21:00 [PATCH v2 0/1] drm/dp_mst: Use kHz as link rate units when settig source max link caps at init Nikola Cornij 2021-05-12 21:00 ` Nikola Cornij 2021-05-12 21:00 ` [Intel-gfx] " Nikola Cornij 2021-05-12 21:00 ` Nikola Cornij 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij 2021-05-12 21:00 ` [PATCH v2 1/1] " Nikola Cornij 2021-05-12 21:00 ` Nikola Cornij 2021-05-12 21:00 ` [Intel-gfx] " Nikola Cornij 2021-05-12 21:00 ` Nikola Cornij 2021-05-12 21:00 ` [Nouveau] " Nikola Cornij 2021-05-13 16:30 ` Lyude Paul 2021-05-13 16:30 ` Lyude Paul 2021-05-13 16:30 ` [Intel-gfx] " Lyude Paul 2021-05-13 16:30 ` Lyude Paul 2021-05-13 16:30 ` [Nouveau] " Lyude Paul 2021-05-12 21:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2021-05-12 21:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-05-13 5:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-05-20 18:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/dp_mst: Use kHz as link rate units when settig source max link caps at init (rev2) Patchwork 2021-05-20 18:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-05-22 2:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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