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* [Intel-gfx] [PATCH] drm/i915/display: Fix the dsc check while selecting min_cdclk
@ 2021-09-15  5:43 Vandita Kulkarni
  2021-09-15  6:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (6 more replies)
  0 siblings, 7 replies; 11+ messages in thread
From: Vandita Kulkarni @ 2021-09-15  5:43 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, Vandita Kulkarni

The right parameter that selects second dsc engine is dsc_split.
Hence use dsc_split instead of slice_count while selecting the
cdclk in order to accommodate 1ppc limitaion of vdsc.

Fixes: fe01883fdcef ("drm/i915: Get proper min cdclk if vDSC enabled")
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..3a1cdb3937aa 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2140,13 +2140,11 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
 	/*
-	 * VDSC engine can process only 1 pixel per Cd clock.
-	 * In case VDSC is used and max slice count == 1,
-	 * max supported pixel clock should be 100% of CD clock.
-	 * Then do min_cdclk and pixel clock comparison to get cdclk.
+	 * When we decide to use only one VDSC engine, since
+	 * each VDSC operates with 1 ppc throughput, pixel clock
+	 * cannot be higher than the VDSC clock (cdclk)
 	 */
-	if (crtc_state->dsc.compression_enable &&
-	    crtc_state->dsc.slice_count == 1)
+	if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
 		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
 
 	/*
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-09-28  8:08 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-15  5:43 [Intel-gfx] [PATCH] drm/i915/display: Fix the dsc check while selecting min_cdclk Vandita Kulkarni
2021-09-15  6:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2021-09-15 11:35 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Fix the dsc check while selecting min_cdclk (rev2) Patchwork
2021-09-16  9:56   ` Kulkarni, Vandita
2021-09-21  4:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Fix the dsc check while selecting min_cdclk (rev3) Patchwork
2021-09-21  5:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-21 10:25   ` Kulkarni, Vandita
2021-09-21 15:20 ` Patchwork
2021-09-21 15:48 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2021-09-27  9:38 ` [Intel-gfx] [PATCH] drm/i915/display: Fix the dsc check while selecting min_cdclk Jani Nikula
2021-09-28  8:07   ` Shankar, Uma

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