[U-Boot] [RESEND PATCH 3/5] usb: host: dwc2: force reset assert

[Marek Vasut <marex@denx.de>]

On 11/8/19 11:51 AM, Patrick DELAUNAY wrote:
[...]
>>>> Isn't there a way to poll the IP to determine whether the reset completed ?
>>>
>>> It is HW IP reset, the complete state is not available for stm32mp1 reset
>> controller (RCC).
>>> And the need reset duration of depends on each IP (can't be handle in reset u-
>> class).
>>
>> If it's a SoC specific delay, it should be in the reset driver.
>>
>>> I check with DWC2 OTG IP expert, and we found in
>>> DWC_otg_databook_3.30a.pdf
>>>
>>> t_rst: DWC_otg PHY clock domain reset and AHB hclk domain reset over lap
>> time
>>>         (a minimum of 12 cycles of the slowest clock is recommended.)
>>>
>>> In our board, we have 209MHz for AHB frequency... USB phy clock is
>>> 48MHz So freq12 cycles is MIN(57ns,  250ns) < 1us.
>>>
>>> The 2us value seens a over protection.
>>>
>>> I will reduce it to 1us in V2 and I will add comments for.
>>
>> Well, why don't you put this into the reset driver ? Seems to be a more fitting place
>> for this. I don't think every single SoC has the same clock settings.
> 
> Ok, I will remove the delay in driver.

Does it make sense to put it into the reset driver though ?